Impulse machining control device

Abstract

A pulse processing control device controls processing performed by periodic multiple pulse-like outputs in synchronization with a clock pulse, wherein the pulse processing control device includes: an output setting value acquisition section that acquires multiple output setting values that respectively determine frequencies or periods of the multiple pulse-like outputs; a clock period acquisition section that acquires a period of the clock pulse; a relationship determination section that determines a quantity relationship of the multiple output setting values; and a count value determination section that determines multiple clock count values in a manner that satisfies the quantity relationship, the multiple clock count values respectively being quantities of the clock pulse per one period of the pulse-like output of the output setting value.

Description

Technical Field

[0001] This invention relates to a pulse machining control device. Background Technology

[0002] Techniques using multiple pulsed lasers for processing are known. For example, there are techniques that improve machinability by overlapping the irradiation of multiple lasers with different wavelengths or intensity distributions (see, for example, Patent Document 1). As a specific example, consider forming a molten pool of metal on the surface of a material by irradiating it with a pulsed laser of a wavelength easily absorbed by solid metals, and then overlapping the irradiation with pulsed lasers of wavelengths easily absorbed by the molten metals to further heat the molten metal, thereby efficiently performing metal welding, cutting, and other processing. Furthermore, as another example, plasma processing apparatuses have separate devices for a main pulse power supply for performing arc discharge for processing and a plasma pulse power supply for forming plasma.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2008-44000 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] When using multiple pulse outputs, it is sometimes desirable to synchronize the start points of the output cycles of these pulses, i.e., to maintain a constant time deviation between the outputs. Typically, the control device operates synchronously with a clock pulse, and the pulse outputs are switched on and off when the clock pulse count reaches a set value. However, if the output frequency is set in the control device, converting one output cycle into the number of clock pulses may result in a fractional part, causing the set clock pulse count to be a value that has been rounded up or down. This rounding up or down error, less than one clock pulse, accumulates during repeated output cycles and can produce a non-negligible deviation relative to other output cycles. Therefore, a technique is desired to prevent timing deviations in multiple pulse outputs.

[0008] Methods for solving problems

[0009] One aspect of this disclosure relates to a pulse processing control apparatus that controls processing performed in sync with a clock pulse through a plurality of periodic pulse-shaped outputs. The apparatus comprises: an output setting value acquisition unit that acquires a plurality of output setting values ​​that respectively determine the frequency or period of the plurality of pulse-shaped outputs; a clock period acquisition unit that acquires the period of the clock pulse; a relationship determination unit that determines a quantitative relationship between the plurality of output setting values; and a count value determination unit that determines a plurality of clock count values ​​in a manner satisfying the quantitative relationship, wherein each of the plurality of clock count values ​​represents the number of clock pulses in one period of the pulse-shaped outputs according to the output setting values. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating the structure of a pulse processing control device according to one embodiment of the present disclosure.

[0011] Figure 2 It means Figure 1 The flowchart of the control process of the pulse processing control device.

[0012] Figure 3 It means Figure 1 A flowchart of the process for an alternative control scheme for a pulse processing control device. Detailed Implementation

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. Figure 1 This is a block diagram showing the structure of a pulse processing control device 1 according to one embodiment of the present disclosure.

[0014] The pulse processing control device 1 controls processing performed in sync with a clock pulse through a series of periodic pulse-shaped outputs. These multiple pulse-shaped outputs, for example, can have different wavelengths or output distributions, and can be configured as multiple laser outputs irradiating coaxially. In other words, the pulse processing control device 1 can control the laser processing apparatus.

[0015] The pulse machining control device 1 includes a memory, a processor, an input / output interface, etc., and can be implemented by one or more computer devices that execute appropriate control programs. The pulse machining control device 1 includes an output setpoint acquisition unit 11, a clock cycle acquisition unit 12, a relationship determination unit 13, a count value determination unit 14, and an output instruction generation unit 15. The constituent elements of the pulse machining control device 1 are categorized according to the functions of the pulse machining control device 1, and may not be constituent elements that can be clearly distinguished in the physical structure and program structure.

[0016] The output setting value acquisition unit 11 acquires multiple output setting values ​​that determine the frequency or period of multiple pulse-like outputs. The output setting value acquisition unit 11 can be configured to accept the input of output setting values ​​via an input device or a communication line. Alternatively, the output setting value acquisition unit 11 can also be configured to parse a processing program describing the processing content to be performed in order to set multiple output setting values.

[0017] The output setting value acquisition unit 11 can also set each output setting value based on a reference value and a setting value ratio relative to the reference value. By setting each output setting value as a ratio relative to the reference value, the relationship between multiple output setting values ​​becomes clear. Furthermore, the reference value can be any output setting value.

[0018] The clock cycle acquisition unit 12 acquires the period of the clock pulse. The clock cycle acquisition unit 12 can calculate the reciprocal of the clock frequency or refer to a pre-stored clock cycle.

[0019] The relationship determination unit 13 determines the quantitative relationship between multiple output setting values ​​set by the output setting value acquisition unit 11. The quantitative relationship is preferably represented by an integer with fewer significant digits than the output setting value. For example, the relationship determination unit 13 can be configured to calculate the multiple of each output setting value relative to a reference value. When setting output setting values ​​based on a reference value and a setting value ratio, the relationship determination unit 13 can also be configured to acquire the setting value ratio. The reference value can be a fixed value, a value input by the user, or a value calculated based on the output setting value and other processing conditions. The relationship determination unit 13 can also be configured to use any one output setting value as a reference value and calculate the multiples of other output setting values ​​relative to the reference output setting value. For example, the reference value can be a predetermined pulse-type output setting value, the minimum value of multiple output setting values, etc.

[0020] Furthermore, the relationship determination unit 13 can also calculate the least common multiple or greatest common divisor of multiple output setting values ​​as a value representing the quantitative relationship between the multiple output setting values. In addition, the relationship determination unit 13 can also calculate multiples or approximations of the least common multiple or greatest common divisor relative to the multiple output setting values. In particular, the relationship determination unit 13 preferably calculates the least common multiple of the frequencies represented by the multiple output setting values, and each multiple of the least common multiple relative to the frequencies represented by the multiple output setting values.

[0021] The count value determination unit 14 determines the number of clock pulses output in a pulse-like pattern according to the output setting value for one cycle, i.e., multiple clock count values, in a manner that satisfies the quantitative relationship determined by the relationship determination unit 13. As a result, during the repeated counting of multiple clock count values, the reset timing of the clock count values ​​is frequently consistent.

[0022] The count value determination unit 14 may also be configured to, after calculating multiple original count values ​​obtained by dividing one cycle of multiple output setting values ​​by the cycle of the clock pulse, correct the original count values ​​in a manner that satisfies the quantitative relationship determined by the relationship determination unit 13, thereby obtaining multiple clock count values.

[0023] Figure 2 The steps shown are up to the determination of the clock count value in the pulse processing control device 1 when the count value determination unit 14 determines the clock count value by calculating and correcting the original count value. Figure 2 The steps for determining the clock count value include: obtaining the output setting value (step S01); obtaining the clock cycle (step S02); determining the quantitative relationship (step S03); calculating the original count value (step S04); confirming whether the relationship of the original count satisfies the quantitative relationship (step S05); and correcting the original count value (step S06).

[0024] In the step S01 of obtaining the output setting value, the output setting value acquisition unit 11 obtains output setting value 1 and output setting value 2, which respectively determine the frequencies of the two pulse-shaped outputs. Furthermore, output setting value 1 is less than output setting value 2. Here, we will describe output setting value 1 as 1000 Hz and output setting value 2 as 3000 Hz.

[0025] In the step S02, the clock period acquisition process obtains the clock pulse period through the clock period acquisition unit 12. Here, the clock period is set to 1.0 μsec (1 × 10⁻¹⁰). -6 sec).

[0026] In step S03, which determines the quantitative relationship, the multiple of output setpoint 2 relative to output setpoint 1 is calculated as the quantitative relationship. The multiple is 3000 / 1000 = 3.

[0027] In step S04, the process of calculating the original count value is performed by calculating the original count value 1 and the original count value 2 based on the output setting value 1, the output setting value 2, and the clock cycle. The original count value 1 is (1 / 1000) / (1×10^2)^2. -6 =1000, the original count value 2 is (1 / 3000) / (1×10 -6 = 333 (discarding the last digit).

[0028] In step S05, which verifies whether the relationship between the original counts satisfies the quantitative relationship, it is confirmed whether the multiple of the original count value 2 relative to the original count value 1 satisfies the quantitative relationship. That is, it is confirmed whether (original count value 1) is consistent with (original count value 2) × (multiple). In this example, 333 × 3 = 999 ≠ 1000, therefore the quantitative relationship is not satisfied.

[0029] If the relationship between the original count value 1 and the original count value 2 satisfies the quantitative relationship in step S05, the original count value 1 and the original count value 2 are set as the clock count value 1 and the clock count value 2 used in actual control. If the relationship between the original count value 1 and the original count value 2 does not satisfy the quantitative relationship in step S05, the original count value 1 is corrected in step S06 to obtain the clock count value 1.

[0030] In step S06, the process of correcting the original count value, the value of clock count value 1 is changed to the value obtained by multiplying the original count value 2 by a factor. In this example, the value of clock count value 1 is corrected to 333 × 3 = 999. Thus, one cycle of pulsed output according to output setting value 1 and three cycles of pulsed output according to output setting value 2 are completely consistent without any deviation of one clock pulse.

[0031] In addition, becoming Figure 2 In that way, the count value determination unit 14 can also directly calculate multiple clock count values ​​that satisfy the quantitative relationship based on multiple output setting values ​​and counting cycles. As a specific example, the count value determination unit 14 can also calculate a basic count value corresponding to one cycle of the least common multiple of the frequencies shown by the multiple output setting values, and multiply the basic count value by each multiple of the least common multiple relative to the multiple output setting values, thereby determining each clock count.

[0032] Figure 3 The steps up to determining the count value in the pulse processing control device 1 when using the least common multiple as the quantitative relationship are shown. Figure 3 The steps for determining the clock count value include: obtaining the output setting value (step S11); obtaining the clock cycle (step S12); determining the quantitative relationship (step S13); and calculating the clock count value (step S14).

[0033] In the process of obtaining the output setting value in step S11, the output setting value acquisition unit 11 obtains output setting value 1 and output setting value 2, which respectively determine the frequencies of the two pulse-shaped outputs. Here, we will explain the process by assuming that output setting value 1 is 800 Hz and output setting value 2 is 600 Hz.

[0034] In step S12, the clock period acquisition unit 12 acquires the period of the clock pulse. Here, the clock period is 1.0 μsec (1 × 10⁻¹⁰). -6 sec).

[0035] In step S13, which determines the quantitative relationship, the least common multiple of output setpoint 1 and output setpoint 2, and the ratio of the least common multiple to output setpoint 1 and output setpoint 2 are calculated as the quantitative relationship. In this example, the least common multiple is 2400 Hz, the ratio of the least common multiple to output setpoint 1 is 3, and the ratio of the least common multiple to output setpoint 1 is 4.

[0036] In step S14, the process of calculating the clock count value first involves calculating a base count value corresponding to one cycle of a frequency with a least common multiple. This base count value is then multiplied by the multiplier to obtain the individual clock count values. In this example, the base count value corresponding to one cycle of the least common multiple 2400 Hz is (1 / 2400) / (1×10⁻⁶). -6 = 416 (discarding the last digit). Furthermore, the clock count value 1 corresponding to output setting value 1 is 416 × 3 = 1248, and the clock count value 2 corresponding to output setting value 2 is 416 × 4 = 1664. Alternatively, the last digit of the base count value can be rounded up to 417, making clock count value 1 1251 and clock count value 2 1668. Thus, the three cycles of pulsed output according to output setting value 1 are completely consistent with the four cycles of pulsed output according to output setting value 2.

[0037] The output instruction generation unit 15 generates multiple output instructions that specify the output states of multiple pulse-shaped outputs. The output instruction generation unit 15 counts clock pulses and repeatedly changes the value of the output instruction for each corresponding clock count value.

[0038] As described above, the pulse processing control device 1 determines the relationship between multiple clock counts that switch the states of multiple pulse-shaped outputs based on the quantitative relationship of the output setpoints. Therefore, even if the output cycle of the pulse-shaped outputs is repeated, there will be no phase shift between the pulse-shaped outputs, thus enabling accurate processing of the desired outputs.

[0039] The following notes further disclose the above-described embodiments and variations.

[0040] (Note 1)

[0041] The pulse processing control device 1 is a pulse processing control device that controls processing performed in sync with a clock pulse through a plurality of periodic pulse-shaped outputs. It includes: an output setting value acquisition unit 11, which acquires a plurality of output setting values ​​that respectively determine the frequency or period of the plurality of pulse-shaped outputs; a clock period acquisition unit 12, which acquires the period of a clock pulse; a relationship determination unit 13, which determines the quantitative relationship between the plurality of output setting values; and a count value determination unit 14, which determines a plurality of clock count values ​​in a manner that satisfies the quantitative relationship. The plurality of clock count values ​​are the number of clock pulses in one period of the pulse-shaped output according to the output setting values.

[0042] (Note 2)

[0043] In the pulse processing control device 1 of Appendix 1, the count value determination unit 14 can also obtain multiple clock count values ​​by calculating multiple original count values ​​obtained by dividing one cycle shown by multiple output setting values ​​by the cycle of the clock pulse and then correcting the original count values.

[0044] (Note 3)

[0045] In the pulse processing control device 1 described in Appendix 1 or 2, the output setting value acquisition unit 11 can also calculate each output setting value based on a reference value and the ratio of the setting value to the reference value.

[0046] (Note 4)

[0047] In the pulse processing control device 1 described in Appendices 1 to 3, the relationship determination unit 13 can also calculate the multiple of other output setting values ​​relative to an output setting value that serves as a reference.

[0048] (Note 5)

[0049] In the pulse processing control device 1 described in Appendices 1 to 3, the relationship determination unit 13 can also calculate the least common multiple or the greatest common divisor of multiple output setting values.

[0050] (Note 6)

[0051] In the pulse processing control device 1 described in Appendices 1 to 3, the relationship determination unit 13 can also calculate the least common multiple of the frequencies shown by the multiple output setting values ​​and each multiple of the least common multiple relative to the frequencies shown by the multiple output setting values.

[0052] (Note 7)

[0053] In the pulse processing control device 1 described in Appendices 1 to 6, multiple pulse-shaped outputs can also be laser outputs.

[0054] The present disclosure has been described in detail above, but it is not limited to the various embodiments described above. Various additions, substitutions, modifications, and partial deletions can be made to these embodiments without departing from the spirit of the present disclosure, or from the spirit of the present disclosure derived from the content described in the claimed scope and its equivalents. Furthermore, these embodiments can also be implemented in combination. For example, in the embodiments described above, the order of each action and the order of each process are shown as an example and are not limited thereto. The same applies to the use of numerical values ​​or mathematical formulas in the description of the above embodiments.

[0055] Symbol Explanation

[0056] 1. Pulse machining control device

[0057] 11 Output setting value acquisition unit

[0058] 12-clock-cycle acquisition unit

[0059] 13 Relationship Decision Department

[0060] 14. Count Value Determination Department

[0061] 15. Output instruction generation unit.

Claims

1. A pulse processing control device for controlling processing performed in sync with a clock pulse through a series of periodic pulse-like outputs, characterized in that, The pulse processing control device includes: The output setting value acquisition unit acquires multiple output setting values ​​that respectively determine the frequency or period of the multiple pulse-shaped outputs; The clock cycle acquisition unit acquires the period of the clock pulse; The relationship determination unit determines the quantitative relationship between the multiple output setpoints; as well as The counting value determination unit determines multiple clock count values ​​in a manner that satisfies the quantity relationship, wherein the multiple clock count values ​​are the number of clock pulses in one cycle of the pulse-shaped output according to the output setting value.

2. The pulse processing control device according to claim 1, characterized in that, The count value determination unit calculates multiple original count values ​​obtained by dividing one cycle of the multiple output setting values ​​by the cycle of the clock pulse, and then corrects the original count values ​​to obtain the multiple clock count values.

3. The pulse processing control device according to claim 1 or 2, characterized in that, The output setting value acquisition unit calculates each output setting value based on a reference value and a setting value ratio relative to the reference value.

4. The pulse processing control device according to any one of claims 1 to 3, characterized in that, The relationship determination unit calculates the multiples of other output settings relative to the output settings that serve as a reference.

5. The pulse processing control device according to any one of claims 1 to 3, characterized in that, The relationship determination unit calculates the least common multiple or the greatest common divisor of the multiple output settings.

6. The pulse processing control device according to any one of claims 1 to 3, characterized in that, The relationship determination unit calculates the least common multiple of the frequencies represented by the plurality of output settings and each multiple of the least common multiple relative to the frequencies represented by the plurality of output settings.

7. The pulse processing control device according to any one of claims 1 to 6, characterized in that, The multiple pulsed outputs are laser outputs.

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