Folded residue system crossbar adder unit

Abstract

An adder circuit adds two selected numbers in a fast, efficient manner modulo p. The addition can be implemented using a crossbar adder circuit. In a folded split crossbar embodiment, for signed-magnitude format operands modulo p, a crossbar of size ((p+1) / 2) x ((p+1) / 2) can be used to compute the magnitude of the sum, and logic circuitry is used to compute the sign of the sum.

Description

Technical Field

[0001] The following text generally pertains to the field of electronic circuits, and more specifically, to electronic circuits used to perform arithmetic functions such as multiplication. Background Technology

[0002] Computer systems typically include one or more circuits for performing arithmetic functions such as addition, subtraction, multiplication, and division. In general-purpose computer architectures, one or more circuits for performing arithmetic operations (such as multiplication) can be integrated into an execution unit within a central processing unit (CPU). For example, computer systems typically include combinational logic circuits such as vector units (VUs), arithmetic logic units (ALUs), and / or floating-point units (FPUs), often referred to as math coprocessors, found in microprocessors. One or more of these units may include addition circuitry (addition units) for performing addition operations. In general-purpose computer architectures, one or more VUs, ALUs, and / or FPUs can be integrated into an execution unit within a central processing unit.

[0003] One way to improve the efficiency of addition is to use Residual / Residue Number System (RNS) addition, where operands are represented by a set of remainders in a modulus set. While this approach offers advantages, it may require m×m lookup tables to find the modulus value of m, and may be restricted to specific values ​​(such as 2). i -1 or 2 i +1, where i is an integer, or not 2. i -1 or 2 i +1 modulo value may require multiple adders, and 2 i -1 or 2 i The +1 modulus limits the possible choices of the modulus. This circuit performs RNS-based addition operations more efficiently than a non-modular implementation of an adder circuit. Summary of the Invention

[0004] According to one aspect of the present invention, an addition circuit includes a cross-switch adder circuit and a sign determination circuit. The cross-switch adder circuit is configured to: receive the amplitude of a first modulo-p input number in a sign-amplitude format; receive the amplitude of a second modulo-p input number in the same sign-amplitude format; and determine the amplitude of the sum of the first and second modulo-p input numbers based on the amplitudes of the first and second modulo-p input numbers. The sign determination circuit is configured to: receive the sign value of the first modulo-p input number in the same sign-amplitude format; receive the sign value of the second modulo-p input number in the same sign-amplitude format; and determine the sign value of the sum of the first and second modulo-p input numbers based on the sign values ​​of the first and second modulo-p input numbers.

[0005] Optionally, in the above aspects, the cross switch adder circuit is a (p+1) / 2×(p+1) / 2 cross switch array.

[0006] Optionally, in the above aspects, the switches are arranged in columns and rows; each column of switches is connected between a corresponding amplitude of one of the first modulo-p inputs and a different row output; the control gate of each switch is connected to receive an amplitude of one of the second modulo-p inputs.

[0007] Optionally, in the above aspects, the adder circuit further includes: a first plurality of multiplexers, each multiplexer being configured to receive the amplitude of a corresponding pair of second modulo-p inputs as input, and apply a selected one of the corresponding pair of second modulo-p inputs along the opposite diagonal of the top triangle of the switch array to the control gate of the switch; and a second plurality of multiplexers, each multiplexer being configured to receive the amplitude of a corresponding pair of second modulo-p inputs as input, and apply a selected one of the corresponding pair of second modulo-p inputs along the opposite diagonal of the bottom triangle of the switch array to the control gate of the switch.

[0008] Optionally, in the above aspects, for each of the first plurality of multiplexers, the corresponding pair of second modulo p inputs are added to obtain a first identical value; for each of the second plurality of multiplexers, the corresponding pair of second modulo p inputs are added to obtain a second identical value.

[0009] Optionally, in any of the four aspects mentioned above, the switch is an NMOS transistor.

[0010] Optionally, in any of the five aspects described above, the switch is implemented as one or more of a finFET transistor, a gate-all-around (GAA) transistor, or a nanowire or nanosheet transistor.

[0011] Optionally, in any of the above aspects, the first modulo-p input number is received as a binary encoded value, the second modulo-p input number is received as a binary encoded value, and the cross-switch adder circuit is further configured to: convert the magnitude of the first modulo-p input number into a first binary value vector, wherein for non-zero values, one of the values ​​of the vector is 1, and the other values ​​of the vector are 0; convert the magnitude of the second modulo-p input number into a second binary value vector, wherein for non-zero values, one of the values ​​of the vector is 1, and the other values ​​of the vector are 0.

[0012] Optionally, in the above aspects, the cross switch adder circuit is further configured to: select between a first input value and a second input value for a non-zero value of the second modulo-p input number, so as to input the input value of the second modulo-p input number into the cross array.

[0013] Optionally, in the above three aspects, the addition circuit is one of a plurality of modular arithmetic units, each modular arithmetic unit corresponding to a different modulus value, and each modular arithmetic unit is used to receive the corresponding component of the input value in the remainder format system.

[0014] Optionally, in any of the above aspects, the adder circuit further includes: a plurality of level recovery circuits, each level recovery circuit being configured to receive two outputs of a row of the cross-switch adder circuit, one of the outputs being valid and the other being invalid, and to provide the output of each row as a strong logic value.

[0015] Optionally, in any of the above aspects, p is an odd number.

[0016] Optionally, in any of the above aspects, the adder circuit further includes: a buffer for connection to the cross-switch adder circuit and for storing a determined amplitude of the sum of the first modulo-p input and the second modulo-p input, wherein the amplitude of the second modulo-p input is the stored determined amplitude.

[0017] According to another aspect of the present invention, a method for performing modulo-p addition is provided, comprising: receiving a first modulo-p input number in a sign-amplitude format; receiving a second modulo-p input number in the sign-amplitude format; determining the amplitude of the sum of the first modulo-p input number and the second modulo-p input number by providing the amplitudes of the first modulo-p input number and the second modulo-p input number as corresponding first and second inputs of a cross-switch multiplier circuit; and determining the sign value of the sum of the first modulo-p input number and the second modulo-p input number based on the sign values ​​of the first modulo-p input number and the second modulo-p input number.

[0018] Optionally, in the above aspects, the method further includes: storing a determined amplitude of the sum in a buffer; and providing the stored determined amplitude of the sum in the buffer as the amplitude of the second modulo p input.

[0019] Optionally, in the above aspects, the method further includes: a modular p multiplier circuit generating the first modular p input number.

[0020] Optionally, in any of the three aspects immediately preceding it, p is an odd number.

[0021] Optionally, in any of the four aspects immediately preceding above, receiving the first modulo-p input number in the sign-amplitude format includes: receiving the first modulo-p input number as a binary encoded value; converting the amplitude of the first modulo-p input number into a first binary value vector, wherein for non-zero values, one of the values ​​of the vector is 1 and the other values ​​of the vector are 0; receiving the second modulo-p input number in the sign-amplitude format includes: receiving the second modulo-p input number as a binary encoded value; converting the amplitude of the second modulo-p input number into a second binary value vector, wherein for non-zero values, one of the values ​​of the vector is 1 and the other values ​​of the vector are 0.

[0022] Optionally, in the above aspects, the method further includes: selecting between a first input value and a second input value for a non-zero value of the second modulo p input number, so as to input the input value of the second modulo p input number into the cross array.

[0023] Optionally, in any of the six aspects immediately preceding above, the method further includes: receiving at each of the plurality of level recovery circuits two outputs of a corresponding row of the cross-switch multiplier circuit, one of the outputs being valid and the other being invalid; each of the level recovery circuits providing the output of the corresponding row as a strong logic value.

[0024] According to another aspect, a multiply-accumulate circuit includes a multiplier circuit and an adder circuit. The multiplier circuit is used to determine the product of a first modulo-p input and a second modulo-p input based on the multiplier circuit. The adder circuit includes: a buffer for storing the output of the adder circuit; a cross-switch adder circuit for: receiving from the multiplier circuit the magnitude of the product of the first modulo-p input and the second modulo-p input; receiving from the buffer the magnitude of the stored output of the adder circuit; determining the magnitude of the sum of the product of the first modulo-p input and the second modulo-p input and the stored output of the adder circuit; and a sign determination circuit for: receiving from the multiplier circuit the sign value of the product of the first modulo-p input and the second modulo-p input; receiving from the buffer the sign value of the stored output of the adder circuit; and determining the sign value of the sum of the product of the first modulo-p input and the second modulo-p input and the stored output of the adder circuit.

[0025] Optionally, in the above aspects, the multiply-accumulate circuit further includes the multiplication circuit, comprising: a cross-switch multiplier circuit, configured to: receive the amplitude of the first modulo-p input number and the amplitude of the second modulo-p input number; determine the amplitude of the product of the first modulo-p input number and the second modulo-p input number based on the amplitude of the first modulo-p input number and the amplitude of the second modulo-p input number; and a sign determination circuit, configured to: receive the sign value of the first modulo-p input number and the sign value of the second modulo-p input number; determine the sign value of the product of the first modulo-p input number and the second modulo-p input number based on the sign value of the first modulo-p input number and the sign value of the second modulo-p input number.

[0026] Optionally, in both of the above aspects, the cross-switch adder circuit is a (p+1) / 2×(p+1) / 2 cross-switch array.

[0027] Optionally, in the above aspects, the switch is an NMOS transistor.

[0028] Alternatively, in either of the above two aspects, the switch is implemented as one or more of a finFET transistor, a gate-all-around (GAA) transistor, or a nanowire or nanosheet transistor.

[0029] Optionally, in any of the aforementioned five aspects, the cross switch adder circuit is further configured to: select between a first input value and a second input value for a non-zero value of the magnitude of the product of the first modulo-p input number and the second modulo-p input number, so as to input the magnitude of the product of the first modulo-p input number and the second modulo-p input number into the cross array.

[0030] Alternatively, p can be a prime number in any of the six aspects mentioned above.

[0031] This invention provides a brief overview of some concepts, which will be further described in the specific embodiments. This invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that address any or all of the shortcomings mentioned in the background art. Attached Figure Description

[0032] Various aspects of the invention are illustrated by way of example and are not limited to the accompanying drawings, in which similar reference numerals denote similar elements.

[0033] Figure 1A and Figure 1B These are block diagrams of a computer system and a microprocessor that can be integrated into such a computer system; Figure 2A The components of a number are shown in the Residual / Residue Number System (RNS) number RNS(8|7|5|3) in binary encoded number format; Figure 2B Examples of structures for adders, subtractors, or multipliers for numbers in RNS format are shown, using the RNS(8|7|5|3) example. Figure 3 This shows how to implement non-2 k or 2 k Components of modular multiplication with a modulus of -1 form; Figure 4 A table is shown to identify primitive roots for an example of prime number p=7; Figure 5 This shows the values ​​of k from 0 to 9. k A table of modulo 11 values; Figure 6 The primitive roots of prime numbers less than 100 are listed, with prime numbers having the primitive root 2 highlighted. Figure 7 This shows the values ​​of k from 0 to 9. k A table of modulo 11 values ​​(for "wrap-around" and "non-wrap-around" remainders); Figure 8 and Figure 9 2 are shown respectively k A table of modulo 7 and modulo 23 values ​​(for wrap-around and non-wrap-around remainders); Figure 10 The primitive roots of prime numbers less than 100 are listed, along with additional available prime numbers that do not have a primitive root of 2, to which the methods presented in this paper can be applied; Figure 11A and Figure 11B Provides 2 for selected small prime numbers k Values ​​(for both wrapped-around and unwrapped-around remainders), these selected small primes have the primitive root 2 and can be used in the process, specifically for modulo values ​​of 5, 11, 13, 19, and 29; Figure 12 An example of a barrel shifter implemented efficiently using a cross switch is shown; Figure 13 A signed remainder table for (n-1) entries is shown for the example n=13; Figure 14 and Figure 15 The implementation methods of the signed modulo 13 multiplication circuit as a full cross switch circuit and the folded split cross switch circuit are illustrated schematically, respectively. Figure 16 The example for n=13 shows how the size of the remainders in the signed remainder table is reduced to only (n-1) / 2 entries; Figure 17A and Figure 17B An embodiment of a split-fold cross switch multiplier circuit is presented; Figure 18 This illustrates an NMOS-only cross-switch shifter circuit implementation that can be used in some embodiments; Figure 19 An example of a level restorer circuit is shown; Figure 20 An embodiment of a cross-connected level restoration circuit for use with the output of a split cross-switch multiplier is shown; Figure 21 and Figure 22 They are shown respectively Figure 20 The cross-connected level recovery circuit embodiment is designed for operation with "0" input and weak "1" input; Figure 23 It is used to show Figure 20 A flowchart illustrating the operation of an embodiment of a cross-connected level restoration circuit; Figure 24A and Figure 24B A portion of another embodiment of the split-folded cross-switch multiplier circuit for the example of n=13 is shown; Figure 25 It is a remainder table for modulo-23 multiplication using the wraparound-amplitude format; Figure 26 and Figure 27 An embodiment of sign bit-wrap-back switching in an NMOS with level recovery and a CMOS embodiment for a modulo 13 example are shown respectively; Figure 28An embodiment of a wrap-around selection circuit for product wrap-around sign conversion is shown for a modulo 13 example; Figure 29A and Figure 29B An embodiment of a folded split NMOS cross-switch multiplier for sign-amplitude format input is presented; Figure 30A and Figure 30B An embodiment of a folded NMOS cross-switch multiplier for inputs in a sign-amplitude format that is not primitive root 2 is presented; Figure 31 Based on Figure 17A , Figure 17B , Figure 24A , Figure 24B , Figure 29A , Figure 29B , Figure 30A and Figure 30B A flowchart illustrating an embodiment of the modular multiplication method; Figures 32 to 35 More details are provided regarding the input ordering of the cross array and its relationship to the modulus with the primitive root 2; Figure 36 A block diagram is shown illustrating a folded and non-folded cross switch embodiment for RNS multiplication using a power of 2 ordering. Figure 37 This is a block diagram of an example of a prior art Modulo 13 RNS adder; Figure 38 and Figure 39 The implementation methods of the modulo-13 adder circuit as a full cross switch circuit and a folded split cross switch circuit are illustrated schematically, respectively. Figures 40A to 40D The addition table for modulo 13 examples is presented when the input values ​​are collapsed; Figure 41 It shows Figures 40A to 40D Folding of each addition table; Figure 42A and Figure 42B Tables are presented for multiplexing the top and bottom triangles of the operand B input for the folded split cross switch adder circuit. Figure 43 yes Figures 40A to 40D A schematic diagram showing how the upper and lower triangles are arranged in a folded, split-type cross switch adder layout; Figure 44A and Figure 44B This is an embodiment of a folded, split-type cross switch adder; Figure 45 This is an embodiment of a folded split cross switch adder, wherein operands are received in a one-hot vector format of amplitude, and the output is provided in a one-hot vector format; Figure 46A and Figure 46B The NMOS cross-switch multi-and accumulate (MAC) embodiment in a folded split configuration is shown, where the input and output are in a sign-one-hot vector format. Figure 47 and Figure 48 They were presented respectively Figure 44A Operand B input multiplexer and Figure 44B A schematic diagram of an embodiment of an output multiplexer; Figures 49A to 49D The diagram illustrates the correspondence between different output choices for the modulo 13 example and the addition table when the input value is folded. Figure 50 yes Figure 44B and Figure 45 A circuit diagram of an embodiment of the output symbol circuit; Figures 51 to 53 Several topologies for accumulator implementations are presented; Figure 54 Based on Figure 44A , Figure 44B , Figure 45 and Figure 46B A flowchart illustrating an embodiment of the modular addition method; Figure 55 Examples of computing systems for implementing embodiments of the present invention are presented. Detailed Implementation

[0034] One technique to improve the efficiency of multiplication circuits is to use a Residual / Residue Number System (RNS), where multiplication operands are represented as a set of remainder values ​​in a modulus set. This allows multiplication to be decomposed into a set of channels, one channel corresponding to each of these modulo values, and modular arithmetic can be performed within each of these channels. This approach has the advantages of using traditional implementations, but it also suffers from several inefficiencies. One inefficiency is that it uses two-dimensional lookup tables for modular multiplication, where the size of such tables expands with the square of the modulus size, meaning these tables can become very large. Another inefficiency problem is that for non-2... k or 2 k Modular multiplication can be slow for modulo numbers of the form -1 because it uses division in the modular reduction of the product. Another inefficiency issue is that for modulo numbers of the form -1, modular multiplication might be slightly slower. kModulo numbers of the form -1 exist only in a finite number of "small" modulo numbers (e.g., 3, 7, 15, 31 for k < 5). This finite number of modulo numbers limits the range of numbers that can be represented by multiple modulo channels. Furthermore, since the modulo numbers must be pairwise coprime, only one 2 can be used. k Modulus of the form. Due to the inherent delay of carry propagation, 2 k Larger moduli in the form of -1 are not desirable.

[0035] In the embodiments presented below, multiplication can be implemented and improved by using a crossbar multiplication circuit. In the folded split crossbar embodiment, for modulo p operands in sign-amplitude format, a crossbar array of size ((p-1) / 2)×(p+1) / 2 can be used to calculate the amplitude of the product, and logic circuitry is used to calculate the sign of the product.

[0036] In another aspect, a cross-connected level recovery circuit is proposed. For each row of the folded split cross-switch multiplier circuit, two outputs are generated: one output is valid and at a low logic level or a degraded high logic level, and the other output is invalid and in a floating state. The cross-connected level recovery circuit restores the logic level of the valid input and returns the floating input to a low logic level.

[0037] The present embodiments of the invention can be implemented in many different forms, and the scope of the claims should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to convey the concept of embodiments of the invention to those skilled in the art. In fact, the invention is intended to cover alternatives, modifications, and equivalents to these embodiments, which are included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present embodiments of the invention, many specific details are set forth in order to provide a thorough understanding. However, it will be apparent to those skilled in the art that the present embodiments of the invention can be practiced without these specific details.

[0038] Figure 1A and Figure 1B These are block diagrams of a computer system for implementing one or more embodiments of the present invention, and a microprocessor that can be integrated into such a computer system. Figure 1AIn this simplified representation, computer system 100 includes a computer 105, one or more input devices 101, and one or more output devices 103. Common examples of input devices 101 include a keyboard or mouse, or even a voice recognition system that supports voice commands. Common examples of output devices 103 include a monitor, speakers, or a printer. Computer 105 includes memory 107 and a microprocessor 120, wherein, in this simplified representation, memory 107 is represented as a single block. Memory 107 may include ROM memory, RAM memory, and / or non-volatile memory, and according to embodiments, may include separate memory for data and instructions.

[0039] Figure 1B It shows Figure 1A One embodiment of the microprocessor 120 also includes a memory 107. Figure 1B In the representation, microprocessor 120 includes control logic 125, processing block 140, input interface 121, and output interface 123. Dashed lines represent control signals exchanged between control logic 125 and other components of microprocessor 120, as well as memory 107. Solid lines represent data and instruction flows within microprocessor 120 and between microprocessor 120 and memory 107.

[0040] Processing block 140 includes combinational logic 143 for executing instructions and register 141, wherein the combinational logic stores instructions and data while executing these instructions. Figure 1B In the simplified representation, certain elements or units are shown, such as vector unit (VU) 146, arithmetic logic unit (ALU) 147, and floating-point unit (FPU) processor 149, while other elements are not explicitly shown in combinational logic 143. Combinational logic 143 is connected to memory 107 to receive and execute instructions and return results. Combinational logic 143 is also connected to input interface 121 to receive input from one or more input devices 101 and / or other sources. Combinational logic 143 is also connected to output interface 123 to provide output to one or more output devices 103 and / or other destinations.

[0041] Microprocessors (such as microprocessor 120) can perform a range of different functions, including arithmetic operations. For example, a microprocessor can perform addition, subtraction, multiplication, multiplicative addition, and / or division. Aspects of the present invention enable microprocessors to perform multiplication operations efficiently. More generally, aspects of the present invention can be applied more generally to embodiments of one or more central processing units (CPUs), graphics processing units (GPUs), artificial intelligence (AI) accelerators, tensor processing units (TPUs), and / or any other digital logic that performs multiplication or multiplication as part of a multiplicative addition operation.

[0042] Multiplication operations can be performed by one or more multiplication circuits in microprocessor 120. For example, one or more of VU 146, ALU 147, and FPU 149 may include one or more multiplication circuits. Other elements of combinational logic 143 may alternatively or additionally include one or more multiplication circuits. The present invention is not limited to multiplication circuits or multiply-accumulate units located in any particular location (in a microprocessor or elsewhere) or used for any particular purpose, and can be applied to any situation requiring efficient multiplication or multiply-accumulate operations.

[0043] Multiplication can be performed using a variety of different methods. The embodiments presented in the following discussion are based on the use of the Residual / Residue Number System (RNS). Before discussing these embodiments, some discussion of the Residual / Residue Number System is necessary.

[0044] The remainder system is based on the use of modular arithmetic and a property known as the Chinese Remainder Theorem. If m 1, ... mk It is an integer greater than 1 (usually called an integer). Modulus or divisor Then the Chinese Remainder Theorem asserts: if mi They are pairwise coprime, and a 1, ... ak It is an integer such that for each i All satisfy 0 ≤ ai < mi Then there exists a unique integer. x , such that 0 ≤ x < N And for each i , x Divide by mi The remainder of Euclidean division is aiThe result is that if M represents the product of k pairwise coprime moduli, M = k 1×……×m1×m0, M is the number of distinct representable values ​​in an RNS, called its dynamic range. This allows any number within this dynamic range to be represented as a vector of values ​​corresponding to each of these moduli.

[0045] Taking moduli 8, 7, 5, and 3 as examples, the dynamic range in this example is M = 8 × 7 × 5 × 3 = 840, which is the total number of distinct values ​​that can be represented in this example's 4-modulus RNS. Numbers in this format consist of four components, one component corresponding to each modulus, and are called RNS(8|7|5|3) numbers. Below are some examples of numbers in the RNS(8|7|5|3) format: (0 | 0 | 0 | 0)RNS represents 0 or 840 or... (1 | 1 | 1 | 1)RNS represents 1 or 841 or... (2 | 2 | 2 | 2)RNS represents 2 or 842 or... (0 | 1 | 3 | 2) RNS represents 8 or 848 or... (5 | 0 | 1 | 0)RNS represents 21 or 861 or... (0 | 1 | 4 | 1)RNS represents 64 or 904 or... (2 | 0 | 0 | 2)RNS represents 70 or 770 or... (7 | 6 | 4 | 2)RNS represents 1 or 839 or... Other numbers (mod 840) can be represented in a similar manner in RNS(8|7|5|3) format. When performing arithmetic operations on integers in RNS format, the corresponding modulus can be used to perform the operations component by component. Performing arithmetic operations on integers in this way has several advantages.

[0046] Continuing with the examples of modulo 8, 7, 5, and 3, Figure 2A This shows an integer in the binary encoded number format of RNS(8|7|5|3) (corresponding to the dynamic range). This includes three 3-bit slots for modulo 8, modulo 7, and modulo 5 components, and one 2-bit slot for the modulo 3 component. When performing arithmetic on two numbers in this format, the operation can be performed separately on each component. This allows arithmetic operations on such RNS-formatted numbers to be separated into independent RNS channels, such as... Figure 2B As shown.

[0047] Figure 2B An embodiment of the structure of an adder, subtractor, or multiplier for RNS-formatted numbers is shown, using an RNS(8|7|5|3) example that can be implemented by a processor. Two operands, operand 1 and operand 2 in RNS(8|7|5|3) format, are shown at the top. They can be stored in corresponding registers 2111 and 2112, where these operands were previously converted to RNS format in an operation that typically requires several steps that can be hidden after other operations. The modulo 8, 7, 5, and 3 components of each operand are fed into corresponding modulo 8 unit 201, modulo 7 unit 203, modulo 5 unit 205, and modulo 3 unit 207, respectively, for pairwise operations using the corresponding modulo operations in each RNS channel. The result component can then be stored in result register 221, which can be used for subsequent RNS calculations or converted from RNS format to other formats if needed.

[0048] Combination Figure 2B The RNS method shown has several advantages. It solves the carry propagation problem because carry propagation is limited to only a few bits. It is faster because, for example, the simplicity of a 4×4 multiplier is far greater than that of a 16×16 multiplier by more than four times. It is also smaller because the size of a 4×4 multiplier is about 1 / 16 of that of a 16×16 multiplier (power and area scaled quadratically). Furthermore, remainder arithmetic can be implemented by direct table lookup. This method does require conversion between RNS format and binary, and some arithmetic operations (e.g., division, sign detection, overflow detection) are more difficult, but multiplication is discussed below, where this method can offer several advantages.

[0049] Considering the details of implementing efficient RNS multiplication, one detail is the choice of the RNS modulus, where two factors are channel width and the number of channels. If the goal is to reduce the execution time of addition / multiplication, a large number of small moduli are preferable, as the execution time is determined by the largest possible modulus, while the power / area of ​​the multiplier is related to n. 2 Proportional.

[0050] One way to choose the modulus is to use 2. k or 2 k A modulus of -1 is used for ease of implementation. In this method, an efficient binary representation can be used to minimize the total number of bits, i.e., for example, by choosing a modulus equal to 2. k or very close (2) k The modulus mi is chosen to maximize the dynamic range. Since the modulus must be coprime, only a modulus mi of 2 can be selected. k m in form i (2) k-1) Modulus m in the form of i The effect is good because a cyclic carry adder can be used for this form; however, not all (2 k -1) Items of the form can all be selected because, for example, when k is even, 2 k -1 = (2 k / 2 – 1)(2 k / 2 +1).

[0051] Consider the case of representing a 32-bit integer in an RNS system, where its range is 2^32. 32 = 4,294,967,296, and using 2 k or 2 k Moduli of the form -1 are used for ease of implementation. The possible set of moduli is m. i = 31, 63, 127, 255, 256. Because M / 2 32 =3.7799, therefore the dynamic range M is sufficiently large, and the set of moduli is coprime. These five moduli are 5-bit, 6-bit, 7-bit, 8-bit, and 8-bit respectively, totaling 34 bits. For 2... k Modulo numbers of the form can be solved using a standard binary adder, where the remainder is read directly from the LSB. For 2... k Modulo numbers in the form of -1 can be added using a "circular carry" adder.

[0052] Another approach is to use the smallest prime modulus that has a symmetric complete remainder system. An example for 32-bit integers is a nine-modulus m. i = 3, 5, 7, 11, 13, 19, 23, 29, 37. Because M / 2 32 = 1.6393, therefore the dynamic range M is sufficiently large, and the nine modules in this group are 2-bit, 3-bit, 3-bit, 4-bit, 4-bit, 5-bit, 5-bit, 5-bit, and 6-bit, for a total of 37 bits. While it has more modules (and a higher total number of bits), its maximum module is much smaller. This has the following advantages: smaller modules start faster, and due to the area / power ratio being log2(m i ) 2 It is proportional, therefore the area / power ratio decreases. However, achieving a non-2 k or 2 k Multiplication of modulo numbers of the form -1 has some complexity, such as the ability to combine... Figure 3 To illustrate.

[0053] Figure 3 This shows how to implement non-2 k or 2 kThe component for modular multiplication of modulo numbers in the form of -1. Multiplier block 301 receives two n-bit operands A and B and multiplies them to produce a 2n-bit result AB. To convert this result into an n-bit modulo m product of these numbers |AB|... m The product AB needs to be reduced modulo in block 303. However, performing modulo reduction requires division, which is a time-consuming multi-step operation that slows down the process. To avoid this problem, the following embodiments propose a simple and efficient method for performing modulo reduction on non-2... k or 2 k Multiplication is performed on modulo numbers in the form of -1.

[0054] The examples presented below involve using the primitive root of a number in modular arithmetic: given g x (mod p ),in p It is a prime number, the problem is that for numbers from 0 to... p Each of 1 x Does a value exist? g Values ​​to ensure that from 1 to p A unique output of 1. If a unique output exists, then the generator (g) is called a primitive root modulo p: Y = g x (mod p This can be achieved using Euler's totient function. φ ( p The Euler's totient function is used to calculate the number of positive integers that are less than or equal to a given integer p and are relatively prime to p (i.e., have no greatest common divisor other than 1). For prime numbers, φ ( p ) = p-1. Then determine φ ( p For each generator g, test g for all factors f. f (mod p). If any g f If (mod p) = 1, then g is not a primitive root of p. Figure 4 The example is shown.

[0055] Figure 4 A table is shown to identify primitive roots for the example prime number p=7. If p=7, then φ (7) = p-1 = 6, and its factors f = 2 and 3. In the table with p = 7, the first row is the generator, and the first column is the power x. The values ​​in the table are the corresponding generator raised to the power of x. As shown in the table, for g = {2, 4}, g 3 = 1, for g = {6}, g 2= 1. Therefore, 2, 3, and 6 are not primitive roots of p=7, and by testing g {2,3} (mod 7) indicates that the original roots are Y = 3 and 5.

[0056] In the following text, we focus on prime numbers with the primitive root 2, because for prime numbers modulo 2, modular multiplication can be performed by rotating a one-hot vector (i.e., a binary value vector that is all zeros except for a single entry "1"). For the example p=11, this can be done by... Figure 5 The table will be used to illustrate this.

[0057] Figure 5 This shows the values ​​of k from 0 to 9. k A table of modulo 11 values. The top row contains the value of k, and the bottom row contains the values ​​of 2. k The corresponding value. 2 k The remainder after modulo 11 reduction is located in the bottom row. Since the prime number 11 has a primitive root 2, therefore 2 k Each remainder modulo 11 is distinct, and all remainders except 0 are represented. (Note that k=0 corresponds to 2^k.) 0 =1, and 0 will be represented as a vector of all zeros. An example computation could be the multiplication of 3 (mod 11) × 6 (mod 11). The first operand is represented as a one-hot vector of (p-1) elements, where the position of 1 is based on the operand's position in the bottom row; therefore, for example, 3 is represented by the one-hot vector 0000000010. The second operand is represented by a rotation, where the rotation is 2 for operand value k. k Modular reduction, so taking 6 as an example, the rotation is 9. To compute the product of these operands, the one-hot vector of the first operand is rotated to the right by the rotation of the second operand; therefore, to compute 3 (mod 11) × 6 (mod 11), 0000000010 is rotated 9 bits to the right. The result is 0000000100, which corresponds to 7 and is the correct result. As this example shows, this method can perform modular multiplication on prime numbers with primitive root 2 using simple rotations.

[0058] Figure 6 The primitive roots of prime numbers less than 100 are listed. Prime numbers with the primitive root 2 are outlined with a thicker line. It can be seen that prime numbers with the primitive root 2 (less than 100) include: 3, 5, 11, 13, 19, 29, 37, 53, 59, 51, 67, and 83. When using this set of prime numbers as the modulus of an RNS number, the examples given below can be performed efficiently using modular multiplication, using only the (positive or "unwrapped") remainder, for example, when p=11. Figure 5 The table is shown in the bottom row. In other embodiments, unwrap remainder and wrap remainder can be used, such as in combination. Figure 7To illustrate.

[0059] Figure 7 This shows the values ​​of k from 0 to 9. k A table of modulo 11 values ​​(for "unwrapped" and "wrapped" remainders). Figure 7 Repeated Figure 5 The elements also include a bottom row for the unwrapped remainder values. For each unwrapped remainder x, there exists a wrapped remainder y such that y = x - p, where p is the modulus. y is called the additive inverse of x. Therefore, for the example p=11, instead of using the set {1, 2, 4, 8, 5, 10, 9, 7, 3, 6}, we can use the combined unwrapped set {1, 2, 4, 8, 5} and the wrapped set {10, 9, 7, 3, 6}, which is the additive inverse of the unwrapped set.

[0060] Consider again the example of multiplication 3 (mod 11) × 6 (mod 11) and looking only at columns 1 through 4. For the wrap-around remainder, 3 is represented by the one-hot vector 00010. 6 in the wrap-around remainder row corresponds to k=4, i.e., a rotation of 4. The product is then calculated by rotating 00010 4 bits to the right, i.e., 00100. This corresponds to k=2, so the result corresponds to either (in the unwrap-around row) +4 or (in the wrap-around row) 7. Determining which of these values ​​to choose is based on whether the operands are chosen from the unwrap-around or wrap-around rows: assign "0" to the unwrap-around selection and "1" to the wrap-around selection, and then you can perform an XOR NOT operation on the operand signs to select the result. In this example, both operands have a sign value of 1, so 1 XNOR 1 = 1, thus selecting the wrap-around value 7, which is the correct result. The reason for using the XOR NOT operation is that the process takes a right-hand rotation (2... 5 to 2 9 (positive modulo of the power of), and replace them with the wrap-around complement of the modulo.

[0061] Using both wraparound and non-wraparound remainders offers additional advantages. One advantage is that the size of the rotation register is halved. Another advantage is that it eliminates the need to generate all values ​​for the primitive root, requiring only half. As discussed above, when using only non-wraparound remainders, the available prime numbers need to have the primitive root 2, but the ability to use both non-wraparound and wraparound negative remainders simultaneously expands the number of available prime numbers. This can be combined with... Figure 8 and Figure 9 The table of prime numbers 7 and 23 will be used to illustrate this.

[0062] Figure 8 and Figure 9 2 are shown respectively kA table of modulo 7 and modulo 23 values ​​(for unwrapped and wrapped remainders). The layout of these graphs is similar to... Figure 7 Similarly, but also includes the "Check" line below, which lists the sum of the unwrap remainder and the wrap remainder directly above it, to check if their sum is 7 or 23 respectively. From Figure 6 It can be seen that modulo 7 has primitive roots 3 and 5, and modulo 23 has primitive roots 5, 7, 10, 11, 14, 15, 18, 19, 21, 26, and 27. Neither of these has a primitive root 2, as shown below. Figure 8 and Figure 9 As shown in the remainder row, for modulo 7, the remainder repeats after 3 k values, and for modulo 23, the remainder repeats after 11 k values. Therefore, if only the unwrapped remainder is used, only half of the roots are available, but if the unwrapped / wrapped remainder values ​​(a set of numbers and their additive inverses) are used, this is sufficient.

[0063] For such roots, the multiplication process using unwrap and wrap remainders can be illustrated with the example of multiplying 3 (mod 23) × 6 (mod 23). Referring to the remainder row, operand 3 is represented by the one-hot vector 00000000100 in the unwrap row. Referring again to the remainder row, the second operand 6 is located in the unwrap remainder row and is represented by the rotation k = 9. The product is then calculated by rotating 00000000100 to the right by 9 bits, resulting in 00000010000, which corresponds to 18 or (wrap) 5. Similarly, the sign encoding using "0" for unwrap and "1" for wrap can be selected by XORing the sign values: 0 XOR 0 = 0, so 18 is selected, which is the correct result. In the case of non-2 primitive roots, XOR (instead of XOR NOT) is used because Figure 9 The wrap-around complement of the module on the left side of the table represents the "true" unwrap-around module value on the right side.

[0064] This technique also supports using some (but not all) primes that do not have the primitive root 2, thus supplementing the primes that do have the primitive root 2, and allows the use of more smaller primes. However, this is not possible for all primes that do not have the primitive root 2. Figure 10 The table is duplicated Figure 6 The table is provided, but newly added prime numbers are highlighted.

[0065] Figure 10The primitive roots of prime numbers less than 100 are listed, with additional available prime numbers that do not have a primitive root of 2 highlighted. As highlighted in the figure, the newly added prime numbers are 7, 23, 47, 79, and 97. However, not all prime numbers possess this property; for example, 17. Using 6 digits or less of available prime numbers, the dynamic range M = 2 x 3 x 5 x 7 x 11 x 13 = 30,030 = 1.83 x 2^14. Using up to 7 digits, the dynamic range M = 2 x 3 x 5 x 7 x 11 x 13 x 19 x 23 x 29 = 380,570,190 = 1.42 x 2^14. 28 When extended to a maximum range of 8 bits, M = 2 x 3 x 5 x 7 x 11 x 13 x 19 x 23 x 29 x 37 x 47 x 53 x 59 x 61 = 1.26 x 10 17 = 1.75 x 2 56 Therefore, the RNS implementation method can support the multiplication of fairly large numbers using relatively small circuits.

[0066] Figure 11A and Figure 11B Provided the addition of smaller prime numbers 2 k The values ​​(for both unwrap and wrap-around remainders) are smaller primes that can be used in this process, specifically modulo values ​​of 5, 11, 13, 19, and 29.

[0067] The following discussion considers embodiments of circuits for implementing the aforementioned remainder system multiplication technique. Specific embodiments include cross-switch-based multiplication circuits that are both scalable and efficient. Compared to prior art modular multiplication circuits, such as combinational multipliers or Wallace tree multipliers, the cross-switch-based approach provides smaller and more energy-efficient circuitry.

[0068] Figure 12 An example of a barrel shifter implemented efficiently using a crossbar switch is shown. A barrel shifter is a digital circuit that can shift a data word by a specified number of bits without using any sequential logic, and can be used to illustrate a relatively simple implementation of a crossbar switch circuit as an introduction to the remainder system crossbar switch multiplication unit presented further below. Figure 12The example is a 4×4 example, where the input (x0, x1, x2, x3) is a one-hot vector (i.e., one entry is "1" and the rest are "0"), the shift count is 0 to 3, and the output (y0, y1, y2, y3) corresponds to the input shifted (modulo 4) by the shift amount. The shift count is received at decoder 1201, which converts the shift count into another one-hot vector specifying a shift of 0, 1, 2, or 3. The barrel shifter is a square switch array (4×4 in this example) connected between the input vector (x0, x1, x2, x3) and the output vector (y0, y1, y2, y3) and controlled by the shift value. The shift value travels diagonally upwards through the array and loops back from the bottom. For example, switch 1203 connects input x0 to output y3 and controls it via a shift of 3, such that input (1, 0, 0, 0) becomes output (0, 0, 0, 1) in response to shift 3. In the example of switch 1205, this switch connects input x3 to output y1 and controls it via a shift of 2, such that for shift 2, input (0, 0, 0, 1) becomes output (0, 1, 0, 0). Note that in Figure 12 In the arrangement, the input range from left to right is x0 to x3, and the shift and output indices increase from bottom to top.

[0069] The array structure of crossbar switches can be quite dense, similar to DRAM devices. For RNS multiplication, for a modulus n, multiplier optimization based on the unwrap / wrap method does not use an (n-1)×(n-1) array, but can instead reduce it to a (n-1) / 2×(n-1) / 2 array, saving 75% of area. By using a single gate for each switch, the circuit can be not only fast but also small in size (e.g., by using a single NMOS pull-down device). Although the array size increases with n... 2 Growth is possible, but this can be mitigated using a wraparound-based "folded" cross switch arrangement, for example, in conjunction with the following... Figure 14 and Figure 15 As described below, crossbar switches may also produce degraded logic "1" output levels when using only NMOS transmission gates, but the level recovery circuit presented below can overcome this problem.

[0070] Figure 13 The wraparound remainder and non-wraparound remainder (the wraparound value is the additive inverse of the non-wraparound value) are shown for an example of a modulus of 13 when a negative remainder is used. Figure 13The modulo-13 table of the diagram is repeated, but remainders greater than 6 are replaced with negative values: for example, -1 replaces 12, -2 replaces 11, and so on. In this arrangement, the wraparound value (wrap=1 row) is the modulo additive inverse of the non-wraparound value (wrap=0 row). Note that in this arrangement, the wraparound bit is not always the same as the sign bit; for example, when k=3 columns, wrap=0 has a value of -5, and wrap=1 has a value of +5. This distinction will be discussed in more detail below.

[0071] Figure 14 and Figure 15 The implementations of the modulo-13 multiplication circuit as a full cross-connect circuit and a folded, split cross-connect circuit are illustrated schematically, respectively. Figure 14 In the full crossbar switch implementation, the input vector is an (n-1)-component one-hot input vector, and the rotation amount is an (n-1)-component one-hot vector, thus obtaining a value of (n-1). 2 The cross-switch multiplier avoids a large (n-1) component one-hot output vector. Figure 14 It shows Figure 13 The example for n=13 uses negative and positive values ​​corresponding to the wraparound=0 and wraparound=1 values ​​when k=0 to 5.

[0072] To reduce the size of the cross array, a folded split cross array can be used, where only wrap-around values ​​(k=0 to 5) are used. In this case, the cross array is folded because the product is used only between + / - 1, 2, 3, 4, 5, and 6, and it is also split because the array is divided into wrap-around and non-wrap-around halves, and the output is divided between wrap-around and non-wrap-around values. This reduces the array size to ((n-1) / 2). 2 Or ¼ of the size of a full cross switch. With n=13, the values ​​used are 1, 2, 4, -5, 3, and 6, but the signs need to be adjusted for the details described below.

[0073] Further consideration Figure 14 Full cross switch and Figure 15 In a folded, split-type cross switch, in a full cross switch implementation, each non-zero value of the two inputs has a corresponding input line after decoding. In a folded cross switch implementation, one or more input lines for each input are shared by a pair of input values, where additional information (e.g., sign or wraparound value) is used to distinguish the value pairs of the shared input lines. Figure 15 As shown and used in the discussion below, "folded" refers to the case where the input is completely folded or folded in half, so each input line of the two inputs is shared by the two non-zero inputs. (For the handling of zero inputs, see example...) Figure 29A and Figure 29BHowever, as an alternative embodiment, a moderate degree of folding can be used, where less than all input values ​​are paired. The cross switches are separate because a portion of the array corresponds to the wrapped-back values ​​and a portion corresponds to the unwound values.

[0074] Using a folded, split-type crossbar switch implementation will reduce the size of the required crossbar array from (n-1). 2 Reduced to ((n-1) / 2) 2 (i.e., one-quarter the size), thus requiring less space on the logic chip. Although the size of the cross array is reduced to one-quarter of its original size (e.g., combined with...) Figure 29A and Figure 29B (As described), but additional circuitry is still required to manage the input sign values. Therefore, for smaller modulo numbers, a full cross switch implementation may occupy less area than a folded split cross switch implementation. For example, in an RNS arithmetic unit, the optimal implementation might use a full cross switch for modulo 5 and below, and a folded split cross switch for modulo 7 and above.

[0075] Figure 16 This shows how, for the example n=13, the size of the remainder table is reduced to only (n-1) / 2 entries. The value after the reduction is... Figure 15 In the embodiment of the folded split cross switch, the values ​​used for input, wherein the wraparound or sign value is processed by additional logic circuitry, Figure 17B An example of this logic circuit is shown.

[0076] Figure 17A and Figure 17B An embodiment of a split-fold cross-switch multiplier circuit for the example of n=13 is presented, where the two figures illustrate different parts of the same circuit. The circuit includes a cross-switch barrel shifter for calculating the product amplitude and circuitry for calculating the product wrap-around value, where the amplitude and wrap-around value together give the final product value. Approximately half of the cross-switch cells (cells with black fill diagonally from the lower left to the upper right, such as 1711 and 1717) calculate the wrap-around condition, indicating that operand A has wrapped around from the end of the barrel shifter by the rotation of operand B. The other cross-switch cells (cells without fill diagonally above and below, such as 1713 and 1715) represent products that have not wrapped around from the end of the barrel shifter.

[0077] The cross-array inputs of operands A and B are received in amplitude form. If a suitable one-hot vector format has not yet been adopted (e.g., from a previous operation of that format), these inputs are transformed in decoder A 1703 and decoder B 1701, respectively. These inputs can then be applied to the cross-array, as described above. Figure 15As described. However, in a folded split arrangement, the outputs of the wrap-around switch and the unwound switch in each row remain separate in each row to determine the product wrap-around value. For example, in the top row, the output of the wrap-around element 1711 goes into the lower output line of the first row, while the output of the unwound element 1713 goes into the upper output line of that row. Similarly, in the third row, the wrap-around switch 1717 goes into the lower line, while the unwound switch 1715 goes into the upper line. (Since the bottom row only has the unwound value, it has only one output.) When the output of the barrel shifter reaches Figure 17B Subsequently, the paired outputs from each row of the barrel shifter are fed into one of the corresponding OR gates 1721, such that the combined result is "1" if the output on any one line is "1". This produces an output in one-hot vector format. In this unwrap / unwrap n=13 embodiment, the different components correspond to the values ​​1, 2, 4, 5, 3, 6 shown, where no OR gate is needed for the bottom row since all elements in the bottom row are non-folded. At this point, the product magnitude is in one-hot vector format, and if the magnitude is not kept in this format (e.g., for subsequent operations), the corresponding one of the AND gates 1725 receives these values. The second input of each AND gate is the corresponding value represented by a 4-bit decimal value, i.e., 4'd1 is 1 in format (0001). Here, the value used is n=13, requiring 4 bits to represent 13 as a binary number. The combined output of the AND gates 1725 is then the magnitude of the product.

[0078] A series of AND gates 1723 form part of a product wraparound determination circuit. Each of these AND gates receives the output of a corresponding OR gate 1721 and its one-hot vector value, as well as another input corresponding to the lower line of that row. The output of AND gate 1723 is then input to OR gate 1733, such that if either output of AND gate 1723 is "1", the OR gate provides a "1" for the wraparound selection value. In the folded embodiment, operands A and B also have wraparound inputs in addition to the amplitude input. The wraparound bits of operand A and operand B are inputs to XOR gate 1731, whose output is then combined with the wraparound selection value in XOR gate 1735 to generate the product wraparound output value. Alternatively, Figure 17B The circuit can be replaced with Figure 29B The circuit is shown below.

[0079] Figure 18An NMOS-only cross-switch shifter circuit implementation that can be used in some embodiments is illustrated. By using a single NMOS for each element of the cross-switch shifter array, such as an NMOS 1801 connected between the input of operand A[0] and the output Out[0] with its control gate connected to operand B[0], the array size can be used in a smaller area than the NMOS / PMOS transmission gate implementation. The cross-switch circuit array device can be implemented using any semiconductor technology, including but not limited to planar transistors, finFET transistors and ribbonFETs, gate-all-around (GAA) transistors, or nanowire or nanosheet transistors.

[0080] Further consideration Figure 18 The NMOS implementation in the code and the NMOS 1801 are discussed. When A[0] is at ground level or logic "0" and B[0] is at logic "1" or V... DD At that time, Out[0] will also be at ground level, so it will definitely be "0". However, when both A[0] and B[0] are V DD When the value is "1", Out[0] will not be all V. DD Value; conversely, if the threshold voltage of the NMOS 1801 is V th Then Out[0] will be downgraded to V. DD -V th And "weak" "1" logic values. To maintain these logic values ​​as they propagate through the arithmetic unit, a level restorer is needed to restore the "1" logic value to a high logic level V. DD The strong "1" value.

[0081] Figure 19 An example of a level restorer circuit is shown. This circuit acts as an inverter, but has well-defined output logic values: "0" corresponds to ground, and "1" corresponds to V. DD This applies even to weak "1" inputs. When a "0" value or ground level is received, the PMOS 1903 turns on and the NMOS 1901 turns off, so the Out value is V. DD With all "1" logic levels, and because Out is high, the PMOS 1905 is off, and the input remains at ground. When a signal is received from V... DDWith a weak "1" input, the NMOS 1901 may not be fully turned on and the PMOS 1903 may not be fully turned off, causing the Out value to be pulled low to some extent, but not completely low to the well-defined ground level "0". Since Out is also connected to the gate of the PMOS 1905, this will cause the PMOS 1905 to be at least partially turned on, thus raising the In value and pulling Out completely to a strong "0" value at ground. While such level restorers will work with standard crossbar shifters, the situation is more complex for discrete crossbar arrangements.

[0082] Figure 20 An embodiment of a cross-connected level restoration circuit for use with the output of a split cross-switch multiplier is shown. Figure 20 On the left is part of a split cross switch 2001, showing four elements in a row. The rightmost input / SO0 (here, " / " is used to indicate NOT, shown as the horizontal line at the top of the name in the diagram) is unwrapped and connected to the output of / xbar, while the other three inputs are wrapped and connected to the inverted output of / (xbar_wrap). If these two outputs were independent, they could be leveled separately using level restoration circuits 2020 or 2025 (V... DD – V th The weak "1" value of ) is restored to full V. DD The logic level; however, these two values ​​are related because the gate selection for one output will always be invalid, resulting in a high-impedance output on the cross-switch output section. To correct these related output values, a cross-connected level restoration circuit is introduced, the implementation of which is shown, for example, in 2021.

[0083] Figure 20 The embodiment includes cross-connected pull-up elements to restore the low z state of both outputs. For the xbar output, at the input of level restoration circuit 2023, the gates of the pull-up elements of PMOS 2031 and 2033 are connected to the input and output of level restoration circuit 2025. For the xbar_wrap output, at the input of level restoration circuit 2025, the gates of the pull-up elements of PMOS 2035 and 2037 are connected to the input and output of level restoration circuit 2023. (The last sentence appears to be incomplete and possibly refers to a different implementation.) Figure 21 and Figure 22 The discussion is in Figure 20In this embodiment, PMOS 2033 and PMOS 2037, along with other pull-up PMOS transistors, can be weak devices relative to the transistors forming the inverters 2023 and 2025, and other components in the multiplication circuit. Circuit 2021 is required because the discrete cross-switch circuit is used to calculate two separate results using the same cross-switch circuit: the cross-switch is used to calculate the product magnitude, and the same cross-switch also generates a wrapback indication.

[0084] Further consideration Figure 20 Since the second input of the split cross switch is a hot vector, only one of S10, S11, S12, and S13 will be high, while the others will be grounded, thus only one column will be conducting. Therefore, if S10 is high, then S11, S12, and S13 will all be "0", the input / (xbar_wrap) will remain floating, and / xbar will be determined by / S00. Therefore, when S10 is high, if / S00=0, then / xbar="0"; if / S00=1, then / xbar is a weak "1", where, as discussed above, V DD The all-1 value will be downgraded or weakened to the reduced (V) DD -V th ) value, where V th This is the threshold voltage of the cross-connected NMOS switch. Similarly, since the cross-connected level recovery circuit 2021 is symmetrical between its inputs, if S10 is low, / xbar is in a floating state, and / (xbar_wrap) will be "0" or a weak "1" depending on the value of / S03, / S02, or / S01, specifically which of S11, S12, or S13 is in the on state. For a floating input, the cross-connected level recovery circuit 2021 will output "0" for "0" or a weak "1" at a non-floating input; and for a floating input, "0" or a weak "1" will generate (full V) respectively. DD The value is either "1" or "0". This operation is combined with... Figure 21 and Figure 22 Let me explain.

[0085] Figure 21 and Figure 22 They are shown respectively Figure 20 The cross-connected level restoration circuit embodiment is designed for operation with both "0" inputs and weak "1" inputs. Figure 21 and Figure 22In this context, the / (xbar_wrap) input is in a floating state, and the / xbar input is "0" or a weak "1", which corresponds to the case where S10 = "1". Due to the symmetry of the circuit topology between the / xbar and / (xbar_wrap) paths, for the case where S10 = "0", this value will be swapped between the upper and lower paths.

[0086] exist Figure 21 In the text, input / xbar="0" to make it like this: Figure 19 As discussed, the output of level restorer 2023 is xbar="1". When xbar="1", the pull-up PMOS of level restorer 2023 is off. Now consider the cross-coupled pull-up device and the / (xbar_wrap) path. Since / xbar="0" is the gate voltage of PMOS 2035, PMOS 2035 is on, the floating input of level restorer 2025 is now "1", making xbar_wrap="0", and the pull-up element of level restorer 2025 is also on. Since xbar="1", pull-up PMOS 2037 is off and does not function. PMOS 2031 now has its gate set to a high "1" level; it is off and does not affect the input of the top-path level restorer 2023.

[0087] For the PMOS 2033, since xbar_wrap is "0", it will also be in the ON state. However, compared to other transistors that set the / xbar level, the PMOS 2033 is formed as a weak device, such that even when it is ON, its output to the / xbar input of the level restorer 2023 is overridden by the "0" value provided by / S00 at the input. For example, the size of the PMOS 2033 can be adjusted to provide a low current when ON, as shown by the dashed arrow. Similarly, in Figure 20 In the symmetrical embodiment, PMOS 2037 will be a similarly weak device. (According to the embodiment, other pull-up PMOS may also be relatively weak devices.) Therefore, when / xbar="0" and / (xbar_wrap) is in a floating state, xbar is a strong "1" and xbar_wrap="0".

[0088] Figure 22 The case where / xbar is a weak "1" and / (xbar_wrap) is again in a floating state is considered. (This is combined with...) Figure 19 As discussed, the output of the level restorer 2023 will be xbar="0", where the return to the input PMOS (corresponding to Figure 19PMOS 1905 is on, pulling the input to a strong "1". Since / xbar is now a strong "1", PMOS 2035 is off; however, since xbar = "0", PMOS 2037 is on. However, because PMOS 2037 is a relatively weak device, this results in a weak "1" at the input of level restorer 2025, which is converted to a strong "1" by level restorer 2025, making the output xbar_wrap = "0". Therefore, PMOS 2031 is off and inactive, while PMOS 2033 is on, further amplifying the "1" at / xbar. Thus, when / xbar is a weak "1" and / (xbar_wrap) is floating, xbar = "0" and xbar_wrap = "0".

[0089] Because the cross-connected level restoration circuit 2021 is symmetrical, when / (xbar_wrap) = "0" and / xbar is floating, xbar_wrap is a strong "1" and xbar = "0"; when / (xbar_wrap) is a weak "1" and / xbar is floating, xbar_wrap = "0" and xbar = "0". In this way, the circuit 2021 will return "0" for floating inputs that are to be ignored, while acting as a level restorer for valid inputs, returning a strong "1" for "0" inputs and "0" for weak "1" inputs.

[0090] Figure 23 It is used to show Figure 20A flowchart illustrating the operation of an embodiment of a cross-connected level restoration circuit is provided. At 2301, the cross-connected level restoration circuit 2021 receives a first input and a second input (e.g., / xbar and / xbar_wrap), where either of these inputs can be valid, while the other is invalid. The invalid input is floating, while the valid input is either a low logic value ("0") or a degraded high logic value ("weak "1"). At 2303 and 2305, corresponding outputs for the two inputs are generated. For the valid input, at 2303, the corresponding output is generated by the level restoration circuit 2023 or 2025 of the valid input, resulting in a full high logic level ("1") for the low logic level input or a low logic level ("0") for a degraded high logic input. The level-biased cross-connected pull-up transistors (e.g., PMOS 2031, 2033, 2035, 2037) on the path of the valid input then set the output corresponding to the invalid input to a low logic level. Although this paper presents it as a split-fold cross-switch circuit for modular multiplication, it can be applied to similar circuits, such as modular adders and other arithmetic circuits. More generally, a cross-connected level recovery circuit can be used when a row of logic circuits provides a pair of correlated outputs for two subsets of switches (where only one subset is active at a time).

[0091] Figure 24A and Figure 24B A portion of an embodiment of a split-folded cross-switch multiplier circuit for an example of n=13 is shown. Relative to Figure 17A , Figure 24A The switches in the array use NMOS, and a cross-connected level recovery circuit and 0 detection are added. More specifically, in the discrete cross-connected array, Figure 17A Each switch is now implemented as a single NMOS, such as a finFET, ribbonFET, gate-all-around (GAA), or nanowire or nanosheet transistor. For 0 detection, there are (p+1) / 2 second inputs, and the size of the decoupled folded cross-switch multiplier circuit is (p-1) / 2 × (p+1) / 2. The operand B amplitude decoder now includes a 0-decoded value 2451. Each decoder now also has an NMOS switch in column 2453 with its gate connected to the 0-decoded value 2451. Zero decoding in the cross-switch ensures low impedance in one of the two sets of cross-switch outputs. Therefore, when operand B has a zero amplitude, each unwrapped output will be pulled high (e.g., V0). DD -V th ), which will then be converted to "0" by the subsequent level restorer 2443.

[0092] The 2443 cross-connected level restorer is connected to receive a pair of outputs for each row, thereby providing a well-defined logic output (i.e., ground level or V). DD (as mentioned above) Figure 23 As described above. Because the cross-connected level restorer 2443 also inverts its input value, each operand A input now receives an inverter 2441 to cancel out the inversion of the level restorer 2443. Figure 17A The bottom row of the shifter array discussed has all the unwound switches, allowing for the formation of a more conventional level restoration circuit 2445, such as... Figure 19 As shown. Alternatively, if a cross-connected level restorer is used at 2445, then to provide a 1-bit value for operand A, the value "1" (1'b1) can be provided as the second input, since this value will be invalid when the first input is valid. The output of level restorer 2443 can then be passed to the rest of the circuit, as shown. Figure 24B This is achieved as shown.

[0093] Figure 24B Repeated Figure 17B The components, numbered in a similar manner (e.g., XOR gate 1741 is now XOR gate 2431), have been modified with the addition of a three-input AND gate 2439. AND gate 2439 ensures that the output product sign is zero when either input source is zero. In other words, it is a three-input AND gate. One input is the output of XOR gate 2435, representing the output sign when both sources are non-zero. The other two inputs of AND gate 2439 have inverted inputs, meaning that these two inputs (operand A decoded 0, operand B decoded 0) must be invalid (logic 0) for the output sign bit in XOR gate 2435 to be passed to the output. If either of these inverted inputs is a logic "1" (indicating that one or both sources are equal to zero), the product sign will be forced to zero. Alternatively, Figure 24B The circuit can be replaced with Figure 29B The circuit is shown below.

[0094] All the cross-switch multiplier embodiments discussed so far have used wraparound-amplitude encoding. The embodiments below, however, consider sign-amplitude encoding instead. In folded multiplying cross-switches, the sign-amplitude encoding format can be implemented with less decoding than binary encoding because only a single decoding (for the amplitude) is required, instead of separately decoding (e.g., "1") and "12" from binary and then performing an OR operation. Furthermore, converting binary-encoded operands to and from sign-amplitude RNS encoding is easier than attempting to convert between binary and "wraparound"-amplitude encoding, because the "wraparound" bit has no standard meaning outside of RNS folded cross-switch multiplication, while the sign bit does. Figure 16 and Figure 25Examples of remainder tables are provided, which can be used to illustrate the conversion of the input sign bit to a wraparound bit.

[0095] Figure 16 and Figure 25 These are the remainder tables for the wraparound-amplitude formats of modulo 13 and 23 multiplication, respectively. Figure 16 In the text, the value "-5" / "5" is in bold to indicate that the sign bit is not equal to the wraparound bit. Figure 25 In the diagram, columns with a lighter background indicate a remainder where the sign bit is not equal to the wraparound bit. Therefore, when decoding the input, if the input matches an entry where the sign bit and wraparound bit are different, a "flip" bit can be set to perform an XOR operation with the sign bit. Since decoding (including the special case of zero) is one-hot vector decoding, the multiplier can be implemented as an NMOS network (with level recovery) to perform this logic OR function, or as a full CMOS circuit using one-hot inputs. Figure 26 and Figure 27 Examples of these two implementation methods are shown.

[0096] Figure 26 and Figure 27 Examples of sign-to-wrap-over switching are shown for both the NMOS (with level recovery) and CMOS embodiments for a modulo-13 example, where the MOSFET can also be implemented in a FinFET embodiment. Return to Reference Figure 16 Considering the wraparound = 0 row, the only negative value is for the value of 5, while all other values ​​(and the undisplayed value of 0) are non-negative. To perform a sign-to-wraparound transition in the NMOS embodiment, input 5 pulls the output ( / flip) low to ground, while other input values ​​pull the output high to V. DD – V th To restore the complete logic value, level restorer 2601 converts the output / flip to flip, so that in an NMOS (with level restoration) implementation, the inverted input can be used to de-invert. For CMOS embodiments, such as... Figure 27 As shown, the inverted value of 5 is used to provide the gate voltage for the PMOS pull-up element, while other (non-negative) values ​​are applied to the corresponding gate voltages of the NMOS pull-down elements. Figure 27 In the CMOS case shown, no level restorer is needed to provide the final output toggle value because the logic value at the output is already defined and no level restore is required.

[0097] Figure 28An embodiment of a wraparound selection circuit for product wraparound-sign conversion is shown for a modulo-13 example. A cross-connected level recovery circuit for the cross array outputs is shown in the upper left, which are then used as inputs to the wraparound selection circuit to determine the product sign. In the NMOS embodiment, the wraparound selection circuit includes a determination circuit 2801, followed by a level recovery circuit 2803 similar to that described above, to provide well-defined logic values ​​for the wraparound selection outputs. Other embodiments may be CMOS-based, although these typically require a larger area and are more complex. Figure 28 The circuitry selects the final wrap-around bit for the multiplier circuitry to create the product sign bit based on the crossbar product output, and this circuitry can be expanded with the folded crossbar. When the product row matches the result, xbar or xbar wrap-around will be logic "1", while for all other product rows, xbar and xbar wrap-around will be logic "0". Xbar 5 is the unwrap-around output of the output value 5, and it is used (instead of xbar wrap-around 5) because the wrap-around bit of output 5 is different from the sign bit of output 5 (i.e., for modulo 13, +5 is wrap-around, while -5 is unwrap-around). The determination circuit 2801 also includes "0" decoding to ensure coverage of all product outputs.

[0098] Figure 29A and Figure 29B An embodiment of a folded split NMOS cross-switch multiplier for sign-amplitude format inputs is presented for an example of n=13, where the two figures illustrate different parts of the same circuit. Figure 29A Repeated Figure 24A The components include decoder 2901 for providing one-hot format operand B (when received as amplitude), and decoder 2903 for providing one-hot format operand A (when received as amplitude). The one-hot format version is optimal for chained (i.e., sequentially related) multiplication because it eliminates one-hot encoding / decoding with binary and does not require corresponding decoders (2901, 2903) when receiving one-hot format operands. Relative to Figure 24A , Figure 29A The embodiments include elements related to operand sign input. For operand B, the one-hot vector format input value is input to the sign-wrap circuit 2913, as follows: Figure 26 or Figure 27 As shown in the embodiment. Then, the sign-flipped value of the result of operand B and the sign value of operand B are input to XOR gate 2915. Similarly, for operand A, the input value in one-hot vector format and the 0 value from operand B are input to the sign-wrap circuit 2911, which can also be as follows. Figure 26 or Figure 27As shown in the embodiment. (The XOR gate corresponding to 2915 is located in...) Figure 29B (The operand A sign flips, the level restorer output, and XOR gate 2915 continue into the next step.) Figure 29B The circuit.

[0099] exist Figure 29B In, relative to Figure 17B OR gate 2921 and AND gate 2923 have the same corresponding functions as OR gate 1721 and AND gate 1725, respectively. If the output is provided in one-hot vector format (e.g., for subsequent multiplication), the product magnitude does not need to be used for AND gate 1723 encoded in binary format. The equivalent element of AND gate 1723 no longer exists, and OR gate 1733 is replaced by wraparound selection circuit 2925, where Figure 28 This is one embodiment of the wraparound selection circuit 2925. Both inputs of the OR gate 2921 are provided to the wraparound selection circuit 2925. The product sign value is generated by the XOR logic circuit 2927 and the AND logic circuit 2929, which receives the wraparound selection value from the wraparound selection circuit 2925. Furthermore, the XOR logic circuit 2927 also receives the output of the XOR gate 2915 for operand B and the output of the XOR gate 2917 for operand A, where the XOR gates have the sign value of operand A and inputs from the sign-wraparound circuit 2911 of operand A. The output of the XOR gate 2927 is then one of the inputs of the AND gate 2929, with additional inputs being the inverted values ​​when operand A is decoded to 0 and when operand B is decoded to 0. Then, Figure 29A and Figure 29B The synthesized output of the circuit shown is the product of the sign value of the product and the product of the one-hot vector format (if not including AND gate 2923) or the magnitude format (if AND gate 2923 is used).

[0100] Figure 29A and Figure 29B A folded split-type crossbar multiplier is presented for the case where the modulus has a primitive root of 2 (specifically, an example for modulo 13). Return to Reference Figure 11A It can be observed that for modulo 13, all remainders are unique, and there are corresponding representations for k = 0 to 11. For... Figure 10 The situation is different if one of the newly added prime numbers in the matrix does not have a modulus of 2. For example, modulo 23... Figure 9 It can be observed that all remainders are unique in the first half of the range (k=0 to 10). All remainders in the first half of the range (k=0 to 10) repeat in exactly the same order in the second half of the range (k=11 to 21).

[0101] In folded cross switches, the multiplication circuit uses only the first half of these remainders (i.e., for RNS-13, ...). Figure 29Aand Figure 29B The circuit uses a remainder range of -6 to +6 instead of 0 to 12. In RNS-13, as... Figure 11A As shown, a remainder of +8 is equivalent to a remainder of -5, therefore for any remainder that is negative in the top row (i.e., 8 or 5), the sign-wrap indicator is set to "1" otherwise to "0". Thus, for RNS-13, the sign-wrap indicator for input 5 is "1", and for all other inputs it is "0". For the case of non-primitive roots 2, for example for... Figure 9 The RNS-23 shown has a sign-wrap indicator of "1" for inputs 7, 5, 10, and 11, while the sign-wrap indicator for all other inputs is "0". Therefore, for the product output, the circuit can use a wrap-around sign that performs the same function as sign-wrap to recover the product sign.

[0102] To determine the final sign of the product with a modulus having a primitive root of 2, for Figure 29B In the RNS-13 example, in AND logic 2929, the product sign is determined as: Product sign = (sign A XOR sign - wrap around A) XOR (symbol B XOR symbol-wrap-B) XOR (product-wrap-symbol) XOR (product-wrap).

[0103] For moduli that do not have a primitive root 2 and whose remainders are unique in the first half of the table and completely repeated in the second half (such as RNS-23), there is no product wraparound: Product sign = (sign A XOR sign - wrap around A) XOR (symbol B XOR symbol-wrap-B) XOR (product-wrap-symbol).

[0104] Figure 30A and Figure 30B An embodiment for implementation is shown.

[0105] Figure 30A and Figure 30B An embodiment of a folded NMOS cross-switch multiplier with a sign-amplitude format input for the example of n=23 is presented, where the two figures illustrate different parts of the same circuit. Figure 30A and Figure 30B Layout and Figure 29A and Figure 29BSimilarly, but without showing equivalent elements for decoders A 2901 and B 2903 for input and decoder 2923 for output. The decoded operand A is provided to the cross array and symbol-wrap circuit 3011 (along with the 0 value of operand B) to provide the symbol-flipped value of operand A. The decoded operand B is provided to the cross array and symbol-wrap circuit 3013 to provide the symbol-flipped value of operand B, which, together with the symbol input of operand B, serves as the input to XOR gate 3015. The cross array is folded but not wrapped, so there is only one output per row, and it can be used as... Figure 19 The example shown is a standard level restorer.

[0106] Move to Figure 30B The sign-inverted value of operand A and the sign of operand A are both received at XOR gate 3017, and the output of this XOR gate, along with the output of XOR gate 3015, are received at XOR gate 3027. Relative to Figure 29B An equivalent circuit for OR gate 2921 is not needed because the array is not wrapped around. The third input of XOR gate 3027 comes from wrap-around-sign circuit 3025, which takes input directly from each row of the cross array. Figure 29B Similarly, the product sign is provided by AND logic 3029, which has the output of XOR gate 3027 and the inverted values ​​of operand A when decoded to 0 and operand B when decoded to 0 as inputs.

[0107] Compared to Figure 29A and Figure 29B Implementation examples, Figure 30A and Figure 30B The non-primitive root 2 embodiment does not have product wrap-around, and therefore also lacks a split cross array (because there is no product wrap-around) and a cross-connected level recovery (because there is no split cross array), allowing the use of more conventional level recovery circuitry. Therefore, in this embodiment, the non-primitive root 2 circuit may be simpler than the primitive root 2 circuit. The non-primitive root 2 must meet the following criteria: the first half of the modulus table must have unique values ​​that represent exactly half of the remainder; the second half of the table must completely repeat the first half in the same order.

[0108] Figure 31 Based on Figure 17A , Figure 17B , Figure 24A , Figure 24B , Figure 29A , Figure 29B , Figure 30A and Figure 30B The flowchart of the embodiment of the modular multiplication method is shown, wherein... Figure 29A and Figure 29B Will be used for rendering Figure 31An exemplary embodiment of the steps is provided. Starting from step 3101, a first modulo p input number is received in a sign-amplitude format, where p is a prime number. For example, the first modulo p input number is used as operand A, the sign value is received at XOR gate 2917, and the amplitude is received at decoder 2903. However, if the amplitude has already been in one-hot vector format, the input can directly enter the inverter and sign-wrap circuit 2911 shown below decoder 2903. In step 3103, which can be performed simultaneously with step 3101, a second modulo p input number is received in a sign-amplitude format. For example, the second modulo p input number is used as operand B, the sign value is received at XOR gate 2915, and the amplitude is received at decoder 2901. However, again, if the amplitude has already been in one-hot vector format, the input can directly enter the switch array and sign-wrap circuit 2913.

[0109] In step 3105, the amplitudes of the first modulo-p input and the second modulo-p input are provided as... Figure 29A Folded split cross switch multiplier circuit and Figure 29B The magnitude of the product of the first modulo-p input number and the second modulo-p input number is determined by the corresponding first and second inputs of the OR gate 2921. In step 3107, the sign value of the product of the first modulo-p input number and the second modulo-p input number is determined based on the sign value of the first modulo-p input number and the sign value of the second modulo-p input number using XOR gates 2915, 2917, 2927 and the wraparound selection circuit 2925.

[0110] In the embodiments presented above, a dense NMOS folded discrete cross-switch circuit replaces the traditional modular multiplier. By using a regular NMOS cross-switch structure, the area required for a wide variety of RNS modules is significantly less than that required by a traditional modular multiplier. Specifically, such embodiments: eliminate the need for combining multipliers or adders, and eliminate the need for division to obtain remainders; use lookup tables to extend the available modules to the traditional 2^n modules. n 2 n -1 or 2 n Beyond +1 modulus and very small modulus; and requiring minimal additional logic—only a decoder and a small number of basic logic gates. The folded, discrete architecture reduces the area occupied in the cross switch by 75% compared to the "naive" (n-1)×(n-1) implementation of a (non-folded, non-discrete) cross switch. Using one-hot encoding in the cross switch reduces switching power compared to traditional modular multipliers. Furthermore, this approach expands the dynamic range of the multiplier by supporting certain non-"primitive 2" primes (e.g., 7, 23, 47, 79, 97 below 100).

[0111] To further improve efficiency and optimize the layout, Figure 29A and Figure 29B The embodiments utilize a regular 1D NMOS device array with one-hot inputs to implement wide logic OR operations or multiple decoding options; that is, this helps ensure that any remaining "glue" logic expands along with the main crossbar switch logic. Furthermore, the use of sign-amplitude encoding for RNS numbers improves RNS multiplication (compared to the unsigned binary encoding of the prior art). The use of a "cross-connected level recovery circuit" enables proper electrical operation of the discrete crossbar switch. These different features can significantly provide better area, power consumption, and performance, providing arguments for the use of signed-amplitude RNS encoding in GPUs, deep learning accelerators, autonomous vehicles, DSPs, vector and tensor processors, and CPUs.

[0112] To provide more context, Figures 32 to 35 More details are provided regarding the input sorting of the cross array and its relationship to the modulus with the primitive root 2. More specifically, Figures 32 to 34 Consider the case of modulo 13 multiplication, where Figure 32 and Figure 33 Consider a fully cross switch layout (e.g.) Figure 13 (illustrative representation), and Figure 34 Consider the layout of folded cross switches (e.g.) Figure 16 (Illustrative representation in Chinese). Figure 32 An RNS-13 all-nxn cross-switch multiplier is shown, where the input values ​​are arranged sequentially, and the two inputs from source 0 and source 1 are both in the range of 1 to 12. The array shows the synthesized RNS-13 products, as indicated by the highlighted output "1". These products have no regular pattern and cannot be extracted along the rows.

[0113] Figure 33 An RNS-13 all-n x n crossbar multiplier is shown, where the input values ​​are ordered modulo 2 powers (i.e., 1, 2, 4, ... in modulo p arithmetic), which is used in both the folded and non-folded embodiments presented herein. In the non-folded embodiment, all values ​​can be positive, and there is no need to use sign or wraparound values ​​to distinguish inputs and outputs as in the folded crossbar embodiment. Figure 33 In the modulo 2 power sort, the products are aligned row by row, making it easy to extract the product values.

[0114] Figure 34 The RNS-13 fully folded crossbar multiplier is shown, where the input values ​​are ordered modulo 2 powers. In this example, the crossbar array is "fully" folded because each input from source 0 and source 1 represents two inputs, and each output represents two outputs, where the value pairs for inputs and outputs are linked by additional information (such as those combined above). Figure 8 , Figure 9 as well as Figures 11A to 16The wraparound value or sign value described is used to distinguish them. Figure 34 The folding cross switch is Figure 33 This is an optimized-size array version of the full crossbar switch implementation, where the crossbar array size is ¼ of the original, but it does require additional circuitry to track the sign values. Therefore, for smaller modules, a full crossbar switch ordered by powers of 2 may require a smaller area, while for other larger modules, a folded, split crossbar array would be preferred. Thus, in some embodiments of the arithmetic logic unit, the first one or a few modules can be implemented non-folded, while the other modules will be implemented folded, split.

[0115] Return to reference combination Figure 6 and Figure 10 The primitive root 2 under discussion, Figure 33 and Figure 34 The method is applicable to prime numbers with the primitive root 2, and in the folded implementation, it is also applicable to some moduli that do not have the primitive root 2. Figure 35 This illustrates what happens when the modulus does not have a primitive root of 2 and an attempt is made to use it in a power-of-2 full-cross switch implementation. Figure 35 Consider the example of power-of-2 source sorting for RNS-17. Given source 0 input, starting from the left, the values ​​are 1, 2, ..., 9, then restarting from 1. The same applies to source 1 input values ​​and products, resulting in missing and duplicate source and product values ​​when applying power-of-2 sorting to the entire array without a primitive root of 2.

[0116] Figure 36 A block diagram is shown illustrating a folded and non-folded cross-switch embodiment for RNS multiplication using a power-of-2 ordering. Input sources 0 and 1 are initially received, and if ordered sequentially or otherwise by a power of 2, they are then ordered at the corresponding source decoders 3601 and 3603. In addition to the above... Figure 29A and Figure 29B or Figure 24A and Figure 24BIn addition to the described input decoding, decoders 3601 and 3603 also arrange the inputs in a power-of-2 order, where these inputs can be in a folded or non-folded format, and then these inputs are applied to a cross array 3605. This cross array will accordingly be a full (p-1)×(p-1) array (for non-zero values), a folded split ((p-1) / 2)×((p-1) / 2) array (for non-zero values), depending on the embodiment. For a non-folded cross array, the output will be non-folded, while for a folded embodiment, the output will include the sign (or wraparound) value and the amplitude. If a folded format is used, an unfolding circuit 3607 is included for the final output. Some embodiments may also be "partially" folded, where some but less than all of the inputs are folded and shared by two non-folded inputs, which are folded into signal amplitudes distinguished by sign or other distinguishing values.

[0117] Return to reference Figure 29A and Figure 29B The embodiments correspond to the folded, separate embodiments, and Figure 29A The size of the non-zero portion of the cross-array is ((p-1) / 2)×((p-1) / 2), and the size of the input is ½(p-1). (If zeros are included, the size is ((p-1) / 2)×((p+1) / 2), and the size of the second input is ½(p+1).) Then, Figure 29B The circuit corresponds to the unfolding circuit 3607. In the complete (i.e., non-folding) embodiment, relative to Figure 29A The size of the (non-zero) portion of the cross-array is (p-1) × (p-1), and the size of each input is (p-1). Furthermore, the cross-connected level restorer 2443 can be replaced with, for example... Figure 19 The standard level restorer shown. About Figure 29B Since the operands and outputs are no longer folded, these components are not required in the fully cross-switch embodiment. In folded and fully cross-switch arrangements, the cross array connections represent the topology of the switch connections, but the actual layout on the die may be arranged differently, and the wiring will also change accordingly.

[0118] The above discussion has already considered the folded RNS cross switch multiplication unit. The following discussion presents an embodiment of the folded RNS cross switch adder unit. More specifically, an embodiment is proposed for an adder unit that adds two selected numbers modulo n in a fast and efficient manner. Addition can be implemented using a dense NMOS “folded split” cross switch. This method bypasses both two-dimensional lookup tables and full-size cross switch adders (which do not scale well with n) and slower non-{2}... n 2 n -1, 2 n Adder. Figure 37 An example of such an existing technology adder is shown.

[0119] Figure 37 This is a block diagram of an example of a modulo-13 RNS adder. X and Y are two inputs, with a fixed value of 3. The value 3 is chosen based on the modulo-13 example because 13 + 3 equals the next 2. n The power of 16 or 2 4 , where n is the number of bits used to represent the modulus in binary. For example, for modulo 7, the fixed input will be 1, because 7 + 1 = 2. 3 For modulo 19, the fixed input will be 13, because 19 + 13 = 2. 5 The values ​​of X and Y are input into the carry-propagate adder (CPA) 3701, and X, Y, and 3 are input into the carry-save adder (CSA) 3703 to compute X+Y and X+Y+3 in parallel. The X+Y+3 output of CSA 3703 is then input into CPA 3705. The multiplexer MUX 3707 receives the outputs of CPA 3701 and CPA 3705, as well as the carry output value Cout from CPA 3705.

[0120] If X+Y+3 has no carry, then X+Y<13 (X+Y in the modulo-13 bit set), and the MUX 3707 selects the output of the CPA3701. If X+Y+3 does have a carry, then X+Y ≥ 13, so 13 needs to be subtracted to calculate the correct modulo-13 sum. Subtracting 13 can be achieved by adding X+Y+3-16, where X+Y+3 comes from the output of the CSA 3703, and -16 is naturally generated since the adder is only a 4-bit adder.

[0121] Figure 37 The required area for a 13-bit adder is: one 4-bit carry-holding adder; two 4-bit carry-propagating adders; and one 4-bit multiplexer. More generally, the number of bits will be k, where 2k k It is the smallest power of 2 greater than the modulus, so the area will increase with log2 of the modulus.

[0122] For multiplication circuits, the embodiments presented above propose a method for non-2... k or 2 kA folded cross-switch multiplier circuit with a modulus of -1 width. The folded cross-switch multiplier uses a sign-amplitude input instead of a direct binary input. By providing embodiments of low-power, low-area sign-amplitude modulus adders, the folded cross-switch adder can be combined with the folded cross-switch multiplier to form a low-power, low-area multiply-accumulate (MAC) unit.

[0123] Figure 38 and Figure 39 The implementations of the modulo-13 adder circuit as a full cross-connect circuit and a folded split cross-connect circuit are illustrated schematically, respectively. Their arrangement is similar to... Figure 14 and Figure 15 (It schematically illustrates the implementation of a signed modulo-13 multiplication circuit.) Similar, but with different input and output arrangements, and different details regarding the crossbar separation method. For Figure 38 The fully crossbar switch takes n=13 values ​​as its first operand at the top, arranged in ascending order from right to left; n=13 values ​​as its second operand at the bottom left diagonal, arranged in descending order from top to bottom; and outputs n=13 sum values ​​at the left, arranged in descending order from top to bottom. Therefore, the size of the fully crossbar array is n. 2 .

[0124] In the folded, split implementation of the crossbar adder, the input and output ranges are now 0 to ½(n-1), i.e., 0 to 6 in the modulo 13 example. Remainders greater than 6 are replaced with negative values, so, for example, -1 is equivalent to 12, -2 is equivalent to 11, and so on, where negative numbers are the modulo inverses of positive numbers. The array is folded because the sum is 0 or + / - 1, 2, 3, 4, 5, 6; the array is split because the output is divided into a "left" and a "right". Therefore, the composite size of the folded, split crossbar adder embodiment is ((n+1) / 2). 2 Unlike the split-fold cross-switch multiplier circuit presented above, which restricts the modulus to certain prime numbers, the split-fold cross-switch adder circuit presented below can represent any modulus value. However, in practice, due to the requirement that all moduli must be pairwise coprime, the modulus will usually be odd.

[0125] Figures 40A to 40D This presents an addition table for modulo 13 examples when the input values ​​are folded. When folded, the non-zero input values ​​for each of the two inputs range from 1 to ½(n-1). Therefore, there are four combinations of + and - values ​​for the two inputs, such as... Figures 40A to 40D The four tables are shown. In each of the four addition tables, there exists a top triangle for the row output and a bottom triangle for the row output. Figure 40A and Figure 40BIn this case, the first operand (operand A) is negative (or 0). Figure 40C and Figure 40D In this context, operand A is positive (or 0). Figure 40A and Figure 40C In this context, the second operand (operand B) is positive in the bottom triangle and negative (or 0) in the top triangle. Figure 40B and Figure 40D In this case, the second operand is negative in the bottom triangle and positive in the top triangle.

[0126] Figure 41 It shows Figures 40A to 40D Folding of each addition table. Figures 40A to 40D Each of these includes a top triangle and a bottom triangle with the same sum of operand A input values, such that the top and bottom triangles can be combined into a rectangular arrangement to achieve a cross array, for example, as described below. Figure 44A and Figure 44B As discussed. Figures 40A to 40D As shown and combined Figure 42A , Figure 42B , Figure 44A and Figure 44B Further discussion reveals that, due to the different output values ​​in different rows, the input values ​​of operand B differ between the top and bottom triangles.

[0127] exist Figure 40A In the diagram, the second operand (operand B) is sorted in the bottom triangle from 1 to 6 (from smallest to largest). Figure 40B In the middle, the second operand (operand B) is sorted in the bottom triangle from -6 to -1 (from smallest to largest). Figure 40C In the middle, the second operand (operand B) is sorted in the bottom triangle from 6 to 1 (from largest to smallest). Figure 40D In this case, the second operand (operand B) is sorted from -1 to -6 (from largest to smallest).

[0128] exist Figure 40A In the top triangle, the second operand (operand B) is sorted from -6 to -1 (from smallest to largest). Figure 40B In the top triangle, the second operand (operand B) is sorted from 0 to 6 (from smallest to largest). Figure 40C In the top triangle, the second operand (operand B) is sorted from 0 to -6 (from largest to smallest). Figure 40D In the top triangle, the second operand (operand B) is sorted from 6 to 1 (from largest to smallest).

[0129] return Figures 40A to 40DThese figures also illustrate examples of calculations using these tables. This example uses -4 as operand A and -1 as operand B. Because operand A has a negative value, it will use... Figure 40A or Figure 40B The table. Figure 40B The bottom triangle contains the value of operand B as -1, so the sum can be determined by following the value of operand B diagonally upwards until it reaches column A of operands, where the value is (-1) + (-4) = -5, corresponding to the output in the second row from the bottom.

[0130] Consider the top triangle and the bottom triangle, when the sign of operand B is the same as the sign of operand A ( Figure 40A or Figure 40D Use the top triangle when operand B is 0 or the sign of operand B is different from the sign of operand A. Figure 40B and Figure 40C When using the top triangle, also use it. Otherwise, for each corresponding... Figures 40A to 40D Use a bottom triangle. Multiplexing of the operand B input value during folding can be combined with... Figure 42A and Figure 42B To illustrate.

[0131] Figure 42A and Figure 42B Tables are presented for multiplexing the top and bottom triangles of the operand B input for a folded split cross switch adder circuit. Figure 42A The columns in the table show the top triangle multiplexing of operand B for the input values. The top triangle values ​​of operand B range from 0 to 6, sorted ascendingly in column A and descendingly in column B. The top multiplexing is: select column A(0,1,2,3,4,5,6) = (OpA_Sign XOR OpB_Sign) OR Src1_Zero; otherwise select column B(6,5,4,3,2,1,0). For the bottom triangle, operand B ranges from 1 to 6, sorted ascendingly in column A and descendingly in column B. The top multiplexing is: select column A(1,2,3,4,5,6) = (OpA_Sign XOR OpB_Sign); otherwise select column B(6,5,4,3,2,1).

[0132] Figure 43 This is for the modulo 13 example. Figures 40A to 40D A schematic diagram illustrating how the upper and lower triangles are arranged in a folded, split-type cross switch adder layout. The top and bottom triangles are placed in a square array, with the top triangle located at the bottom right and the bottom triangle at the top left. In this embodiment, with... Figure 40B and Figure 40CThe middle portion of the addition table corresponding to the rows of "0" values ​​between the top and bottom triangles is placed along the top of the cross array. For the top triangle, the operand B values ​​are arranged according to... Figure 42A Multiplexing is performed in the order of columns A or B. For the bottom triangle, the operand B values ​​are multiplexed according to... Figure 42B The order of column A or column B in the data is multiplexed.

[0133] Figure 44A and Figure 44B This is an embodiment of a folded, split-type cross switch adder, wherein Figure 44A and Figure 44B They are two parts of the same circuit. Figure 44A and Figure 44B Adder circuit layout and Figure 29A and Figure 29B The multiplier circuit is similar and is also an NMOS-based embodiment for switching arrays. The input values ​​of operands A and B are received in sign-amplitude format. Operand A is received at decoder 4401, which converts the input to a one-hot vector format, and then this operand (inverted form) is applied to each column of the cross array. In this modulo-13 example, the value ranges from 0 to 6 (=(n+1) / 2). The amplitude of operand B is received in a similar manner at decoder 4403 to convert it to a one-hot vector format.

[0134] To explain Figures 40A to 40D The four addition tables, for the bottom and top input values ​​of operand B, are multiplexed in the corresponding multiplexers 4405 and 4407. For the bottom input multiplexer 4405 of operand B, as combined with... Figure 42B These multiplexers are selected as discussed. For the top input multiplexer 4407 of operand B, as combined... Figure 42A These multiplexers are selected as discussed. Examples of multiplexer circuits 4405 and 4407 are described below. Figure 47 As shown. The four combinations of the outputs of the multiplexing circuits 4405 and 4407 enable the cross switch circuit to cover... Figures 40A to 40DThe four combinations are as follows. The inputs of multiplexer 4405, starting from the top, are pairs of numbers: (1, 6), (2, 5), (3, 4), (4, 3), (5, 2), and (6, 1), which add up to the same value (7 in this case) in each case. The inputs of multiplexer 4407, starting from the left, are pairs of numbers: (0, 6), (1, 5), (2, 4), (4, 2), and (5, 1), which add up to the same value (6 in this case) in each case, as well as in the case of 3 unpaired or multiplexed numbers. The outputs of multiplexers 4405 and 4407 are applied diagonally upwards to the control gates of switches in the bottom (i.e., upper left) and top (i.e., lower right) portions of the array, respectively.

[0135] Each row's synthesized output line includes a top row output and a bottom row output pair, similar to... Figure 29A The top five rows. For example, in the bottom triangle, the gate of transistor 4413 receives the output of multiplexer 4405, which receives the values ​​1 and 6 of operand B, where transistor 4413 is connected between the value 0 of operand A and the bottom output of row 5. In the top triangle, the gate of transistor 4415 receives the output of multiplexer 4407, which receives the values ​​0 and 6 of operand B, where transistor 4415 is connected between the value 1 of operand A and the top output of row 5. Then, the top and bottom outputs of each row from 0 to 5 pass through the corresponding cross-connected level restoration circuit 4409, as described above. Figures 20 to 22 The discussion.

[0136] To determine the 0 output, the middle row (located at the top of the array) is a row of switches 4411 connected between the value of the (inverted) decoded operand A and the middle output. The control gates of the row 4411 receive the values ​​of the corresponding decoded operand B. Since the middle row has only one output, as shown... Figure 19 The single-input level restorer shown is used in the top circuit of level restorer 4409. Figure 44A The symbolic input of operand B is also shown, which is used for Figure 44B In the circuit.

[0137] Figure 44A and Figure 44B It is part of the same circuit, in which Figure 44B The final sum output is determined in sign-amplitude format. For illustration... Figures 40A to 40DThe four tables, each in the amplitude selection output multiplexer 4421, receive four inputs corresponding to the top and bottom pairs of two rows in the cross-array output, where these rows are paired from top to bottom as (0, 5), (1, 4), (2, 3), (3, 2), (4, 1), and (5, 0). The implementation of the four-input multiplexing circuit 4421 is as follows: Figure 48 As shown. Then, the hot-swappable output of the multiplexing circuit 4421 is converted into a summed amplitude format by the AND gate circuit 4423, as shown in the figure. Figure 29B The AND gate circuit 2923 is discussed. The sign of the sum is determined in the output sign circuit 4425, which has the operand B sign as input, the top row value T5:0, the middle value, and the bottom row value B5:0, wherein an embodiment of the output sign circuit 4425 is described below. Figure 50 As shown.

[0138] Figure 45 This is an embodiment of a folded, split-type cross switch adder, wherein operands are received in a one-hot vector format of amplitude, and the output is provided in a one-hot vector format. Therefore, Figure 45 Corresponding to Figure 44A and Figure 44B ,and Figure 30A and Figure 30B The multiplier corresponds to Figure 29A and Figure 29B The method is the same. Figure 45 Repeated Figure 44A and Figure 44B Many components are included, however, decoders 4401 and 4403 are not included because amplitude operands A and B are now provided in one-hot vector format. Similarly, AND gate 4423 is omitted because the sum's amplitude is also provided in one-hot vector format. When addition is performed using a cross-switch adder, a cross-switch multiplier, or a combination thereof (such as...), the following steps are taken: Figure 46A and Figure 46B When performing a series of operations (in a multiply-accumulate-add circuit), Figure 45 The embodiments may be useful.

[0139] Figure 46A and Figure 46B The diagram illustrates a NMOS cross-switch multiply-accumulate (MAC) implementation in a folded, split-type embodiment, where the inputs and outputs are in a sign-one-hot vector format. Figure 46A and Figure 46B Together they form a MAC unit; for example, this MAC unit can collectively serve as a module 13 RNS MAC unit in a certain stage of a neural network. Figure 46A It is a folded, separate cross switch multiplication circuit. Figure 46BIt is an adder used to accumulate multiplication values.

[0140] Figure 46A The multiplier 4601 is with Figure 30A and Figure 30B Modulo 23 example or (without input decoders 2901 and 2903 and output decoder 2923). Figure 29A and Figure 29B The modulo-13 example corresponds to the modulo-13 example. In Figure 46A In this context, the input uses a sign-one-hot vector format (e.g., from the previous stage), but if the input of operand A or operand B is received in a sign-amplitude format, it can include... Figure 29A The corresponding decoders (such as 2901 and 2903). The output of multiplier 4601 is a sign-only output, which is provided to... Figure 46B Adder 4603.

[0141] Adder 4603, etc. Figure 45 The arrangement shown, where the output of multiplier 4601 is used as... Figure 45 The operand B is input. The output of adder 4603 is received at buffer 4605, where the output (corresponding to the accumulated value) is looped back to adder 4603 to correspond to... Figure 45 The operand A is input. As multiplier 4601 produces additional multiplication results, adder 4603 adds this new result to the previously accumulated result in buffer 4605 to generate the sum sign value and sum magnitude for this stage. For example, if this output is the output of the final stage, it can be like... Figure 44B It converts the encoder to a sum amplitude format, similar to the AND gate circuit 4423.

[0142] Figure 47 and Figure 48 They were presented respectively Figure 44A Operand B-input multiplexers 4405, 4407 and Figure 44B Output multiplexer 4421 and Figure 45 and Figure 46B A schematic diagram of an embodiment of those multiplexers. The two source inputs, SrcIn0 and SrcIn1, are connected to the output node Out via an inverter 4705 through switches (here, NMOS transistors 4701 and 4703), respectively. For example, refer to... Figure 44A or Figure 45 For the topmost MUX 4405, the two input values ​​will be 1 and 6. Similarly, for the leftmost MUX 4407, the inputs will be 0 and 6. The selection of the two source inputs SrcIn0 and SrcIn1 is based on the corresponding selection signals Sel0 and Sel1 applied to the gates of switches 4701 and 4703, respectively, where combined Figure 42A and Figure 42B The table makes this selection. To obtain a well-defined output level, the gate of the PMOS 4709 is connected to the Out node, such that... Figure 19 As shown, if Out is low, a strong 1 is generated at the strong 0 input of Out.

[0143] Figure 48 An embodiment of a 4-to-1 multiplexer 4421 is shown, with row outputs T2, B2, T5, and B5 as multiplexed inputs. The top values ​​Out T2 and Out T5 are provided to the gates of PMOS 4811 and NMOS 4813 via corresponding NMOS switches 4801 and 4803. The bottom values ​​Out B5 and Out B2 are provided to the gates of PMOS 4815 and NMOS 4817 via corresponding NMOS switches 4805 and 4807. The selection is based on the signs of operands A and B; an XOR operation on these values ​​is equivalent to a valid subtraction of these values, applied to the gates of transistors 4803 and 4807; and the inverse of the XOR operation is equivalent to a valid addition of these values, applied to the gates of transistors 4801 and 4805.

[0144] Figures 49A to 49D The diagram illustrates the correspondence between different output choices for the modulo 13 example and the addition table when the input value is folded. Figures 49A to 49D The same four cases are shown again, corresponding to Figures 40A to 40D The four sign pairs are highlighted, but the different outputs when the sum is ±2 are shown in bold. Figures 49A to 49D The output is the corresponding combination (T2, B2), (B5, T5), (B5, T5) and (B2, T2).

[0145] return Figure 48 PMOS 4811 and 4815 are connected in series between the high supply voltage level and the input of inverter 4821, and NMOS 4813 and 4817 are connected in parallel between the ground level and the input of inverter 4821. The output of multiplexer 4421 is the output Out2 of inverter 4821. To provide a well-defined Out2 value, Out2 is connected to the gates of PMOS 4823 and 4825 for level restoration.

[0146] Figure 50 yes Figure 44B and Figure 45 A circuit diagram of an embodiment of the output symbol circuit 4425. (This is related to input / output multiplexing.) Figure 47 and Figure 48 Same, Figure 50The embodiment used for sign determination employs an NMOS device layout for density considerations. Each bottom row output of the cross array is applied to the gate of one of the NMOS 5003s, which are connected in parallel between the input of inverter 5007 and the inversion of the sign value Src1_Sign of source 1. Figure 44B and Figure 45 In this array, source 1 is operand B, and source 0 is operand A. Each top row output of the cross array is applied to the gate of one of the NMOS 5001s, which are connected in parallel between the input of inverter 5007 and a combination of the OR operation of Src1_Sign and the inverted AND operation of Src1_Zero and Src0_Sign. The input of inverter 5007 is also connected to a high logic level via NMOS 5005, whose gate is connected to the middle row output of the cross array. The sign value is then the output of inverter 5007, which is also applied to the gate of PMOS 5009 for level recovery.

[0147] Further consideration Figure 50 And return to reference Figures 40A to 40D The table shows the result with the opposite sign (inside the top triangle) to OpB_Sign. Figure 40C The case of SrcB = 0 on slide 1 is an exception. In this case, the sign of the sum (positive) is the same as the sign of operand B (positive, since sign(0) = 0). The output sign circuit 4425 adjusts the source input of the top NMOS device 5001 (corresponding to the top triangle to account for this case). The output sign circuit of the bottom triangle does not include the case of SrcB = 0 and is therefore unaffected. The output sign circuit 4425 is an inverting circuit and produces the inverted (or opposite) sign of any signal fed into the source input of the NMOS device.

[0148] The embodiments of the cross-switched adder circuit presented in this paper are proposed in the context of remainder systems, just as the embodiments of the cross-switched multiplier circuits proposed prior to the adder. In the case of the multiplier, the circuit can be applied to prime modulo numbers with primitive root 2 and combinations thereof. Figure 10 The additional prime numbers discussed. The adder circuit can be applied more broadly to all odd prime moduli, and also to non-prime odd moduli. The folded split cross-switch adder circuit can be applied to even moduli, but it needs to be adjusted because the number of rows in the top and bottom triangles are not equal; however, since the main application in this paper is an embodiment of the remainder system using prime moduli (or at least moduli without common factors), which are odd (except for the “degenerate” case of p=2), the even case will not be discussed further.

[0149] Returning to the application of multiplication, accumulation, and addition, Figures 51 to 53 Several topologies for accumulator implementations are presented. MAC is a common implementation in applications involving very large datasets, such as neural networks. To accommodate these large datasets, different implementations can use different degrees of parallelism. One approach is to use a sequential accumulation topology, such as... Figure 51 As shown in the embodiments. In Figure 51 In one embodiment, a single source S0 of the multiplication result is received at adder circuit 5101, where it is added to the current accumulated value in the accumulated result within accumulator 5141. Figure 46A and Figure 46B This arrangement is presented in which the output of multiplication circuit 4601 is received sequentially at adder 4603 (corresponding to adder 5101), and the accumulated result is accumulated in buffer 4605 (corresponding to accumulator 5141).

[0150] Figure 52 A spatial accumulation topology is illustrated, where computation is split into multiple channels executed in parallel. In this example, there are eight multiplication sources S0 to S7 of a modulo p channel, such as in an RNS implementation. Figure 45 The first set of adders 5201, 5203, 5205, and 5207 perform paired addition, followed by the second set of adders 5211 and 5213, and finally the last adder 5221. Figure 52 The number of stages of such adders in a tree will be based on the number of multiplication channels.

[0151] Figure 53 The combination is shown Figure 51 and Figure 52 The topology is accumulated sequentially based on the features. The tree of the first-level adders 5301, 5303, 5305, 5307, the second-level adders 5311, 5313, and the third-level adder 5321 is arranged according to... Figure 52 The corresponding level arrangement of the tree. (and) Figure 51 Similarly, the last-stage adder 5331 and accumulator 5341 are located in a loop to accumulate multiple sets of multiplication results received at S0 to S7.

[0152] Figure 54 Based on Figure 44A , Figure 44B , Figure 45 and Figure 46B The flowchart illustrates an embodiment of the modular addition method. At 5401, the first modulo p input number is received in sign-amplitude format. Figure 44A and Figure 45 In this context, the first input can correspond to operand A, where operand A can be received using a one-hot vector format (e.g., ...). Figure 45 (as shown), or decoded into this format in decoder 4401. Figure 46A and Figure 46B In the multiplicative summation embodiment, the first input may correspond to a value stored in buffer 4605. At 5403, the first modulo p input number is received in sign-amplitude format. Figure 44A and Figure 45 In this context, the first input can correspond to operand B, where operand B can be received in a one-hot vector format (e.g., ...). Figure 45 (as shown), or decoded into this format in decoder 4403. Figure 46A and Figure 46B In the multiplicative accumulation embodiment, the first input may correspond to the output of multiplier 4601.

[0153] At 5405, the magnitude of the sum of the first and second modulo-p inputs is generated as outputs in each row by providing the magnitudes of the first and second modulo-p inputs as corresponding first and second inputs to the cross-switch multiplier circuit, applying the first inputs to each column of the cross-switch array, and applying the second inputs diagonally to the control gates. Then, multiplexer 4421 determines the magnitude of the sum. At 5407, output sign circuit 4425 determines the sign value of the sum of the first and second modulo-p inputs based on the sign values ​​of the first and second modulo-p inputs.

[0154] The above embodiments present dense, NMOS-based implementations of folded cross-switch adder circuits that require a smaller area than conventional modulus adders for various RNS moduli. This extends the available moduli beyond the single-adder case, which requires 2 n or 2 n Modulus of form -1. For non-2 n or 2 n The -1 modulus, folded cross switch implementation is denser than existing "dual adder" designs. Compared to traditional modulus multipliers, the use of one-hot encoding in the cross switch reduces switching power. The adder implementation also expands the dynamic range of representable digital formats by allowing the use of any modulus. Furthermore, by working with sign-amplitude RNS multipliers, they can perform multiply-accumulate (MAC) operations in sign-amplitude RNS format.

[0155] Figure 55 This is a schematic block diagram of a computing system 5501 that can be used to implement various embodiments of the microprocessor described above. In one example, the computing system 5501 is a network system 5501. A particular device may utilize all or only a subset of the components shown, and the level of integration may vary from device to device. Furthermore, a device may contain multiple instances of components, such as multiple processing units, processors, memories, transmitters, receivers, etc.

[0156] The network system may include a computing system 5501 equipped with one or more input / output devices (e.g., network interfaces, storage interfaces, etc.). The computing system 5501 may include a central processing unit (CPU) 5510, memory 5520, mass storage device 5530, and I / O interface 5560 connected to a bus 5570. The CPU may include the components described above. Figure 1A and Figure 1B The microprocessor described. The computing system 5501 is used to connect to various input / output devices (keyboard, display, etc.) via I / O interface 5560. Bus 5570 can be one or more of several bus architectures of any type, including a memory bus or memory controller, peripheral bus, etc.

[0157] CPU 5510 can include any type of electronic data processor, including Figure 1B The microprocessor 120 includes a division circuit (such as any of the division circuits described above). The CPU 5510 can be used to implement any of the division-related schemes described herein using any step or combination of steps described in the embodiments. The memory 5520 may include any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), or combinations thereof. In embodiments, the memory 5520 may include ROM for use at startup and DRAM for storing programs and data for use during program execution.

[0158] Mass storage device 5530 may include any type of storage device for storing data, programs, and other information, and making such data, programs, and other information accessible via bus 5570. For example, mass storage device 5530 may include one or more of solid-state drives, hard disk drives, disk drives, optical disk drives, etc.

[0159] The computing system 5501 also includes one or more network interfaces 5550, which may include wired links (e.g., Ethernet cables) and / or wireless links connecting access nodes or one or more networks 5580. The network interface 5550 enables the computing system 5501 to communicate with remote units via the network 5580. For example, the network interface 5550 may provide wireless communication via one or more transmitter / transmit antennas and one or more receiver / receive antennas. In embodiments, the computing system 5501 is coupled to a local area network (LAN) or wide area network (WAN) for data processing and communication with other processing units, the Internet, remote storage devices, and other remote devices. In one embodiment, the network interface 5550 may be used to receive and / or transmit interest packets and / or data packets in an ICN. Throughout this document, the term "network interface" will be understood to include ports.

[0160] Figure 55 The components described in the computing system are those typically found in computing systems to which the techniques described herein are applicable, and are intended to represent a broad category of such computer components well known in the art. Many different bus configurations, network platforms, and operating systems can be used.

[0161] The techniques described herein can be implemented using hardware, firmware, software, or a combination thereof. According to this embodiment, the elements in the above embodiments may include only hardware or a combination of hardware and software (including firmware). For example, a logic element programmed by firmware to perform the functions described herein is an example of an element of the described multiplication circuit. The multiplication circuit may include a processor, FGA, ASIC, integrated circuit, or other types of circuitry. The software used is stored in one or more processor-readable storage devices to program one or more processors to perform the functions described herein. The processor-readable storage device may include computer-readable media, such as volatile and non-volatile media, removable and non-removable media. For example, but not limited to, computer-readable media may include computer-readable storage media and communication media. The computer-readable storage medium may be implemented in any method or technique for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media include RAM, ROM, EEPROM, flash memory or other storage technologies, CD-ROM, digital versatile disk (DVD) or other optical disc storage, magnetic tape cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible by a computer. Computer-readable media do not include propagating signals, modulated signals, or transient signals.

[0162] Communication media typically embody computer-readable instructions, data structures, program modules, or other data in the form of propagating data signals, modulated data signals, or transient data signals (e.g., carrier waves or other transmission mechanisms), and include any information transmission medium. The term "modulated data signal" refers to a signal in which one or more characteristics of the signal have been configured or altered in a manner to encode information within the signal. By way of example and not limitation, communication media include wired media such as wired networks or direct wired connections, as well as wireless media such as RF and other wireless media. Combinations of the foregoing are also included within the scope of computer-readable media.

[0163] In alternative embodiments, some or all of the software may be replaced by dedicated hardware logic components. Examples, but not limited to, illustrative types of hardware logic components that may be used include Field-programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Application-specific Standard Products (ASSPs), System-on-a-chip (SOCs), Complex Programmable Logic Devices (CPLDs), dedicated computers, and the like. In one embodiment, software implementing one or more embodiments (stored in a storage device) is used to program one or more processors. These one or more processors may communicate with one or more computer-readable media / storage devices, peripheral devices, and / or communication interfaces.

[0164] It should be understood that this subject matter can be embodied in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the subject matter thorough and complete and to fully convey the invention to those skilled in the art. In fact, this subject matter is intended to cover alternatives, modifications, and equivalents to these embodiments, which are included within the scope and spirit of the subject matter as defined by the appended claims. Furthermore, in the following detailed description of the subject matter, numerous specific details are set forth in order to provide a thorough understanding of the subject matter. However, it will be apparent to those skilled in the art that the subject matter can be practiced without these specific details.

[0165] This document describes aspects of the invention in conjunction with flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to generate a machine, such that the instructions, which execute via a processor of a computer or other programmable instruction execution apparatus, create mechanisms for implementing the functions / actions specified in the flowcharts and / or one or more block diagrams.

[0166] The invention has been presented for purposes of illustration and description, but it is not intended to be exhaustive or to limit the invention in any way disclosed. Many modifications and alterations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Aspects of the invention were chosen and described in order to better explain the principles and practical application of the invention and to enable those skilled in the art to understand the invention and the various modifications suited to the intended particular use.

[0167] For the purposes of this document, each process associated with the disclosed technology may be performed sequentially by one or more computing devices. Each step in the process may be performed by the same or different computing devices used in other steps, and each step is not necessarily performed by a single computing device.

[0168] Although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter as defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing the claims.

Claims

1. An adder circuit, characterized in that, include: Cross switch adder circuit, used for: Receive the amplitude of the first modulo p input in sign-amplitude format; The amplitude of the second modulo p input number is received in the aforementioned sign-amplitude format; The amplitude of the sum of the first modulo-p input and the second modulo-p input is determined based on the amplitude of the first modulo-p input and the amplitude of the second modulo-p input. The sign determination circuit is used for: The sign value of the first modulo p input number is received in the sign-amplitude format; The sign value of the second modulo p input number is received in the sign-amplitude format. The sign value of the sum of the first modulo-p input and the second modulo-p input is determined based on the sign value of the first modulo-p input and the sign value of the second modulo-p input.

2. The adder circuit according to claim 1, characterized in that, The cross switch adder circuit is a (p+1) / 2×(p+1) / 2 cross switch array.

3. The adder circuit according to claim 2, characterized in that: The switches are arranged in columns and rows; Each column of switches is connected between a corresponding amplitude of one of the first modulo p inputs and a different row output; The control gate of each of the switches is connected to receive the amplitude of one of the second modulo-p inputs.

4. The adder circuit according to claim 3, characterized in that, Also includes: The first plurality of multiplexers, each multiplexer is used to receive the amplitude of a corresponding pair of second modulus p inputs as input, and to apply a selected one of the corresponding pair of second modulus p inputs along the opposite diagonal of the top triangle of the switch array to the control gate of the switch; The second plurality of multiplexers, each multiplexer is used to receive the amplitude of a corresponding pair of second modulus p inputs as input, and to apply one of the corresponding pair of second modulus p inputs along the opposite diagonal of the bottom triangle of the switch array to the control gate of the switch.

5. The adder circuit according to claim 4, characterized in that: For each of the first plurality of multiplexers, the corresponding pair of second modulo p inputs are added to obtain a first identical value; For each of the second plurality of multiplexers, the corresponding pair of second modulo p inputs are added to obtain a second identical value.

6. The adder circuit according to any one of claims 2 to 5, characterized in that, The switch is an NMOS transistor.

7. The adder circuit according to any one of claims 2 to 6, characterized in that, The switch is implemented as one or more of a finFET transistor, a gate-all-around (GAA) transistor, or a nanowire or nanosheet transistor.

8. The adder circuit according to any one of claims 1 to 7, characterized in that, The first modulo-p input number is received as a binary encoded value, the second modulo-p input number is received as a binary encoded value, and the cross-switch adder circuit is further used for: The magnitude of the first modulo p input number is converted into a first binary value vector, wherein for non-zero values, one of the values ​​in the vector is 1, and the other values ​​in the vector are 0; The magnitude of the second modulo p input number is converted into a second binary value vector, wherein for non-zero values, one of the values ​​in the vector is 1, and the other values ​​in the vector are 0.

9. The adder circuit according to claim 8, characterized in that, The cross switch adder circuit is also used for: For a non-zero value of the second modulo p input number, a choice is made between a first input value and a second input value to input the second modulo p input number into the cross array.

10. The adder circuit according to claims 1 to 9, characterized in that, The addition circuit is one of a plurality of modular arithmetic units, each of which corresponds to a different modulus value, and each modular arithmetic unit is used to receive the corresponding component of the input value in the remainder format system.

11. The adder circuit according to any one of claims 1 to 10, characterized in that, Also includes: Multiple level recovery circuits, each level recovery circuit being used to receive two outputs of a row of the cross-switch adder circuit, one of the outputs being valid and the other being invalid, and providing the output of each row as a strong logic value.

12. The adder circuit according to any one of claims 1 to 11, characterized in that, p is an odd number.

13. The adder circuit according to any one of claims 1 to 12, characterized in that, Also includes: A buffer is provided for connection to the cross-switch adder circuit and for storing a determined amplitude of the sum of the first modulo-p input and the second modulo-p input, wherein the amplitude of the second modulo-p input is the stored determined amplitude.

14. A method for performing modulo p addition, characterized in that, include: The first modulus p input number is received in sign-amplitude format; The second modulus p input number is received in the aforementioned sign-amplitude format; The magnitude of the sum of the first modulo-p input and the second modulo-p input is determined by providing the magnitudes of the first and second modulo-p inputs as the corresponding first and second inputs of the cross-switch multiplier circuit. The sign value of the sum of the first modulo-p input and the second modulo-p input is determined based on the sign value of the first modulo-p input and the sign value of the second modulo-p input.

15. The method according to claim 14, characterized in that, Also includes: The determined magnitude of the sum is stored in a buffer; The determined amplitude of the sum stored in the buffer is provided as the amplitude of the second modulo p input.

16. The method according to claim 14 or 15, characterized in that, Also includes: The modulo-p multiplier circuit generates the first modulo-p input number.

17. The method according to any one of claims 14 to 16, characterized in that, p is an odd number.

18. The method according to any one of claims 14 to 17, characterized in that: Receiving the first modulo-p input number in the symbol-amplitude format includes: Receive the first modulo p input number as a binary encoded value; The magnitude of the first modulo p input number is converted into a first binary value vector, wherein for non-zero values, one of the values ​​in the vector is 1, and the other values ​​in the vector are 0; Receiving the second modulo-p input number in the symbol-amplitude format includes: Receive the second modulo p input number as a binary encoded value; The magnitude of the second modulo p input number is converted into a second binary value vector, wherein for non-zero values, one of the values ​​in the vector is 1, and the other values ​​in the vector are 0.

19. The method according to claim 18, characterized in that, Also includes: For a non-zero value of the second modulo p input number, a choice is made between a first input value and a second input value to input the second modulo p input number into the cross array.

20. The method according to any one of claims 14 to 19, characterized in that, Also includes: At each of the multiple level recovery circuits, two outputs of the corresponding row of the cross-switch multiplier circuit are received, one of which is valid and the other is invalid; Each of the level recovery circuits provides the output of the corresponding row as a strong logic value.

21. A multiply-accumulate circuit, characterized in that, include: A multiplication circuit is used to determine the product of the first modulo-p input number and the second modulo-p input number. Adder circuit, including: A buffer is used to store the output of the adder circuit; Cross switch adder circuit, used for: The multiplication circuit receives the magnitude of the product of the first modulo-p input and the second modulo-p input. Receive the stored output amplitude of the adder circuit from the buffer; Determine the magnitude of the sum of the product of the first modulo-p input and the second modulo-p input and the stored output of the adder circuit; The sign determination circuit is used for: The sign value of the product of the first modulo-p input number and the second modulo-p input number is received from the multiplication circuit; Receive the stored sign value of the adder circuit from the buffer; Determine the sign value of the sum of the product of the first modulo p input and the second modulo p input and the stored output of the adder circuit.

22. The multiply-accumulate circuit according to claim 21, characterized in that, Also includes: The multiplication circuit includes: Cross-switch multiplier circuit, used for: Receive the amplitude of the first modulo-p input and the amplitude of the second modulo-p input; The magnitude of the product of the first modulo-p input and the second modulo-p input is determined based on the magnitude of the first modulo-p input and the magnitude of the second modulo-p input. The sign determination circuit is used for: Receive the sign value of the first modulo-p input number and the sign value of the second modulo-p input number; The sign value of the product of the first modulo p input and the second modulo p input is determined based on the sign value of the first modulo p input and the sign value of the second modulo p input.

23. The multiply-accumulate circuit according to claim 21 or 22, characterized in that, The cross switch adder circuit is a (p+1) / 2×(p+1) / 2 cross switch array.

24. The multiply-accumulate circuit according to claim 23, characterized in that, The switch is an NMOS transistor.

25. The multiply-accumulate circuit according to claim 23 or 24, characterized in that, The switch is implemented as one or more of a finFET transistor, a gate-all-around (GAA) transistor, or a nanowire or nanosheet transistor.

26. The multiply-accumulate circuit according to any one of claims 21 to 25, characterized in that, The cross switch adder circuit is also used for: For a non-zero value of the amplitude of the product of the first modulo-p input and the second modulo-p input, a selection is made between a first input value and a second input value to input the amplitude of the product of the first modulo-p input and the second modulo-p input into the cross array.

27. The multiply-accumulate circuit according to any one of claims 21 to 26, characterized in that, p is a prime number.

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