Neural network generation

Abstract

Apparatuses, systems, and techniques for generating one or more neural networks. In at least one embodiment, a processor includes one or more circuits to generate one or more second versions of one or more second neural networks based at least in part on one or more first versions of the one or more second neural networks and one or more hardware resources to be used to perform the one or more second versions of the one or more second neural networks using one or more first neural networks.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for performing and facilitating artificial intelligence. For example, at least one embodiment relates to a processor or computing system for generating compressed neural networks according to the various new techniques described herein. Background Technology

[0002] Generating multiple versions of a neural network that will be executed by different platforms, computer systems, or any other hardware resources consumes significant time and computational resources because it requires knowledge of different types of platforms, computer systems, or other hardware resources. The amount of time and computational resources used to generate new or updated neural networks can be improved. Attached Figure Description

[0003] Figure 1 The illustration shows an example system for generating one or more neural networks executed by hardware resources, according to at least one embodiment; Figure 2 The illustration shows an example system for training one or more generator neural networks according to at least one embodiment; Figure 3 The illustration depicts an example process for generating one or more neural networks executed by hardware resources, according to at least one embodiment; Figure 4 The illustration depicts an example process for training one or more generator neural networks according to at least one embodiment; Figure 5 The illustration depicts an example process for fine-tuning one or more generator neural networks according to at least one embodiment; Figure 6 The illustration shows an example system for generating one or more neural networks executed by hardware resources, according to at least one embodiment; Figure 7 An example system is illustrated according to at least one embodiment for generating one or more neural networks executed by hardware resources using one or more application programming interfaces (APIs); Figure 8A The logic according to at least one embodiment is shown; Figure 8B The logic according to at least one embodiment is shown; Figure 9 The training and deployment of a neural network according to at least one embodiment are illustrated; Figure 10 An example data center system according to at least one embodiment is shown; Figure 11A An example of an autonomous vehicle according to at least one embodiment is shown; Figure 11B The illustration shows an embodiment according to at least one of the embodiments. Figure 11A Examples of camera positions and field of view for autonomous vehicles; Figure 11C This is an illustration based on at least one embodiment. Figure 11A A block diagram of an example system architecture for an autonomous vehicle; Figure 11D The illustration, according to at least one embodiment, is for one or more cloud-based servers and Figure 11A A diagram of a system for communication between autonomous vehicles; Figure 12 This is a block diagram illustrating a computer system according to at least one embodiment; Figure 13 This is a block diagram illustrating a computer system according to at least one embodiment; Figure 14 A computer system according to at least one embodiment is shown; Figure 15 A computer system according to at least one embodiment is shown; Figure 16A A computer system according to at least one embodiment is shown; Figure 16B A computer system according to at least one embodiment is shown; Figure 16C A computer system according to at least one embodiment is shown; Figure 16D A computer system according to at least one embodiment is shown; Figure 16E and Figure 16F A shared programming model according to at least one embodiment is shown; Figure 17 An exemplary integrated circuit and a related graphics processor according to at least one embodiment are shown; Figures 18A-18B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown; Figures 19A-19B Additional exemplary graphics processor logic according to at least one embodiment is shown; Figure 20 A computer system according to at least one embodiment is shown; Figure 21A A parallel processor according to at least one embodiment is shown; Figure 21B A partitioning unit according to at least one embodiment is shown; Figure 21C A processing cluster according to at least one embodiment is shown; Figure 21D A graphics multiprocessor according to at least one embodiment is shown; Figure 22 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated; Figure 23 A graphics processor according to at least one embodiment is shown; Figure 24 It is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment; Figure 25 A deep learning application processor according to at least one embodiment is shown; Figure 26 A block diagram of an example neuromorphic processor is shown according to at least one embodiment; Figure 27 At least a portion of a graphics processor according to one or more embodiments is shown; Figure 28 At least a portion of a graphics processor according to one or more embodiments is shown; Figure 29 At least a portion of a graphics processor according to one or more embodiments is shown; Figure 30 It is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment; Figure 31 It is a block diagram of at least a portion of a graphics processor core according to at least one embodiment; Figures 32A-32B The diagram illustrates thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core.

[0004] Figure 33 A parallel processing unit (“PPU”) according to at least one embodiment is shown. Figure 34 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated. Figure 35 A memory partitioning unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown; Figure 36 A streaming multiprocessor according to at least one embodiment is illustrated; Figure 37 This is an example data flow diagram of an advanced computing pipeline according to at least one embodiment; Figure 38 This is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment; Figure 39Example illustrations of an advanced computing pipeline for processing imaging data according to at least one embodiment; Figure 40A Includes example data flow diagrams of virtual instruments supporting ultrasound equipment according to at least one embodiment; Figure 40B Includes example data flow diagrams of virtual instruments supporting CT scanners according to at least one embodiment; Figure 41A A data flow diagram illustrating the process for training a machine learning model according to at least one embodiment is shown; and Figure 41B This is an example illustration of a client-server architecture that utilizes a pre-trained annotation model to enhance an annotation tool according to at least one embodiment; Figure 42 Components of a system for accessing a large language model according to at least one embodiment are shown. Detailed Implementation

[0005] In the following description, various technologies and systems are described. For illustrative purposes, specific configurations and details are presented to provide a thorough understanding of the possible ways in which the technologies can be implemented. However, it will be apparent that the technologies described below can be practiced in different configurations without specific details. Furthermore, well-known aspects may be omitted or simplified to avoid obscuring the technologies being described.

[0006] Figure 1 An example system 100 for generating one or more neural networks to be executed by one or more hardware resources is illustrated according to at least one embodiment. In at least one embodiment, system 100 is a combination of hardware and software, both of which are described herein. In at least one embodiment, system 100 includes a neural network training module 110 and a neural network generation module 120.

[0007] In at least one embodiment, as used in any implementation described herein, in Figures 1-42 Each of the terms described herein, such as “module” and nominalized verbs (e.g., neural network training module 110, neural network generation module 120, training module 230, training module 610, compressed neural network generation module 612, training data collection module 614, etc.), refers to any combination of software logic, hardware logic, and / or circuitry configured to provide the functions described herein, unless clearly or explicitly stated to the contrary from the context.

[0008] In at least one embodiment, throughout Figure 1-42The software described includes, individually or in any combination, operating systems, device drivers, application software, database software, graphics software (e.g., Radeon, Intel Graphics), web browsers, development software (e.g., integrated development environments, code editors, compilers, interpreters), networking software (e.g., Intel Proset, Intel Advanced Networking Services), simulation software, real-time operating systems (RTOS), artificial intelligence software (e.g., Scikit-learn, TensorFlow, PyTorch, Accord.NET, Apache Machout), robotics software (ROBEL, MS AirSi, Apollo Baidu, AWS RoboMaker, ROSbot 2.0, Poppy Project), firmware (e.g., BIOS / UEFI, routers, smartphones, consumer electronics, embedded systems, printers, solid-state drives (SSDs)), application programming interfaces (APIs), containerized software (e.g., Nginx, Apache HTTP Server, MySQL, PostgreSQL, Redis, Memcached, Node.js, Elasticsearch, GitLab, Jenkins, WordPress), and container orchestration platforms (e.g., Kubernetes, Docker Swarm, Apache Mesos, Nomad, Amazon). ECS, Microsoft Azure Kubernetes Service, Google Kubernetes Engine, Red Hat OpenShift, Rancher, or any other implementation that is embodied as a package, code, and / or instruction set.

[0009] In at least one embodiment, throughout Figure 1-42The described hardware includes, for example, hardwired circuit systems, programmable circuit systems, state machine circuit systems, fixed-function circuit systems, execution unit circuit systems, and / or firmware storing instructions executed by the programmable circuit system, either individually or in any combination. In at least one embodiment, the circuit system may be part of a larger system, such as an integrated circuit (IC), system-on-a-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), data processing unit (DPU), digital signal processor (DSP), tensor processing unit (TPU), accelerated processing unit (APU), application-specific integrated circuit (ASIC), intelligent processing unit (IPU), neural processing unit (NPU), smart network interface controller (SmartNIC), vision processing unit (VPU), field-programmable gate array (FPGA), etc.

[0010] In at least one embodiment, unless otherwise expressly stated, this applies throughout. Figures 1-42 The neural network described refers to one or more of the following: feedforward neural network, convolutional neural network (CNN), recurrent neural network (RNN), long short-term memory (LSTM) network, generative adversarial network (GAN), restricted Boltzmann machine (RBM), deep belief network (DBN), radial basis function network (RBFN), hopfield network, self-organizing map, perceptron with one or more layers, modular neural network, spike neural network, deep reinforcement learning network, echo state network, time-delay neural network, support vector machine, attention-based neural network, autoencoder, graph neural network (e.g., graph convolutional network), variational autoencoder and / or transformer neural network (e.g., transformer-based bidirectional encoder representation (BERT), generative pre-trained transformer (GPT)), large language model (LLM). In at least one embodiment, the transformer neural network refers to an architecture that uses a self-attention mechanism (e.g., multi-head attention) to process sequential data.

[0011] In at least one embodiment, various neural network training techniques (e.g., supervised learning, unsupervised learning, reinforcement learning, transfer learning, online learning, batch learning, joint learning) are used to train the neural network (e.g., neural network 114, neural network 232, neural network 234, neural network 236).

[0012] In at least one embodiment, in addition to performing the binding Figures 1-7In addition to the various operations described, the neural network or portions thereof can perform a variety of computer vision and natural language processing (NLP) operations, unless otherwise explicitly stated. In at least one embodiment, the various computer vision operations, individually or in any combination, include object recognition, face recognition, image segmentation, object tracking, gesture recognition and optical character recognition, and augmented reality. In at least one embodiment, the various NLP operations, individually or in any combination, include sentiment analysis, chatbot generation, language translation, text detection, text recognition, text summarization, named entity recognition, text classification, speech recognition, computer program (e.g., a set of code) generation, and text generation.

[0013] In at least one embodiment, the neural network training module 110 trains one or more neural networks (e.g., neural network 114, neural network 232, neural network 236, etc.). Figure 3-5 The generator neural network (described) is a module. In at least one embodiment, the one or more neural networks are at least combined with Figure 2 Further description.

[0014] In at least one embodiment, the neural network training module 110 receives training data 112 to train one or more neural networks 114. In at least one embodiment, the training data 112 includes hardware features of different computer systems (e.g., NVIDIA H100, AMD MI300 APU, Intel Habana's Gaudi chip). In at least one embodiment, the hardware features are at least combined with… Figure 2 Further description. In at least one embodiment, the training data 112 includes software features of the different computer systems. In at least one embodiment, the software features are at least combined with... Figure 2 Further description. In at least one embodiment, training data 112 includes a first software program (e.g., code example) utilizing the software features and the hardware features. In at least one embodiment, hardware resources execute the first software program. In at least one embodiment, the first software program is at least combined with... Figure 2 Further description.

[0015] In at least one embodiment, the training data 112 includes a second software program (e.g., code example) for executing different versions of the compressed neural network on different platforms, computer systems, or any other hardware resources. In at least one embodiment, the second software program is at least combined with Figure 2 Further description. In at least one embodiment, the training data 112 includes manual feedback (e.g., a heuristic dataset) that includes multiple configuration information selected by one or more engineers based on their experience.

[0016] In at least one embodiment, the neural network training module 110 trains one or more neural networks 114 to generate one or more trained neural networks 116. In at least one embodiment, the neural network training module 110 uses the hardware features, the software features, and the first software program to initially train one or more neural networks 114 to generate one or more trained neural networks 116.

[0017] In at least one embodiment, the neural network training module 110 uses the second software program for further training (e.g., performing a combination). Figure 2 (Further described as a first fine-tuning) one or more neural networks 116. In at least one embodiment, after performing the first fine-tuning, one or more trained neural networks 116 can be ready for deployment. In at least one embodiment, the neural network training module 110 further trains using the manual feedback (e.g., performing a combination of...). Figure 2 (Further described as a second fine-tuning) one or more neural networks 116. In at least one embodiment, after performing the second fine-tuning, one or more trained neural networks 116 are ready for deployment. In at least one embodiment, the neural network training module 110 uses a training framework 904, wherein one or more neural networks 114 include untrained neural networks 906, and one or more trained neural networks 116 include trained neural networks 908.

[0018] In at least one embodiment, the neural network training module 110 includes a model training system 3704, wherein one or more neural networks 114 include a pre-trained model 3806 and / or an initial model 4104, and model training 3714 is performed to generate a refined model 4112. In at least one embodiment, one or more trained neural networks 116 include the refined model 4112.

[0019] In at least one embodiment, the neural network generation module 120 is a module that generates one or more versions of one or more compressed neural networks, wherein the one or more versions correspond to different platforms, computer systems, or any other hardware resources. In at least one embodiment, the neural network generation module 120 uses one or more trained neural networks (e.g., neural network 124, neural network 234, neural network 236) to generate the one or more neural networks (e.g., compressed neural networks). In at least one embodiment, the neural network generation module 120 deploys one or more trained neural networks 116 in a computer system, such that one or more deployed neural networks 124 generate the one or more neural networks defined or implemented by one or more software programs 122.

[0020] In at least one embodiment, combined Figures 1-7 The compressed neural network described refers to a neural network that has not only been compressed using general model compression techniques but has also been further optimized for a specific platform, computer system, or any other hardware resource (such as an NVIDIA H100 GPU). In at least one embodiment, the optimization leverages the unique features and capabilities of the hardware resources to maximize the efficiency, speed, and effectiveness of the neural network when running on that platform.

[0021] In at least one embodiment, software tools (e.g., TensorRT, openVINO, Intel Math Kernel Library for Deep Neural Networks (NKL-DNN), oneAPI toolkit) are used to compress the neural network. These software tools are designed to optimize the neural network for deployment on specific hardware resources (e.g., NVIDIA GPUs). In at least one embodiment, the compression includes combining two or more layers of one or more neural networks into a single layer. In at least one embodiment, the compression includes adjusting the numerical precision of the computation (e.g., from 32-bit floating-point to 16-bit or 8-bit) to reduce memory usage and increase throughput while minimizing the impact on accuracy. In at least one embodiment, different versions are generated to dynamically compress the neural network based on the data types that the hardware resources can only support. In at least one embodiment, a neural network optimized in INT8 format must be converted into different versions for execution by a set of hardware resources that only support FP32 or FP16.

[0022] In at least one embodiment, the compression includes: selecting the most efficient computational kernel for a specific operation in one or more neural networks based on the target GPU architecture. In at least one embodiment, the compression includes: performing dynamic tensor memory allocation. In at least one embodiment, the compression includes: utilizing the sparsity (result of pruning) of the model's weights to skip zero-value weights during computation.

[0023] In at least one embodiment, the compression includes: utilizing Intel Thread Building Blocks (TBBs) and OpenMP to efficiently distribute computation across multiple CPU cores. In at least one embodiment, the compression includes: executing Intel-optimized mathematical routines from libraries such as oneDNN to ensure that each operation in one or more neural networks is executed as efficiently as possible, thereby fully utilizing Intel CPU vectorized instructions such as AVX-512. In at least one embodiment, the compression includes: optimizing lightweight neural networks for tasks such as defect detection or predictive maintenance using Intel Atom processors or Movidius VPU accelerators employing OpenVINO.

[0024] In at least one embodiment, the compression includes using a mobile-specific library to ensure the ability of one or more neural networks to fit on a mobile GPU. In at least one embodiment, the compression includes using NVIDIA's Jetson to compress one or more neural networks (e.g., recurrent neural networks, transformer neural networks) performing speech recognition.

[0025] In at least one embodiment, the compression includes: model compression techniques optimized for a destination platform, computer system, or any other hardware resources. In at least one embodiment, the model compression techniques include pruning, quantization, knowledge distillation, weight sharing, and low-rank factorization.

[0026] In at least one embodiment, the neural network generation module 120 receives one or more instructions 118 as input to one or more deployed neural networks 124. In at least one embodiment, the one or more instructions 118 include a previous version of the neural network compressed for a previous hardware resource, the name of the previous hardware resource, and / or the name of a new hardware resource to which a new version of the compressed neural network to be generated by the neural network generation module 120 is to be executed. In at least one embodiment, generating a neural network (e.g., a compressed neural network) includes generating one or more software programs 122 that define or implement the new version of the compressed neural network. In at least one embodiment, the one or more software programs 122 include code or any other instructions that cause the one or more compressed neural networks to be deployed on a destination platform, computer system, or any other hardware resource. In at least one embodiment, the code can be written using: Python with TensorFlow, PyTorch, Keras, Scikit-learn, C++ with Caffe, OpenCV's DNN module, Java with Deeplearning4j, DL4J, Javascript with TensorFlow.js, Brain.js, R with KerasR and MXNet, Julia with Flux, Jil, and Knet, MATLAB, ONNX, TensorRT, TVM, OpenVINO, etc. In at least one embodiment, one or more software programs 122 are used to deploy a compressed model (e.g., a neural network) based on the deployment system 3706.

[0027] In at least one embodiment, one or more software programs 122 include software code written in a programming language, wherein the software code includes imported libraries, definitions of neural network architectures (e.g., input layers, hidden layers, output layers), loss functions, optimizers, data preprocessing, training, evaluation, and prediction.

[0028] In at least one embodiment, one or more deployed neural networks 124 include a large language model 4242. In at least one embodiment, one or more deployed neural networks 124 receive input data 5210 to generate output data 4220, which includes software program 122 for implementing the one or more target neural networks. In at least one embodiment, a large language model API 4204 is used to receive input data 5210 and generate output data 4220, which includes software program 122 for implementing the one or more target neural networks.

[0029] In at least one embodiment, system 100 includes one or more circuits for generating one or more second versions of the one or more second neural networks using one or more first neural networks, at least in part based on one or more first versions of one or more second neural networks and one or more hardware resources for executing the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks refer to one or more deployed neural networks 124. In at least one embodiment, the one or more second neural networks refer to one or more compressed neural networks defined by software program 122. In at least one embodiment, the hardware resources include computer systems, platforms, or any other combination of hardware and software described herein capable of executing compressed neural networks.

[0030] In at least one embodiment, different versions of the neural network are generated by the neural network generation module 120, such that the neural network is compressed or optimized for each set of hardware resources. In at least one embodiment, if a first version of the neural network is compressed (e.g., converted to a low-precision format) to fit hardware resources supporting INT8 operations, and a new set of hardware resources does not support it, a second version of the neural network is generated to fit other data types (e.g., FP32), while minimizing accuracy loss and utilizing additional optimization techniques specific to the new set of hardware resources. In at least one embodiment, the neural network generation module 120 generates compressed neural networks to be executed by various hardware resources, which are supported by their respective software stacks. In at least one embodiment, there may be one set of APIs for NVIDIA hardware only, and there may be a different set of APIs for Intel hardware only. Figure 2 An example system 200 for training one or more generator neural networks is illustrated according to at least one embodiment. In at least one embodiment, system 200 is combined with... Figure 1 The described combination of hardware and software. In at least one embodiment, system 200 includes training module 230.

[0031] In at least one embodiment, the training module 230 is a module that trains one or more compressed neural networks (e.g., neural network 114, neural network 116, neural network 124, neural network 232, neural network 234, neural network 236) to generate one or more compressed neural networks, wherein the one or more compressed neural networks will be deployed on a different platform, computer system, or any other hardware resource than one or more compressed neural networks previously deployed. In at least one embodiment, the one or more compressed neural networks can perform a combination Figure 1 Various tasks are described (e.g., computer vision, NLP). In at least one embodiment, training module 230 includes model training system 3704.

[0032] In at least one embodiment, the training module 230 receives information from a first computer system, platform, or any other hardware resource (e.g., NVIDIA) 212, information from a second computer system, platform, or any other hardware resource (e.g., Intel) 214, and information from a third computer system, platform, or any other hardware resource (e.g., AMD) 216. In at least one embodiment, there exists Figure 2 Additional information on additional computer systems, platforms, or any other hardware resources not shown in the diagram.

[0033] In at least one embodiment, there is a separate module ( Figure 2 (Not shown in the figure), which is configured to receive information from a first computer system 212, a second computer system 214, and a third computer system 216 for training module 230. In at least one embodiment, training module 230 and / or the individual modules receive the information from different sources (e.g., websites (NVIDIA, Intel, AMD), white papers, analytics articles, release notes, tutorials, toolkits, etc.) using different technologies (e.g., APIs, manual copy and paste, automated web scraping (e.g., BeautifulSoup, Scrapy, Octoparse, ParseHub), HTML parsing, Document Object Model (DOM) parsing, web crawling, text pattern matching (Regex), headless browsers, subscriptions (e.g., RSS feeds), etc.).

[0034] In at least one embodiment, training module 230 or the individual module (e.g., data collection module 616) uses information from the first computer system 212, information from the second computer system 214, information from the third computer system 216, and / or Figure 2Additional information, not illustrated, is used to generate the hardware characteristics of computer system 222. In at least one embodiment, the hardware characteristics include the number of cores, clock speed, data type (e.g., floating-point 32, integer 8), memory capacity and type, memory bandwidth, shared cores, ray tracing cores, tensor cores, thermal design power, API support, connectivity and ports, form factor and size, manufacturing process, electrical characteristics, data propagation delay, power consumption, integrated peripherals, application circuitry, or any other characteristics that can be obtained from the chip's datasheet.

[0035] In at least one embodiment, the hardware features for NVIDIA (obtained from information from the first computer system 212) include chip information such as, but not limited to, Tesla (e.g., Tesla K80, P100, V100, T4), Ampere (e.g., A100), Volta (e.g., V100), Turing (e.g., RTX 2080), Pascal (e.g., P100), DGX systems (e.g., DGX-1, DGX A100), Jetson (e.g., Jetson Nano, Jetson TX1 / TX2, Jetson Xavier NX, and Jetson AGX Xavier), BlueField for DPUs, Mellanox for networking products, DRIVE (e.g., DRIVEXavier, DRIVE Pegasus, DRIVE Orin), and the RTX series. In at least one embodiment, different chips provide one or more features, such as, but not limited to, CUDA cores, precision support (e.g., INT8, FP16, FP32, FP64), tensor cores, sparsity acceleration, high memory bandwidth and capacity, multi-instance GPUs, RT cores, NVLink, NVSwitch, etc.

[0036] In at least one embodiment, the hardware features for NVIDIA (obtained from information from the second computer system 214) include chip information, such as, but not limited to, Xeon Scalable processors (e.g., Xeon Phi), Nervana (e.g., NNP-I, NNP-T), Movidius (e.g., Movidius Myriad X VPU), Agilex, Stratix, Arria, EyeQ, Loihi, Habana Labs Gaudi, and Goya processors (e.g., Gaudi AI training processor, Goya AI inference processor). In at least one embodiment, different chips provide one or more features, such as, but not limited to, Intel deep learning enhancement, neural computing engine, neuromorphic computing architecture, converged Ethernet RDMA, etc.

[0037] In at least one embodiment, the hardware features for NVIDIA (obtained from information from the third computer system 216) include chip information, such as, but not limited to, the Ryzen Treaddripper series, Ryzen 9, 7, and 5 series, EPYC server processors, Radeon Instinct series, Radeon Pro series, and Radeon RX 5000 and 6000 series. In at least one embodiment, different chips provide one or more features, such as, but not limited to, Zen microarchitecture, PCIe 4.0 / 5.0 support, ray tracing capabilities, etc.

[0038] In at least one embodiment, training module 230 or a separate module (e.g., data collection module 616) uses information from the first computer system 212, the second computer system 214, the third computer system 216, and / or additional information to generate software features of computer system 224. In at least one embodiment, software features of a platform, computer system, or any other hardware resource refer to a software stack used to perform one or more computational operations using said platform, computer system, or any other hardware resource. In at least one embodiment, the software stack includes software programs, operating systems, runtime environments, development frameworks, programming languages, libraries, APIs, etc.

[0039] In at least one embodiment, the software features for NVIDIA (e.g., tools, functions, libraries, APIs) (obtained from information from the first computer system 212) include, but are not limited to, CUDA, cuDNN, TensorRT, NVIDIA Collective Communication Library, NVIDIA RAPIDS, NVIDIA Deep Learning AI and HPC software, NVIDIA DALI, NVIDIA Nsight tools, NVIDIA JetPack SDK, NVIDIA Deep Learning GPU Training System, NVIDIA Clara, NVIDIA Omniverse, etc.

[0040] In at least one embodiment, the software features for Intel (e.g., tools, functions, libraries, APIs) (obtained from information from the second computer system 214) include, but are not limited to, OpenVINO, oneAPI, Intel Data Analytics Accelerator Library, Intel Math Kernel Library, Intel distribution for Python, Intel Machine Learning Extension Library, Intel optimizations for TensorFlow, Intel optimizations for PyTorch, Intel FPGA SDK for OpenCI, Intel Deep Learning Enhancement, Intel Movidius Neural Computing SDK, Intel RealSense SDK, Intel Integrated Performance Primitives, etc.

[0041] In at least one embodiment, the software features for AMD (e.g., tools, functions, libraries, APIs) (obtained from information from the third computer system 216) include, but are not limited to, ROCm, AMD MIOpen, AMD Infinity Hub, AMDBlis and libFLAME, AMD Math kernel library, a portable heterogeneous computing interface, AMD Data Parallel C++, AMD optimization library, Radeon ProRender, etc.

[0042] In at least one embodiment, training module 230 or the individual module (e.g., data collection module 616) uses information from the first computer system 212, the second computer system 214, the third computer system 216, and / or additional information to generate information associated with connection 226 of the computer system's hardware and software characteristics (e.g., code example). In at least one embodiment, the connection includes using a CUDA API to control one or more chips (e.g., Tesla P100) for neural network inference / training. In another example, in at least one embodiment, the connection includes using a oneAPI API to control one or more chips (e.g., Gaudi / Goya) for neural network inference / training. In yet another example, in at least one embodiment, the connection includes using ROCm functions to control one or more chips (e.g., Radeon) for neural network inference / training. In at least one embodiment, the APIs and functions are defined in one or more software programs.

[0043] In at least one embodiment, the training module 230 uses the hardware features of the computer system 222, the software features of the computer system 224, and information associated with the connection 226 of the hardware and software features of the computer system to train an initial neural network 232 to generate a first fine-tuned neural network 234. In at least one embodiment, the initial neural network 232 includes a pre-trained neural network (e.g., GPT, GPT-2, GPT-3, GPT-4, BERT, RoBERTa, DistilBERT, T5 (text-to-text transition transformer), XLNet, Codex, BART, BlenderBot, Turing-NLG, LaMDA, CTRL, Gopher, RETRO, Chinchilla, Megatron-LM, LLaMA, ERNIE, ALBERT, ELECTRA, BLOOM, OpenAICodex, Transformer-XL, AlexNet, VGGNet, RestNet, Inception, EfficientNet, YOLO, R-CNN, Mask R-CNN, StyleGAN, StyleGAN2, OpenPose, ULMFIT, TextBlob Blob, spaCy models, DeepSpeech, Wavenet, Tacotron, WaveGlow, ROS SLAM, U-Net, DeepVariant, AlphaFold, etc.).

[0044] In at least one embodiment, training module 230 trains initial neural network 232 using training framework 904, wherein initial neural network 232 includes untrained neural network 906 and first fine-tuned neural network 234 includes trained neural network 908. In at least one embodiment, one or more initial neural networks 232 include pre-trained model 3806, pre-trained model 4142, and / or initial model 4104. In at least one embodiment, the training is used for initial neural network 232 to learn fundamental knowledge of source and target platforms, computer systems, or any other hardware resources to solve model conversion tasks (e.g., generating different versions to be deployed on different hardware resources).

[0045] In at least one embodiment, training module 230 trains a first fine-tuned neural network 234 using an optimized dataset 228 to generate a second fine-tuned neural network 236. In at least one embodiment, the optimized dataset 228 includes a one-to-one correspondence between a source computer system and a target computer system (e.g., code examples). In at least one embodiment, the one-to-one correspondence includes a set of code to deploy a compressed neural network (e.g., GPT-3) in a source system (e.g., Intel Gaudi) and a target system (e.g., NVIDIA H100), where the relationship shows a tight mapping between individual codes on different computer systems. In at least one embodiment, the one-to-one correspondence includes a compressed neural network to be executed by different computer systems, platforms, or any other hardware resources.

[0046] In at least one embodiment, training module 230 trains a first fine-tuned neural network 234 training framework 904, wherein the first fine-tuned neural network 234 includes an untrained neural network 906, and a second fine-tuned neural network 236 includes a trained neural network 908. In at least one embodiment, the second fine-tuned neural network 236 includes a refined model 4112 trained using model training 3714. In at least one embodiment, during training, training module 230 compares the output of the first fine-tuned neural network 234 with an optimized dataset 228. In at least one embodiment, training module 230 uses the difference in the comparison as input to a contrastive learning algorithm and uses the output to prompt adjustments to the first fine-tuned neural network 234.

[0047] In at least one embodiment, training module 230 uses heuristic dataset 242 to train a second fine-tuned neural network 236 to generate a trained neural network. In at least one embodiment, heuristic dataset 242 includes prior experience of users deploying the neural network on different computer systems to determine a preferred platform. In at least one embodiment, the prior experience includes using a particular computer system (e.g., NVIDIA H100) superior to another computer system (e.g., Intel Habana's Gaudi chip) due to accuracy support (e.g., FP8 support). In at least one embodiment, the prior experience includes using a particular computer system (e.g., NVIDIA H100) superior to another computer system (e.g., AMD's MI300 APU) due to the efficiency of the trained neural network. In at least one embodiment, the prior experience includes individual user preferences for software (e.g., CUDA superior to oneAPI or ROCm).

[0048] In at least one embodiment, training module 230 trains a second fine-tuned neural network 236 using training framework 904, wherein the second fine-tuned neural network 236 includes an untrained neural network 906, and the trained neural network includes a trained neural network 908. In at least one embodiment, the trained neural network includes a refined model 4112 trained using model training 3714. In at least one embodiment, one or more neural networks after the second fine-tuning include the refined model 4112 trained using model training 3714.

[0049] In at least one embodiment, one or more trained neural networks 238 are prepared to be deployed in one or more computer systems to generate one or more computer programs that cause one or more compressed neural networks (e.g., combined with...) Figure 1 The different neural networks described are optimally deployed to enable the other neural networks to perform various computer vision, natural language processing, and other tasks. In at least one embodiment, depending on the target platform, computer system, or any other hardware resources for executing the one or more compressed neural networks, one or more trained neural networks 238 generate one or more different versions of the compressed neural network.

[0050] In at least one embodiment, the trained neural network includes a neural network 124, combined with... Figure 3 The description includes one or more generator neural networks, and / or one or more neural networks used in box 510. In at least one embodiment, the trained neural network includes a large language model 4212, which can be used to generate output data 4220 using input data 5210. In at least one embodiment, a large language model API 4204 can be used to generate output data 4220.

[0051] In at least one embodiment, system 200 includes one or more circuits for generating the one or more second versions of the one or more second neural networks using one or more first neural networks, at least in part based on one or more first versions of one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks refer to any one of a first fine-tuned neural network 234, a second fine-tuned neural network 236, or the trained neural network. In at least one embodiment, the one or more second neural networks refer to one or more compressed neural networks described herein.

[0052] In at least one embodiment, the one or more trained neural networks generate different versions of the neural network (e.g., a first version, a second version), such that the neural network is compressed on various hardware resources with different characteristics. In at least one embodiment, the first version can be compressed to be executed by a first hardware resource that only supports FP32, while the second version can be compressed to be executed by a second hardware resource that also supports INT8.

[0053] Figure 3 An example process 300 for generating one or more compressed neural networks executed by hardware resources, according to at least one embodiment, is illustrated. Although the example process 300 is depicted as a series of steps or operations, it will be understood that at least one embodiment of process 300 includes modified or reordered steps or operations, or omissions of certain steps or operations, unless explicitly stated or logically required, such as when the output of one step or operation is used as the input of another step or operation. In at least one embodiment, each block of process 300 is composed of... Figure 1 , Figure 2 , Figure 6 and Figure 7 The described one or more entities may be performed individually or in any combination. In at least one embodiment, the one or more entities include a neural network training module 110, a neural network generation module 120, a training module 230, a training module 610, a compressed neural network generation module 612, and a training data collection module 614.

[0054] In at least one embodiment, the one or more entities further include a combination Figure 1 The described combination of hardware and software. In at least one embodiment, various functions or blocks are implemented by a processor executing instructions stored in (e.g., computer-readable, machine-readable) memory to implement process 300. In at least one embodiment, process 300 may also be implemented as computer-usable instructions (e.g., macro instructions, micro instructions) stored on a computer storage medium or provided by a standalone application, service, or managed service (independently or in combination with another managed service). In at least one embodiment, the computer-usable instructions executed by at least one processor (e.g., processor 602) are provided by one or more programming models (e.g., CUDA oneAPI, ROCm). In at least one embodiment, processor 602 executes one or more blocks of process 300. In at least one embodiment, one or more APIs 710 or software programs 702 execute one or more blocks of process 300, individually or in combination.

[0055] According to at least one embodiment, at block 302, the one or more entities receive one or more inputs indicating one or more compressed neural networks for a source platform, the source platform, and a target platform for executing a new version of the one or more compressed neural networks. In at least one embodiment, the indication includes the names of the source platform and the target platform. In at least one embodiment, the one or more inputs are received via an API or web interface.

[0056] According to at least one embodiment, in block 304, the one or more entities utilize one or more generator neural networks (e.g., neural network 116, neural network 124, neural network 232, neural network 234, neural network 236) to generate new versions of one or more compressed neural networks for the target platform using the one or more inputs.

[0057] In block 306, the one or more entities deploy the one or more compressed neural networks on the target platform, enabling the target platform to execute the new version of the one or more compressed neural networks. In at least one embodiment, the one or more entities include deployment system 3706.

[0058] In at least one embodiment, at least one of blocks 302, 304, and / or 306 is used to generate the one or more second versions of the one or more second neural networks using one or more first neural networks, at least in part based on one or more first versions of one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks refer to the one or more generator neural networks. In at least one embodiment, the one or more second versions refer to the new version of the one or more compressed neural networks. In at least one embodiment, the one or more first versions refer to the compressed neural network for the source platform.

[0059] Figure 4 An example process 400 for training one or more generator neural networks is illustrated according to at least one embodiment. Although the example process 400 is depicted as a series of steps or operations, it will be understood that at least one embodiment of process 400 includes modified or reordered steps or operations, or omissions of certain steps or operations, unless explicitly stated or logically required, such as when the output of one step or operation is used as the input to another step or operation. In at least one embodiment, each block of process 400 is composed of... Figure 1 , Figure 2 , Figure 6and Figure 7 The described one or more entities may be performed individually or in any combination. In at least one embodiment, the one or more entities include a neural network training module 110, a neural network generation module 120, a training module 230, a training module 610, a compressed neural network generation module 612, and a training data collection module 614.

[0060] In at least one embodiment, the one or more entities further include a combination Figure 1 The described combination of hardware and software. In at least one embodiment, various functions are implemented by a processor executing instructions stored in (e.g., computer-readable, machine-readable) memory to implement process 400. In at least one embodiment, process 400 may also be implemented as computer-usable instructions (e.g., macro instructions, micro instructions) stored on a computer storage medium or provided by a standalone application, service, or managed service (independently or in combination with another managed service). In at least one embodiment, the computer-usable instructions executed by at least one processor (e.g., processor 602) are provided by one or more programming models (e.g., CUDA oneAPI, ROCm). In at least one embodiment, processor 602 executes one or more blocks of process 400. In at least one embodiment, one or more APIs 710 or software programs 702 execute one or more blocks of process 400, individually or in combination.

[0061] According to at least one embodiment, at box 404, the one or more entities receive information from different computer systems. In at least one embodiment, the information is obtained from websites (e.g., NVIDIA, Intel, AMD), white papers, analytical articles, release notes, tutorials, toolkits, etc. In at least one embodiment, the one or more entities use different technologies to obtain the information, which will combine... Figure 2 The following description is provided. In at least one embodiment, the one or more entities collect hardware characteristics of the different computer systems based on the received information. In at least one embodiment, the hardware characteristics include the hardware characteristics of computer system 222.

[0062] According to at least one embodiment, at block 404, the one or more entities collect software features of the different computer systems based on the received information. In at least one embodiment, the software features include software features of computer system 224.

[0063] According to at least one embodiment, at block 406, the one or more entities collect information based on a software program. In at least one embodiment, the software program includes code providing examples of hardware features of a platform, computer system, or any other hardware resource based on software features. In at least one embodiment, the software program includes a connection 226 of hardware and software features, which may be represented as one or more software programs. In at least one embodiment, the one or more software programs are executed by multiple platforms, computer systems, or any other hardware resources.

[0064] In block 408, the one or more entities train one or more generator neural networks (e.g., neural network 116, neural network 124, neural network 232) based on collected hardware features, software features, and the software program. In at least one embodiment, the one or more generator neural networks include a pre-trained large language model that can generate one or more software programs and / or one or more compressed neural networks.

[0065] In at least one embodiment, one or more entities use training framework 904 to train the one or more neural networks. In at least one embodiment, the one or more generator neural networks include an untrained neural network 906, and the one or more trained neural networks include a trained neural network 908. In at least one embodiment, the one or more trained neural networks include neural network 234 or neural network 116. In at least one embodiment, the one or more trained neural networks include a large language model 4212. In at least one embodiment, the one or more entities include a model training system 3704, wherein the one or more trained neural networks include a refined model 4112 trained using model training 3714.

[0066] In at least one embodiment, at least one of blocks 402, 404, 406, and / or 408 is used to generate the one or more second versions of the one or more second neural networks using one or more first neural networks, at least in part based on one or more first versions of one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks refer to the generator neural network.

[0067] Figure 5An example process 500 for fine-tuning one or more generator neural networks according to at least one embodiment is illustrated. Although the example process 500 is described as a series of steps or operations, it will be understood that at least one embodiment of process 500 includes modified or reordered steps or operations, or omissions of certain steps or operations, unless explicitly stated or logically required, such as when the output of one step or operation is used as the input to another step or operation. In at least one embodiment, each block of process 500 is composed of... Figure 1 , Figure 2 , Figure 6 and Figure 7 The described one or more entities may be performed individually or in any combination. In at least one embodiment, the one or more entities include a neural network training module 110, a neural network generation module 120, a training module 230, a training module 610, a compressed neural network generation module 612, and a training data collection module 614.

[0068] In at least one embodiment, the one or more entities further include a combination Figure 1 The described combination of hardware and software. In at least one embodiment, various functions are implemented by a processor executing instructions stored in (e.g., computer-readable, machine-readable) memory to implement process 500. In at least one embodiment, process 500 may also be implemented as computer-usable instructions (e.g., macro instructions, micro instructions) stored on a computer storage medium or provided by a standalone application, service, or managed service (independently or in combination with another managed service). In at least one embodiment, the computer-usable instructions executed by at least one processor (e.g., processor 602) are provided by one or more programming models (e.g., CUDA oneAPI, ROCm). In at least one embodiment, processor 602 executes one or more blocks of process 500. In at least one embodiment, one or more APIs 710 or software programs 702 execute one or more blocks of process 500, individually or in combination.

[0069] According to at least one embodiment, at block 502, the one or more entities receive an optimized dataset comprising pairs of software programs with a one-to-one correspondence across different platforms, computer systems, or other hardware resources. In at least one embodiment, the optimized dataset comprises pairs of compressed neural networks (e.g., defined by software programs) deployed for each platform, computer system, or other hardware resource. In at least one embodiment, the one or more compressed neural networks comprise a first version executed by a first hardware resource and a second version executed by a second hardware resource. In at least one embodiment, the optimized dataset comprises an optimized dataset 228. In at least one embodiment, the one or more entities receive the optimized dataset from websites (e.g., NVIDIA, Intel, AMD), white papers, analytical articles, release notes, tutorials, toolkits, etc. In at least one embodiment, the one or more entities use different technologies to obtain the information, which will combine... Figure 2 Describe it.

[0070] According to at least one embodiment, in block 504, the one or more entities train one or more neural networks (e.g., neural network 114, neural network 234, and the one or more generator neural networks trained as a result of executing block 410) based on the optimized dataset. In at least one embodiment, the one or more entities use training framework 904 to train the one or more neural networks. In at least one embodiment, the one or more neural networks include an untrained neural network 906, and the one or more trained neural networks include a trained neural network 908. In at least one embodiment, the one or more trained neural networks include neural network 236 or neural network 116. In at least one embodiment, the one or more entities include model training system 3704, wherein the one or more trained neural networks include a refined model 4112 trained using model training 3714.

[0071] According to at least one embodiment, at box 506, the one or more entities receive a heuristic dataset comprising configuration information received from a user (e.g., an AI engineer). In at least one embodiment, the configuration information includes heuristic dataset 242.

[0072] According to at least one embodiment, in block 508, the one or more entities train the one or more neural networks based on the heuristic dataset. In at least one embodiment, the one or more neural networks include network 114, neural network 236, and one or more neural networks trained as a result of executing block 504. In at least one embodiment, the one or more entities train the one or more neural networks using training framework 904. In at least one embodiment, the one or more neural networks include an untrained neural network 906, and the one or more trained neural networks include a trained neural network 908. In at least one embodiment, the one or more trained neural networks include neural network 238 or neural network 116. In at least one embodiment, the one or more entities include a model training system 3704, wherein the one or more trained neural networks include a refined model 4112 trained using model training 3714. In at least one embodiment, the one or more neural networks can generate different versions of compressed neural networks (in the form of software programs) depending on the type of platform, computer system, or any other hardware resource.

[0073] In at least one embodiment, at least one of blocks 502, 504, 506, and / or 508 is used to generate the one or more second versions of the one or more second neural networks using one or more first neural networks, at least in part based on one or more first versions of one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks refer to the one or more neural networks trained as part of executing blocks 502, 504, 506, and / or 508. In at least one embodiment, the one or more second versions refer to the compressed neural network (in the form of a software program) in different versions depending on the platform, computer system, or other type of hardware resources.

[0074] According to at least one embodiment, Figure 6An example system 600 for generating one or more compressed neural networks executed by hardware resources, according to at least one embodiment, is illustrated. In at least one embodiment, system 600 uses one or more non-transitory machine-readable media on which an instruction set is stored, which, if executed by one or more processors (e.g., processor 602), causes the one or more processors to implement an optimized deployment of one or more neural networks. In at least one embodiment, system 600 includes one or more processors 602 that use one or more first neural networks to generate one or more second versions of the one or more second neural networks, at least in part based on one or more first versions of one or more second neural networks and one or more hardware resources to be used to execute one or more second versions of the one or more second neural networks. In at least one embodiment, one or more processors 602 include a training module 610, a compressed neural network generation module 612, and a training data collection module 614.

[0075] In at least one embodiment, one or more processors 602 implement at least a portion of system 100 and / or system 200. In at least one embodiment, processor 602 executes blocks 302, 304, 306, 402, 404, 406, 408, 410, 502, 504, 506, 508 and / or 510.

[0076] In at least one embodiment, one or more processors 602 execute logic 815. In at least one embodiment, one or more processors 602 are part of data center 1000. In at least one embodiment, one or more processors 602 are part of CPU (e.g., CPU 1106, CPU 1118) and / or processor 1110. In at least one embodiment, one or more processors 602 are part of CPU 1180(A) or CPU 1180(B). In at least one embodiment, one or more processors 602 are processor 1202. In at least one embodiment, one or more processors 602 are processor 1310. In at least one embodiment, one or more processors 602 are part of CPU 1402. In at least one embodiment, one or more processors 602 are part of computer 1510. In at least one embodiment, one or more processors 602 are any of the multi-core processors 1605(1)...1605(M). In at least one embodiment, one or more processors 602 are processor 1607. In at least one embodiment, one or more processors 602 are application processors 1705. In at least one embodiment, one or more processors 602 are processors 2002. In at least one embodiment, one or more processors 602 are processors 2202. In at least one embodiment, one or more processors 602 are processors 2400. In at least one embodiment, one or more processors 602 are processors 2702. In at least one embodiment, one or more processors 602 are processors 2800 as described herein.

[0077] In at least one embodiment, one or more processors 602 are part of GPU 1118 or GPU 1120. In at least one embodiment, one or more processors 602 are part of any of GPUs 1184(A)...1184(H). In at least one embodiment, one or more processors 602 are part of graphics card 1212. In at least one embodiment, one or more processors 602 are part of parallel processing unit 1414. In at least one embodiment, one or more processors 602 are part of any of GPUs 1610(1)...(N). In at least one embodiment, one or more processors 602 are part of graphics acceleration module 1646. In at least one embodiment, one or more processors 602 are graphics processor 1710. In at least one embodiment, one or more processors 602 are graphics processor 1810. In at least one embodiment, one or more processors 602 are graphics processor 1840. In at least one embodiment, one or more processors 602 include at least one graphics core 1900. In at least one embodiment, one or more processors 602 are part of a general-purpose graphics processing unit (GPGPU) 1930. In at least one embodiment, one or more processors 602 are parallel processors 2012. In at least one embodiment, one or more processors 602 are parallel processors 2100. In at least one embodiment, one or more processors 602 are graphics multiprocessors 2132. In at least one embodiment, one or more processors 602 are part of any of the GPGPUs 2206A…2206D. In at least one embodiment, one or more processors 602 are graphics processors 2300. In at least one embodiment, one or more processors 602 are part of a deep learning application processor 2500. In at least one embodiment, one or more processors 602 are part of a neuromorphic processor 2600. In at least one embodiment, one or more processors 602 are graphics processors 2708. In at least one embodiment, one or more processors 602 are integrated graphics processors 2808. In at least one embodiment, one or more processors 602 are graphics processors 2900. In at least one embodiment, one or more processors 602 are part of the graphics processing engine 3010 described herein. In at least one embodiment, one or more processors 602 are any of the shader processors 3107A…3107F described herein. In at least one embodiment, one or more processors 602 are shader processors 3202. In at least one embodiment, one or more processors 602 are connected to a graphics execution unit 3208.In at least one embodiment, one or more processors 602 are part of a parallel processing unit (PPU) 3300. In at least one embodiment, one or more processors 602 are part of a general-purpose processor cluster (GPC) 3400. In at least one embodiment, one or more processors 602 are a streaming multiprocessor 3600. In at least one embodiment, one or more processors 602 are part of hardware 3722. In at least one embodiment, one or more processors 602 execute a model training system 3704. In at least one embodiment, one or more processors 602 are processors 4206.

[0078] In at least one embodiment, training module 610 is a module that trains one or more neural networks to generate a software program that defines the architecture of a compressed model (e.g., an optimized neural network) on a target platform, computer system, or any other hardware resource.

[0079] In at least one embodiment, the training module 610 uses the coarse hardware features dataset, the coarse software stack dataset, and the coarse hardware-software connectivity dataset collected by the data collection module 614 to perform fine-tuning on a general pre-trained LLM, wherein the fine-tuning aims to leverage the semantic understanding and analytical capabilities of the pre-trained LLM to learn fundamental knowledge of the original and target platforms, computer systems, or any other hardware resources. In at least one embodiment, the fine-tuned pre-trained LLM refers to an LLM that has undergone coarse-to-fine tuning.

[0080] In at least one embodiment, the training module 610 performs further training on the pre-trained LLM by generating several standard model compression tasks for some typical neural networks as cues and comparing them with content generated by the pre-trained LLM (e.g., corresponding code examples for deploying such compressed models on the original platform and the target platform). In at least one embodiment, the training is at least partially based on a comparison of the output of the coarsely tuned LLM with the fine-grained model compression dataset collected by the training data collection module 614, wherein the trained LLM refers to the finely tuned LLM. In at least one embodiment, manual feedback is performed (in conjunction with...) Figures 1-5 (Description) To add the user's prior experience to further train the fine-tuned LLM.

[0081] In at least one embodiment, the compressed neural network generation module 612 is a module that generates a compressed model (e.g., an optimized neural network) on a target computer system using the one or more neural networks. In at least one embodiment, the compressed neural network generation module 612 generates a computer program that deploys the compressed model on the target platform using an LLM trained by the training module 610 (e.g., a pre-trained LLM, a coarse-tuned LLM, a fine-tuned LLM). In at least one embodiment, the LLM receives the name of the original platform, computer system, or any other hardware resource, the compressed model for the original platform, computer system, or any other hardware resource, and / or the name of the target platform, computer system, or any other hardware resource as input to generate the compressed model for the target platform, computer system, or any other hardware resource.

[0082] In at least one embodiment, the training data collection module 614 is a module that collects different information (e.g., configuration, features) of different computer systems (e.g., platforms provided by NVIDIA, Intel, AMD).

[0083] In at least one embodiment, the training data collection module 614 collects descriptions of hardware configurations and characteristics from websites (e.g., chip datasheets, computer system white papers, or analysis articles between different hardware) to generate a coarse hardware characteristics dataset (e.g., Dataset_h).

[0084] In at least one embodiment, the training data collection module 614 collects descriptions of software stacks and libraries from websites (e.g., release notes and tutorials for software libraries, white papers for software toolkits, or analytical articles between different software stacks) to generate a coarse software stack dataset (e.g., Dataset_s).

[0085] In at least one embodiment, the training data collection module 614 collects introductions and code examples on how to invoke hardware features in a specific platform in a software manner (e.g., how to accelerate convolution operations using typical CUDA toolkits) to generate a coarse hardware-software connected dataset (e.g., Dataset_hs).

[0086] In at least one embodiment, the training data collection module 614 collects pairs of code examples with a one-to-one correspondence on the original and target platforms, computer systems, or any other hardware resources used for model compression operations (e.g., how to quantize the FP32 model post-training to an INT8 format compatible with NVIDIA A100 GPUs using the quantization tools provided by TensorRT, and the exact same semantic example for quantizing the FP32 model post-training to an INT8 format compatible with Intel Gaudi v2 chips using the quantization tools provided by Intel Neural Compressor) to generate a fine-grained model compression dataset (e.g., Dataset_c).

[0087] In at least one embodiment, the training data collection module 614 collects descriptions of software stacks and libraries from websites (e.g., release notes and tutorials for software libraries, white papers for software toolkits, or analytical articles between different software stacks) to generate a coarse software stack dataset.

[0088] In at least one embodiment, compressing the model includes: as part of deploying the model on the target platform, accelerating tensor operations (e.g., addition, subtraction, multiplication, division, dot product, matrix multiplication, integerization, squashing, expansion, slicing, concatenation, stacking, transpose, inversion, determinant, eigenvalue, eigenvector, singular value decomposition, exponentiation, logarithm, square root, absolute value, power, convolution, pooling, ReLU, softmax, batch normalization, gradient calculation, backpropagation, broadcasting, indexing, one-hot encoding, etc.) so that the target platform can execute the model.

[0089] In at least one embodiment, one or more platforms / frameworks / APIs, such as CUDA, oneAPI, OpenCL, ROCM, etc., individually or in combination with one or more hardware acceleration libraries, such as TensorFlow, PyTorch, Keras, Theano, Microsoft Cognitive Toolkit, MXnet, Caffe, Chainer, DeepLearning4J, ONNX, JAX, accelerate one or more operations performed by the model by implementing parallel execution, batch processing, kernel optimization, and memory utilization. In at least one embodiment, one or more operations include, but are not limited to, tensor operations, training (e.g., forward pass, backward pass, weight update), and inference.

[0090] Figure 7An example system 700 according to at least one embodiment is illustrated, which uses one or more application programming interfaces (APIs) to generate one or more compressed neural networks executed by hardware resources. In at least one embodiment, system 700 is used to implement an optimized deployment of one or more neural networks on multiple platforms, computer systems, or any other hardware resources. In at least one embodiment, system 700 uses one or more first neural networks to generate the one or more second versions of the one or more second neural networks, at least in part based on one or more first versions of one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks.

[0091] In at least one embodiment, software program 702 is combined with Figure 1 The described modules. In at least one embodiment, the software program 702 includes one or more modules. In at least one embodiment, one or more APIs 710 include combinations of... Figure 1 The APIs described herein. In at least one embodiment, one or more APIs 710 are software instruction sets that, when executed, cause one or more processors to perform one or more computational operations. In at least one embodiment, one or more APIs 710 refer to reusable blocks of code that perform a specific task and are capable of accepting data, processing data, and returning results. In at least one embodiment, the reusable block of code refers to a block of code that allows one or more APIs 710 to be called multiple times within software program 702 (possibly using different input values) to perform their specified actions without having to repeatedly write the same code. In at least one embodiment, one or more APIs 710 are distributed or otherwise provided as part of one or more libraries 706, runtimes 704, drivers, and / or any other software and / or executable code groups further described herein. In at least one embodiment, one or more APIs 710 perform one or more computational operations in response to invocation by software program 702.

[0092] In at least one embodiment, software program 702 is a collection of software code, commands, instructions, or other text sequences that instruct a computing device (which includes a processor such as processor 702) to perform one or more computational operations and / or invoke one or more other instruction sets (such as API 710 or API function 712) for execution. In at least one embodiment, the functionality provided by one or more APIs 710 includes software functions 712, such as software functions that can be used to accelerate one or more portions of software program 702 using one or more parallel processing units (PPUs) (such as graphics processing units (GPUs)). In at least one embodiment, software program 702 includes a compiler.

[0093] In at least one embodiment, one or more APIs 710 include hardware interfaces for one or more circuits for performing one or more computational operations. In at least one embodiment, one or more software APIs 710 described herein are implemented for performing the operations described below. Figure 1-6 The description refers to one or more circuits employing one or more techniques. In at least one embodiment, one or more software programs 702 include instructions that, when executed, cause one or more hardware devices and / or circuits to perform the aforementioned combined... Figure 1-6 Describes one or more technologies.

[0094] In at least one embodiment, software program 702 (such as a user-implemented software program) utilizes one or more APIs 710 to perform various computational operations, such as memory reservation, matrix multiplication, arithmetic operations, or any computational operation performed by a parallel processing unit (PPU) (such as a graphics processing unit (GPU)), as further described herein. In at least one embodiment, one or more APIs 710 provide a set of callable functions 712 (referred to herein as APIs, API functions, and / or functions), which each perform one or more computational operations, such as computational operations related to parallel computing. In at least one embodiment, one or more APIs 710 provide functions 712 to generate the one or more second versions of the one or more second neural networks, at least in part, based on one or more first versions of one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, one or more APIs 710 provide functions 712 to cause the neural network to perform one or more operations, such as by returning a called function to a processor, wherein the processor invokes the neural network. In at least one embodiment, the processor includes one or more processors 602. In at least one embodiment, the neural network is combined with... Figure 1 One of the neural networks described.

[0095] In at least one embodiment, one or more software programs 702 interact with or otherwise communicate with one or more APIs 710 to perform one or more computational operations using one or more PPUs (such as GPUs). In at least one embodiment, the one or more computational operations using one or more PPUs include at least a group of one or more computational operations to be accelerated by being executed at least partially by said one or more PPUs. In at least one embodiment, one or more software programs 702 interact with one or more APIs 710 to facilitate parallel computation using remote or local interfaces.

[0096] In at least one embodiment, the interface includes software instructions that, if executed, provide access to one or more functions 712 provided by one or more APIs 710. In at least one embodiment, when a software developer compiles one or more software programs 702 in conjunction with one or more libraries 706, the software program 702 uses a native interface, the one or more libraries 706 including one or more APIs 710 or otherwise providing access to one or more APIs 710. In at least one embodiment, one or more software programs 702 are statically compiled in conjunction with pre-compiled libraries 706 or uncompiled source code including instructions for executing one or more APIs 710. In at least one embodiment, one or more software programs 702 are dynamically compiled, and the one or more software programs are linked using a linker to one or more pre-compiled libraries 706, the one or more pre-compiled libraries 706 including one or more APIs 710.

[0097] In at least one embodiment, when a software developer executes a software program that communicates with a library 706 including one or more APIs 710, or otherwise via a network or other remote communication medium, the software program 702 uses a remote interface. In at least one embodiment, the one or more libraries 706 include one or more APIs 710, which will be executed by a remote computing service (such as a computing resource service provider). In another embodiment, the one or more libraries 706 include one or more APIs 710, which will be executed by any other computing host that provides the one or more APIs 710 to the one or more software programs 702. In at least one embodiment, one or more libraries 706 include Intel's Math Kernel Library (MKL), Intel's Data Analytics Acceleration Library (DAAL), Intel's Integrated Performance Primitives (IPP), Intel's Threading Building Blocks (TBB), Intel oneAPI DPC++ / C++ compiler Zen SoftwareStudio, ROCm Hub, Vitis software platform, and Vitis AI.

[0098] In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 to allocate and otherwise manage memory to be used by the software program 702. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 to allocate and manage memory to be used by one or more portions of the software program 702, which will be accelerated using one or more PPUs (such as GPUs or any other accelerators or processors further described herein). Those software programs 702 request that a neural network generate one or more portions of an image based at least in part on one or more of these portions.

[0099] In at least one embodiment, one or more APIs 710 include APIs for facilitating parallel computing. In at least one embodiment, API 710 is provided by a driver and / or runtime 704. In at least one embodiment, API 710 is provided by a CUDA user-mode driver. In at least one embodiment, API 710 is provided by a CUDA runtime. In at least one embodiment, driver 704 is data values ​​and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 712 of API 710 during the loading and execution of one or more portions of software program 702. In at least one embodiment, driver 704 includes Intel graphics drivers, Intel chipset drivers, Intel network adapter drivers, Intel audio drivers, drivers for Intel Movidius VPUs and / or Intel Nervana Neural Processing Units, and drivers that work with AMD Software: PRO Edition, AMD Radeon ProRender, AMD Software: Adrenalin Edition, AMD RyzenMaster Utility, and AMD StoreMI Technology and AMD ROCm.

[0100] In at least one embodiment, runtime 704 includes data values ​​and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 712 of API 710 during the execution of software program 702. In at least one embodiment, runtime 704 includes the Intel Graphics Runtime, the Intel oneAPI Runtime, and the AMD Radeon Open Compute Platform. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 implemented or otherwise provided by drivers and / or runtime 704 to perform combinatorial arithmetic operations by the one or more software programs 702 during execution by one or more PPUs (such as GPUs).

[0101] In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by a driver and / or runtime 704 to perform combined arithmetic operations on one or more PPUs (such as GPUs). In at least one embodiment, one or more APIs 710 provide combined arithmetic operations via a driver and / or runtime 704, as described above. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by a driver and / or runtime 704 to allocate or otherwise reserve one or more blocks of memory 714 for one or more PPUs (such as GPUs). In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by a driver and / or runtime 704 to allocate or otherwise reserve blocks of memory.

[0102] In one embodiment, to improve the usability of software program 702 and / or optimize one or more portions of software program 702 that will be accelerated by one or more PPUs (such as GPUs), one or more APIs 710 provide one or more API functions 712 to utilize combined Figures 1-6 The described system and process are at least in part based on one or more first versions of one or more second neural networks and one or more hardware resources for executing one or more second versions of the one or more second neural networks to generate the one or more second versions of the one or more second neural networks. In at least one embodiment, system 700 includes a processor that includes one or more circuitry for executing one or more software programs to combine two or more APIs into a single API.

[0103] exist Figures 1-7 In at least one embodiment described herein, alone or in conjunction with Figure 8- Figure 42 At least one embodiment of the present invention provides one or more technical improvements. In at least one embodiment, Figures 1-7 The at least one embodiment described herein enables the efficient deployment of compressed models (e.g., optimized neural networks) across different platforms, computer systems, or any other hardware resources (e.g., NVIDIA, AMD, Intel, etc.) without having to migrate / transfer different hardware and / or software. In one example, Figures 1-7The at least one embodiment described enables the efficient deployment of a compressed model (e.g., an optimized neural network) on the different platforms, computer systems, or any other hardware resources without excessive retraining of the compressed model to maintain its accuracy on platforms, computer systems, or any other hardware resources different from the initially deployed platform, computer system, or any other hardware resource. In another example, in Figures 1-7 The at least one embodiment described herein performs the deployment of a compression model while saving time and computational resources. In another example, Figures 1-7 The at least one embodiment described herein performs the deployment and generation of a compression model without requiring users of the compression model to learn information associated with the different computer systems and manually redesign it to adapt to new platforms, computer systems, or any other hardware resources (e.g., using intermediate open-source formats). In another example, in Figures 1-7 The at least one embodiment described herein performs accurate and efficient deployment of the compressed model by performing on-the-fly adjustments and semantic reasoning.

[0104] logic Figure 8A Logic 815 is illustrated, and as described elsewhere herein, it can be used in one or more devices to perform operations such as those discussed herein, according to at least one embodiment. In at least one embodiment, logic 815 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 815 is inference and / or training logic. The following is in conjunction with... Figure 8A and / or Figure 8B Detailed information about logic 815 is provided. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide the functionality or operation described herein, wherein the logic may be embodied collectively or individually as circuitry forming part of a larger system, such as an integrated circuit (IC), a system-on-a-chip (SoC), or one or more processors (e.g., CPU, GPU).

[0105] In at least one embodiment, logic 815 may include, but is not limited to, code and / or data storage 801 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, logic 815 may include or be coupled to code and / or data storage 801 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 801 stores weight parameters and / or input / output data of each layer of a neural network trained or used in one or more embodiments during forward propagation of input / output data and / or weight parameters using aspects of one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 801 may be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0106] In at least one embodiment, any portion of the code and / or data storage 801 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 801 may be a cache memory, dynamic random access memory (“DRAM”), static random access memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 801 is internal or external to the processor, for example, or including DRAM, SRAM, flash memory, or some other storage type, may depend on the on-chip versus off-chip available storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0107] In at least one embodiment, logic 815 may include, but is not limited to, code and / or data storage 805 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, code and / or data storage 805 stores weight parameters and / or input / output data of each layer of the neural network trained or used in one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, logic 815 may include or be coupled to code and / or data storage 805 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)).

[0108] In at least one embodiment, code (such as graph code) causes the architecture of the neural network corresponding to that code to load weights or other parameter information into the processor ALU. In at least one embodiment, any portion of the code and / or data storage 805 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 805 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 805 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 805 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other type of storage, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0109] In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be separate storage structures. In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be the same storage structure. In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 801 and code and / or data storage 805 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0110] In at least one embodiment, logic 815 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 810 (including integer and / or floating-point units) for performing logical and / or mathematical operations at least in part based on or instructed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from layers or neurons within a neural network) stored in activation storage 820, which are functions of input / output and / or weight parameter data stored in code and / or data storage 801 and / or code and / or data storage 805. In at least one embodiment, activations stored in activation storage 820 are generated based on linear algebra and / or matrix-based mathematics performed by ALU 810 in response to execution instructions or other code, wherein weight values ​​stored in code and / or data storage 805 and / or code and / or data storage 801 are used as operands, and other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, may be stored in code and / or data storage 805 or code and / or data storage 801 or other on-chip or off-chip storage.

[0111] In at least one embodiment, one or more processors or other hardware logic devices or circuits include one or more ALUs 810, while in another embodiment, one or more ALUs 810 may be external to the processor or other hardware logic device or the circuitry that uses them (e.g., a coprocessor). In at least one embodiment, ALUs 810 may be included within an execution unit of a processor, or otherwise included in an ALU bank accessible by the execution unit of the processor, which may be within the same processor or distributed among different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed-function unit, etc.). In at least one embodiment, code and / or data storage 801, code and / or data storage 805, and activation storage 820 may share a processor or other hardware logic device or circuitry, while in another embodiment, they may be in different processors or other hardware logic devices or circuitry, or in some combination of the same and different processors or other hardware logic devices or circuitry. In at least one embodiment, any portion of activation storage 820 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be retrieved and / or processed using the processor’s fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0112] In at least one embodiment, the active memory 820 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the active memory 820 may be entirely or partially located within or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the active memory 820 is internal to or external to the processor, for example, or including DRAM, SRAM, flash memory, or certain other memory types, may depend on the available on-chip versus off-chip memory, the latency requirements for performing training and / or inference functions, the batch size of the data used in inference and / or training the neural network, or some combination of these factors.

[0113] In at least one embodiment, Figure 8A The logic 815 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® processor from Intel (e.g., “Lake Crest”). In at least one embodiment, Figure 8A The logic 815 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate array (“FPGA”).

[0114] Figure 8B A logic 815 according to at least one embodiment is illustrated. In at least one embodiment, the logic 815 is inference and / or training logic. In at least one embodiment, the logic 815 may include, but is not limited to, hardware logic, wherein computational resources, along with weight values ​​or other information corresponding to one or more layers of neurons within a neural network, are used dedicatedly or otherwise exclusively. In at least one embodiment, Figure 8B The logic 815 shown can be used in conjunction with an application-specific integrated circuit (ASIC), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® processor from Intel (e.g., "Lake Crest"). In at least one embodiment, Figure 8B The logic 815 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field-programmable gate array (FPGA)). In at least one embodiment, logic 815 includes, but is not limited to, code and / or data storage 801 and code and / or data storage 805, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 8B In at least one embodiment shown, each of code and / or data storage 801 and code and / or data storage 805 is associated with dedicated computing resources (e.g., computing hardware 802 and computing hardware 806), respectively. In at least one embodiment, each of computing hardware 802 and computing hardware 806 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) on the information stored in code and / or data storage 801 and code and / or data storage 805, respectively, with the results stored in active memory 820.

[0115] In at least one embodiment, each of the code and / or data storage 801 and 805 and the corresponding computing hardware 802 and 806 corresponds to a different layer of the neural network, such that an activation obtained from one storage / computation pair 801 / 802 of the code and / or data storage 801 and computing hardware 802 is provided as input to the next storage / computation pair 805 / 806 of the code and / or data storage 805 and computing hardware 806, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 801 / 802 and 805 / 806 may correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) may be included in logic 815 following or in parallel with the storage / computation pairs 801 / 802 and 805 / 806.

[0116] Neural network training and deployment Figure 9 Training and deployment of a deep neural network according to at least one embodiment are illustrated. In at least one embodiment, an untrained neural network 906 is trained using a training dataset 902. In at least one embodiment, the training framework 904 is a PyTorch framework, while in other embodiments, the training framework 904 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 904 trains the untrained neural network 906 and enables it to be trained using the processing resources described herein to generate a trained neural network 908. In at least one embodiment, the weights may be randomly selected or selected by pre-training using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0117] In at least one embodiment, supervised learning is used to train an untrained neural network 906, wherein the training dataset 902 includes inputs paired with desired outputs for inputs, or wherein the training dataset 902 includes inputs with known outputs and the outputs of the neural network 906 are manually graded. In at least one embodiment, the untrained neural network 906 is trained in a supervised manner and processes inputs from the training dataset 902, comparing the resulting outputs with a set of expected or desired outputs. In at least one embodiment, the error is then backpropagated through the untrained neural network 906. In at least one embodiment, a training framework 904 adjusts the weights controlling the untrained neural network 906. In at least one embodiment, the training framework 904 includes tools for monitoring the degree to which the untrained neural network 906 converges to a model (such as a trained neural network 908) suitable for generating correct answers (such as results 914) based on input data (such as a new dataset 912). In at least one embodiment, the training framework 904 repeatedly trains the untrained neural network 906 while adjusting the weights to refine the output of the untrained neural network 906 using a loss function and tuning algorithms such as stochastic gradient descent. In at least one embodiment, the training framework 904 trains the untrained neural network 906 until the untrained neural network 906 reaches the desired accuracy. In at least one embodiment, the trained neural network 908 can then be deployed to implement any number of machine learning operations.

[0118] In at least one embodiment, unsupervised learning is used to train an untrained neural network 906, wherein the untrained neural network 906 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 902 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 906 can learn groupings within the training dataset 902 and can determine how each input relates to the untrained dataset 902. In at least one embodiment, unsupervised training can be used to generate a self-organizing graph in a trained neural network 908, which is capable of performing operations useful for reducing the dimensionality of a new dataset 912. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in the new dataset 912 that deviate from the normal patterns of the new dataset 912.

[0119] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 902. In at least one embodiment, the training framework 904 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 908 to adapt to a new dataset 912 without forgetting the knowledge injected into the trained neural network 908 during initial training.

[0120] In at least one embodiment, the training framework 904 is a framework processed in conjunction with a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is, for example, a toolkit developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes or uses logic 815 to perform the operations described herein. In at least one embodiment, a SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0121] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations, such as human visual simulation, speech recognition, natural language processing, recommender systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variations thereof.

[0122] In at least one embodiment, OpenVINO supports neural network models for a variety of tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., people and / or objects), monocular depth estimation, image inpainting, style transfer, action recognition, colorization, and / or variations thereof.

[0123] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command-line tool that facilitates the transition between training and deployment of a neural network model. In at least one embodiment, the model optimizer optimizes the neural network model for execution on various devices and / or processing units such as GPUs, CPUs, PPUs, GPGPUs, and / or variations thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes layers from the model used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying the model's input (e.g., adjusting the size of the model's input), modifying the size of the model's input (e.g., modifying the model's batch size), modifying the model's structure (e.g., modifying the model's layers), normalizing, standardizing, quantizing (e.g., converting the model's weights from a first representation such as floating-point to a second representation such as integer), and / or variations thereof.

[0124] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or any suitable programming language library. In at least one embodiment, the inference engine is used to infer input data. In at least one embodiment, the inference engine implements various classes to infer input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions to process intermediate representations, set input and / or output formats, and / or execute models on one or more devices.

[0125] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computational processes and / or systems utilizing one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or portions of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., executing a first set of layers on a first device (e.g., a GPU) and a second set of layers on a second device (e.g., a CPU).

[0126] In at least one embodiment, OpenVINO includes various functionalities similar to those associated with CUDA programming models, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or their variations. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0127] Data Center Figure 10 An example data center 1000 that can be used in at least one embodiment is shown. In at least one embodiment, the data center 1000 includes a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

[0128] In at least one embodiment, such as Figure 10As shown, the data center infrastructure layer 1010 may include a resource coordinator 1012, grouped computing resources 1014, and node computing resources (“nodes CR”) 1016(1)-1016(N), where “N” represents a positive integer (which may be an integer “N” different from the integers used in other diagrams). In at least one embodiment, nodes CR 1016(1)-1016(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1018(1)-1018(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 1016(1)-1016(N) may be servers having one or more of the aforementioned computing resources.

[0129] In at least one embodiment, the grouped computing resources 1014 may include individual groups of node CRs housed within one or more racks (not shown), or a plurality of racks housed within data centers (also not shown) in various geographical locations. In at least one embodiment, the individual groups of node CRs within the grouped computing resources 1014 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0130] In at least one embodiment, resource coordinator 1012 may be configured or otherwise control one or more nodes CR 1016(1)-1016(N) and / or grouped computing resources 1014. In at least one embodiment, resource coordinator 1012 may include a Software Design Infrastructure (“SDI”) management entity for data center 1000. In at least one embodiment, resource coordinator 1012 may include hardware, software, or some combination thereof.

[0131] In at least one embodiment, such as Figure 10As shown, framework layer 1020 includes job scheduler 1022, configuration manager 1024, resource manager 1026, and distributed file system 1028. In at least one embodiment, framework layer 1020 may include a framework of software 1032 supporting software layer 1030 and / or one or more applications 1042 supporting application layer 1040. In at least one embodiment, software 1032 or application 1042 may respectively include web-based service software or applications, such as service software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1020 may be, but is not limited to, a type of free and open-source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark") which can leverage distributed file system 1028 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 1022 may include Spark drivers for facilitating the scheduling of workloads supported by the various layers of data center 1000. In at least one embodiment, configuration manager 1024 may be able to configure different layers, such as software layer 1030 and framework layer 1020 including Spark and distributed file system 1028 for supporting large-scale data processing. In at least one embodiment, resource manager 1026 may be able to manage clustered or grouped computing resources mapped to or allocated to support distributed file system 1028 and job scheduler 1022. In at least one embodiment, clustered or grouped computing resources may include grouped computing resources 1014 at data center infrastructure layer 1010. In at least one embodiment, resource manager 1026 may coordinate with resource coordinator 1012 to manage these mapped or allocated computing resources.

[0132] In at least one embodiment, the software 1032 included in the software layer 1030 may include software used by at least portions of nodes CR1016(1)-1016(N), grouped computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0133] In at least one embodiment, one or more applications 1042 included in application layer 1040 may include one or more types of applications used by at least portions of nodes CR 1016(1)-1016(N), grouped computing resources 1014, and / or the distributed file system 1028 of framework layer 1020. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0134] In at least one embodiment, any of the configuration manager 1024, resource manager 1026, and resource coordinator 1012 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 1000 and can prevent underutilization and / or poor performance of the data center.

[0135] In at least one embodiment, data center 1000 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 1000. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 1000 by using weight parameters calculated through one or more training techniques described herein.

[0136] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0137] The logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 8A and / or Figure 8BDetails regarding logic 815 are provided. In at least one embodiment, logic 815 may be used in data center 1000 for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0138] Figures 1-10 At least one embodiment is used for the optimized deployment of one or more second neural networks in new platforms, computer systems, and any other hardware resources provided by, for example, NVIDIA, AMD, and Intel, by using one or more first neural networks. In at least one embodiment, the processor includes one or more circuitry for generating the one or more second versions of the one or more second neural networks using the one or more first neural networks, at least in part based on one or more first versions of the one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks are trained based on hardware features, software features, and software programs associated with multiple platforms, computer systems, and any other hardware resources.

[0139] Autonomous vehicles Figure 11A Examples of autonomous vehicles 1100 according to at least one embodiment are shown. In at least one embodiment, the autonomous vehicle 1100 (which may alternatively be referred to herein as "vehicle 1100") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle accommodating one or more passengers. In at least one embodiment, vehicle 1100 may be a semi-tractor-trailer truck for hauling goods. In at least one embodiment, vehicle 1100 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0140] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation in their “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of that standard). In at least one embodiment, vehicle 1100 may be able to have one or more functions according to levels 1 through 5 of autonomous driving levels. For example, in at least one embodiment, vehicle 1100 may be able to have conditional automation (level 3), high automation (level 4), and / or full automation (level 5), depending on the embodiment.

[0141] In at least one embodiment, vehicle 1100 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1100 may include, but is not limited to, propulsion system 1150, such as an internal combustion engine, a hybrid powertrain, a fully electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1150 may be connected to the drivetrain of vehicle 1100, which may include, but is not limited to, a transmission, for enabling propulsion of vehicle 1100. In at least one embodiment, propulsion system 1150 may be controlled in response to receiving a signal from throttle / accelerator 1152.

[0142] In at least one embodiment, when the propulsion system 1150 is operating (e.g., when the vehicle 1100 is in motion), the steering system 1154 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 1100 (e.g., along a desired path or route). In at least one embodiment, the steering system 1154 may receive signals from the steering actuator 1156. In at least one embodiment, for fully automated (Level 5) functionality, the steering wheel may be optional. In at least one embodiment, the brake sensor system 1146 may be used to operate the vehicle brakes in response to signals received from the brake actuator 1148 and / or brake sensors.

[0143] In at least one embodiment, one or more controllers 1136 may include, but are not limited to, one or more systems-on-a-chip (“SoC”). Figure 11A(not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1100. For example, in at least one embodiment, one or more controllers 1136 may send signals to operate vehicle braking via brake actuator 1148, to operate steering system 1154 via one or more steering actuators 1156, and to operate propulsion system 1150 via one or more throttle / accelerators 1152. In at least one embodiment, one or more controllers 1136 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1100. In at least one embodiment, one or more controllers 1136 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the functions described above, and two or more controllers may handle a single function and / or any combination thereof.

[0144] In at least one embodiment, one or more controllers 1136 provide signals for controlling one or more components and / or systems of vehicle 1100 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from, for example, but not limited to, the following sensors: one or more Global Navigation Satellite System (“GNSS”) sensors 1158 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1160, one or more ultrasonic sensors 1162, one or more LIDAR sensors 1164, one or more inertial measurement unit (IMU) sensors 1166 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1196, one or more stereo cameras 1168, one or more wide-angle cameras 1170 (e.g., fisheye cameras), one or more infrared cameras 1172, one or more surround cameras 1174 (e.g., 360-degree cameras), remote cameras ( Figure 11A (not shown in the image), medium-range camera ( Figure 11A(not shown), one or more speed sensors 1144 (e.g., for measuring the speed of vehicle 1100), one or more vibration sensors 1142, one or more steering sensors 1140, one or more brake sensors (e.g., as part of brake sensor system 1146) and / or other sensor types.

[0145] In at least one embodiment, one or more controllers 1136 may receive input (e.g., represented by input data) from the dashboard 1132 of the vehicle 1100 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1134, a voice signaler, a speaker, and / or via other components of the vehicle 1100. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 11A The HMI display 1134 may display information such as (not shown), location data (e.g., the location of vehicle 1100, for example on a map), direction, the location of other vehicles (e.g., occupying a grid), information about objects, and the state of objects perceived by one or more controllers 1136. For example, in at least one embodiment, the HMI display 1134 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers that have been, are being, or will be made (e.g., changing lanes now, reaching exit 34B within two miles, etc.).

[0146] In at least one embodiment, vehicle 1100 further includes a network interface 1124 that can communicate over one or more networks using one or more wireless antennas 1126 and / or one or more modems. For example, in at least one embodiment, network interface 1124 may be able to communicate over Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1126 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (“LPWAN”) (such as LoRaWAN, SigFox, etc. protocols).

[0147] The logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 8A and / or Figure 8BDetails regarding logic 815 are provided. In at least one embodiment, logic 815 may be used in vehicle 1000 for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0148] Figures 1-11A At least one embodiment is used for the optimized deployment of one or more second neural networks in new platforms, computer systems, and any other hardware resources provided by, for example, NVIDIA, AMD, and Intel, by using one or more first neural networks. In at least one embodiment, the processor includes one or more circuitry for generating the one or more second versions of the one or more second neural networks using the one or more first neural networks, at least in part based on one or more first versions of the one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks are trained based on hardware features, software features, and software programs associated with multiple platforms, computer systems, and any other hardware resources.

[0149] Figure 11B The illustration shows an embodiment according to at least one of the embodiments. Figure 11A Examples of camera positions and fields of view for the autonomous vehicle 1100. In at least one embodiment, the camera and its respective field of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 1100.

[0150] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for use with components and / or systems of vehicle 1100. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or combinations thereof. In at least one embodiment, the color filter array may include a red transparent transparent transparent (“RCCC”) color filter array, a red transparent transparent blue (“RCCB”) color filter array, a red blue green transparent (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera having RCCC, RCCB, and / or RBGC color filter arrays, may be used to improve photosensitivity.

[0151] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0152] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (three-dimensional (“3D” printed) assembly, to remove stray light and reflected light from within the vehicle 1100 (e.g., reflected light from the dashboard reflected in the windshield mirror), which may interfere with the camera’s image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated into four pillars at each corner of the cabin.

[0153] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including portions of the environment in front of the vehicle 1100 can be used for surround view to help identify the path and obstacles ahead, and to assist in providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path, with the help of one or more controllers 1136 and / or control SoCs. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions such as traffic sign recognition.

[0154] In at least one embodiment, a variety of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal-oxide-semiconductor” color imager. In at least one embodiment, a wide-angle camera 1170 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Figure 11B Only one wide-angle camera 1170 is shown, but in other embodiments, the vehicle 1100 may have any number (including zero) of wide-angle cameras. In at least one embodiment, any number of remote cameras 1198 (e.g., a pair of telescopic stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, one or more remote cameras 1198 can also be used for object detection and classification, as well as basic object tracking.

[0155] In at least one embodiment, any number of stereo cameras 1168 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1168 may include an integrated control unit comprising a scalable processing unit that can provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of vehicle 1100, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1168 may include, but are not limited to, a compact stereo vision sensor, which may include, but is not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from vehicle 1100 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1168 may be used in addition to or instead of those described herein.

[0156] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including portions of the environment on the sides of the vehicle 1100 can be used for surround view, providing information for creating and updating the occupied grid, and generating a side impact collision warning. For example, in at least one embodiment, a surround camera 1174 (e.g., such as...) Figure 11B The four surround cameras shown can be positioned on vehicle 1100. In at least one embodiment, one or more surround cameras 1174 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras can be located at the front, rear, and sides of vehicle 1100. In at least one embodiment, vehicle 1100 can use three surround cameras 1174 (e.g., left, right, and rear) and can utilize one or more other cameras (e.g., forward-facing cameras) as a fourth surround-view camera.

[0157] In at least one embodiment, a camera (e.g., a rear-view camera) having a field of view including portions of the environment behind vehicle 1100 can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1198 and / or one or more mid-range cameras 1176, one or more stereo cameras 1168, one or more infrared cameras 1172, etc.), as described herein.

[0158] Figures 1-11B At least one embodiment is used for the optimized deployment of one or more second neural networks in new platforms, computer systems, and any other hardware resources provided by, for example, NVIDIA, AMD, and Intel, by using one or more first neural networks. In at least one embodiment, the processor includes one or more circuitry for generating the one or more second versions of the one or more second neural networks using the one or more first neural networks, at least in part based on one or more first versions of the one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks are trained based on hardware features, software features, and software programs associated with multiple platforms, computer systems, and any other hardware resources.

[0159] Figure 11C It is shown that according to at least one embodiment Figure 11AA block diagram of an example system architecture for an autonomous vehicle 1100. In at least one embodiment, Figure 11C Each component, feature, and system of vehicle 1100 is shown connected via bus 1102. In at least one embodiment, bus 1102 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as “CAN bus”). In at least one embodiment, CAN may be a network within vehicle 1100 for assisting in the control of various features and functions of vehicle 1100, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1102 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 1102 may be read to locate steering wheel angle, ground speed, engine revolutions per minute (“RPM”), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1102 may be an ASIL B compliant CAN bus.

[0160] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, any number of buses forming bus 1102 may be present, including but not limited to zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for a collision avoidance function, and a second bus may be used for actuation control. In at least one embodiment, each bus in bus 1102 may communicate with any component of vehicle 1100, and two or more buses in bus 1102 may communicate with corresponding components. In at least one embodiment, each of any number of System-on-Chip (“SoC”) 1104 (e.g., SoC 1104(A) and SoC 1104(B)), each of one or more controllers 1136 and / or each computer within the vehicle can access the same input data (e.g., input from sensors of vehicle 1100) and can be connected to a common bus, such as a CAN bus.

[0161] In at least one embodiment, vehicle 1100 may include one or more controllers 1136, such as those described herein. Figure 11AAs described above. In at least one embodiment, controller 1136 can be used for a wide variety of functions. In at least one embodiment, controller 1136 can be coupled to any of various other components and systems of vehicle 1100 and can be used to control vehicle 1100, artificial intelligence of vehicle 1100, infotainment and / or other functions of vehicle 1100.

[0162] In at least one embodiment, vehicle 1100 may include any number of SoCs 1104. In at least one embodiment, each of the SoCs 1104 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1106, a graphics processing unit (“one or more GPUs”) 1108, one or more processors 1110, one or more caches 1112, one or more accelerators 1114, one or more data storage 1116, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1104 may be used to control vehicle 1100 on a wide variety of platforms and systems. For example, in at least one embodiment, one or more SoCs 1104 may be combined with a high-definition (“HD”) map 1122 in a system (e.g., the system of vehicle 1100), which may be located from one or more servers via a network interface 1124. Figure 11C (Not shown in the image) Get map refresh and / or update.

[0163] In at least one embodiment, one or more CPUs 1106 may include CPU clusters or CPU complexes (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1106 may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPUs 1106 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, one or more CPUs 1106 may include four dual-core clusters, each with a dedicated L2 cache (e.g., 2 megabytes (MB) L2 cache). In at least one embodiment, one or more CPUs 1106 (e.g., CCPLEX) may be configured to support simultaneous cluster operation, which allows any combination of clusters of one or more CPUs 1106 to be active at any given time.

[0164] In at least one embodiment, one or more CPUs 1106 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware blocks to conserve dynamic power when idle; clock gating of each core when the core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Wait for Event (“WFE”) instructions; power gating of each core independently; clock gating of each core cluster independently when all cores are clock-gated or power-gated; and / or power gating of each core cluster independently when all cores are power-gated. In at least one embodiment, one or more CPUs 1106 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state to input for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, wherein work is offloaded to the microcode.

[0165] In at least one embodiment, one or more GPUs 1108 may include integrated GPUs (which may alternatively be referred to herein as “iGPUs”). In at least one embodiment, one or more GPUs 1108 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1108 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1108 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 (“L1”) cache (e.g., an L1 cache with at least 96 KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512 KB of storage capacity). In at least one embodiment, one or more GPUs 1108 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1108 may use one or more computation application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1108 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA’s CUDA model).

[0166] In at least one embodiment, one or more GPU 1108s may be power-optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPU 1108s may be fabricated on FinFET (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may comprise multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a scheduler (e.g., a thread bundle scheduler) or sequencer, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths for employing a mixture of computation and addressing operations to provide efficient execution of workloads. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0167] In at least one embodiment, one or more GPUs 1108 may include high-bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem, used in some examples to provide a peak memory bandwidth of approximately 900 GB / s. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”), such as fifth-generation graphics double data rate type synchronous random access memory (“GDDR5”), may also be used.

[0168] In at least one embodiment, one or more GPUs 1108 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support can be used to allow one or more GPUs 1108 to directly access the page tables of one or more CPUs 1106. In at least one embodiment, when the memory management unit (“MMU”) of one or more GPUs 1108 experiences a miss, an address translation request can be sent to one or more CPUs 1106. In response, in at least one embodiment, two CPUs of one or more CPUs 1106 can look up the virtual-physical mapping of the address in their page tables and send the translation back to one or more GPUs 1108. In at least one embodiment, unified memory technology can allow a single unified virtual address space to be used for the memory of both one or more CPUs 1106 and one or more GPUs 1108, thereby simplifying the programming of one or more GPUs 1108 and the porting of applications to one or more GPUs 1108.

[0169] In at least one embodiment, one or more GPUs 1108 may include any number of access counters that can track the frequency with which one or more GPUs 1108 access the memory of other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of sharing memory ranges among processors.

[0170] In at least one embodiment, one or more SoCs 1104 may include any number of caches 1112, including those described herein. For example, in at least one embodiment, one or more caches 1112 may include a Level 3 (“L3”) cache that can be used for both one or more CPUs 1106 and one or more GPUs 1108 (e.g., connected to one or more CPUs 1106 and one or more GPUs 1108). In at least one embodiment, one or more caches 1112 may include a write-back cache that can track the state of each row, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, depending on the embodiment, the L3 cache may include 4 MB of memory or more.

[0171] In at least one embodiment, one or more SoCs 1104 may include one or more accelerators 1114 (e.g., hardware accelerators, software accelerators, or combinations thereof). In at least one embodiment, one or more SoCs 1104 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1108 and offload some tasks from one or more GPUs 1108 (e.g., to free up more cycles of one or more GPUs 1108 to perform other tasks). In at least one embodiment, one or more accelerators 1114 may be used for a target workload (e.g., perceptual, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.) that is sufficiently stable to withstand acceleration. In at least one embodiment, the CNN may include region-based or region-based convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0172] In at least one embodiment, one or more accelerators 1114 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, the TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, rapidly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphones; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for protection and / or safety-related events.

[0173] In at least one embodiment, one or more DLAs can perform any function of one or more GPUs 1108, and by using inference accelerators, for example, the designer can target one or more DLAs or one or more GPUs 1108 for any function. For example, in at least one embodiment, the designer can concentrate the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 1108 and / or one or more accelerators 1114.

[0174] In at least one embodiment, one or more accelerators 1114 may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, a PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1138, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, a PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0175] In at least one embodiment, the RISC core can interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, depending on the embodiment, the RISC core may use any of a variety of protocols. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0176] In at least one embodiment, DMA enables components of the PVA to access system memory independently of one or more CPUs 1106. In at least one embodiment, DMA can support any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0177] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly perform programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may operate as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as, for example, a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0178] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Therefore, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute general computer vision algorithms, but on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on a single image, or even execute different algorithms on a sequence of images or different portions of an image. In at least one embodiment, any number of PVAs may be included in the hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code (“ECC”) memory for enhancing overall system security.

[0179] In at least one embodiment, one or more accelerators 1114 may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 1114. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an Advanced Peripheral Bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0180] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0181] In at least one embodiment, one or more SoCs 1104 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to rapidly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0182] In at least one embodiment, one or more accelerators 1114 may have broad applications for autonomous driving. In at least one embodiment, PVAs may be used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVAs with low power consumption and low latency are well-matched to algorithmic domains requiring predictable processing. In other words, PVAs perform well in semi-intensive or intensive conventional computations, even on small datasets that may require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in vehicle 1100, PVAs may be designed to run classical computer vision algorithms, as they can be efficient in object detection and integer mathematical operations.

[0183] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure reconstruction from motion, pedestrian recognition, lane detection, etc.) during operation. In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0184] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, for example, the PVA is used to perform time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data.

[0185] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks, whose output is a measurement of confidence for each object detection. In at least one embodiment, the confidence can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. In at least one embodiment, the confidence measurement enables the system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, the system can set a threshold for the confidence and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence values. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, ground plane estimate (e.g., from another subsystem), and outputs of one or more IMU sensors 1166 related to vehicle 1100 orientation, distance, and object 3D position estimates obtained from the neural network and / or other sensors (e.g., one or more LiDAR sensors 1164 or one or more RADAR sensors 1160).

[0186] In at least one embodiment, one or more SoCs 1104 may include one or more data stores 1116 (e.g., memory). In at least one embodiment, one or more data stores 1116 may be on-chip memory of one or more SoCs 1104, which may store neural networks to be executed on one or more GPUs 1108 and / or DLAs. In at least one embodiment, one or more data stores 1116 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data stores 1116 may include one or more L2 or L3 caches.

[0187] In at least one embodiment, one or more SoCs 1104 may include any number of processors 1110 (e.g., embedded processors). In at least one embodiment, one or more processors 1110 may include a startup and power management processor, which may be a dedicated processor and subsystem for handling startup power and management functions, as well as associated security execution. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 1104 and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 1104s, and / or power state management of one or more SoCs 1104s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 1104s may use the ring oscillator to detect the temperature of one or more CPUs 1106, one or more GPUs 1108, and / or one or more accelerators 1114. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 1104 in a lower power state and / or place the vehicle 1100 in a driver safe parking mode (e.g., bring the vehicle 1100 to a safe stop).

[0188] In at least one embodiment, one or more processors 1110 may further include a set of embedded processors that can be used as an audio processing engine. The audio processing engine may be an audio subsystem that provides full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor having dedicated RAM.

[0189] In at least one embodiment, one or more processors 1110 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, support for peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0190] In at least one embodiment, one or more processors 1110 may further include a security cluster engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the security cluster engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In a secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1110 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1110 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0191] In at least one embodiment, one or more processors 1110 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video playback applications to generate final images for video post-processing functions required by the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1170, one or more surround cameras 1174, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, the in-cabin monitoring camera sensors are monitored by a neural network running on another instance of SoC 1104, the neural network being configured to recognize in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, and are otherwise disabled.

[0192] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for both spatial and temporal noise reduction. For example, in at least one embodiment, in the case of motion in the video, denoising appropriately weights spatial information to reduce the weight of information provided by adjacent frames. In at least one embodiment, in the case where the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0193] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereoscopic shot frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing, and does not require one or more GPUs 1108 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1108 are powered and active for 3D rendering, the video image compositor can be used to offload one or more GPUs 1108 to improve performance and responsiveness.

[0194] In at least one embodiment, one or more SoCs of SoC 1104 may further include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs of SoC 1104 may further include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0195] In at least one embodiment, one or more SoCs of SoC 1104 may further include extensive peripheral interfaces for enabling communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. In at least one embodiment, one or more SoCs of SoC 1104 may be used to process data from (e.g., connected via gigabit multimedia serial links and Ethernet channels) cameras, sensors (e.g., one or more LiDAR sensors 1164, one or more RADAR sensors 1160, etc., which may be connected via Ethernet channels), data from bus 1102 (e.g., vehicle 1100 speed, steering wheel position, etc.), data from one or more GNSS sensors 1158 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more SoCs of SoC 1104 may further include dedicated high-performance large-scale memory controllers, which may include their own DMA engines and may be used to free one or more CPUs of SoC 1106 from routine data management tasks.

[0196] In at least one embodiment, one or more SoCs 1104 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy, and provides a platform for a flexible, reliable driving software stack and deep learning tools. In at least one embodiment, one or more SoCs 1104 can be faster, more reliable, and even more energy- and space-efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1114, when combined with one or more CPUs 1106, one or more GPUs 1108, and one or more data storage 1116, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0197] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute various processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0198] The embodiments described herein allow for the simultaneous and / or sequential execution of multiple neural networks and allow for the combination of results to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPUs 1120) may include text and word recognition, thereby allowing the reading and understanding of traffic signs, including signs for which the neural network has not yet been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing a semantic understanding of the signs, and passing this semantic understanding to a path planning module running on a CPU complex.

[0199] In at least one embodiment, multiple neural networks can operate simultaneously for driving levels 3, 4, or 5. For example, in at least one embodiment, a warning sign stating "Caution: flashing lights indicate icy conditions," along with the lights, can be interpreted independently or jointly by several neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which informs the vehicle's path planning software (preferably executing on a CPU complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can operate simultaneously, for example within the DLA and / or on one or more GPUs 1108.

[0200] In at least one embodiment, the CNN for face recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 1100. In at least one embodiment, a normally open sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in a safe mode, it can be used to disable the vehicle when the owner leaves it. In this way, one or more SoCs 1104 provide protection against theft and / or carjacking.

[0201] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 1196 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1104 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, such as those identified by one or more GNSS sensors 1158. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1162, to execute emergency vehicle safety routines, such as slowing the vehicle, pulling the vehicle to the side of the road, stopping, and / or idling the vehicle until the emergency vehicle passes.

[0202] In at least one embodiment, vehicle 1100 may include one or more CPUs 1118 (e.g., one or more discrete CPUs or one or more dCPUs) coupled to one or more SoCs 1104 via high-speed interconnects (e.g., PCIe). In at least one embodiment, one or more CPUs 1118 may include, for example, x86 processors. One or more CPUs 1118 may be used to perform any of a variety of functions, such as arbitrating potentially inconsistent results between ADAS sensors and one or more SoCs 1104, and / or monitoring the status and health of one or more controllers 1136 and / or the on-chip infotainment system (“infotainment SoC”) 1130. In at least one embodiment, one or more SoCs 1104 include one or more interconnects, and the interconnects may include Fast Peripheral Component Interconnect (PCIe).

[0203] In at least one embodiment, vehicle 1100 may include one or more GPUs 1120 (e.g., one or more discrete GPUs or one or more dGPUs) coupled to one or more SoCs 1104 via high-speed interconnects (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 1120 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on inputs from sensors of vehicle 1100 (e.g., sensor data).

[0204] In at least one embodiment, vehicle 1100 may further include a network interface 1124, which may include, but is not limited to, one or more wireless antennas 1126 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1124 may be used to enable wireless connectivity to Internet cloud services (e.g., with servers and / or other network devices), with other vehicles, and / or with computing devices (e.g., passenger client devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and the Internet) may be established between vehicle 1100 and another vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1100 with information about vehicles near vehicle 1100 (e.g., vehicles in front, to the side, and / or behind vehicle 1100). In at least one embodiment, the foregoing functionality may be part of a cooperative adaptive cruise control function of vehicle 1100.

[0205] In at least one embodiment, network interface 1124 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 1136 to communicate over a wireless network. In at least one embodiment, network interface 1124 may include a radio frequency (RF) front-end for up-conversion from baseband to RF and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed using known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0206] In at least one embodiment, vehicle 1100 may further include one or more data storage units 1128, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoC 1104) storage. In at least one embodiment, one or more data storage units 1128 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0207] In at least one embodiment, vehicle 1100 may further include one or more GNSS sensors 1158 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy grid generation, and / or route planning functions. In at least one embodiment, any number of GNSS sensors 1158 may be used, including, for example, but not limited to, GPS sensors using a USB connector with an Ethernet-to-serial interface (e.g., RS-232) bridge.

[0208] In at least one embodiment, vehicle 1100 may further include one or more RADAR sensors 1160. In at least one embodiment, one or more RADAR sensors 1160 may be used by vehicle 1100 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 1160 may use a CAN bus and / or bus 1102 (e.g., for transmitting data generated by one or more RADAR sensors 1160) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, but not limited to, one or more RADAR sensors 1160 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the RADAR sensors 1160 are pulse Doppler RADAR sensors.

[0209] In at least one embodiment, one or more RADAR sensors 1160 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 250m range). In at least one embodiment, one or more RADAR sensors 1160 can help distinguish between static and moving objects and can be used by the ADAS system 1138 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1160 included in the long-range RADAR system may include, but are not limited to, a monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, employing six antennas, the four central antennas can create a focused beammap designed to record the surrounding environment of the vehicle 1100 at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling them to quickly detect vehicles entering or leaving the lane of vehicle 1100.

[0210] In at least one embodiment, as an example, a mid-range RADAR system may include a range of up to 160m (front) or 80m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1160 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rearward direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system may be used in ADAS system 1138 for blind spot detection and / or lane change assistance.

[0211] In at least one embodiment, vehicle 1100 may further include one or more ultrasonic sensors 1162. In at least one embodiment, one or more ultrasonic sensors 1162, which may be positioned at the front, rear, and / or sides of vehicle 1100, may be used for parking assistance and / or creating and updating occupancy grids. In at least one embodiment, a wide variety of ultrasonic sensors 1162 may be used, and different ultrasonic sensors 1162 may be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 1162 may operate at ASIL B functional safety level.

[0212] In at least one embodiment, vehicle 1100 may include one or more LiDAR sensors 1164. In at least one embodiment, one or more LiDAR sensors 1164 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LiDAR sensors 1164 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1100 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 1164 that can use Ethernet channels (e.g., to provide data to a Gigabit Ethernet switch).

[0213] In at least one embodiment, one or more LiDAR sensors 1164 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 1164 may, for example, have an advertising range of approximately 100m, an accuracy of 2cm-3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors may be used. In such an embodiment, one or more LiDAR sensors 1164 may include small devices that can be embedded in the front, rear, side, and / or corner locations of vehicle 1100. In at least one embodiment, one or more LiDAR sensors 1164, in such an embodiment, may provide up to 120 degrees of horizontal field of view and 35 degrees of vertical field of view, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, one or more forward-mounted LiDAR sensors 1164 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0214] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate the area around vehicle 1100 up to approximately 200m. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the propagation time of the laser pulse and the reflected light on each pixel, which in turn corresponds to the range from vehicle 1100 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of vehicle 1100. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture reflected laser light as a 3D ranging point cloud and co-registered intensity data.

[0215] In at least one embodiment, vehicle 1100 may further include one or more IMU sensors 1166. In at least one embodiment, one or more IMU sensors 1166 may be located at the center of the rear axle of vehicle 1100. In at least one embodiment, one or more IMU sensors 1166 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1166 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1166 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0216] In at least one embodiment, one or more IMU sensors 1166 can be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, one or more IMU sensors 1166 enable vehicle 1100 to estimate its heading by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1166, without requiring input from a magnetic sensor. In at least one embodiment, one or more IMU sensors 1166 and one or more GNSS sensors 1158 can be combined in a single integrated unit.

[0217] In at least one embodiment, vehicle 1100 may include one or more microphones 1196 placed inside and / or around vehicle 1100. In at least one embodiment, one or more microphones 1196 may be used for emergency vehicle detection and identification.

[0218] In at least one embodiment, vehicle 1100 may further include any number of camera types, including one or more stereo cameras 1168, one or more wide-angle cameras 1170, one or more infrared cameras 1172, one or more surround cameras 1174, one or more long-range cameras 1198, one or more mid-range cameras 1176, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 1100. In at least one embodiment, the type of camera used depends on vehicle 1100. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 1100. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1100 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may support, by way of example but not limited to, gigabit multimedia serial link (“GMSL”) and / or gigabit Ethernet communication. In at least one embodiment, references previously made herein... Figure 11A and Figure 11B Each camera is described in more detail.

[0219] In at least one embodiment, vehicle 1100 may further include one or more vibration sensors 1142. In at least one embodiment, one or more vibration sensors 1142 may measure vibrations of components of vehicle 1100 (e.g., axles). For example, in at least one embodiment, changes in vibration may indicate changes in road surface. In at least one embodiment, when two or more vibration sensors 1142 are used, differences between vibrations may be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a free-rotating axle).

[0220] In at least one embodiment, vehicle 1100 may include ADAS system 1138. In at least one embodiment, ADAS system 1138 may include, but is not limited to, SoC in some examples. In at least one embodiment, ADAS system 1138 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control (“ACC”) system, cooperative adaptive cruise control (“CACC”) system, forward collision warning (“FCW”) system, automatic emergency braking (“AEB”) system, lane departure warning (“LDW”) system, lane keeping assist (“LKA”) system, blind spot warning (“BSW”) system, rear cross traffic warning (“RCTW”) system, collision warning (“CW”) system, lane centering (“LC”) system and / or other systems, features and / or functions.

[0221] In at least one embodiment, the ACC system may use one or more RADAR sensors 1160, one or more LIDAR sensors 1164, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of vehicle 1100 and automatically adjusts the speed of vehicle 1100 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance holding and suggests that vehicle 1100 change lanes if necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0222] In at least one embodiment, the CACC system uses information from other vehicles, which may be received indirectly from other vehicles via a wireless link or through a network connection (e.g., via the Internet) via network interface 1124 and / or one or more wireless antennas 1126. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Typically, V2V communication provides information about the vehicle immediately ahead (e.g., a vehicle immediately in front of vehicle 1100 and in the same lane as it), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicles ahead of vehicle 1100, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0223] In at least one embodiment, the FCW system is designed to warn the driver of danger so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration components. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual, haptic, and / or rapid braking pulses.

[0224] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply braking if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system may automatically apply braking to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or collision proximity braking.

[0225] In at least one embodiment, when vehicle 1100 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is not activated when the driver indicates intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1100 begins to leave its lane, the LKA system provides steering input or braking to correct vehicle 1100.

[0226] In at least one embodiment, the BSW system detects and warns the driver that the vehicle is in the blind spot of the car. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses turn signals. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback such as a display, speaker, and / or vibration components.

[0227] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when the vehicle 1100 detects an object outside the range of the rear camera while reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure that vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as displays, speakers, and / or vibration components.

[0228] In at least one embodiment, conventional ADAS systems may be prone to generating false alarms, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, vehicle 1100 decides for itself whether to follow the result of the main computer or auxiliary computer (e.g., the first or second controller in controller 1136). For example, in at least one embodiment, ADAS system 1138 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, a backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, output from ADAS system 1138 may be provided to a supervisory MCU. In at least one embodiment, if output from the main computer and output from the auxiliary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0229] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU, indicating the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflict), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0230] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the auxiliary computer provides a false alarm based on outputs from a host computer and an auxiliary computer. In at least one embodiment, one or more neural networks in the supervisory MCU may learn when the outputs of the auxiliary computer can be trusted and when they cannot. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, one or more neural networks in the supervisory MCU may learn when the FCW system is recognizing a metallic object that is not actually dangerous, such as a drain grille or manhole cover that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC 1104s.

[0231] In at least one embodiment, the ADAS system 1138 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and the not-quite-same software code running on the auxiliary computer provides consistent overall results, the supervisory MCU can have greater confidence that the overall results are correct, and that the vulnerability in the software or hardware on the host computer will not lead to a major error.

[0232] In at least one embodiment, the output of the ADAS system 1138 may be fed into the perception block and / or the dynamic driving task block of the main computer. For example, in at least one embodiment, if the ADAS system 1138 indicates a forward collision warning due to an object directly ahead, the perception block may use the information when the object is identified. In at least one embodiment, as described herein, the assistance computer may have its own neural network, which is trained to reduce the risk of false alarms.

[0233] In at least one embodiment, vehicle 1100 may further include an infotainment SoC 1130 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1130 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1130 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to vehicle 1100. For example, the infotainment SoC 1130 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, in-vehicle computer, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 1134, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 1130 may further be used to provide information (e.g., visual and / or auditory information) to one or more users of the vehicle 1100, such as information from ADAS system 1138, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0234] In at least one embodiment, the infotainment SoC 1130 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1130 may communicate with other devices, systems, and / or components of the vehicle 1100 via bus 1102. In at least one embodiment, the infotainment SoC 1130 may be coupled to a supervisory MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of one or more main controllers 1136 (e.g., the main computer and / or backup computer of the vehicle 1100). In at least one embodiment, the infotainment SoC 1130 may place the vehicle 1100 into a driver-to-safe parking mode, as described herein.

[0235] In at least one embodiment, vehicle 1100 may further include instrument panel 1132 (e.g., digital instrument panel, electronic instrument panel, digital instrument cluster, etc.). In at least one embodiment, instrument panel 1132 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). In at least one embodiment, instrument panel 1132 may include, but is not limited to, any number and combination of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1130 and instrument panel 1132. In at least one embodiment, instrument panel 1132 may be included as part of infotainment SoC 1130, or vice versa.

[0236] Figures 1-11C At least one embodiment is used for the optimized deployment of one or more second neural networks in new platforms, computer systems, and any other hardware resources provided by, for example, NVIDIA, AMD, and Intel, by using one or more first neural networks. In at least one embodiment, the processor includes one or more circuitry for generating the one or more second versions of the one or more second neural networks using the one or more first neural networks, at least in part based on one or more first versions of the one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks are trained based on hardware features, software features, and software programs associated with multiple platforms, computer systems, and any other hardware resources.

[0237] Figure 11D It is based on at least one embodiment in one or more cloud-based servers and Figure 11AA diagram of a system for communication between autonomous vehicles 1100. In at least one embodiment, the system may include, but is not limited to, one or more servers 1178, one or more networks 1190, and any number and type of vehicles, including vehicle 1100. In at least one embodiment, one or more servers 1178 may include, but is not limited to, multiple GPUs 1184(A)-1184(H) (collectively referred to herein as GPU 1184), PCIe switches 1182(A)-1182(D) (collectively referred to herein as PCIe switch 1182), and / or CPUs 1180(A)-1180(B) (collectively referred to herein as CPU 1180). In at least one embodiment, GPU 1184, CPU 1180, and PCIe switch 1182 may be interconnected with high-speed interconnects, such as, for example, but not limited to, NVLink interface 1188 developed by NVIDIA and / or PCIe connection 1186. In at least one embodiment, the GPU 1184 is connected via NVLink and / or NVSwitch SoC, and the GPU 1184 and PCIe switch 1182 are connected via PCIe interconnect. Although eight GPUs 1184, two CPUs 1180, and four PCIe switches 1182 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 1178 may include, but is not limited to, any number of GPUs 1184, CPUs 1180, and / or PCIe switches 1182 in any combination. For example, in at least one embodiment, one or more servers 1178 may each include eight, sixteen, thirty-two, and / or more GPUs 1184.

[0238] In at least one embodiment, one or more servers 1178 may receive image data representing images from vehicles via one or more networks 1190, the images showing unexpected or changed road conditions, such as recently commenced roadworks. In at least one embodiment, one or more servers 1178 may send updated neural network 1192 and / or map information 1194 to vehicles via one or more networks 1190, including but not limited to information about traffic and road conditions. In at least one embodiment, updates to map information 1194 may include, but are not limited to, updates to HD map 1122, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, neural network 1192 and / or map information 1194 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed at a data center (e.g., using one or more servers 1178 and / or other servers).

[0239] In at least one embodiment, one or more servers 1178 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., sent to the vehicle via one or more networks 1190, and / or the machine learning model may be used by one or more servers 1178 to remotely monitor the vehicle).

[0240] In at least one embodiment, one or more servers 1178 may receive data from the vehicle and apply the data to a state-of-the-art real-time neural network for real-time intelligent inference. In at least one embodiment, one or more servers 1178 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1184, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1178 may include a deep learning infrastructure in a data center using CPU power.

[0241] In at least one embodiment, the deep learning infrastructure of one or more servers 1178 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processor, software, and / or associated hardware in vehicle 1100. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1100, such as image sequences and / or objects located by vehicle 1100 in the image sequences (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1100, and if the results do not match and the deep learning infrastructure determines that the AI ​​in vehicle 1100 is malfunctioning, one or more servers 1178 may signal to vehicle 1100, instructing vehicle 1100's fail-safe computer to take control, notify passengers, and complete a safe stopping operation.

[0242] In at least one embodiment, one or more servers 1178 may include one or more GPUs 1184 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration enables real-time response. In at least one embodiment, servers driven by CPUs, FPGAs, and other processors may be used for inference, such as in situations where performance is less critical. In at least one embodiment, one or more hardware structures 815 are used to execute one or more embodiments. This document incorporates... Figure 8A and / or Figure 8B Provide details about the 815 hardware architecture.

[0243] Computer System Figure 12 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system with interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof formed with a processor, which may include an execution unit for executing instructions. In at least one embodiment, according to this disclosure, such as in the embodiments described herein, computer system 1200 may include, but is not limited to, components such as processor 1202 for employing execution units (including logic) to execute algorithms for process data. In at least one embodiment, computer system 1200 may include a processor, such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™ or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, the computer system 1200 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0244] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system capable of executing one or more instructions according to at least one embodiment.

[0245] In at least one embodiment, the computer system 1200 may include, but is not limited to, a processor 1202, which may include, but is not limited to, one or more execution units 1208 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 1200 is a single-processor desktop or server system, but in another embodiment, the computer system 1200 may be a multiprocessor system. In at least one embodiment, the processor 1202 may include, but is not limited to, for example, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1202 may be coupled to a processor bus 1210, which can transmit data signals between the processor 1202 and other components in the computer system 1200.

[0246] In at least one embodiment, processor 1202 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1204. In at least one embodiment, processor 1202 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside external to processor 1202. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 1206 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0247] In at least one embodiment, an execution unit 1208, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1202. In at least one embodiment, the processor 1202 may also include a microcode (“ucode”) read-only memory (“ROM”) storing microcode of certain macro instructions. In at least one embodiment, the execution unit 1208 may include logic for processing a packaged instruction set 1209. In at least one embodiment, by including the packaged instruction set 1209 in the instruction set of the general-purpose processor and the associated circuitry to be executed, packaged data in the processor 1202 can be used to perform operations used by numerous multimedia applications. In at least one embodiment, numerous multimedia applications can be accelerated and executed more efficiently by using the full width of the processor’s data bus to perform operations on the packaged data, eliminating the need to transfer smaller data units on the processor’s data bus to perform one or more operations on one data element at a time.

[0248] In at least one embodiment, execution unit 1208 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1200 may include, but is not limited to, memory 1220. In at least one embodiment, memory 1220 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. In at least one embodiment, memory 1220 may store one or more instructions 1219 and / or data 1221 represented by data signals executable by processor 1202.

[0249] In at least one embodiment, the system logic chip may be coupled to processor bus 1210 and memory 1220. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1216, and processor 1202 may communicate with MCH 1216 via processor bus 1210. In at least one embodiment, MCH 1216 may provide a high-bandwidth memory path 1218 to memory 1220 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1216 may direct data signals between processor 1202, memory 1220, and other components in computer system 1200, and bridge data signals between processor bus 1210, memory 1220, and system I / O interface 1222. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1216 can be coupled to memory 1220 via high-bandwidth memory path 1218, and graphics / video card 1212 can be coupled to MCH 1216 via Accelerated Graphics Port (“AGP”) interconnect 1214.

[0250] In at least one embodiment, the computer system 1200 may use the system I / O interface 1222 as a proprietary hub interface bus to couple the MCH 1216 to the I / O controller hub (“ICH”) 1230. In at least one embodiment, the ICH 1230 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1220, chipset, and processor 1202. Examples may include, but are not limited to, an audio controller 1229, a firmware hub (“Flash BIOS”) 1228, a wireless transceiver 1226, a data storage 1224, a conventional I / O controller 1223 including a user input and keyboard interface 1225, a serial expansion port 1227 (such as a Universal Serial Bus (“USB”) port), and a network controller 1234. In at least one embodiment, the data storage 1224 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0251] In at least one embodiment, Figure 12 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 12 An exemplary SoC can be shown. In at least one embodiment, Figure 12The devices shown can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 1200 are interconnected using a Compute Fast Link (CXL) interconnect.

[0252] The logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 8A and / or Figure 8B Details regarding logic 815 are provided. In at least one embodiment, logic 815 may be used in computer system 1200 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0253] Figures 1-12 At least one embodiment is used for the optimized deployment of one or more second neural networks in new platforms, computer systems, and any other hardware resources provided by, for example, NVIDIA, AMD, and Intel, by using one or more first neural networks. In at least one embodiment, the processor includes one or more circuitry for generating the one or more second versions of the one or more second neural networks using the one or more first neural networks, at least in part based on one or more first versions of the one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks are trained based on hardware features, software features, and software programs associated with multiple platforms, computer systems, and any other hardware resources.

[0254] Figure 13 This is a block diagram illustrating an electronic device 1300 for utilizing a processor 1310 according to at least one embodiment. In at least one embodiment, the electronic device 1300 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0255] In at least one embodiment, the electronic device 1300 may, but is not limited to, a processor 1310 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1310 uses a bus or interface coupling, such as an I2C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advanced Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 13 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 13 An exemplary SoC can be shown. In at least one embodiment, Figure 13 The devices shown can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 13 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0256] In at least one embodiment, Figure 13 This may include a display 1324, a touchscreen 1325, a touchpad 1330, a near-field communication unit (“NFC”) 1345, a sensor hub 1340, a thermal sensor 1346, a fast chipset (“EC”) 1335, a trusted platform module (“TPM”) 1338, a BIOS / firmware / flash (“BIOS, FW Flash”) 1322, a DSP 1360, a drive 1320 (such as a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1350, a Bluetooth unit 1352, a wireless wide area network unit (“WWAN”) 1356, a global positioning system (GPS) unit 1355, a camera (“USB 3.0 camera”) 1354 (such as a USB 3.0 camera), and / or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1315 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0257] In at least one embodiment, other components may be communicatively coupled to processor 1310 via the components described herein. In at least one embodiment, accelerometer 1341, ambient light sensor (“ALS”) 1342, compass 1343, and gyroscope 1344 may be communicatively coupled to sensor hub 1340. In at least one embodiment, thermal sensor 1339, fan 1337, keyboard 1336, and touchpad 1330 may be communicatively coupled to EC 1335. In at least one embodiment, speaker 1363, earphone 1364, and microphone (“mic”) 1365 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1362, which in turn may be communicatively coupled to DSP 1360. In at least one embodiment, audio unit 1362 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1357 may be communicatively coupled to WWAN unit 1356. In at least one embodiment, components such as WLAN unit 1350, Bluetooth unit 1352, and WWAN unit 1356 may be implemented as next-generation form factors (“NGFF”).

[0258] The logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 8A and / or Figure 8B Details regarding logic 815 are provided. In at least one embodiment, logic 815 may be used in electronic device 1300 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0259] Figures 1-13 At least one embodiment is used for the optimized deployment of one or more second neural networks in new platforms, computer systems, and any other hardware resources provided by, for example, NVIDIA, AMD, and Intel, by using one or more first neural networks. In at least one embodiment, the processor includes one or more circuitry for generating the one or more second versions of the one or more second neural networks using the one or more first neural networks, at least in part based on one or more first versions of the one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks are trained based on hardware features, software features, and software programs associated with multiple platforms, computer systems, and any other hardware resources.

[0260] Figure 14 A computer system 1400 according to at least one embodiment is shown. In at least one embodiment, the computer system 1400 is configured to implement various processes and methods described throughout this disclosure.

[0261] In at least one embodiment, the computer system 1400 includes, but is not limited to, at least one central processing unit (“CPU”) 1402 connected to a communication bus 1410 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Fast (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1400 includes, but is not limited to, main memory 1404 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data is stored in the main memory 1404, which may take the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1422 provides an interface to other computing devices and networks for receiving data from and sending data to other systems using the computer system 1400.

[0262] In at least one embodiment, the computer system 1400 includes, but is not limited to, an input device 1408, a parallel processing system 1412, and a display device 1406, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”) display, plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1408 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each module described herein may reside on a single semiconductor platform to form the processing system.

[0263] The logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 8A and / or Figure 8B Details are provided regarding inference and / or training logic 815. In at least one embodiment, logic 815 may be used in computer system 1400 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0264] Figures 1-14At least one embodiment is used for the optimized deployment of one or more second neural networks in new platforms, computer systems, and any other hardware resources provided by, for example, NVIDIA, AMD, and Intel, by using one or more first neural networks. In at least one embodiment, the processor includes one or more circuitry for generating the one or more second versions of the one or more second neural networks using the one or more first neural networks, at least in part based on one or more first versions of the one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks are trained based on hardware features, software features, and software programs associated with multiple platforms, computer systems, and any other hardware resources.

[0265] Figure 15 A computer system 1500 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1500 includes, but is not limited to, a computer 1510 and a USB flash drive 1520. In at least one embodiment, the computer 1510 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1510 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0266] In at least one embodiment, the USB flash drive 1520 includes, but is not limited to, a processing unit 1530, a USB interface 1540, and USB interface logic 1550. In at least one embodiment, the processing unit 1530 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1530 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1530 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1530 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1530 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0267] In at least one embodiment, the USB interface 1540 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1540 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1540 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1550 may include any amount and type of logic enabling the processing unit 1530 to interface with a device (e.g., computer 1510) via the USB connector 1540.

[0268] The logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 8A and / or Figure 8B Details regarding logic 815 are provided. In at least one embodiment, logic 815 may be used in computer system 1500 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0269] Figures 1-15 At least one embodiment is used for the optimized deployment of one or more second neural networks in new platforms, computer systems, and any other hardware resources provided by, for example, NVIDIA, AMD, and Intel, by using one or more first neural networks. In at least one embodiment, the processor includes one or more circuitry for generating the one or more second versions of the one or more second neural networks using the one or more first neural networks, at least in part based on one or more first versions of the one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks are trained based on hardware features, software features, and software programs associated with multiple platforms, computer systems, and any other hardware resources.

[0270] Figure 16AAn exemplary architecture is shown in which multiple GPUs 1610(1)-1610(N) are communicatively coupled to multiple multi-core processors 1605(1)-1605(M) via high-speed links 1640(1)-1640(N) (e.g., bus, point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1640(1)-1640(N) support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, “N” and “M” represent positive integers, the values ​​of which may vary from figure to figure. In at least one embodiment, as Figure 19A and Figure 19B The disclosed GPUs 1610(1)-1610(N) include one or more graphics cores (also referred to simply as “cores”) 1900. In at least one embodiment, one or more graphics cores 1900 may be referred to as a streaming multiprocessor (“SM”), a streaming processor (“SP”), a streaming processing unit (“SPU”), a compute unit (“CU”), an execution unit (“EU”), and / or a slice, wherein a slice in this context may refer to a portion of the processing resources within a processing unit (e.g., 16 cores, a ray tracing unit, a thread bootstrap, or a scheduler).

[0271] Furthermore, in at least one embodiment, two or more GPUs 1610 are interconnected via high-speed links 1629(1)-1629(2), which can be implemented using a protocol / link similar to or different from that used for high-speed links 1640(1)-1640(N). Similarly, two or more multi-core processors 1605 can be connected via high-speed link 1628, which can be a symmetric multiprocessor (SMP) bus operating at speeds of 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links (e.g., via a common interconnect structure) can be used. Figure 16A All communication between the various system components shown. In at least one embodiment, one or more of the plurality of GPUs 1610(1)-1610(N) include, as shown in the figure Figure 19A and 19BThe disclosed one or more graphics cores (also referred to simply as "cores") 1900. In at least one embodiment, one or more graphics cores 1900 may be referred to as streaming multiprocessors ("SM"), streaming processors ("SP"), streaming processing units ("SPU"), compute units ("CU"), execution units ("EU"), and / or slices, wherein a slice in this context may refer to a portion of the processing resources within a processing unit (e.g., 16 cores, a ray tracing unit, a thread bootstrap, or a scheduler).

[0272] In at least one embodiment, each multi-core processor 1605 is communicatively coupled to processor memories 1601(1)-1601(M) via memory interconnects 1626(1)-1626(M), and each GPU 1610(1)-1610(N) is communicatively coupled to GPU memories 1620(1)-1620(N) via GPU memory interconnects 1650(1)-1650(N). In at least one embodiment, memory interconnects 1626 and 1650 may utilize similar or different memory access technologies. By way of example and not limitation, processor memories 1601(1)-1601(M) and GPU memories 1620 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM. In at least one embodiment, some portions of the processor memory 1601 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0273] As described herein, although the individual multi-core processors 1605 and GPUs 1610 can be physically coupled to specific memories 1601 and 1620 respectively, and / or can implement a unified memory architecture, in which the virtual system address space (also known as the “effective address” space) is distributed among the individual physical memories. For example, processor memories 1601(1)–1601(M) can each include 64 GB of system memory address space, and GPU memories 1620(1)–1620(N) can each include 32 GB of system memory address space, resulting in a total of 256 GB of addressable memory when M = 2 and N = 4. Other values ​​for N and M are possible.

[0274] Figure 16BAdditional details are shown regarding the interconnection between a multi-core processor 1607 and a graphics acceleration module 1646 according to one exemplary embodiment. In at least one embodiment, the graphics acceleration module 1646 may include one or more GPU chips integrated on a line card coupled to the processor 1607 via a high-speed link 1640 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1646 may alternatively be integrated on a package or chip having the processor 1607.

[0275] In at least one embodiment, the processor 1607 includes a plurality of cores 1660A-1660D (which may be referred to as “execution units”), each core having a translation back cover buffer (“TLB”) 1661A-1661D and one or more caches 1662A-1662D. In at least one embodiment, the cores 1660A-1660D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 1662A-1662D may include Level 1 (L1) and Level 2 (L2) caches. Furthermore, one or more shared caches 1656 may be included in the caches 1662A-1662D and shared by the respective groups of cores 1660A-1660D. For example, one embodiment of the processor 1607 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1607 and the graphics acceleration module 1646 are connected to the system memory 1614, which may include... Figure 16A The processor memory in the memory is 1601(1)-1601(M).

[0276] In at least one embodiment, consistency of data and instructions stored in the various caches 1662A-1662D, 1656 and system memory 1614 is maintained via inter-core communication through the consistency bus 1664. In at least one embodiment, for example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 1664 in response to the detection of a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the consistency bus 1664 to snoop on cache accesses.

[0277] In at least one embodiment, proxy circuitry 1625 communicatively couples graphics acceleration module 1646 to coherence bus 1664, thereby allowing graphics acceleration module 1646 to participate in cache coherence protocols as a peer of cores 1660A-1660D. Specifically, in at least one embodiment, interface 1635 provides connectivity to proxy circuitry 1625 via high-speed link 1640, and interface 1637 connects graphics acceleration module 1646 to high-speed link 1640.

[0278] In at least one embodiment, the accelerator integrated circuit 1636 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 1631(1)-1631(N) of the graphics acceleration module 1646. In at least one embodiment, each of the graphics processing engines 1631(1)-1631(N) may include a separate graphics processing unit (GPU). In at least one embodiment, the plurality of graphics processing engines 1631(1)-1631(N) of the graphics acceleration module 1646 includes a combination of Figure 19A and Figure 19B The discussion concerns one or more graphics cores 1900. In at least one embodiment, graphics processing engines 1631(1)-1631(N) may alternatively include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit (block transport) engines. In at least one embodiment, graphics acceleration module 1646 may be a GPU having multiple graphics processing engines 1631(1)-1631(N), or graphics processing engines 1631(1)-1631(N) may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0279] In at least one embodiment, the accelerator integrated circuit 1636 includes a memory management unit (MMU) 1639 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1614. In at least one embodiment, the MMU 1639 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, cache 1638 may store commands and data for efficient access by graphics processing engines 1631(1)-1631(N). In at least one embodiment, a fetch unit 1644 may be used to keep data stored in cache 1638 and graphics memory 1633(1)-1633(M) consistent with core caches 1662A-1662D, 1656 and system memory 1614. As previously stated, this can represent cache 1638 and memory 1633(1)-1633(M) being implemented via proxy circuit 1625 (e.g., sending updates related to the modification / access of cache lines on processor caches 1662A-1662D, 1656 to cache 1638 and receiving updates from cache 1638).

[0280] In at least one embodiment, a set of registers 1645 stores context data of threads executed by graphics processing engines 1631(1)-1631(N), and context management circuitry 1648 manages the thread context. For example, context management circuitry 1648 may perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1648 may store the current register value in a designated area of ​​memory (e.g., identified by a context pointer). The register value can then be restored upon returning to the context. In at least one embodiment, interrupt management circuitry 1647 receives and processes interrupts received from system devices.

[0281] In at least one embodiment, MMU 1639 translates virtual / effective addresses from graphics processing engine 1631 into real / physical addresses in system memory 1614. In at least one embodiment, accelerator integrated circuit 1636 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1646 and / or other accelerator devices. In at least one embodiment, graphics accelerator module 1646 may be dedicated to a single application executing on processor 1607, or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented, wherein resources of graphics processing engines 1631(1)-1631(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0282] In at least one embodiment, the accelerator integrated circuit 1636 acts as a bridge to the system of the graphics acceleration module 1646 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1636 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1631(1)-1631(N).

[0283] In at least one embodiment, since the hardware resources of the graphics processing engines 1631(1)-1631(N) are explicitly mapped to the real address space seen by the host processor 1607, any host processor can directly address these resources using valid address values. In at least one embodiment, a function of the accelerator integrated circuit 1636 is the physical separation of the graphics processing engines 1631(1)-1631(N), making them appear as independent units to the system.

[0284] In at least one embodiment, one or more graphics memories 1633(1)-1633(M) are coupled to each graphics processing engine 1631(1)-1631(N), where N = M. In at least one embodiment, the graphics memories 1633(1)-1633(M) store instructions and data being processed by each graphics processing engine 1631(1)-1631(N). In at least one embodiment, the graphics memories 1633(1)-1633(M) may be volatile memories, such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM.

[0285] In at least one embodiment, to reduce data traffic on the high-speed link 1640, a biasing technique can be used to ensure that the data stored in the graphics memory 1633(1)-1633(M) is the data most frequently used by the graphics processing engine 1631(1)-1631(N), and preferably data that the cores 1660A-1660D do not use (or at least not frequently use). Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not needed by the graphics processing engine 1631(1)-1631(N)) in the caches 1662A-1662D, 1656 and system memory 1614.

[0286] Figure 16C Another exemplary embodiment is shown, wherein the accelerator integrated circuit 1636 is integrated within the processor 1607. In this embodiment, the graphics processing engines 1631(1)-1631(N) communicate directly with the accelerator integrated circuit 1636 via a high-speed link 1640 through interfaces 1637 and 1635 (again, which may be any form of bus or interface protocol). In at least one embodiment, the accelerator integrated circuit 1636 can perform operations related to... Figure 16B The described operation is similar, but due to its close proximity to the coherence bus 1664 and caches 1662A-1662D, 1656, it may have higher throughput. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). These programming models may include a programming model controlled by the accelerator integrated circuit 1636 and a programming model controlled by the graphics acceleration module 1646.

[0287] In at least one embodiment, graphics processing engines 1631(1)-1631(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1631(1)-1631(N), thereby providing virtualization within a VM / partition.

[0288] In at least one embodiment, graphics processing engines 1631(1)-1631(N) can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1631(1)-1631(N) to allow access by each operating system. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns graphics processing engines 1631(1)-1631(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1631(1)-1631(N) to provide access to each process or application.

[0289] In at least one embodiment, the graphics acceleration module 1646 or the individual graphics processing engine 1631(1)-1631(N) uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1614 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 1631(1)-1631(N) (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0290] Figure 16D An exemplary accelerator integration slice 1690 is illustrated. In at least one embodiment, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit 1636. In at least one embodiment, the application is an effective address space 1682 in system memory 1614, which stores process element 1683. In at least one embodiment, process element 1683 is stored in response to a GPU call 1681 from an application 1680 executing on processor 1607. In at least one embodiment, process element 1683 contains the process state of the corresponding application 1680. In at least one embodiment, a job descriptor (WD) 1684 contained in process element 1683 may be a single job requested by the application, or it may contain a pointer to a job queue. In at least one embodiment, WD 1684 is a pointer to a job request queue in the effective address space 1682 of the application.

[0291] In at least one embodiment, the graphics acceleration module 1646 and / or the various graphics processing engines 1631(1)-1631(N) may be shared by all processes or subsets of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1684 to the graphics acceleration module 1646 to begin operations in a virtualized environment.

[0292] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either the graphics acceleration module 1646 or an individual graphics processing engine 1631. In at least one embodiment, when the graphics acceleration module 1646 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1646 is assigned, the operating system initializes the accelerator integrated circuit 1636 for the owned process.

[0293] In at least one embodiment, during operation, the WD acquisition unit 1691 in the accelerator integration slice 1690 acquires the next WD 1684, which includes instructions for work to be performed by one or more graphics processing engines of the graphics acceleration module 1646. In at least one embodiment, data from the WD 1684 may be stored in register 1645 and used by the MMU 1639, interrupt management circuitry 1647, and / or context management circuitry 1648, as shown. For example, one embodiment of the MMU 1639 includes segment / page walk circuitry for accessing segment / page tables 1686 within the OS virtual address space 1685. In at least one embodiment, the interrupt management circuitry 1647 may process an interrupt event 1692 received from the graphics acceleration module 1646. In at least one embodiment, when performing graphics operations, a valid address 1693 generated by graphics processing engines 1631(1)-1631(N) is translated into a real address by the MMU 1639.

[0294] In at least one embodiment, register 1645 is copied for each graphics processing engine 1631(1)-1631(N) and / or graphics acceleration module 1646, and register 1645 may be initialized by a hypervisor or operating system. In at least one embodiment, each of these copied registers may be included in accelerator integration slice 1690. Exemplary registers that may be initialized by a hypervisor are shown in Table 1. Table 2 shows exemplary registers that can be initialized by the operating system. In at least one embodiment, each WD 1684 is specific to a particular graphics acceleration module 1646 and / or graphics processing engine 1631(1)-1631(N). In at least one embodiment, it contains all the information required for the graphics processing engine 1631(1)-1631(N) to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0295] Figure 16E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1698, in which a list of process elements 1699 is stored. In at least one embodiment, the hypervisor real address space 1698 can be accessed via a hypervisor 1696, which virtualizes the graphics acceleration module engine for operating system 1695.

[0296] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1646. In at least one embodiment, there are two programming models in which the graphics acceleration module 1646 is shared by multiple processes and partitions, namely time-slice sharing and graphics-oriented sharing.

[0297] In at least one embodiment, in this model, the hypervisor 1696 owns the graphics acceleration module 1646 and makes its functionality available to all operating systems 1695. In at least one embodiment, for the graphics acceleration module 1646 to support virtualization through the hypervisor 1696, the graphics acceleration module 1646 may comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1646 must provide a context saving and restoring mechanism, (2) the graphics acceleration module 1646 guarantees that the job requests of the application are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 1646 provides the ability to preempt job processing, and (3) when operating in a directed shared programming model, the fairness of the graphics acceleration module 1646 among processes must be ensured.

[0298] In at least one embodiment, application 1680 needs to make operating system 1695 system calls using the graphics acceleration module type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function used for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1646 and can take the form of graphics acceleration module 1646 commands, valid address pointers to user-defined structures, valid address pointers to command queues, or any other data structure describing the work to be performed by graphics acceleration module 1646.

[0299] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1636 (not shown) and the graphics acceleration module 1646 does not support the User Rights Mask Overwrite Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1696 may selectively apply the current Rights Mask Overwrite Register (AMOR) value before placing the AMR into the process element 1683. In at least one embodiment, CSRP is one of the registers 1645 that contains the effective address of a region in the effective address space 1682 of the application for the graphics acceleration module 1646 to save and restore the context state. In at least one embodiment, this pointer is optional if it is not necessary to save state between jobs or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0300] Upon receiving a system call, the operating system 1695 can verify that the application 1680 has been registered and granted permission to use the graphics acceleration module 1646. Then, in at least one embodiment, the operating system 1695 uses the information shown in Table 3 to invoke the hypervisor 1696. In at least one embodiment, upon receiving a hypervisor call, the hypervisor 1696 verifies that the operating system 1695 has been registered and granted permission to use the graphics acceleration module 1646. Then, in at least one embodiment, the hypervisor 1696 adds the process element 1683 to a linked list of process elements of the corresponding graphics acceleration module 1646 type. In at least one embodiment, the process element may include the information shown in Table 4. In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 1690 registers 1645.

[0301] like Figure 16F As shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1601(1)-1601(N) and GPU memories 1620(1)-1620(N). In this implementation, operations performed on GPUs 1610(1)-1610(N) utilize the same virtual / effective memory address space to access processor memories 1601(1)-1601(M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1601(1), a second portion to second processor memory 1601(N), a third portion to GPU memory 1620(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1601 and GPU memory 1620, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0302] In at least one embodiment, the bias / coherence management circuitry 1694A-1694E within one or more MMUs 1639A-1639E ensures cache coherence between one or more host processors (e.g., 1605) and the cache of the GPU 1610, and implements biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, although in Figure 16F Several instances of the bias / coherence management circuitry 1694A-1694E are shown, but the bias / coherence circuitry can be implemented within the MMU of one or more host processors 1605 and / or within the accelerator integrated circuit 1636.

[0303] One embodiment allows GPU memory 1620 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with system-wide cache coherence. In at least one embodiment, the ability of GPU memory 1620 to be accessed as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the host processor 1605 to software-set operands and access computation results without the overhead of conventional I / O DMA data copying. In at least one embodiment, such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1620 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in cases with high streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1610. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation can play a role in determining the effectiveness of GPU offloading.

[0304] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which may be a page-granular structure (e.g., controlled at the memory page level) comprising 1 or 2 bits of memory pages attached per GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPU 1610, the bias table can be implemented over one or more stolen memory ranges of GPU memory 1620. Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0305] In at least one embodiment, prior to actual access to GPU memory, an access to the bias table entry associated with each access to GPU-attached memory 1620 is performed, resulting in the following operations: In at least one embodiment, a local request from GPU 1610 to find its page in the GPU bias is directly forwarded to the corresponding GPU memory 1620. In at least one embodiment, a local request from the GPU to find its page in the host bias is forwarded to processor 1605 (e.g., via the high-speed link described herein). In at least one embodiment, a request from processor 1605 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request for a page pointing to the GPU bias can be forwarded to GPU 1610. In at least one embodiment, if the GPU is not currently using the page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed by a software-based mechanism, a hardware-assisted software mechanism, or, in a limited set of cases, by a purely hardware-based mechanism.

[0306] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn invokes the GPU's device driver, which in turn sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migration, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migrating from the host processor 1605 bias to the GPU bias, but not for the reverse migration.

[0307] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1605 cannot cache. In at least one embodiment, to access these pages, the processor 1605 may request access from the GPU 1610, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between the processor 1605 and the GPU 1610, it is beneficial to ensure that the GPU bias pages are pages needed by the GPU rather than those needed by the host processor 1605, and vice versa.

[0308] One or more hardware structures 815 are used to execute one or more embodiments. This document may combine... Figure 8A and / or Figure 8B Provide details about one or more hardware architectures 815.

[0309] Figure 17Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which can be manufactured using one or more IP cores. In addition to those illustrated, at least one embodiment may also include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0310] Figure 17 This is a block diagram illustrating an exemplary system on a chip integrated circuit 1700 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1700 includes one or more application processors 1705 (e.g., CPUs), at least one graphics processor 1710, and may additionally include an image processor 1715 and / or a video processor 1720, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1700 includes peripheral or bus logic including a USB controller 1725, a UART controller 1730, an SPI / SDIO controller 1735, and an I2S / I2C controller 1740. In at least one embodiment, the integrated circuit 1700 may include a display device 1745 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1750 and a Mobile Industrial Processor Interface (MIPI) display interface 1755. In at least one embodiment, storage may be provided by a flash memory subsystem 1760, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1765 for accessing an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits also include an embedded security engine 1770.

[0311] The logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 8A and / or Figure 8B Details regarding logic 815 are provided. In at least one embodiment, logic 815 may be used in integrated circuit 1700 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0312] Figures 1-17At least one embodiment is used for the optimized deployment of one or more second neural networks in new platforms, computer systems, and any other hardware resources provided by, for example, NVIDIA, AMD, and Intel, by using one or more first neural networks. In at least one embodiment, the processor includes one or more circuitry for generating the one or more second versions of the one or more second neural networks using the one or more first neural networks, at least in part based on one or more first versions of the one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks are trained based on hardware features, software features, and software programs associated with multiple platforms, computer systems, and any other hardware resources.

[0313] Figures 18A-18B Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be fabricated using one or more IP cores. In addition to those illustrated, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0314] Figures 18A-18B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 18A An exemplary graphics processor 1810 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 18B An additional exemplary graphics processor 1840 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 18A The graphics processor 1810 is a low-power graphics processor core. In at least one embodiment, Figure 18B The graphics processor 1840 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1810, 1840 may be... Figure 17 Variations of the graphics processor 1710.

[0315] In at least one embodiment, the graphics processor 1810 includes a vertex processor 1805 and one or more fragment processors 1815A-1815N (e.g., 1815A, 1815B, 1815C, 1815D to 1815N-1 and 1815N). In at least one embodiment, the graphics processor 1810 may execute different shader programs via separate logic, such that the vertex processor 1805 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1815A-1815N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1805 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1815A-1815N use the primitive and vertex data generated by the vertex processor 1805 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 1815A-1815N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0316] In at least one embodiment, the graphics processor 1810 additionally includes one or more memory management units (MMUs) 1820A-1820B, one or more caches 1825A-1825B, and one or more circuit interconnects 1830A-1830B. In at least one embodiment, the one or more MMUs 1820A-1820B provide virtual-to-physical address mapping for the graphics processor 1810 (including for the vertex processor 1805 and / or fragment processors 1815A-1815N), and may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 1825A-1825B. In at least one embodiment, the one or more MMUs 1820A-1820B may be synchronized with other MMUs within the system, including with... Figure 17 One or more application processors 1705, graphics processors 1715, and / or video processors 1720 are associated with one or more MMUs, such that each processor 1705-1720 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1830A-1830B enable the graphics processor 1810 to interface with other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0317] In at least one embodiment, the graphics processor 1840 includes, as shown below: Figure 18B The one or more shader cores 1855A-1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F to 1855N-1 and 1855N) shown provide a unified shader core architecture, wherein a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1840 includes an inter-core task manager 1845, which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1855A-1855N and a tile unit 1858 to accelerate tile-based rendering operations, where scene rendering operations are subdivided in image space, for example, to utilize local spatial consistency within the scene or optimize the use of internal caches.

[0318] The logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 8A and / or Figure 8B Details regarding logic 815 are provided. In at least one embodiment, logic 815 may be used in graphics processor 1810 and / or 1840 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0319] Figures 1-18B At least one embodiment is used for the optimized deployment of one or more second neural networks in new platforms, computer systems, and any other hardware resources provided by, for example, NVIDIA, AMD, and Intel, by using one or more first neural networks. In at least one embodiment, the processor includes one or more circuitry for generating the one or more second versions of the one or more second neural networks using the one or more first neural networks, at least in part based on one or more first versions of the one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks are trained based on hardware features, software features, and software programs associated with multiple platforms, computer systems, and any other hardware resources.

[0320] Figures 19A-19B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, in... Figures 19A-19B The text shows and about Figures 19A-19B The described components are integrated into a single system, such as a graphics processing unit (GPU), a SoC, or other types of processors. In at least one embodiment, Figure 19A It shows that it can be included in Figure 17 The graphics core 1900 within the graphics processor 1710, and in at least one embodiment, may be as follows: Figure 18B The Unified Shader Core 1855A-1855N is shown. Figure 19B A highly parallel general-purpose graphics processing unit (“GPGPU”, which may be referred to as a “graphics processing unit”) 1930 suitable for deployment on a multi-chip module is illustrated in at least one embodiment. In at least one embodiment, the graphics processing unit 1930 is a GPGPU that includes a graphics processor. In at least one embodiment, the integrated circuit 1700 includes a graphics core 1900, for example, for forming an integrated circuit and / or a SoC, wherein such an integrated circuit and / or such a SoC performs the operations described herein.

[0321] In at least one embodiment, the graphics core 1900 includes a shared instruction cache 1902, texture units 1918, and cache / shared memory 1920 (e.g., including L1, L2, L3, the last level cache, or other caches), which are shared for execution resources within the graphics core 1900. In at least one embodiment, the graphics core 1900 may include multiple slices 1901A-1901N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 1900. In at least one embodiment, each slice 1901A-1901N refers to the graphics core 1900. In at least one embodiment, slices 1901A-1901N have sub-slices, which are part of slices 1901A-1901N. In at least one embodiment, slices 1901A-1901N are independent of or dependent on other slices. In at least one embodiment, slices 1901A-1901N may include supporting logic, which includes local instruction caches 1904A-1904N, thread schedulers (orderers) 1906A-1906N, thread dispatchers 1908A-1908N, and a set of registers 1910A-1910N. In at least one embodiment, slices 1901A-1901N may include a set of additional functional units (AFU 1912A-1912N), floating-point units (FPU 1914A-1914N), integer arithmetic logic units (ALU 1916A-1916N), address calculation units (ACU 1913A-1913N), double-precision floating-point units (DPFPU 1915A-1915N), and matrix processing units (MPU 1917A-1917N). In at least one embodiment, the MPU 1917A-1917N is referred to as a matrix engine.

[0322] In at least one embodiment, each slice 1901A-1901N includes one or more engines for floating-point and integer vector operations and one or more engines for accelerating convolution and matrix operations in artificial intelligence, machine learning, or large dataset workloads. In at least one embodiment, one or more slices 1901A-1901N include one or more vector engines for computing vectors (e.g., computing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16-bit floating-point (also referred to as "FP16"), 32-bit floating-point (also referred to as "FP32"), or 64-bit floating-point (also referred to as "FP64"). In at least one embodiment, one or more slices 1901A-1901N include 16 vector engines paired with 16 matrix math units to compute matrix / tensor operations, wherein the vector engines and math units are exposed via matrix extensions. In at least one embodiment, a slice is a designated portion of the processing resources of a processing unit, such as 16 cores and ray tracing units or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units of the processor. In at least one embodiment, the graphics core 1900 includes one or more matrix engines for performing matrix operations, such as when performing tensor operations.

[0323] In at least one embodiment, one or more slices 1901A-1901N include one or more ray tracing units for calculating ray tracing operations (e.g., 16 ray tracing units per slice 1901A-1901N). In at least one embodiment, the ray tracing units calculate ray traversal, triangle intersection, bounding box intersection, or other ray tracing operations.

[0324] In at least one embodiment, one or more slices 1901A-1901N include media slices that encode, decode, and / or transcode data; scale data and / or convert data formats; and / or perform video quality operations on video data.

[0325] In at least one embodiment, one or more slices 1901A-1901N are linked to an L2 cache and memory architecture, link connectors, a high-bandwidth memory (HBM) stack (e.g., HBM2e, HDM3), and a media engine. In at least one embodiment, one or more slices 1901A-1901N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16 units) paired with each core. In at least one embodiment, one or more slices 1901A-1901N have one or more L1 caches. In at least one embodiment, one or more slices 1901A-1901N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memory (SLM) for storing data (e.g., data corresponding to instructions); one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometry units for performing operations in the geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing images in a vector graphics format (e.g., shapes) and converting them into raster images (e.g., a series of pixels, points, or lines, creating an image represented by shapes when they are displayed together); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel back-ends. In at least one embodiment, slices 1901A-1901N include memory structures, such as L2 caches.

[0326] In at least one embodiment, the FPU 1914A-1914N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1915A-1915N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1916A-1916N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1917A-1917N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1917A-1917N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 1912A-1912N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric function operations (e.g., sine, cosine, etc.).

[0327] The logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 8A and / or Figure 8B Details regarding logic 815 are provided. In at least one embodiment, logic 815 may be used in graphics core 1900 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0328] In at least one embodiment, the graphics core 1900 includes an interconnect and link structure sublayer attached to a switch and a GPU-GPU bridge, which enables multiple graphics processors 1900 (e.g., eight) to load / store units (LSUs), data transfer units, and synchronous semantic interconnects across the multiple graphics processors 1900 without glued to each other. In at least one embodiment, the interconnect includes standardized interconnects (e.g., PCIe) or some combination thereof.

[0329] In at least one embodiment, the graphics core 1900 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, wherein the individual dies may be connected using an interconnect (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, the graphics core 1900 includes compute tiles, memory tiles (e.g., where memory tiles may be dedicated to different tiles or different chipsets (such as Rambo tiles)), substrate tiles, base tiles, HMB tiles, link tiles, and EMIB tiles, wherein all tiles are packaged together in the graphics core 1900 as part of the GPU. In at least one embodiment, the graphics core 1900 may include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, the compute tile may have eight graphics cores 1900, an L1 cache; and the base tile may have a host interface employing PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with eight links, and eight ports with an embedded switch. In at least one embodiment, the tiles are connected via fine-pitch 36-micron microbumps (e.g., copper pillars) in a face-to-face (F2F) on-chip bonding manner. In at least one embodiment, the graphics core 1900 includes a memory structure (which includes memory) and is tiles accessible to the plurality of tiles. In at least one embodiment, the graphics core 1900 stores, accesses, or loads its own hardware context in memory, wherein the hardware context is a dataset loaded from registers prior to process resumption, and wherein the hardware context can indicate the state of the hardware (e.g., the state of the GPU).

[0330] In at least one embodiment, the graphics core 1900 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream into a parallel data stream, or a parallel data stream into a serial data stream.

[0331] In at least one embodiment, the graphics core 1900 includes a high-speed consistent unified architecture (GPU-to-GPU), load / store units, bulk data transfer and synchronization semantics, and GPUs connected via an embedded switch, wherein the GPU-to-GPU bridge is controlled by a controller.

[0332] In at least one embodiment, the graphics core 1900 executes an API, wherein the API abstracts the hardware of the graphics core 1900 and accesses libraries with instructions to perform mathematical operations (e.g., a mathematical kernel library), deep neural network operations (e.g., a deep neural network library), vector operations, collective communication, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0333] Figures 1-19A At least one embodiment is used for the optimized deployment of one or more second neural networks in new platforms, computer systems, and any other hardware resources provided by, for example, NVIDIA, AMD, and Intel, by using one or more first neural networks. In at least one embodiment, the processor includes one or more circuitry for generating the one or more second versions of the one or more second neural networks using the one or more first neural networks, at least in part based on one or more first versions of the one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks are trained based on hardware features, software features, and software programs associated with multiple platforms, computer systems, and any other hardware resources.

[0334] Figure 19BA GPGPU 1930 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 1930 can be directly linked to other instances of the GPGPU 1930 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 1930 includes a host interface 1932 for establishing a connection to a host processor. In at least one embodiment, the host interface 1932 is a PCI Express interface. In at least one embodiment, the host interface 1932 can be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1930 receives commands from the host processor and uses a global scheduler 1934 (which may be referred to as a thread sequencer and / or asynchronous computing engine) to allocate the execution threads associated with those commands to a set of computing clusters 1936A-1936H. In at least one embodiment, the computing clusters 1936A-1936H share a cache memory 1938. In at least one embodiment, cache memory 1938 may be used as a higher-level cache than the cache memory within compute clusters 1936A-1936H. In at least one embodiment, compute clusters 1936A-1936H include slices, or are also referred to as "slices". In at least one embodiment, GPGPU 1930 is part of a SoC, such as part of integrated circuit 1700. Figure 17 ).

[0335] In at least one embodiment, the GPGPU 1930 includes memories 1944A-1944B coupled to the compute cluster 1936A-1936H via a set of memory controllers 1942A-1942B (e.g., one or more controllers for HBM2e). In at least one embodiment, memories 1944A-1944B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0336] In at least one embodiment, each of the computing clusters 1936A-1936H includes a set of graphics cores, such as Figure 19AThe graphics core 1900 may include various types of integer and floating-point logic units that can perform computational operations over a range of precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 1936A-1936H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0337] In at least one embodiment, multiple instances of GPGPU 1930 can be configured to operate as a computing cluster. In at least one embodiment, the communication used for synchronization and data exchange by computing clusters 1936A-1936H varies between embodiments. In at least one embodiment, multiple instances of GPGPU 1930 communicate via host interface 1932. In at least one embodiment, GPGPU 1930 includes an I / O hub 1939 that couples GPGPU 1930 to GPU link 1940, which provides direct connectivity to other instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1930 reside in a separate data processing system and communicate via a network device accessible via host interface 1932. In at least one embodiment, in addition to or as an alternative to host interface 1932, GPU link 1940 may also be configured to implement a connection to the host processor.

[0338] In at least one embodiment, the GPGPU 1930 can be configured to train a neural network. In at least one embodiment, the GPGPU 1930 can be used within an inference platform. In at least one embodiment, when using the GPGPU 1930 for inference, the GPGPU 1930 may include fewer compute clusters 1936A-1936H compared to when using the GPGPU 1930 to train a neural network. In at least one embodiment, the memory technology associated with the memories 1944A-1944B can differ between inference and training configurations, with higher bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1930 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0339] The logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 8A and / or Figure 8B Details regarding logic 815 are provided. In at least one embodiment, logic 815 may be used in the GPGPU 1930 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0340] Figures 1-19B At least one embodiment is used for the optimized deployment of one or more second neural networks in new platforms, computer systems, and any other hardware resources provided by, for example, NVIDIA, AMD, and Intel, by using one or more first neural networks. In at least one embodiment, the processor includes one or more circuitry for generating the one or more second versions of the one or more second neural networks using the one or more first neural networks, at least in part based on one or more first versions of the one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks are trained based on hardware features, software features, and software programs associated with multiple platforms, computer systems, and any other hardware resources.

[0341] Figure 20 This is a block diagram illustrating a computing system 2000 according to at least one embodiment. In at least one embodiment, the computing system 2000 includes a processing subsystem 2001 having one or more processors 2002 and a system memory 2004 communicating via an interconnect path that may include a memory hub 2005. In at least one embodiment, the memory hub 2005 may be a separate component within a chipset assembly or may be integrated within one or more processors 2002. In at least one embodiment, the memory hub 2005 is coupled to an I / O subsystem 2011 via a communication link 2006. In at least one embodiment, the I / O subsystem 2011 includes an I / O hub 2007 that enables the computing system 2000 to receive input from one or more input devices 2008. In at least one embodiment, the I / O hub 2007 enables a display controller to provide output to one or more display devices 2010A, the display controller being included in one or more processors 2002. In at least one embodiment, one or more display devices 2010A coupled to the I / O hub 2007 may include local, internal or embedded display devices.

[0342] In at least one embodiment, the processing subsystem 2001 includes one or more parallel processors 2012 coupled to the memory hub 2005 via a bus or other communication link 2013. In at least one embodiment, the communication link 2013 may use one of any number of standards based on a communication link technology or protocol (such as, but not limited to, PCI Express), or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, one or more parallel processors 2012 form a computationally concentrated parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as integrated many-core (MIC) processors. In at least one embodiment, some or all of the parallel processors 2012 form a graphics processing subsystem that can output pixels to one or more display devices 2010A coupled via an I / O hub 2007. In at least one embodiment, one or more parallel processors 2012 may also include a display controller and a display interface (not shown) for implementing direct connections to one or more display devices 2010B. In at least one embodiment, one or more parallel processors 2012 include one or more cores, such as the graphics core 1900 discussed herein.

[0343] In at least one embodiment, system storage unit 2014 may be connected to I / O hub 2007 to provide a storage mechanism for computing system 2000. In at least one embodiment, I / O switch 2016 may be used to provide an interface mechanism for enabling connectivity between I / O hub 2007 and other components, such as network adapter 2018 and / or wireless network adapter 2019 integrated into the platform, and various other devices that can be added via one or more additional devices 2020. In at least one embodiment, network adapter 2018 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 2019 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless devices.

[0344] In at least one embodiment, the computing system 2000 may include other components, not explicitly shown, that may also be connected to the I / O hub 2007, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the interconnect can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (e.g., NV-Link high-speed interconnect or interconnect protocols). Figure 20The communication paths of each component.

[0345] In at least one embodiment, one or more parallel processors 2012 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU). For example, one or more parallel processors 2012 include a graphics core 1900. In at least one embodiment, one or more parallel processors 2012 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computing system 2000 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2012, a memory hub 2005, one or more processors 2002, and an I / O hub 2007 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computing system 2000 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 2000 may be integrated into a multi-chip module (MCM), which may interconnect with other MCMs to a modular computing system.

[0346] The logic 815 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 8A and / or Figure 8B Details regarding logic 815 are provided. In at least one embodiment, logic 815 may be used in computing system 2000 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0347] Figures 1-20 At least one embodiment is used for the optimized deployment of one or more second neural networks in new platforms, computer systems, and any other hardware resources provided by, for example, NVIDIA, AMD, and Intel, by using one or more first neural networks. In at least one embodiment, the processor includes one or more circuitry for generating the one or more second versions of the one or more second neural networks using the one or more first neural networks, at least in part based on one or more first versions of the one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks. In at least one embodiment, the one or more first neural networks are trained based on hardware features, software features, and software programs associated with multiple platforms, computer systems, and any other hardware resources.

[0348] processor Figure 21A A parallel processor 2100 according to at least one embodiment is illustrated. In at least one embodiment, the various components of the parallel processor 2100 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2100 is according to an exemplary embodiment. Figure 20 Variations of the one or more parallel processors 2012 shown. In at least one embodiment, the parallel processor 2100 includes one or more graphics cores 1900.

[0349] In at least one embodiment, the parallel processor 2100 includes a parallel processing unit 2102. In at least one embodiment, the parallel processing unit 2102 includes an I / O unit 2104 that enables communication with other devices, including other instances of the parallel processing unit 2102. In at least one embodiment, the I / O unit 2104 can be directly connected to other devices. In at least one embodiment, the I / O unit 2104 is connected to other devices via a hub or switch interface (e.g., a memory hub 2105). In at least one embodiment, the connection between the memory hub 2105 and the I / O unit 2104 forms a communication link 2113. In at least one embodiment, the I / O unit 2104 is connected to a host interface 2106 and a memory crossbar switch 2116, wherein the host interface 2106 receives commands for performing processing operations, and the memory crossbar switch 2116 receives commands for performing memory operations.

[0350] In at least one embodiment, when host interface 2106 receives a command buffer via I / O unit 2104, host interface 2106 can route work operations for executing those commands to front end 2108. In at least one embodiment, front end 2108 is coupled to scheduler 2110 (which may be referred to as an orderer), which is configured to assign commands or other work items to processing cluster array 2112. In at least one embodiment, scheduler 2110 ensures that processing cluster array 2112 is correctly configured and in an active state before assigning tasks to clusters in processing cluster array 2112. In at least one embodiment, scheduler 2110 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, microcontroller-implemented scheduler 2110 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing cluster array 2112. In at least one embodiment, host software can demonstrate workloads for scheduling on processing cluster array 2112 via one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed on the processing cluster array 2112 by the scheduler 2110 logic within the microcontroller, which includes the scheduler 2110.

[0351] In at least one embodiment, the processing cluster array 2112 may include up to "N" processing clusters (e.g., clusters 2114A, 2114B to 2114N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other diagrams). In at least one embodiment, each cluster 2114A-2114N of the processing cluster array 2112 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2110 may use various scheduling and / or work allocation algorithms to allocate work to clusters 2114A-2114N in the processing cluster array 2112, which may vary depending on the workload generated for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2110, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2112. In at least one embodiment, different clusters 2114A-2114N in the processing cluster array 2112 may be assigned to process different types of programs or to perform different types of computations.

[0352] In at least one embodiment, the processing cluster array 2112 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2112 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2112 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0353] In at least one embodiment, the processing cluster array 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2112 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2112 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2102 may transfer data from system memory via I / O unit 2104 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2122) and then written back to system memory.

[0354] In at least one embodiment, when the parallel processing unit 2102 is used to perform graphics processing, the scheduler 2110 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among multiple clusters 2114A-2114N in the processing cluster array 2112. In at least one embodiment, portions of the processing cluster array 2112 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2114A-2114N can be stored in a buffer to allow intermediate data to be transferred between the clusters 2114A-2114N for further processing.

[0355] In at least one embodimen...

Claims

1. A processor, comprising: One or more circuits, the one or more circuits being used to generate one or more second versions of the one or more second neural networks using one or more first neural networks, at least in part based on one or more first versions of one or more second neural networks and one or more hardware resources to be used to execute one or more second versions of the one or more second neural networks.

2. The processor of claim 1, wherein the one or more first versions of the one or more second neural networks are compressed at least in part based on one or more features of one or more other hardware resources that are different from the one or more hardware resources.

3. The processor of claim 1, wherein the one or more first neural networks comprise a transformer neural network.

4. The processor of claim 1, wherein the one or more second versions of the one or more second neural networks are generated at least in part based on one or more other hardware resources for executing the one or more first versions of the one or more second neural networks.

5. The processor of claim 1, wherein the one or more circuits are further configured to: update the one or more first neural networks at least in part based on one or more hardware features of a plurality of hardware resources, wherein the one or more hardware features include numerical data types.

6. The processor of claim 1, wherein the one or more circuits are further configured to: update the one or more first neural networks at least in part based on one or more software features of a plurality of hardware resources, wherein the one or more software features include development tools, runtime environments, or libraries.

7. The processor of claim 1, wherein the one or more circuits are further configured to: update the one or more first neural networks at least in part based on one or more first software programs and one or more second software programs for deploying one or more neural networks on different hardware resources.

8. The processor of claim 1, wherein the one or more circuits are further configured to: cause one or more software programs to be executed by the one or more hardware resources, wherein one or more second versions of the one or more second neural networks are implemented in the one or more software programs.

9. A method comprising: The one or more second versions of the one or more second neural networks are generated using one or more first neural networks, at least in part based on one or more first versions of one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks.

10. The method of claim 9, wherein the one or more first versions of the one or more second neural networks are executed by one or more other hardware resources different from the one or more hardware resources.

11. The method of claim 9, wherein the one or more first neural networks comprise a transformer neural network.

12. The method according to claim 9, further comprising: Receive information including one or more features of multiple hardware resources, wherein the one or more features can be used to update the one or more first neural networks.

13. The method of claim 9, further comprising: The one or more first neural networks are modified, at least in part, based on one or more first software programs and one or more second software programs executed by different hardware resources, to implement one or more compressed neural networks.

14. The method of claim 9, further comprising: The one or more first neural networks are modified at least in part based on one or more hardware features of a plurality of hardware resources, wherein the one or more hardware features include the number of processing units, clock speed, or memory capacity.

15. A system comprising: One or more processors, the one or more processors being configured to use one or more first neural networks to generate the one or more second versions of the one or more second neural networks, at least in part based on one or more first versions of one or more second neural networks and one or more hardware resources to be used to execute the one or more second versions of the one or more second neural networks.

16. The system of claim 15, wherein the one or more first versions of the one or more second neural networks and the one or more second versions of the one or more second neural networks are executed by different hardware resources.

17. The system of claim 15, wherein the one or more first neural networks comprise pre-trained neural networks.

18. The system of claim 15, wherein one or more processors are further configured to: update the one or more first neural networks at least in part based on a compressed neural network, the compressed neural network comprising multiple versions corresponding to multiple hardware resources.

19. The system of claim 15, wherein the one or more processors are further configured to: update the one or more first neural networks at least in part based on one or more software programs associated with a plurality of hardware resources.

20. The system of claim 15, wherein the one or more processors are further configured to: update the one or more first neural networks at least in part based on one or more software features of a plurality of hardware resources, wherein the one or more software features include libraries, runtime environments, or application programming interfaces (APIs).

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