Signal enhancement circuit and signal enhancement module

Abstract

The utility model provides a signal enhancement circuit and a signal enhancement module. The signal enhancement circuit comprises a first switch, a second switch, a signal input circuit, a signal output circuit, a grounding end and a standard voltage end. Wherein the control end of the first switch is electrically connected with the signal input circuit, the first end of the first switch is connected with the grounding end, and the second end of the first switch is electrically connected with the standard voltage end and the control end of the second switch; the first end of the second switch is connected with the grounding end, and the second end of the second switch is electrically connected with the signal output circuit. According to the signal enhancement circuit, fluctuation and interference of input signals can be filtered out, physical isolation of the signals is achieved, and the driving capacity of the circuit is enhanced.

Description

Technical Field

[0001] The present application relates to the field of controlling signal transmission, and in particular to a signal enhancement circuit and a signal enhancement module. Background Art

[0002] As the complexity of automotive electronic systems increases, the amount of data required to be transmitted between the MCU and the lower-level actuators is also increasing, and high-speed communication protocols such as IIC / SPI / QSPI are widely used. However, due to the limitation of application space, the MCU is often not on the same PCB as the lower-level actuators.

[0003] At this time, the high-speed signal needs to be transferred through connectors or even connectors + wiring harnesses, and the signal integrity is very poor. Under extreme working conditions, the system may fail due to distortion of the high-speed signal. Utility Model Content

[0004] In order to solve the above problems, the technical solutions adopted in the embodiments of the present application are as follows:

[0005] A signal enhancement circuit includes: a first switch, a second switch, a signal input circuit,

[0006] A signal output circuit, a ground terminal and a standard voltage terminal; wherein the control terminal of the first switch is electrically connected to the signal input circuit, the first terminal of the first switch is connected to the ground terminal, and the second terminal of the first switch is electrically connected to the standard voltage terminal and the control terminal of the second switch respectively; the first terminal of the second switch is connected to the ground terminal, and the second terminal of the second switch is electrically connected to the signal output circuit.

[0007] The above signal enhancement circuit, by electrically connecting the control end of the first switch to the signal input circuit, can use the level of the input signal to control the on and off of the first switch, and then control the on and off of the second switch; when the second switch is turned on, the signal output end is forced to be grounded, so that the output signal is low level; when the second switch is turned off, the voltage of the signal output end is forced to be pulled up by the standard voltage end, so as to output a high level. In this way, the fluctuation and interference of the input signal can be filtered out, the physical isolation of the signal can be achieved, and the driving ability of the circuit can be enhanced.

[0008] As an optional implementation, in an embodiment of the present application, the signal input circuit includes a signal input terminal, a first resistor and a second resistor; wherein the first resistor and the second resistor are connected in series between the signal input terminal and the ground terminal; and the control terminal of the first switch is connected to the node between the first resistor and the second resistor.

[0009] As an optional implementation, in an embodiment of the present application, the signal output circuit includes a signal output terminal and a third resistor; wherein the third resistor is connected between the standard voltage terminal and the signal output terminal; and the second end of the second switch is connected to the signal output terminal.

[0010] As an optional implementation, in an embodiment of the present application, the signal enhancement circuit further includes a fourth resistor; wherein one end of the fourth resistor is connected to the standard voltage end, and the other end is connected to the second end of the first switch.

[0011] As an optional implementation, in the embodiment of the present application, the first switch and the second switch are both MOS tubes.

[0012] As an optional implementation, in the embodiment of the present application, the first switch and the second switch are both NMOS tubes.

[0013] As an optional implementation, in the embodiment of the present application, the voltage of the standard voltage terminal is 5V or 3.3V.

[0014] As an optional implementation, in an embodiment of the present application, the signal enhancement circuit further includes an enable terminal; the signal enhancement circuit is in a working state when the enable terminal is at a high level, and is in a non-working state when the enable terminal is at a low level.

[0015] A signal enhancement module comprises the above-mentioned signal enhancement circuit; wherein each of the signal enhancement circuits is connected in series.

[0016] As an optional implementation, in an embodiment of the present application, the input end of the signal enhancement module is connected to the control module, and the output end of the signal enhancement module is connected to the load module.

[0017] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of the structure of a signal enhancement circuit provided in one embodiment of the present application.

[0020] Figure 2A schematic diagram of a signal enhancement module provided in an embodiment of the present application.

[0021] In the figure: first switch-K1; second switch-K2; first resistor-R1; second resistor-R2; third resistor-R3; fourth resistor-R4; ground terminal-GND; standard voltage terminal-VCC;

[0022] Signal enhancement circuit-10; signal input circuit-11; signal output circuit-12;

[0023] Signal boost module-100. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0026] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0027] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0028] In the description of this application, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0029] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0030] As described in the background technology, as the complexity of automotive electronic systems increases, the amount of data that needs to be transmitted between the MCU and the lower-level actuators also gradually increases. High-speed signals are very easy to be distorted during long-distance transmission, which can cause system failure.

[0031] In order to solve the above problems, the present application provides a signal enhancement circuit. The signal enhancement circuit provided by the present application is exemplarily described below.

[0032] As an alternative implementation, see Figure 1 The present application discloses a signal enhancement circuit 10, comprising: a first switch K1, a second switch K2, a signal input circuit 11, a signal output circuit 12, a ground terminal GND and a standard voltage terminal VCC; wherein the control end of the first switch K1 is electrically connected to the signal input circuit 11, the first end of the first switch K1 is connected to the ground terminal GND, the second end of the first switch K1 is electrically connected to the standard voltage terminal VCC and the control end of the second switch K2 respectively; the first end of the second switch K2 is connected to the ground terminal GND, and the second end of the second switch K2 is electrically connected to the signal output circuit 12.

[0033] In this embodiment, by Figure 1The signal enhancement circuit 10 shown can convert the input signal An into an output signal Bn with a stable amplitude, realize physical isolation of the signal, and improve the circuit driving capability. Specifically, when the input signal An is at a high level, the first switch K1 is turned on, thereby forcibly grounding the control end of the second switch K2, so that the second switch K2 is turned off. Therefore, the output voltage of the signal output circuit 12 is determined by the voltage of the standard voltage terminal VCC, and is not affected by the amplitude of the input signal An. When the input signal is at a low level, the first switch K1 is turned off, so that the level of the control end of the second switch K2 is pulled up by the standard voltage terminal VCC, so that the second switch K2 is turned on, so that the signal output circuit 12 is connected to the ground terminal GND, and the output signal is at a low level. It can be seen from this that when the input signal An is at a high level, the amplitude of the output signal Bn is determined by the voltage of the standard voltage terminal VCC; when the input signal is at a low level, the amplitude of the output signal Bn is 0. Therefore, the input signal An and the output signal Bn can be physically separated by the above-mentioned signal enhancement circuit 10, that is, the amplitude of Bn will not be affected by the fluctuation of the input signal An.

[0034] The above-mentioned signal enhancement circuit 10, by electrically connecting the control end of the first switch K1 with the signal input circuit 11, can use the level of the input signal to control the conduction and disconnection of the first switch K1, and then control the conduction and disconnection of the second switch K2; when the second switch K2 is turned on, the signal output end is forced to be grounded, so that the output signal is low level; when the second switch K2 is turned off, the voltage of the signal output end is forced to be pulled up by the standard voltage end VCC, so as to output a high level. In this way, the fluctuation and interference of the input signal can be filtered out to a certain extent, the physical isolation of the signal can be achieved, and the driving ability of the circuit can be enhanced.

[0035] In one embodiment, the signal input circuit 11 includes a signal input terminal, a first resistor R1 and a second resistor R2; wherein the first resistor R1 and the second resistor R2 are connected in series between the signal input terminal and a ground terminal GND; and the control terminal of the first switch K1 is connected to a node between the first resistor R1 and the second resistor R2.

[0036] For details, please continue to refer to Figure 1. The first resistor R1 and the second resistor R2 are connected in series between the signal input terminal and the ground terminal GND to form a voltage divider circuit. When the signal An is input, the voltage value between the first resistor R1 and the second resistor R2 is An*R2 / (R1+R2). In addition, since the control end of the first switch K1 is connected to the node between the first resistor R1 and the second resistor R2, the voltage at the control end of the first switch K1 is An*R2 / (R1+R2). When the input signal An is at a high level, the control end of the first switch K1 receives a high level signal, thereby turning on the first switch K1; when the input signal is at a low level, the control end of the first switch K1 receives a low level signal, thereby turning off the first switch K1.

[0037] The on and off of the first switch K1 can affect the voltage of the control end of the second switch K2, thereby controlling the on and off of the second switch K2, thereby controlling the voltage of the signal output end.

[0038] In one embodiment, the signal output circuit 12 includes a signal output terminal and a third resistor R3; wherein the third resistor R3 is connected between the standard voltage terminal VCC and the signal output terminal; and the second end of the second switch K2 is connected to the signal output terminal.

[0039] For details, please refer to Figure 1 The signal output circuit 12 includes a third resistor R3 and a signal output terminal, wherein the third resistor R3 is connected between the standard voltage terminal VCC and the second switch K2, and the signal output terminal is connected between the third resistor R3 and the second switch K2. Such a design can produce the following effects: when the second switch K2 is turned on, the signal output terminal is forced to be grounded, so that the output signal is a low level; when the second switch K2 is turned off, the ground terminal GND is separated from the signal output terminal and will not be affected by the ground terminal GND, and the signal output terminal is forced to be pulled up to a high level by the standard voltage terminal VCC, and a stable high-level voltage is output.

[0040] In one embodiment, the signal enhancement circuit 10 further includes a fourth resistor R4; wherein one end of the fourth resistor R4 is connected to the standard voltage terminal VCC, and the other end of the fourth resistor R4 is connected to the second end of the first switch K1.

[0041] With such a configuration, when the first switch K1 is turned on, it is not necessary to directly connect the standard voltage terminal VCC to the ground terminal GND, but the voltage of the standard voltage terminal VCC can be applied to the fourth resistor R4, so that the voltage of the control terminal of the second switch K2 is easier to control, so that the conduction state of the second switch K2 can be more clearly determined. For example, when the first switch K1 is turned on, the control terminal of the second switch K2 is grounded, the voltage is 0V, and the second switch K2 is turned off; when the first switch K1 is turned off, the control terminal of the second switch K2 is connected to the standard voltage terminal VCC through R4, which is a high level, and the second switch K2 is turned on.

[0042] In some embodiments, both the first switch K1 and the second switch K2 are MOS transistors.

[0043] MOS tubes have the advantages of high input impedance, low on-resistance and fast switching speed, and can meet the use scenarios of high-frequency switches. For example, when the input signal An is a clock signal, the first switch K1 needs to be frequently turned on and off. At this time, the advantages of fast switching speed and low on-resistance of MOS tubes can be fully reflected.

[0044] More specifically, in some embodiments, both the first switch K1 and the second switch K2 are NMOS transistors.

[0045] When the control terminal of the NMOS tube is at a high level, the NMOS tube is turned on, and when the control terminal is at a low level, the NMOS tube is turned off. Therefore, in the above signal enhancement circuit 10, the NMOS tube is preferably used.

[0046] In some embodiments, the voltage of the standard voltage terminal VCC is 5V or 3.3V.

[0047] In some embodiments, the signal enhancement circuit 10 further includes an enable terminal; the signal enhancement circuit 10 is in a working state when the enable terminal is at a high level, and is in a non-working state when the enable terminal is at a low level.

[0048] By setting the enable terminal, it is possible to control whether the signal enhancement circuit 10 is in a working state to prevent signal mistransmission. For example, only when the enable terminal is at a high level, the signal input terminal can receive the input signal and convert the input signal into an output signal; when the enable terminal is at a low level, the signal enhancement circuit 10 does not work and does not transmit or enhance the signal.

[0049] The present application also discloses a signal enhancement module 100, such as Figure 2 As shown, it includes a plurality of the above-mentioned signal enhancement circuits 10; wherein each of the signal enhancement circuits 10 is connected in series.

[0050] For example, Figure 2As shown, the signal enhancement module 100 includes three signal enhancement circuits 10, IC1, IC2 and IC3, wherein each signal enhancement circuit 10 is connected in series, which means that the signal output end of IC1 is connected to the signal input end of IC2, and the signal output end of IC2 is connected to the signal input end of IC3. In addition, each signal enhancement circuit 10 is connected to an independent standard voltage end VCC, so that the signal can be ensured not to be distorted during transmission.

[0051] In one embodiment, the input end of the signal enhancement module 100 is connected to the control module, and the output end of the signal enhancement module 100 is connected to the load module.

[0052] For details, please continue to refer to Figure 2 The signal enhancement module 100 is set between the MCU and the load module (such as the lower actuator) to suppress signal attenuation and achieve high-speed and stable signal transmission. In particular, when high-speed communication signals such as IIC / SPI / QSPI are transmitted across boards or over long distances, the signal distortion problem can be solved by using the signal enhancement module 100.

[0053] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0054] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A signal enhancement circuit, It is characterized in that include: A first switch, a second switch, a signal input circuit, a signal output circuit, a ground terminal and a standard voltage terminal; wherein, The control end of the first switch is electrically connected to the signal input circuit, the first end of the first switch is connected to the ground end, and the second end of the first switch is electrically connected to the standard voltage end and the control end of the second switch respectively; A first end of the second switch is connected to the ground end, and a second end of the second switch is electrically connected to the signal output circuit.

2. The signal enhancement circuit according to claim 1, It is characterized in that The signal input circuit comprises a signal input terminal, a first resistor and a second resistor; Wherein, the first resistor and the second resistor are connected in series between the signal input terminal and the ground terminal; The control end of the first switch is connected to a node between the first resistor and the second resistor.

3. The signal enhancement circuit according to claim 2, It is characterized in that The signal output circuit comprises a signal output terminal and a third resistor; Wherein, the third resistor is connected between the standard voltage terminal and the signal output terminal; and the second terminal of the second switch is connected to the signal output terminal.

4. The signal enhancement circuit according to claim 3, It is characterized in that The signal enhancement circuit further includes a fourth resistor; One end of the fourth resistor is connected to the standard voltage end, and the other end is connected to the second end of the first switch.

5. The signal enhancement circuit according to any one of claims 1 to 4, It is characterized in that The first switch and the second switch are both MOS tubes.

6. The signal enhancement circuit according to any one of claims 1 to 4, It is characterized in that The first switch and the second switch are both NMOS tubes.

7. The signal enhancement circuit according to any one of claims 1 to 4, It is characterized in that The voltage of the standard voltage terminal is 5V or 3.3V.

8. The signal enhancement circuit according to any one of claims 1 to 4, It is characterized in that The signal enhancement circuit also includes an enable terminal; The signal enhancement circuit is in an operating state when the enable terminal is at a high level, and is in a non-operating state when the enable terminal is at a low level.

9. A signal enhancement module, It is characterized in that The invention comprises a plurality of signal enhancement circuits as described in any one of claims 1 to 8; wherein each of the signal enhancement circuits is connected in series.

10. The signal enhancement module according to claim 9, It is characterized in that The input end of the signal enhancement module is connected to the control module, and the output end of the signal enhancement module is connected to the load module.

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