Semiconductor device

Abstract

The utility model discloses a semiconductor device. The semiconductor device comprises a first region and a second region, the semiconductor device comprises a substrate, a first metal layer, an insulating layer, a first capacitor structure, a second metal layer and a second capacitor structure, the first metal layer is arranged in the second region, the insulating layer is arranged in the first region and the second region and covers the first metal layer, and the second metal layer covers the second capacitor structure. The first capacitor structure is arranged on the insulating layer in the first region and partially penetrates through the insulating layer, the second metal layer is arranged on the insulating layer in the second region and is electrically connected with the first metal layer, and the second capacitor structure is arranged on the second metal layer. Therefore, according to the semiconductor device provided by the invention, different capacitor structures with height difference are respectively arranged in the two areas so as to be electrically connected to different components and execute different operations, thereby achieving more optimized operation performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology and provides a semiconductor device, in particular, a semiconductor device with a capacitor structure. Background Art

[0002] As various electronic products develop towards miniaturization, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally speaking, a dynamic random access memory with a recessed gate structure is composed of a large number of memory cells gathered to form an array area for storing information, and each memory cell can be composed of a transistor component and a capacitor component connected in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product requirements, the density of memory cells in the array area must be continuously improved, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, the existing technology or structure needs to be further improved to effectively improve the performance and reliability of related memory devices. Utility Model Content

[0003] An object of the present application is to provide a semiconductor device and a method for manufacturing the same, in which capacitor structures with height differences are respectively arranged in two regions of a substrate to electrically connect to different components and perform different operations, thereby achieving more optimized operating performance.

[0004] To achieve the above-mentioned purpose, an embodiment of the present application provides a semiconductor device, including a first area and a second area, the semiconductor device including a substrate, a first metal layer, an insulating layer, a first capacitor structure, a second metal layer and a second capacitor structure. The first metal layer is arranged on the substrate and is located in the second area. The insulating layer is arranged in the first area and the second area and covers the first metal layer. The first capacitor structure is arranged on the insulating layer in the first area and partially penetrates the insulating layer. The second metal layer is arranged on the insulating layer and is electrically connected to the first metal layer. The second capacitor structure is arranged on the insulating layer and the second metal layer in the second area and is located in the second area.

[0005] To achieve the above-mentioned purpose, an embodiment of the present application provides a method for manufacturing a semiconductor device, the semiconductor device includes a first area and a second area, and the manufacturing method includes the following steps. Provide a substrate. Form a first metal layer on the substrate, and the first metal layer is located in the second area. Form an insulating layer in the first area and the second area, and the insulating layer covers the first metal layer. Form a first capacitor structure on the insulating layer in the first area, and the first capacitor structure partially penetrates the insulating layer. Form a second metal layer on the insulating layer in the second area, and the second metal layer is electrically connected to the first metal layer. Form a second capacitor structure on the second metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings provide a deeper understanding of the embodiments of the present application and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and the relative sizes and proportions have been adjusted for the purpose of illustration and drawing convenience. The same symbols represent corresponding or similar features in different embodiments.

[0007] Figure 1 FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present application.

[0008] Figure 2 FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present application.

[0009] Figures 3 to 9 The figure is a schematic diagram of a method for manufacturing a semiconductor device according to a preferred embodiment of the present application, wherein:

[0010] Figure 3 is a schematic cross-sectional view of a semiconductor device after a barrier material layer is formed;

[0011] Figure 4 is a schematic cross-sectional view of a semiconductor device after a metal material layer is formed;

[0012] Figure 5 is a schematic cross-sectional view of a semiconductor device after an insulating layer is formed;

[0013] Figure 6 is a schematic cross-sectional view of a semiconductor device after another insulating layer is formed;

[0014] Figure 7 is a schematic cross-sectional view of a semiconductor device after a support layer structure is formed;

[0015] Figure 8 is a schematic cross-sectional view of a semiconductor device after a through hole is formed; and

[0016] Fig. 9It is a schematic cross-sectional view of a semiconductor device after forming a capacitor structure.

[0017] The reference numerals are described as follows:

[0018] 10, 30 Semiconductor devices

[0019] 100 Substrate

[0020] 101 District 1

[0021] 102 District 2

[0022] 104 Shallow Trench Isolation

[0023] 110 First Gate

[0024] 112 Dielectric layer

[0025] 114 Gate dielectric layer

[0026] 116 Gate layer

[0027] 118 Covering layer

[0028] 120 Dielectric layer

[0029] 122 Silicon oxide layer

[0030] 124 Silicon nitride layer

[0031] 126 Silicon oxide layer

[0032] 132 First Plug

[0033] 134 Metal silicide layer

[0034] 136 Insulation spacing

[0035] 138a, 238a Insulation material layer

[0036] 140 pads

[0037] 142, 242 Barrier layer

[0038] 144, 244 Metal layer

[0039] 144a, 244a Metal material layer

[0040] 150 Insulation layer

[0041] 160 First capacitor structure

[0042] 160b bottom

[0043] 162, 262 bottom electrode layer

[0044] 164, 264 Capacitor dielectric layer

[0045] 166, 266 Top electrode layer

[0046] 170, 270 Intermetallic dielectric layer

[0047] 176, 276 connection structure

[0048] 180, 280 support layer structure

[0049] 180a, 280a perforation

[0050] 182, 282 first supporting material layer

[0051] 184, 284 second supporting material layer

[0052] 186, 286 third supporting material layer

[0053] 188, 288 fourth supporting material layer

[0054] 210 Second Gate

[0055] 212 Semiconductor layer

[0056] 214 Barrier Layer

[0057] 216 Metal Layer

[0058] 218 Covering layer

[0059] 220 Doping area

[0060] 222 Gate dielectric layer

[0061] 230 Spacer structure

[0062] 232, 234, 236 Spacer

[0063] 238 interlayer dielectric layer

[0064] 238b Insulation material

[0065] 240 First Metal Layer

[0066] 240t Top

[0067] 242a Barrier material layer

[0068] 250 Second Metal Layer

[0069] 250e Sidewall

[0070] 250t top surface

[0071] 252 Insulation layer

[0072] 260 Second capacitor structure

[0073] 260b bottom

[0074] 272, 372 Second plug

[0075] 274 Metal Interconnect Structure

[0076] 302 Intermetallic dielectric layer

[0077] 310, 320 Metal interconnect layer

[0078] 374 Third Plug

[0079] D1 Horizontal direction

[0080] D2 vertical direction

[0081] O1, O2 openings DETAILED DESCRIPTION

[0082] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0083] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0084] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0085] Please refer to Figure 1 As shown, Figure 1 FIG. 1 is a cross-sectional diagram of a semiconductor device 10 in the first embodiment of the present application. Figure 1As shown, the semiconductor device 10 includes a substrate 100, a first metal layer 240, an insulating layer 150, a first capacitor structure 160, a second metal layer 250 and a second capacitor structure 260. The substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate or a substrate composed of other suitable materials, but is not limited thereto. The semiconductor device 10 further includes a first region 101 with a relatively high component concentration, for example, as a storage region (cell region) of the semiconductor device 10, and a second region 102 with a relatively low component concentration, for example, as a peripheral region (periphery region) of the semiconductor device 10. In one embodiment, the first region 101 and the second region 102 are, for example, arranged adjacent to each other, such as Figure 1 In addition, a plurality of shallow trench isolations (STI) 104 are disposed in the substrate 100 in the first region 101 and the second region 102 , and a plurality of active regions are defined in the substrate 100 .

[0086] like Figure 1 As shown, the first metal layer 240 is disposed on the substrate 100 and is located in the second area 102. The insulating layer 150 is disposed in the first area 101 and the second area 102 at the same time, and the insulating layer 150 disposed in the second area 102 covers the first metal layer 240. The second metal layer 250 is further disposed above the insulating layer 150 located in the second area 102, and is electrically connected to the first metal layer 240 disposed below the insulating layer 150. It should be particularly noted that the first capacitor structure 160 is disposed on the insulating layer 150 in the first area 101, and partially penetrates the insulating layer 150 to electrically connect the lower component, and the second capacitor structure 260 is disposed on the second metal layer 250 located in the second area 102, so that the bottom surface 160b of the first capacitor structure 160 and the bottom surface 260b of the second capacitor structure 260 are not coplanar. That is to say, by setting the insulating layer 150 and additionally setting the second metal layer 250 in the second area 102, a height difference is created between the first capacitor structure 160 and the second capacitor structure 260 in the first area 101 and the second area 102, which is beneficial for electrically connecting the first capacitor structure 160 and the second capacitor structure 260 set in different areas to different components through individual connection structures 176 and 276 in the subsequent manufacturing process to form different devices to perform different operations, thereby enabling the semiconductor device 10 to achieve more optimized operating performance.

[0087] In one embodiment, if Figure 1 As shown, the first capacitor structure 160 includes a plurality of bottom electrode layers 162, a capacitor dielectric layer 164, and a top electrode layer 166 arranged in sequence, while the second capacitor structure 260 includes a plurality of bottom electrode layers 262, a capacitor dielectric layer 264, and a top electrode layer 266 arranged in sequence. Wherein, each bottom electrode layer 162 and each bottom electrode layer 262 respectively have a U-shaped cross-sectional structure, each bottom electrode layer 162 penetrates the insulating layer 150 located in the first area 101, and each bottom electrode layer 262 penetrates the insulating layer 252 located in the second area 102, so as to physically contact and electrically connect the plurality of pads 140 arranged in the first area 101 and the second metal layer 250 arranged in the second area 102. An insulating spacer 136 is also arranged between adjacent pads 140 to isolate each other. The pads 140 and the first metal layer 240 located in the second area 102 preferably include the same conductive material. Wherein, the pad 140 and the first metal layer 240, for example, respectively include barrier layers 142, 242 and metal layers 144, 244 stacked in sequence, the barrier layers 142, 242, for example, include conductive barrier materials such as titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), and the metal layers 144, 244, for example, include copper (Cu), aluminum (Al), tungsten (W) or other suitable low resistivity conductive materials, but are not limited thereto. It should be noted that the second capacitor structure 260 is disposed on the insulating layer 150 and the second metal layer 250 in the second region 102, so that the bottom surface of the bottom electrode layer 262 of the second capacitor structure 260 (i.e., the bottommost surface 260b of the second capacitor structure 260) is higher than the bottom surface of the bottom electrode layer 162 of the first capacitor structure 160 (i.e., the bottommost surface 160b of the first capacitor structure 160), as shown in FIG. Figure 1 shown.

[0088] Specifically, if Figure 1As shown, the semiconductor device 10 further includes a plurality of first plugs 132 and a plurality of first gates 110 disposed in the first region 101. The first plugs 132 are disposed on the substrate 100, are located below each pad 140, and physically contact the active region of the substrate 100. A metal silicide layer 134 may be further disposed between the first plugs 132 and the pad 140, and adjacent first plugs 132 are also isolated from each other by insulating spacers 136. In one embodiment, the metal silicide layer 134 includes, for example, metal silicide materials such as cobalt disilicide (CoSi2), titanium silicide (TiSi2), or nickel silicide (Ni2Si), and the first plugs 132 include, for example, epitaxial materials such as silicon (Si), silicon phosphorus (SiP), silicon germanium (SiGe), or germanium (Ge), but is not limited thereto. Thus, the first plug 132 and the pad 140 can respectively serve as a storage node contact (SN contact) and a storage node pad (SN pad) of the semiconductor device 10 to be electrically connected to the first capacitor structure 160 .

[0089] like Figure 1As shown, the first gate 110 is disposed in the substrate 100, and includes a dielectric layer 112, a gate dielectric layer 114, a gate layer 116, and a cap layer 118 disposed in sequence. The top surface of the cap layer 118 is, for example, flush with the top surface of the substrate 100, so that the first gate 110 is covered by the dielectric layer 120 disposed on the substrate 100 in the first region 101, and is a buried gate. In one embodiment, the dielectric layer 120 includes, for example, a silicon oxide layer 122, a silicon nitride layer 124, and a silicon oxide layer 126 stacked in sequence to have an oxide-nitride-oxide (ONO) structure, but is not limited thereto. Thus, the first gate 110 can be used as a buried word line (BWL) of the semiconductor device 10, and can also form a transistor element (not shown) together with a doped region (not shown) in the substrate 100 also disposed in the first region 101. Under this setting, the semiconductor device 10 of this embodiment can receive voltage information from a bit line (not shown) and the buried word line by means of the first capacitor structure 160 located in the first region 101 and the transistor component together forming a minimum memory cell of the memory device. In addition, the minimum memory cell can be further electrically connected to a specific required component through a connection structure 176 arranged in an intermetallic dielectric layer 170 that entirely covers the first capacitor structure 160, so that the semiconductor device 10 of this embodiment can be used as a dynamic random access memory device (DRAM), thereby achieving more optimized operating performance.

[0090] On the other hand, Figure 1As shown, the semiconductor device 10 further includes a plurality of second gates 210, a second plug 272 and a metal interconnect structure 274 disposed in the second region 102. The second gate 210 is disposed on a gate dielectric layer 222 on the substrate 100, and includes in detail a semiconductor layer 212, a barrier layer 214, a metal layer 216 and a cap layer 218 stacked in sequence from bottom to top. In one embodiment, the gate dielectric layer 222 includes, for example, an insulating material such as silicon oxide, the semiconductor layer 212 includes, for example, a semiconductor material such as doped polysilicon or doped amorphous silicon, the barrier layer 214 includes, for example, a conductive barrier material such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, the metal layer 216 includes, for example, copper, aluminum, tungsten or other suitable low-resistivity conductive materials, and the cap layer 218 includes, for example, an insulating material such as silicon oxide, silicon nitride or silicon oxynitride, but is not limited thereto. A spacer structure 230 is also disposed on the sidewalls on both sides of each second gate 210, and the details include a spacer 232, a spacer 234, and a spacer 236 stacked in sequence on the sidewalls. In one embodiment, the spacer 232 and the spacer 236 include, for example, the same insulating material, such as silicon nitride, silicon carbonitride, etc., and the spacer 234 includes, for example, an insulating material different from the spacers 232 and 236, such as silicon oxide, silicon oxynitride, etc., but is not limited thereto. In addition, a doped region 220 is also disposed in the substrate 100 on both sides of the second gate 210, so that the second gate 210 and the doped region 220 together constitute a transistor component (not shown) in the second region 102.

[0091] It should be noted that the aforementioned first metal layer 240 is disposed in the interlayer dielectric layer 238 on the second gate 210, and specifically includes a conductive line portion located in the horizontal direction D1 and a plug portion located in the vertical direction D2. The plug portion of each first metal layer 240 physically contacts the metal layer 216 of the second gate 210 or the doped region 220 on one side of the second gate 210, and the aforementioned insulating layer 150 covers the conductive line portion of each first metal layer 240.

[0092] like Figure 1As shown, the second plug 272 and the metal interconnect structure 274 are respectively arranged in the metal inter-dielectric layer 270 on the insulating layer 150 and the second capacitor structure 260, so that each second plug 272 penetrates the insulating layer 150 and physically contacts the wire portion of the first metal layer 240, and the metal interconnect structure 274 simultaneously physically contacts the wire portion of at least one first metal layer 240 and the second metal layer 250. In other words, the metal interconnect structure 274 simultaneously contacts the top surface 240t of the first metal layer 240, the top surface 250t and the sidewall 250e of the second metal layer 250, so as to electrically connect the transistor components in the second region 102 and the second capacitor structure 260. Under this setting, the second capacitor structure 260 and the transistor group located in the second region 102 also together constitute the minimum storage unit, and can be electrically connected to a specific required component through the connection structure 276 also arranged in the metal inter-dielectric layer 270, so as to achieve a more optimized operation performance. In one embodiment, each second plug 272 and metal interconnect structure 274, for example, respectively includes a barrier layer (not shown, for example, including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide) and a metal layer (not shown, for example, including copper, aluminum, tungsten or other low-resistivity conductive materials) stacked in sequence, but is not limited to this.

[0093] According to the semiconductor device 10 of this embodiment, Figure 1 As shown, an insulating layer 150 is disposed in both the first region 101 and the second region 102, and a second metal layer 250 is additionally disposed in the second region 102, so that the first capacitor structure 160 in the first region 101 and the second capacitor structure 260 in the second region 102 are disposed on the insulating layer 150 and the second metal layer 250, respectively, and are not coplanar with each other. In addition, an insulating layer 252 that is only disposed in the second region 102 is additionally disposed on the second metal layer 250, so that the first capacitor structure 160 disposed in the first region 101 partially penetrates the insulating layer 150, and is electrically connected to the transistor component in the first region 101 through the storage node pad and the storage node plug, while the second capacitor structure 260 disposed in the second region 102 partially penetrates the insulating layer 252, and is electrically connected to the transistor component in the second region 102 through the second metal layer 250 and the first metal layer 240. Under this configuration, by additionally setting up a second metal layer 250 in the second region 102, a height difference is created between the first capacitor structure 160 and the second capacitor structure 260 in different regions, which is beneficial for electrically connecting to different components and forming different devices to perform different operations with the help of individual connection structures 176 and 276 in the subsequent manufacturing process, thereby enabling the semiconductor device 10 to achieve more optimized operating performance.

[0094] A person skilled in the art of the present application should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device of the present application may also have other aspects and is not limited to the above. Other embodiments or variations of the semiconductor device of the present application will be further described below. In order to simplify the description, the following description mainly details the differences between the embodiments, and no longer repeats the same aspects. In addition, the same components in the embodiments of the present application are marked with the same reference numerals to facilitate comparison between the embodiments.

[0095] Please refer to Figure 2 , which is a cross-sectional schematic diagram of a semiconductor device 30 in the second embodiment of the present application. The structure of the semiconductor device 30 of this embodiment is substantially the same as that of the semiconductor device 10 in the aforementioned embodiment, such as the semiconductor device 30 also includes a first region 101 and a second region 102, and the same parts are not repeated here. The main difference between the semiconductor device 30 of this embodiment and the aforementioned embodiment is that the semiconductor device 30 includes a metal interconnect layer 320 and a plurality of third plugs 374 disposed in the second region 102, wherein the third plugs 374 are respectively physically in contact with a first metal layer 240 and a second metal layer 250.

[0096] Specifically, if Figure 2 As shown, the semiconductor device 30 of this embodiment is provided with a second plug 372 and a third plug 374 in the intermetallic dielectric layer 270, respectively physically contacting the wire portion of each first metal layer 240 and the second metal layer 250. In addition, an intermetallic dielectric layer 302 and metal interconnection layers 310 and 320 located in the intermetallic dielectric layer 302 are provided on the intermetallic dielectric layers 170 and 270, so that the metal interconnection layer 310 disposed in the first area 101 physically contacts the connection structure 176 and is electrically connected to the minimum storage unit located in the first area 101, and the metal interconnection layer 320 disposed in the second area 102 physically contacts the connection structure 276, the second plug 372 and the third plug 374 respectively. It should be noted that at least one metal interconnect layer 320 is in physical contact with at least two third plugs 374 at the same time, wherein the bottom of at least one third plug 374 is in physical contact with the second metal layer 250, and the bottom of another third plug 374 is in physical contact with the conductive line portion of the first metal layer 240, and its side wall may selectively not be in contact with the side wall of the second metal layer 250 (e.g. Figure 2 Thus, the second metal layer 250 of the present embodiment is also electrically connected to the first metal layer 240, so that the metal interconnection layer 320 disposed in the second region 102 can be electrically connected to the minimum memory cell located in the second region 102 through the connection structure 276.

[0097] Under this setting, the semiconductor device 30 of the present embodiment can also create a height difference between the first capacitor structure 160 and the second capacitor structure 260 in the first area 101 and the second area 102 by means of the setting of the insulating layer 150 and the second metal layer 250, which is beneficial for electrically connecting the first capacitor structure 160 and the second capacitor structure 260 set in different areas to different components and forming different devices through the connection structures 176, 276 and the metal interconnection layers 310, 320 in the subsequent manufacturing process to perform different operations, thereby achieving more optimized operating performance.

[0098] In order to enable a person skilled in the art to which the present application belongs to easily understand the semiconductor device of the present application, the manufacturing method of the semiconductor device of the present application will be further described below.

[0099] See also Figures 3 to 9 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device 10 / 30 in a preferred embodiment of the present application, wherein the semiconductor device 10 / 30 includes a first region 101 and a second region 102. First, as Figure 3 As shown, a substrate 100 is provided, and shallow trench isolations 104 are formed in the substrate 100 in the first region 101 and the second region 102, respectively, and the active regions are simultaneously defined in the first region 101 and the second region 102, respectively. In one embodiment, the shallow trench isolations 104 are formed by, for example, first forming a plurality of trenches (not shown) in the substrate 100 using an etching process, and then filling the trenches with at least one insulating material (such as silicon oxide, silicon nitride, etc.) to form shallow trench isolations 104 whose surfaces are flush with the top surface of the substrate 100, but the present invention is not limited thereto.

[0100] Then, if Figure 3As shown, a plurality of first gates 110 are formed in the substrate 100 in the first region 101. In one embodiment, the method for making the first gate 110 includes but is not limited to the following steps, for example, first forming a plurality of trenches (not shown) that can simultaneously pass through the plurality of active regions and the shallow trench isolation 104, and then forming a dielectric layer 112 covering the entire surface of the trench, a gate dielectric layer 114 covering the surface of the lower half of the trench, a gate layer 116 filling the lower half of the trench, and a cap layer 118 filling the upper half of the trench in the trench, but not limited thereto. In addition, a dielectric layer 120 and a gate dielectric layer 222 are formed on the substrate 100 in the first region 101 and the second region 102, respectively. In one embodiment, the manufacturing method of the dielectric layer 120 and the gate dielectric layer 222 includes but is not limited to the following steps, for example, firstly forming a dielectric material layer on the substrate 100 in the first area 101 and the second area 102, including a first silicon oxide material layer (not shown), a silicon nitride material layer (not shown) and a second silicon oxide material layer (not shown) stacked in sequence, and then removing at least the second silicon oxide material layer and the silicon nitride material layer formed on the substrate 100 in the second area 102, so that the first silicon oxide material layer in the second area 102 of the substrate 100 forms the gate dielectric layer 222, and the dielectric material layer on the substrate 100 in the first area 101 forms the dielectric layer 120. Alternatively, in another embodiment, the dielectric material layer on the substrate 100 in the second area 102 can be completely removed, and then the gate dielectric layer 222 is formed separately. That is, the manufacturing process of the gate dielectric layer 222 in the second region 102 can be selectively integrated with the manufacturing process of the dielectric layer 120 in the first region, so that the gate dielectric layer 222 preferably includes the same material as the silicon oxide layer 122, but not limited thereto.

[0101] Then, if Figure 3As shown, a second gate 210 and a spacer structure 230 are formed on the substrate 100 in the second region 102. Furthermore, a doped region 220 is formed in the substrate 100 on one side of the second gate 210 and the spacer structure 230. In one embodiment, the manufacturing process of the second gate 210 includes, but is not limited to, the following steps. First, a semiconductor material layer (not shown, for example, including semiconductor materials such as polysilicon and doped amorphous silicon), a barrier material layer (not shown, for example, including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide), a metal material layer (not shown, for example, including metal materials with low resistivity such as tungsten, aluminum or copper) and a capping material layer (not shown, for example, including insulating materials such as silicon oxide, silicon nitride or silicon oxynitride) are sequentially formed in the second region 102, and finally the second gate 210 is formed by a patterning process. Furthermore, a spacer structure 230 is formed on the sidewall of the second gate 210. In one embodiment, the manufacturing process of the spacer structure 230 includes, for example, sequentially forming a first spacer material layer (not shown, for example, including silicon nitride, silicon carbonitride), a second spacer material layer (not shown, for example, including silicon oxide, silicon oxynitride) and a third spacer material layer (not shown, for example, including silicon nitride, silicon carbonitride) to cover the second gate 210 as a whole, and then performing an etch-back process to form spacers 232, 234 and 236 sequentially arranged on the sidewalls of each second gate 210 to form the spacer structure 230. It should be noted that, in a preferred embodiment, the manufacturing process of the second gate 210 located in the second region 102 can also be selectively integrated with the manufacturing process of the bit line structure (not shown) located in the first region 101, so that the bit line and the second gate 210 include the same stacking structure and material, but the present invention is not limited thereto.

[0102] Then, if Figure 3As shown, a deposition process is performed to simultaneously form insulating material layers 138a and 238a on the substrate 100 in the first region 101 and the second region 102, and the insulating material layer 138a in the first region 101 and the insulating material layer 238a in the second region 102 are partially removed through a mask layer (not shown), and a plurality of openings O1 and O2 are formed in the first region 101 and the second region 102, respectively. Each opening O1 exposes a portion of the substrate 100 in the first region 101, and each opening O2 exposes the metal layer 216 and the doped region 220 of the second gate 210, respectively. After the mask layer is completely removed, an epitaxial process is performed through another mask layer (not shown), and a first plug 132 is sequentially formed in the opening O1 in the first region 101, and then a metal silicide process is performed to form a metal silicide layer 134 on the first plug 132. In this way, the formed first plug 132 can be used as a storage node plug of the semiconductor device 10 / 30. After completely removing the other mask layer, the deposition process is performed again to form a barrier material layer (not shown, for example, including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide) on the substrate 100 covering both the first area 101 and the second area 102, wherein the barrier material layer is partially located in the openings O1 and O2, and partially located outside the openings O1 and O2, as shown in FIG. Figure 3 Afterwards, the barrier material layer in the first region 101 is subjected to an etch-back process to form a barrier layer 142 in the first region 101 , and a barrier material layer 242 a is formed in the second region 102 .

[0103] like Figure 4 As shown, another deposition process is performed to simultaneously form metal material layers 144a, 244a (for example, including copper, aluminum, tungsten or other suitable low-resistivity metal materials) on the substrate 100 in the first zone 101 and the second zone 102 to fill the remaining space of the openings O1, O2 and further cover the top surfaces of the insulating material layers 138a, 238a.

[0104] like Figure 5As shown, the metal material layers 144a, 244a and the barrier material layer 242a are patterned to form pads 140 and first metal layers 240 on the substrate 100 in the first region 101 and the second region 102, respectively. Next, the insulating material layer 138a in the first region 101 is completely removed, and a deposition and back etching process is performed in the first region 101, and a suitable insulating material such as silicon nitride, silicon oxynitride or silicon carbonitride is filled between adjacent pads 140 and adjacent first plugs 132 to form insulating spacers 136 whose top surfaces are aligned with the pads 140. In this way, the formed pads 140 can be used as storage node pads of the semiconductor device 10 / 30, and the formed first metal layer 240 includes both the plug portion that physically contacts the metal layer 216 or the doped region 220, and the conductive line portion located in the horizontal direction D1. In addition, another deposition and back-etching process is performed in the second area 102 to fill the insulating material 238b between the adjacent first metal layers 240, so that the insulating material 238b and the aforementioned insulating material layer 238a together form an interlayer dielectric layer 238 whose top surface is flush with the first metal layer 240. Afterwards, a deposition process is performed to form an insulating layer 150 on the substrate 100 in the first area 101 and the second area 102, such as an insulating material including silicon oxide, silicon nitride, silicon oxynitride or silicon carbonitride, to cover the pad 140 and the insulating spacer 136 in the first area 101 as a whole, and the first metal layer 240 and the interlayer dielectric layer 238 in the second area 102.

[0105] like Figure 6 As shown, at least one deposition process and a patterning process are performed to form a second metal layer 250 and an insulating layer 252 on the substrate 100 in the second region 102. The second metal layer 250 and the insulating layer 252 cover a portion of the first metal layer 240 and have sidewalls that are aligned with each other. In one embodiment, the second metal layer 250 includes, for example, copper, aluminum, tungsten or other low resistivity conductive materials, but is not limited thereto.

[0106] like Figure 7As shown, a support layer structure 180, 280 is simultaneously formed on the substrate 100 in the first area 101 and the second area 102, and the details include a first support material layer 182, 282 (for example, including silicon oxide), a second support material layer 184, 284 (for example, including silicon nitride or silicon carbonitride), a third support material layer 186, 286 (for example, including silicon oxide), and a fourth support material layer 188, 288 (for example, including silicon nitride or silicon carbonitride) stacked in sequence from bottom to top, but not limited thereto. In one embodiment, the first support material layer 182, 282 and the third support material layer 186, 286 preferably have a relatively large thickness, for example, about 5 to 10 times the thickness of the second support material layer 184, 284 and the fourth support material layer 188, 288, and the thickness of the fourth support material layer 188, 288 is preferably greater than the thickness of the second support material layer 184, 284, but not limited thereto. Thus, the overall thickness of the support layer structures 180 and 280 can reach about 1600 angstroms to 2000 angstroms, but is not limited thereto.

[0107] like Figure 8 As shown, a plurality of through holes 180a, 280a are formed in the support layer structures 180, 280, sequentially penetrating the fourth support material layers 188, 288, the third support material layers 186, 286, the second support material layers 184, 284, and the first support material layers 182, 282. The through holes 180a further penetrate the insulating layer 150 formed in the first region 101 to align with and physically contact the pads 140 thereunder, respectively, while the through holes 280a further penetrate the insulating layer 252 formed only in the second region 102 to physically contact the second metal layer 250 thereunder.

[0108] like Fig. 9 As shown, bottom electrode layers 162 and 262 with U-shaped cross-sections are formed in the through-holes 180a and 280a of the first area 101 and the second area 102, respectively. Then, at least one etching process is performed through a mask layer (not shown) to completely remove the third support material layer 186 and 286 and the first support material layer 182 and 282, and partially remove the fourth support material layer 188 and 288 and the second support material layer 184 and 284. Then, after completely removing the mask layer, at least one deposition process is performed to simultaneously form capacitor dielectric layers 164 and 264 and top electrode layers 166 and 266 on the substrate 100 in the first area 101 and the second area 102. The capacitor dielectric layers 164 and 264 cover the bottom electrode layers 162 and 262, while the top electrode layers 166 and 266 fill the remaining space between adjacent bottom electrode layers 162 and 262.

[0109] So, like Fig. 9As shown, the bottom electrode layer 162, the capacitor dielectric layer 164, and the top electrode layer 166 located in the first area 101 together form a first capacitor structure 160, and the remaining fourth support material layer 188 and the second support material layer 184 together form a support structure of the first capacitor structure 160. On the other hand, the bottom electrode layer 262, the capacitor dielectric layer 264, and the top electrode layer 266 located in the second area 102 together form a second capacitor structure 260, and the remaining fourth support material layer 288 and the second support material layer 284 together form a support structure of the second capacitor structure 260. Among them, the bottom electrode layer 162 of the first capacitor structure 160 passes through the insulating layer 150 located in the first area 101, and the bottom electrode layer 262 of the second capacitor structure 260 passes through the insulating layer 252 located in the second area 102, and is respectively arranged on the pad 140 and the first metal layer 240, so that the first capacitor structure 160 and the second capacitor structure 260 are not coplanar with each other. In this operation, by taking advantage of the height difference between the first capacitor structure 160 and the second capacitor structure 260 in different areas, it is beneficial to form a connection structure that electrically connects the first capacitor structure 160 and the second capacitor structure 260 respectively in the subsequent manufacturing process, so that the first capacitor structure 160 and the second capacitor structure 260 can be synchronously connected to different components to form different devices to perform different operations.

[0110] For example, in the subsequent manufacturing process, the intermetallic dielectric layers 170 and 270 that completely cover the first capacitor structure 160 and the second capacitor structure 260 may be further formed on the first region 101 and the second region 102, and then similar processes are performed to simultaneously or separately form the intermetallic dielectric layers 170 and 270. Figure 1 The second plug 272, the metal interconnect structure 274, and the connection structures 176 and 276 are shown. Alternatively, the metal interlayer 270 may be formed simultaneously or separately. Figure 2 After the second plug 372 and the third plug 374 are formed, a metal interconnection layer 320 is formed. The metal interconnection layer 320 physically contacts at least two third plugs 374 at the same time, wherein the bottom of at least one third plug 374 is in physical contact with the second metal layer 250, and the bottom of another third plug 374 is in contact with the first metal layer 240, and its side wall can selectively be not in contact with or in physical contact with the side wall of the second metal layer 250, but is not limited thereto.

[0111] According to the manufacturing method of this embodiment, an insulating layer 150 covering the entire area 101 and the second area 102 is formed, and a second metal layer 250 is formed on the second area 102, and then by integrating the manufacturing process of the components on the substrate 100 in the first area 101 and the second area 102, a first capacitor structure 160 and a second capacitor structure 260 are formed in the first area 101 and the second area 102 respectively by a similar process, resulting in a height difference between the first capacitor structure 160 and the second capacitor structure 260 in the first area 101 and the second area 102. In this way, it is beneficial to electrically connect the first capacitor structure 160 and the second capacitor structure 260 formed in different areas to different components and form different devices to perform different operations through the connection structure 176, 276 and the metal interconnection layer 310, 320 in the subsequent manufacturing process. Under this operation, the manufacturing method of the semiconductor device 10 / 30 in this embodiment can form a semiconductor device 10 / 30 with reliable structure and performance under the premise of simplified manufacturing.

[0112] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises a first region and a second region, and includes: substrate; A first metal layer, disposed on the substrate and located in the second region; an insulating layer, disposed in the first region and the second region and covering the first metal layer; A first capacitor structure is disposed on the insulating layer in the first region and partially penetrates the insulating layer; a second metal layer disposed on the insulating layer in the second region and electrically connected to the first metal layer; and The second capacitor structure is arranged on the second metal layer.

2. The semiconductor device according to claim 1, wherein: The bottom surface of the second capacitor structure and the bottom surface of the first capacitor structure are not coplanar.

3. The semiconductor device according to claim 1, wherein: The second capacitor structure and the first capacitor structure respectively include a bottom electrode layer, a capacitor dielectric layer and a top electrode layer which are arranged in sequence, and the bottom electrode layer of the second capacitor structure physically contacts the second metal layer.

4. The semiconductor device according to claim 3, characterized in that A bottom surface of the bottom electrode layer of the second capacitor structure is higher than a bottom surface of the bottom electrode layer of the first capacitor structure.

5. The semiconductor device according to claim 1, wherein: Also includes: A pad is arranged in the first region and below the insulating layer, the pad and the first metal layer comprise the same conductive material, wherein the first capacitor structure is arranged on the pad.

6. The semiconductor device according to claim 5, characterized in that Also includes: The first gate is disposed in the substrate in the first region and forms a storage unit together with the first capacitor structure.

7. The semiconductor device according to claim 1, wherein: Also includes: A first gate is disposed in the substrate in the first region; A first plug is disposed in the substrate within the first region and physically contacts the substrate; as well as The second gate is disposed on the substrate and located in the second region, wherein the first metal layer includes a plug portion that physically contacts the doped region on one side of the second gate.

8. The semiconductor device according to claim 7, characterized in that Also includes: a plurality of second plugs, disposed in the second region and physically contacting the first metal layer and the second metal layer respectively; as well as The metal interconnection layer is disposed on the second plug and physically contacts the second plug.

9. The semiconductor device according to claim 1, wherein: Also includes: The metal interconnection structure physically contacts a top surface of the first metal layer, a top surface of the second metal layer, and a side wall of the second metal layer.

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