Semiconductor device and method of manufacturing the same

Abstract

This application discloses a semiconductor device and a method for fabricating the same, relating to the field of semiconductor device technology. The semiconductor device includes a substrate, a stacked structure, and a first capping layer. The stacked structure is disposed on the substrate and includes an array portion and a first stepped portion, wherein the first stepped portion has a plurality of first stepped surfaces with gradually decreasing height along a first direction. The first capping layer is disposed on the stacked structure, covering the array portion and exposing the first stepped portion, wherein the top surface of the first capping layer is higher than the top surface of the first stepped portion. In a direction perpendicular to the substrate, the plurality of first stepped surfaces are simultaneously flush with the sidewalls of the first capping layer. Thus, the length ratio or area ratio of the first stepped portion relative to the array portion is effectively reduced, resulting in a more compact and robust semiconductor device structure, thereby achieving optimized operational performance.

Description

Technical Field

[0001] This application relates to a semiconductor device, and more particularly to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In modern electronic products, memory plays an indispensable and crucial role. Besides storing user data, memory is also responsible for storing program code executed by the central processing unit (CPU) and information that needs to be temporarily saved during computation. Memory can be divided into volatile memory and non-volatile memory. Common volatile memory includes dynamic random access memory (DRAM) and static random access memory (SRAM), whose data is lost after power is turned off and must be re-entered when power is restored. Non-volatile memory includes read-only memory (ROM) and flash memory, whose stored data persists even when power is cut off, allowing for direct retrieval of previously stored valid data upon power restoration.

[0003] With advancements in semiconductor manufacturing processes, memory has evolved from planar structures to three-dimensional (3D) stacked structures to achieve higher cell density per unit wafer area, meeting the demand for higher storage capacity. 3D memories typically include staircase structures formed on one or more sides of the memory stack to fan out word lines from each layer for electrical connection to interconnect structures (such as word line contact plugs). However, as the number of layers in the memory stack increases, related manufacturing processes and device structures require further improvement to maintain good device performance while simplifying the manufacturing process. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor device in which a stepped portion for pre-connecting to a plug is disposed on one side of an array portion. In this way, the length ratio or area ratio of the stepped portion to the array portion can be effectively reduced, making the structure of the semiconductor device more compact and stable, and achieving more optimized operating performance.

[0005] The purpose of this application is to provide a method for manufacturing a semiconductor device, in which a step portion is pre-formed on one side of an array portion by forming a cover layer. This effectively simplifies the manufacturing process of the step portion and reduces the length ratio or area ratio of the step portion to the array portion, resulting in a more compact and stable semiconductor device structure and optimized operational performance.

[0006] One embodiment of this application provides a semiconductor device including a substrate, a stacked structure, and a first cover layer. The stacked structure is disposed on the substrate and includes an array portion and a first stepped portion, wherein the first stepped portion has a plurality of first stepped surfaces with gradually decreasing height along a first direction. The first cover layer is disposed on the stacked structure, covering the array portion and exposing the first stepped portion, wherein the bottom surface of the first cover layer is higher than the top surface of the first stepped portion. In a direction perpendicular to the substrate, the plurality of first stepped surfaces are simultaneously flush with the sidewalls of the first cover layer.

[0007] An embodiment of this application provides a method for fabricating a semiconductor device, comprising the following steps: A substrate is provided, and a stacked structure is formed on the substrate. The stacked structure includes an array portion and a first stepped portion, wherein the array portion is disposed on one side of the first stepped portion, and the first stepped portion has a plurality of first stepped surfaces whose height gradually decreases along a first direction. A first cover layer is formed on the stacked structure, covering the array portion and exposing the first stepped portion, wherein the bottom surface of the first cover layer is higher than each of the first stepped surfaces. Attached Figure Description

[0008] The accompanying drawings are provided to give a more in-depth understanding of this embodiment and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams for illustrative and drafting purposes, and relative dimensions and scales have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0009] Figure 1 The drawing is a top view of a semiconductor device according to a first embodiment of this application;

[0010] Figure 2 The illustration is a three-dimensional schematic diagram of a semiconductor device according to the first embodiment of this application;

[0011] Figure 3 The illustration is a three-dimensional schematic diagram of the semiconductor device fabrication method according to the first embodiment of this application after the formation of the first mask layer;

[0012] Figure 4The illustration shows other schematic diagrams after the formation of the first mask layer in the method for fabricating a semiconductor device according to the first embodiment of this application;

[0013] Figure 5 The illustration is a three-dimensional schematic diagram of the semiconductor device fabrication method according to the first embodiment of this application after the etching process is performed;

[0014] Figure 6 The illustration shows another schematic diagram of the method for fabricating a semiconductor device according to the first embodiment of this application after performing an etching process;

[0015] Figure 7 The illustration is a schematic diagram of the semiconductor device fabrication method according to the first embodiment of this application after the formation of the second mask layer;

[0016] Figure 8 The illustration is a schematic diagram of the semiconductor device fabrication method according to the first embodiment of this application after the second mask layer has been trimmed;

[0017] Figure 9 The illustration is a schematic diagram of the semiconductor device fabrication method according to the first embodiment of this application after the second mask layer has been further modified;

[0018] Figure 10 The illustration is a schematic diagram of the semiconductor device fabrication method according to the first embodiment of this application after the formation of the stepped portion;

[0019] Figure 11 The diagram shown is a schematic diagram of the structure of a semiconductor device according to the second embodiment of this application;

[0020] Figure 12 The diagram shown is a schematic diagram of the structure of a semiconductor device according to the third embodiment of this application.

[0021] The reference numerals in the attached figures are explained as follows:

[0022] 10, 30, 40 semiconductor devices

[0023] 100 substrate

[0024] 102 Stop Layer

[0025] 110 stacked structure

[0026] 112 First Steps

[0027] 114 array section

[0028] 112s First Step Surface

[0029] 112t top surface

[0030] 112w sidewall

[0031] 114t top surface

[0032] 120 Conductive-Dielectric Layer Pair

[0033] 122 Dielectric Layer

[0034] 124 conductive layer

[0035] 130 Etching Stop Layer

[0036] 130a Etching Stop Material Layer

[0037] 140 First Covering Layer

[0038] 140t top surface

[0039] 150 First Plug

[0040] 150t top surface

[0041] 160 isolation layers

[0042] 162 First Isolation Layer

[0043] 164 Second Isolation Layer

[0044] 166 electrical connector

[0045] 166t top surface

[0046] 170 First mask layer

[0047] 172 Second mask layer

[0048] 212, 312, 412 Second Step Section

[0049] 212s, 312s, 412s second-step surface

[0050] Top surface of 212t and 312t

[0051] 250 Second plug

[0052] 340 Second Covering Layer

[0053] A1 First District

[0054] A2 Second Zone

[0055] A3 Third District

[0056] D1 First Direction

[0057] D2 Second Direction

[0058] D3 vertical direction

[0059] Distances of H1, H3, and H5

[0060] Distances of H2, H4, and H6

[0061] Lengths of L1 and L2

[0062] R1, R2, R3 gaps

[0063] S1, S3, S5 stepped surfaces

[0064] S2, S4, S6 stepped surfaces Detailed Implementation

[0065] To enable those skilled in the art to further understand this application, several preferred embodiments are listed below, along with accompanying drawings, to explain in detail the composition and desired effects of this application. Those skilled in the art can, without departing from the spirit of this application, substitute, recombine, or combine features from the following embodiments to complete other embodiments.

[0066] Figures 1 to 2 The illustrations are schematic diagrams of a semiconductor device 10 according to an embodiment of this application, including a top view and a perspective view of the semiconductor device 10. Those skilled in the art will readily understand that, in order to clearly present the three-dimensional structure of the components in the semiconductor device 10, Figure 2 Only present Figure 1 The structure of a part of the semiconductor device 10.

[0067] Please refer to Figure 1 and Figure 2 As shown, the semiconductor device 10 includes a substrate 100, a stacked structure 110, a plurality of electrical connectors 166, and a first capping layer 140. The substrate 100 is, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or other suitable materials. The stacked structure 110, the electrical connectors 166, and the first capping layer 140 are respectively disposed on the substrate 100, and the electrical connectors 166 pass through the stacked structure 110 and are connected to the substrate 100.

[0068] The stacked structure 110 includes an array portion 114 and a first stepped portion 112 disposed on one side of the array portion 114. The first stepped portion 112 has a plurality of first stepped surfaces 112s with gradually decreasing height along a first direction D1. In a direction perpendicular to the substrate 100, each first stepped surface 112s is tangent to the sidewall of the first capping layer 140. Those skilled in the art will readily understand that the height of the first stepped surface 112s refers to the distance from the first stepped surface 112s of each layer to the top surface of the substrate 100. Figure 2 The distance H1 shown is not a limitation.

[0069] Multiple electrical connectors 166 are disposed within the array portion 114 of the stacked structure 110, wherein each electrical connector 166 is arranged sequentially along a first direction D1 and a second direction D2 perpendicular to the first direction D1 to achieve the following configuration: Figure 1 The top view shown presents a memory array.

[0070] It should be noted that the first cover layer 140 is additionally disposed on the stacked structure 110, covering the array portion 114 and exposing the first step portion 112. The bottom surface of the first cover layer 140 is higher than the first step surface 112s of each layer. Thus, the arrangement of the first cover layer 140 can effectively cover and protect the array portion 114 of the stacked structure 110, and confine the first step portion 112 to one side of the array portion 114, greatly reducing the length or area occupied by the first step portion 112 in the stacked structure 110, making the structure of the semiconductor device 10 more compact and stable, and achieving more optimized operation performance.

[0071] In one embodiment, the ratio (L1 / L2) of the first step portion 112 of the stacked structure 110 to the length L2 of the array portion 114 of the stacked structure 110 in the second direction D2 is, for example, about 1 / 10 to 1 / 100, and the area ratio of the first step portion 112 to the array portion 114 may also be reduced accordingly, but is not limited thereto.

[0072] In detail, the stacked structure 110 includes multiple layers of dielectric layers 122 and multiple layers of conductive layers 124 alternately stacked in a vertical direction D3 (e.g., a direction perpendicular to the substrate 100), and each conductive layer 124 and the dielectric layer 122 above it together form a set of conductive-dielectric layer pairs 120, such as... Figure 2As shown. That is, the stacked structure 110 includes multiple sets of conductive-dielectric layer pairs 120 stacked sequentially, wherein the dielectric layer 122 and the conductive layer 124 in each set of conductive-dielectric layer pairs 120 extend completely across the entire array portion 114, and at least partially extend across the first step portion 112. The top surface 112t of the first step portion 112 is, for example, at the same horizontal height as the top surface 114t of the array portion 114, and is higher than the first step surface 112s of each layer.

[0073] In one embodiment, the conductive layer 124 includes, for example, a conductive material such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium-tungsten (Ti / W), titanium and titanium nitride (Ti / TiN), doped polysilicon, doped silicon, metal silicide, and other metallic or non-metallic conductive materials or any combination thereof, while the dielectric layer 122 includes, for example, a dielectric material such as silicon oxide (SiOx), silicon nitride (SiN), silicon oxynitride (SiON), and other dielectric materials or any combination thereof, but is not limited thereto.

[0074] For example Figure 1 and Figure 2 As shown, the semiconductor device 10 also includes a plurality of first plugs 150 disposed on the first step portion 112 and an isolation layer 160 disposed sequentially on the first cover layer 140. In detail, the first plugs 150 are all disposed on one side of the electrical connector 166 in the second direction D2 and are arranged sequentially in the second direction D2. Each first plug 150 is disposed in part in the isolation layer 160 and partly in the first step portion 112 of the stacked structure 110, and penetrates the dielectric layer 122 in the corresponding set of conductive-dielectric layer pairs 120, and is physically contacted and electrically connected to the conductive layer 124 in the same set of conductive-dielectric layer pairs 120. On the other hand, each electrical connector 166 has, for example, a cylindrical shape (e.g., a cylindrical shape), and is partially disposed in the isolation layer 160 and partially disposed in the array portion 114 of the stacked structure 110, so as to be electrically connected through the array portion 114 to a plug (not shown) or conductive structure (not shown) disposed in the substrate 100. Thus, the top surface 140t of the first cover layer 140 is lower than the top surface 150t of the first plug 150 or lower than the top surface 166t of the electrical connector 166.

[0075] In one embodiment, each first plug 150 and each electrical connector 166 includes, for example, a conductive material, such as a low-resistivity metallic conductive material like aluminum, titanium, tantalum, tungsten, niobium, molybdenum, or copper, preferably tungsten, but not limited thereto. In another embodiment, the insulating layer 160 includes, for example, a first insulating layer 162 and a second insulating layer 164 stacked in sequence, wherein the first insulating layer 162 and the second insulating layer 164 each include, for example, a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but not limited thereto.

[0076] In addition, a pad layer (not shown) and a stop layer 102 may be additionally provided between the substrate 100 and the stacked structure 110. The pad layer may include, for example, a material such as silicon oxide, while the stop layer 102 may include, for example, a dielectric material such as aluminum oxide (Al2O3) that has an etch selectivity with the dielectric layer 122 and the pad layer, but is not limited thereto.

[0077] Furthermore, in another embodiment, the stacked structure 110 of the semiconductor device 10 may also include a second step portion 212 disposed on one side of the array portion 114, and the semiconductor device 10 may additionally include an etch stop layer 130 disposed in the vertical direction D3 between the second step portion 212 and the first step portion 112, and a plurality of second plugs 250 disposed on the second step portion 212. Specifically, the second step portion 212 is disposed adjacent to the first step portion 112, and is also exposed from the first cover layer 140 and has a plurality of second step surfaces 212s with a gradually decreasing height along the first direction D1. The top surface 212t of the second step portion 212 is, for example, at the same horizontal height as the bottom surface of the etch stop layer 130, and is significantly lower than the bottom surface of the first cover layer 140, the top surface 114t of the array portion 114, or the top surface 112t of the first step portion 112. Those skilled in the art will readily understand that the height of the second stepped surface 212s refers to the distance from the second stepped surface 212s of each layer to the top surface of the substrate 100, such as... Figure 2 The distance H2 shown is not a limitation.

[0078] On the other hand, the etch stop layer 130 is disposed within the stacked structure 110 and has sidewalls flush with the first step portion 112, such that the second step portion 212 is exposed from the etch stop layer 130. The etch stop layer 130 may include, for example, a dielectric material having etch selectivity with the dielectric layer 122 and the pad layer, such as alumina, but is not limited thereto.

[0079] The second plug 250 is disposed on one side of the electrical connector 166 in the second direction D2, adjacent to the first plug 150, and arranged sequentially in the second direction D2, respectively corresponding to each of the second stepped surfaces 212s located in the second stepped portion 212. Each second plug 250 is also partially disposed in the insulating layer 160 and partially disposed within the second stepped portion 212 of the stacked structure 110, respectively penetrating the dielectric layer 122 in a corresponding set of conductive-dielectric layer pairs 120, and physically contacting and electrically connecting to the conductive layer 124 in the same set of conductive-dielectric layer pairs 120. In one embodiment, each second plug 250 may also include a conductive material, such as a low-resistivity metallic conductive material like aluminum, titanium, tantalum, tungsten, niobium, molybdenum, or copper, preferably including tungsten, but not limited thereto. It should be noted that each second stepped surface 212s is, for example, aligned with each adjacent first stepped surface 112s in the second direction D2. Figure 2 As shown, each of the second plugs 250 is offset from each of the adjacent first plugs 150 in the second direction D2, as follows: Figure 1 As shown, this allows both the second plug 250 and the first plug 150 to retain relatively sufficient manufacturing space (process window) in subsequent manufacturing processes.

[0080] Since the first step portion 112 and / or the second step portion 212 in this embodiment are both confined to one side of the array portion 114, the placement positions of the first plug 150 and / or the second plug 250 can also be confined to one side of the array portion 114. This significantly reduces the length or area occupied by the first step portion 112 and / or the second step portion 212 in the stacked structure 110, resulting in a more compact and stable structure for the semiconductor device 10. Furthermore, since the first step portion 112 and the second step portion 212 in this embodiment are respectively disposed above and below the etch stop layer 130, each first plug 150 and each second plug 250 can alternately fan out sequentially from different regions on each first step surface 112s and each second step surface 212s, avoiding compression of the fabrication space for the first plug 150 and the second plug 250. This allows the semiconductor device 10 in this embodiment to have a more reliable component structure and achieve more optimized operational performance.

[0081] However, those skilled in the art will readily understand that although the semiconductor device 10 of the foregoing embodiment is described as having both a first step portion 112 and a second step portion 212 on one side of the array portion 114, it is not limited thereto. Depending on the actual device requirements, either the first step portion 112 or the second step portion 212 may be provided only on one side of the array portion 114, and the etch stop layer 130 may be omitted. To enable those skilled in the art to implement the semiconductor device 10 of the foregoing embodiments of this application, a method for fabricating the semiconductor device 10 is further described below.

[0082] Please refer to Figures 3 to 10 The diagram illustrates the steps of a method for fabricating a semiconductor device 10 according to the first embodiment of this application, wherein... Figure 3 and Figure 5 The first diagram is a three-dimensional schematic diagram of the semiconductor device 10 at different manufacturing stages, while the other diagrams are top views and cross-sectional views of the semiconductor device 10 at different manufacturing stages.

[0083] First, such as Figure 3 and Figure 4 As shown, a substrate 100 is provided, and a stop layer 102, alternating layers of dielectric and conductive layers 122, an etch stop material layer 130a, alternating layers of dielectric and conductive layers 122, and a first capping layer 140 are sequentially formed on the substrate 100. Each conductive layer 124 and the dielectric layer 122 above it together form a set of conductive-dielectric layer pairs 120. Preferably, the number of dielectric layers 122 and conductive layers 124 stacked above and below the etch stop material layer 130a is the same, and the number of sets of conductive-dielectric layer pairs 120 disposed above and below the etch stop material layer 130a is also the same, but not limited thereto. Next, a first mask layer 170 is formed on the first capping layer 140. In one embodiment, the first mask layer 170 includes, for example, a photoresist material or other suitable material, but is not limited thereto.

[0084] Those skilled in the art should readily understand that Figure 4 This diagram simultaneously presents a top view of the semiconductor device 10 after the formation of the first mask layer 170, and a cross-sectional view along tangents A-A' and B-B'. It should be noted that the first capping layer 140 completely covers the second region A2 of the substrate 100, exposing the first region A1, while the first mask layer 170 completely covers the second region A2 and part of the first region A1 of the substrate 100, exposing the third region A3 of the substrate 100 (i.e., the portion of the first region A1 not covered by the first mask layer 170). Figure 3 and Figure 4As shown. In one embodiment, the second region A2 and the first region A1 of the substrate 100 are disposed adjacent to each other, for example, in the second direction D2, as shown. Figure 3 and Figure 4 As shown, but not limited thereto, and in another embodiment, the first region A1 may be set on the other side of the second region A2 in the second direction D2, or on one side of the second direction D2, depending on the actual device requirements.

[0085] like Figure 5 and Figure 6 As shown, an etching process, such as a dry etching process or a wet etching process, is performed using the first mask layer 170 to remove the dielectric layer 122 and conductive layer 124 exposed from the first mask layer 170, that is, to remove the aforementioned dielectric layer 122 and conductive layer 124 located in the third region A3 of the substrate 100. Those skilled in the art will readily understand that... Figure 6 This diagram simultaneously presents a top view of the semiconductor device 10 after the etching process, and a cross-sectional view along tangents A-A' and B-B'. It should be noted that the etching process uses an etch stop material layer 130a as the etch stop layer. Therefore, the dielectric layer 122 and conductive layer 124, located above the etch stop material layer 130a, within the third region A3, and exposed from the first mask layer 170, are completely removed. Furthermore, the etch stop material layer 130a is also partially removed, forming an etch stop layer 130 with sidewalls flush with the first mask layer 170, as shown below. Figure 5 and Figure 6 As shown. Then, the first mask layer 170 is completely removed.

[0086] like Figure 7 As shown, a second mask layer 172 is formed on the first cover layer 140, and then a first etching process, such as a dry etching process or a wet etching process, is performed using the second mask layer 172. Those skilled in the art will readily understand that... Figure 7 This diagram simultaneously presents a top view of the semiconductor device 10 after the first etching process and a cross-sectional view along tangents A-A', B-B', and C-C'. It should be noted that the second mask layer 172 completely covers the second region A2 and most of the first region A1 of the substrate 100, while only a portion of the first region A1 and a portion of the third region A3 are exposed by a notch R1 in the second mask layer 172. The notch R1, for example, presents as shown in... Figure 7 The rectangular opening shown is preferably located as follows: Figure 7This is shown as a corner of the second mask layer 172, but not limited thereto. Thus, the dielectric layer 122 and the conductive layer 124 located on the first region A1 and the third region A3 side in the second direction D2 are exposed from the second mask layer 172. Specifically, the dielectric layer 122 exposed from the notch R1 within the third region A3 is located below the etch stop layer 130, while the dielectric layer 122 exposed from the notch R1 within the first region A1 outside the third region A3 is located above the etch stop layer 130. Figure 7 The cross-sectional schematic diagram is shown. Then, using a first etching process, a pair of conductive-dielectric layers 120 located within the third region A3 and a pair of conductive-dielectric layers 120 located within the first region A1 outside the third region A3 are simultaneously removed downwards from the notch R1. A stepped surface S2 is formed within the third region A3 below the etch stop layer 130, and a stepped surface S1 is formed within the first region A1 outside the third region A3 above the etch stop layer 130. The stepped surface S2 is lower than the bottom surface of the etch stop layer 130 in the vertical direction D3, while the stepped surface S1 is lower than the bottom surface of the first cover layer 140 in the vertical direction D3. In one embodiment, the second mask layer 172 may include, for example, a photoresist material or other suitable material, but is not limited thereto.

[0087] like Figure 8 As shown, a trim-etching fabrication process is performed. First, the second mask layer 172 is trimmed, for example, by using a dry etching process or a wet etching process to further enlarge the size of the aforementioned notch R1, forming notch R2. Then, a second etching process is performed using the trimmed second mask layer 172. Those skilled in the art will readily understand that... Figure 8 This is a top view of the semiconductor device 10 of this embodiment after the trimming-etching process has been performed, and a cross-sectional view along tangents A-A', B-B' and C-C'.

[0088] It should be noted that the size of the enlarged notch R1 refers to the length of the enlarged notch R1 in the first direction D1 and / or the second direction D2. Preferably, the lengths of the notch R1 in both the first direction D1 and the second direction D2 are enlarged simultaneously, so that the notch R2 has a length greater than that of the notch R1 in both the first direction D1 and the second direction D2. Figure 8As shown in the top view diagram. Furthermore, during the finishing process, the thickness of the second mask layer 172 is relatively reduced. Thus, the notch R2 completely exposes the stepped surface S2 formed in the third region A3 and a portion of the dielectric layer 122 located in the third region A3, and completely exposes the stepped surface S1 formed in the first region A1 outside the third region A3 and a portion of the dielectric layer 122 located in the first region A1 outside the third region A3, while also partially exposing the first cover layer 140, but not limited thereto.

[0089] The second etching process involves simultaneously removing a pair of conductive-dielectric layers 120 downwards from the dielectric layer 122 exposed by the notch R2 and the stepped surfaces S1 and S2. Further, a stepped surface S4 is formed in the third region A3 below the etch stop layer 130, and a stepped surface S3 is formed in the first region A1 outside the third region A3 above the etch stop layer 130, further reducing the height of the stepped surfaces S1 and S2. It should be noted that because the portion exposed by the notch R2 is covered by the first capping layer 140, the formation of the stepped surfaces S1, S2, S3, and S4 is confined to the first region A1, allowing for more efficient control over the formation range and position of the stepped surfaces S1, S2, S3, and S4.

[0090] like Figure 9 As shown, a trimming-etching process is performed again. First, the second mask layer 172 is trimmed again, for example, by using a dry etching process or a wet etching process to further enlarge the size of the aforementioned notch R2, forming notch R3. Then, a third etching process is performed to remove the portion exposed from notch R3. Those skilled in the art should easily understand that... Figure 9 This is a top view of the semiconductor device 10 of this embodiment after the trimming-etching process has been performed, and a cross-sectional view along tangents A-A', B-B' and C-C'.

[0091] It should be noted that the size of the enlarged notch R2 refers, for example, to the length of the enlarged notch R2 in the first direction D1 and / or the second direction D2. Preferably, it only enlarges the length of the notch R2 in the first direction D1, so that the notch R3 has a length greater than that of the notch R2 in the second direction D2. Figure 9As shown in the top view diagram. Thus, the notch R3 completely exposes the stepped surfaces S2 and S4 formed in the third region A3 and a portion of the dielectric layer 122 located in the third region A3, and completely exposes the stepped surfaces S1 and S3 formed in the first region A1 outside the third region A3 and a portion of the dielectric layer 122 located in the first region A1 outside the third region A3, while also partially exposing the first cover layer 140, but not limited thereto. The third etching process involves simultaneously removing a pair of conductive-dielectric layers 120 downward from the dielectric layer 122 and the stepped surfaces S1, S2, S3, and S4 exposed by the notch R3, and further forming a stepped surface S6 located below the etch stop layer 130 in the third region A3, and a stepped surface S5 located above the etch stop layer 130 in the first region A1 outside the third region A3, and further reducing the height of the stepped surfaces S1, S2, S3, and S4 downward. It should be noted that, since the portion exposed from the notch R3 is still covered by the first covering layer 140, the formation of the stepped surfaces S1, S2, S3, S4, S5, and S6 is only located within the first region A1.

[0092] Thus, after repeating the aforementioned trimming-etching process, the second mask layer 172 is completely removed, allowing new stepped surfaces to be gradually formed within the third region A3 and the first region A1 outside the third region A3. Furthermore, the heights of the aforementioned stepped surfaces S1, S2, S3, S4, S5, and S6 are further reduced. Finally, multiple second stepped surfaces 212s with gradually decreasing heights along the first direction D1 are formed within the third region A3, and multiple first stepped surfaces 112s with gradually decreasing heights along the first direction D1 are formed within the first region A1 outside the third region A3. The second region A2, covered by the first cover layer 140, can then serve as the subsequent array portion 114, forming as shown... Figure 10 The stacked structure 110 shown is readily understood by those skilled in the art. Figure 10Similarly, a top view of the semiconductor device 10 of this embodiment after repeated trimming-etching fabrication processes and a cross-sectional view along tangents A-A', B-B', and C-C' are presented simultaneously. Specifically, the first stepped portion 112 and the second stepped portion 212 are adjacent to each other and are both formed on one side of the array portion 114. In the first stepped portion 112, the first stepped surface 112s of each layer is significantly lower than the bottom surface of the first capping layer 140. In the direction perpendicular to the substrate (i.e., in the top view direction), each first stepped surface 112s is flush with the sidewall of the first capping layer 140, and the distances H5, H3, and H1 from the first stepped surface 112s of each layer to the top surface of the substrate 100 gradually decrease in the first direction D1. The second step surface 212s of each layer in the second step section 212 is also lower than the top surface 114t of the array section 114 or the bottom surface of the etch stop layer 130, and the distances H6, H4, and H2 from the second step surface 212s of each layer to the top surface of the substrate 100 gradually decrease in the first direction D1.

[0093] Subsequently, an isolation layer 160 (including a first isolation layer 162 and a second isolation layer 164 stacked sequentially) can be formed on the stacked structure 110. Electrical connectors 166 arranged sequentially along the first direction D1 and the second direction D2 are formed in the array portion 114, and a first plug 150 and a second plug 250 are formed on the first step portion 112 and the second step portion 212, respectively. Finally, a structure is formed as shown in the figure. Figure 1 and Figure 2 The semiconductor device 10 shown.

[0094] Under this operation, the fabrication of the semiconductor device 10 in this embodiment is completed. It should be noted that since the first capping layer 140 is pre-formed on the alternating layers of dielectric layers 122 and conductive layers 124, the array portion 114 of the stacked structure 110 is pre-defined. The subsequent trimming-etching process will also be affected by the first capping layer 140 and will be limited to the first region A1 exposed outside the first capping layer 140. In other words, the first capping layer 140 can effectively protect the pre-defined array portion 114 from the trimming-etching process, so that the trimming-etching process will only simultaneously etch the pre-defined first step portion 112 and / or second step portion 212 to form the step surfaces S1, S3, S5 and step surfaces S2, S4, S6. Therefore, the first step portion 112 and / or the second step portion 212 can only be formed on one side of the array portion 114, and the positions of the subsequently formed first plug 150 and / or second plug 250 can also be correspondingly limited to one side of the array portion 114, so as to significantly reduce the length or area occupied by the first step portion 112 and / or the second step portion 212 in the stacked structure 110, so that the formed semiconductor device 10 has a more compact and stable structure, and can achieve more optimized operation performance. Furthermore, since the first step portion 112 and the second step portion 212 in this embodiment are respectively disposed above and below the etch stop layer 130, the subsequently formed first plug 150 and second plug 250 can alternately fan out from different regions on the first step surface 112s and the second step surface 212s, avoiding compression of the fabrication space of the first plug 150 and the second plug 250, thereby having a more reliable component structure.

[0095] Please refer to Figure 11 As shown, Figure 11 This is a cross-sectional schematic diagram of the semiconductor device 30 according to the second embodiment of this application. The structure and fabrication method of the semiconductor device 30 in this embodiment are generally the same as those of the semiconductor device 10 in the first embodiment described above, and the similarities will not be repeated here. The main difference between the semiconductor device 30 in this embodiment and the semiconductor device 10 described above is that it further includes a second cover layer 340 additionally disposed above the first cover layer 140, covering the top surface 140t of the first cover layer 140, the top surface 112t of the first stepped portion 112, and multiple sidewalls 112w and the first stepped surfaces 112s of each layer, and exposing the second stepped portion 312 of this embodiment.

[0096] In detail, the second stepped portion 312 in this embodiment is also disposed adjacent to the first stepped portion 112, and has a plurality of second stepped surfaces 312s with a gradually decreasing height along the first direction D1. In the direction perpendicular to the substrate, each second stepped surface 312s is tangent to the sidewall of the second cover layer 340. Furthermore, the top surface 312t of the second stepped portion 312 is, for example, at the same horizontal height as the bottom surface of the etch stop layer 130, and is significantly lower than the top surface 114t of the array portion 114 or the top surface 112t of the first stepped portion 112. It should be noted that the second stepped portion 312 is fabricated, for example, after the first stepped portion 112 is formed, by forming the second cover layer 340 on the first cover layer 140, thus defining the formation area of ​​the second stepped portion 312 (i.e., Figure 5 The third region A3 is shown. Then, another mask layer (not shown) with a notch (not shown) is formed on the second cover layer 340. Then, under the cover of the other mask layer and the second cover layer 340, an etching process is performed and a trimming-etching process is repeated until the second stepped portion 312 of this embodiment is formed. In this operation, each of the formed second stepped surfaces 312s is preferably staggered from each of the adjacent first stepped surfaces 112s in the second direction D2, such as... Figure 11 As shown, each second plug 250 disposed on each second stepped surface 312s is also staggered with each adjacent first plug 150 in the second direction D2 to further improve the manufacturing space of the second plug 250 and the first plug 150 in subsequent manufacturing processes. Furthermore, since the second cover layer 340 also covers the top surface 112t and side wall 112w of the first stepped portion 112, it can additionally protect the first stepped portion 112 when manufacturing the second stepped portion 312, and each second plug 250 penetrates the second cover layer 340 covering each first stepped surface 112s and contacts the corresponding conductive layer 124.

[0097] Since this embodiment employs a two-stage trimming-etching process using the first cover layer 140 and the second cover layer 340 respectively, the first stepped portion 112 and the second stepped portion 312 formed in the two-stage trimming-etching process can also have other appearances, not limited to those described above. For example, the stepped portions formed in the two-stage trimming-etching process can be formed on opposite sides of the array portion 114, or the stepped surfaces of the stepped portions formed in the two-stage trimming-etching process can, for example, have gradually increasing heights along different directions, or the stepped surfaces can have different dimensions, etc., but are not limited thereto.

[0098] According to the semiconductor device 30 in this embodiment, the first step portion 112 and / or the second step portion 312 are still confined to the same side of the array portion 114, so that the placement positions of the first plug 150 and / or the second plug 250 can still be confined to the same side of the array portion 114, and relatively sufficient manufacturing space is obtained. Therefore, in the semiconductor device 30 in this embodiment, the length or area occupied by the first step portion 112 and / or the second step portion 312 in the stacked structure 110 can also be significantly reduced, and the manufacturing space of the first plug 150 and the second plug 250 can be further improved, so that the semiconductor device 30 in this embodiment has a more reliable component structure and can achieve more optimized operation performance.

[0099] Please refer to Figure 12 As shown, Figure 12 This is a cross-sectional schematic diagram of the semiconductor device 40 according to the third embodiment of this application. The structure and fabrication method of the semiconductor device 40 in this embodiment are generally the same as those of the semiconductor device 20 in the second embodiment described above, and the similarities will not be repeated here. The main difference between the semiconductor device 40 in this embodiment and the semiconductor device 30 described above is that the second stepped portion 412 in this embodiment has a plurality of second stepped surfaces 412s with gradually increasing height along the first direction D1.

[0100] In detail, the second stepped portion 412 in this embodiment is also disposed adjacent to the first stepped portion 112, and is also formed after the first stepped portion 112 is formed, by performing an etching process and repeating a trimming-etching process under the cover of another mask layer and a second cover layer 340. However, the notch (not shown) on the other mask layer in this embodiment is formed in another corner of the other mask layer, so that the distances H2, H4, and H6 from the second stepped surface 412s of each layer in the second stepped portion 412 to the top surface of the substrate 100 gradually increase in the first direction D1, and are also staggered from each adjacent first stepped surface 112s, such as... Figure 12 As shown. In this configuration, each second plug 250 disposed on each second step surface 412s is also staggered from each adjacent first plug 150 in the second direction D2, thereby increasing the manufacturing space for the second plug 250 and the first plug 150 in subsequent manufacturing processes. Furthermore, the second cover layer 340 can also additionally protect the first step portion 112 when manufacturing the second step portion 412, and each second plug 250 penetrates the second cover layer 340 covering each first step surface 112s and contacts the corresponding conductive layer 124.

[0101] According to the semiconductor device 40 in this embodiment, the first step portion 112 and / or the second step portion 412 are still confined to the same side of the array portion 114, so that the placement positions of the first plug 150 and / or the second plug 250 can still be confined to the same side of the array portion 114, and relatively sufficient fabrication space is obtained. Therefore, in the semiconductor device 40 of this embodiment, the length or area occupied by the first step portion 112 and / or the second step portion 412 in the stacked structure 110 can also be significantly reduced, and the fabrication space of the first plug 150 and the second plug 250 can be further improved, so that the semiconductor device 40 in this embodiment has a more reliable component structure and can achieve more optimized operation performance.

[0102] In general, this application utilizes an additional capping layer to pre-define the positions of the array and stepped portions of the stacked structure on alternating dielectric and conductive layers. This allows the capping layer to further limit the etched areas in subsequent processes, particularly during etching and / or trim-etch fabrication. Therefore, the fabrication method of this application significantly reduces the length or area occupied by the stepped portions in the formed stacked structure through the capping layer, resulting in a more compact and robust semiconductor device with optimized operational performance. Furthermore, the subsequently fabricated plugs can be selectively fanned out sequentially from different regions of the stepped portions, improving the plug fabrication space and creating a more reliable component structure. Thus, the semiconductor device of this application achieves optimized structural integrity, thereby enhancing its component performance.

[0103] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0104] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," and "some embodiments" used in the specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A stacked structure is disposed on the substrate, including an array portion, a first stepped portion and a second stepped portion, wherein the first stepped portion has a plurality of first stepped surfaces with gradually decreasing height along a first direction. as well as A first cover layer is disposed on the stacked structure, covering the array portion and exposing the first step portion, wherein the top surface of the first cover layer is higher than the top surface of the first step portion; In a direction perpendicular to the substrate, the plurality of first stepped surfaces are simultaneously flush with the sidewalls of the first cover layer; The second stepped portion has a plurality of second stepped surfaces with gradually increasing height along the first direction; each of the second stepped surfaces and each of the first stepped surfaces are staggered relative to each other in a second direction, the second direction being perpendicular to the first direction; The stacked structure includes multiple sets of conductive-dielectric layer pairs arranged sequentially in the vertical direction; A pair of conductive-dielectric layers is formed by a conductive layer and an upper dielectric layer.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: Multiple first plugs are disposed on the first stepped portion and are respectively electrically connected to the conductive layer of a portion of the conductive-dielectric layer pair; and An isolation layer covers the top surface of the first cover layer and the first stepped portion.

3. The semiconductor device according to claim 2, characterized in that, An etch stop layer is disposed on the substrate and positioned in the vertical direction between the first step portion and the second step portion; Also includes: A second covering layer is disposed above the first covering layer, covering the top surface of the first covering layer, the topmost surface of the first stepped portion, and a plurality of sidewalls, and exposing the second stepped portion.

4. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; Multiple conductive layers and multiple dielectric layers are formed on the substrate in alternating stacks, forming multiple sets of conductive-dielectric layer pairs; A pair of conductive-dielectric layers is formed by a conductive layer and an upper dielectric layer together. A first capping layer is formed on the conductive-dielectric layer pair, exposing a first region of the conductive-dielectric layer pair and covering a second region of the conductive-dielectric layer pair; A second mask layer is formed on the first cover layer, and the first area is exposed through a notch in the second mask layer; A first etching process is performed using the second mask layer to partially remove one of the conductive-dielectric layer pairs. Repeated trimming-etching process is performed to form a stacked structure, which includes an array portion formed in the second region and a first stepped portion formed in the first region. The first stepped portion has a plurality of first stepped surfaces whose height gradually decreases along a first direction. as well as The second mask layer is completely removed; in a direction perpendicular to the substrate, the plurality of first stepped surfaces are simultaneously aligned with the sidewalls of the first cover layer.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The trimming-etching process also includes: The second mask layer is processed to widen the gap to partially expose the first cover layer and the conductive-dielectric layer pair; and A second etching process is performed using the modified second mask layer to partially remove one of the conductive-dielectric layer pairs again.

6. The method for fabricating a semiconductor device according to claim 4, characterized in that, The process includes the following steps before forming the second mask layer: An etch stop layer is formed on the substrate, located on a portion of the conductive-dielectric layer pair in the vertical direction; A first mask layer is formed on the first cover layer, and a third region is exposed from the first mask layer, the third region being completely located within the first region; The conductive-dielectric layer pair and the etch stop layer are removed from the portion through the first mask layer; and Completely remove the first mask layer.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, Also includes: The first etching process partially removes one pair of conductive-dielectric layers from the portion. The trimming-etching process is repeated to form a second step in the third region of the stacked structure. A plurality of first plugs are formed on the first step portion, and are electrically connected to the conductive layer of the corresponding conductive-dielectric layer pair respectively; as well as A plurality of second plugs are formed on the second step portion, and are electrically connected to the conductive layer of the conductive-dielectric layer pair of the corresponding portion, wherein the first plug and the second plug are staggered in a second direction, the second direction being perpendicular to the first direction.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The second stepped portion has a plurality of second stepped surfaces whose height gradually decreases along the first direction.

9. The method for fabricating a semiconductor device according to claim 7, characterized in that, The second stepped portion has a plurality of second stepped surfaces whose height gradually increases along the first direction.

10. The method for fabricating a semiconductor device according to claim 6, characterized in that, After the first stepped section is formed, the following is also included: A second covering layer is formed on the first covering layer, covering the top surface and sidewalls of the first stepped portion of the first region, and exposing the third region; Another mask layer is formed on the second cover layer, exposing the first region through a notch in the other mask layer; and Another trimming-etching process is repeated using the second cover layer and the other mask layer to form a second stepped portion in the third region of the stacked structure. The second stepped portion has a plurality of second stepped surfaces, and each of the second stepped surfaces and each of the first stepped surfaces are staggered with each other in a second direction, which is perpendicular to the first direction.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, Also includes: A plurality of first plugs are formed on the first stepped portion, each penetrating the second covering layer covering the first stepped portion and electrically connected to the conductive layer of the corresponding conductive-dielectric layer pair; as well as A plurality of second plugs are formed on the second step portion, and are electrically connected to the conductive layer of the conductive-dielectric layer pair of the corresponding portion, wherein the first plug and the second plug are staggered in the second direction.

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