Semiconductor device

Abstract

The utility model discloses a semiconductor device. The semiconductor device comprises a first wire, a first insulating layer, a second wire and a metal interconnection structure, the first wire is arranged in a first dielectric layer, the first insulating layer is arranged on the first dielectric layer and covers the first wire, the second wire is arranged in a second dielectric layer and partially overlaps the first wire, and the metal interconnection structure is arranged on the second dielectric layer. A metal interconnect structure is disposed within the second dielectric layer and the first insulating layer and physically contacts a top surface of the first conductive line, a top surface of the second conductive line, and a sidewall on one side of the second conductive line. Therefore, by means of the arrangement of the metal interconnection structure, the efficiency and the reliability of the wiring structure are improved on the premise that the space is saved, and the semiconductor device achieves more optimized operation performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology and provides a semiconductor device, in particular a semiconductor device with a metal interconnection structure. Background Art

[0002] As various electronic products develop towards miniaturization, the design of semiconductor devices must also meet the requirements of high integration and high density. Among them, in order to make miniaturized semiconductor devices meet the effects of high integration and high-speed operation, conventional technology uses miniaturized through holes and interlayer dielectric layers to form multi-layer interconnected metal interconnections. Generally speaking, the production of the metal interconnection line first forms a through hole in the dielectric layer, and then fills the barrier layer and the conductive layer in sequence. However, in response to product demand, the unit density of semiconductor devices must continue to increase, making the requirements for the setting position of the through hole and its critical size more stringent, making the difficulty and complexity of related manufacturing processes and designs continue to increase. When the deviation of the setting position or critical size of the through hole is too large, it is easy to cause component damage and affect the overall performance of the semiconductor device. Therefore, the existing technology or structure needs to be further improved to effectively improve the performance and reliability of related semiconductor devices. Utility Model Content

[0003] An object of the present application is to provide a semiconductor device and a method for manufacturing the same, which electrically connects a second wire and a first wire located above and below an insulating layer at the same time by setting a metal interconnection structure. In this way, the semiconductor device of the present application can improve the performance and structural reliability of the metal interconnection line while saving space, thereby achieving a more optimized operating performance.

[0004] To achieve the above-mentioned purpose, an embodiment of the present application provides a semiconductor device, comprising a first conductive line, a first insulating layer, a second conductive line, and a metal interconnection structure. The first conductive line is arranged in a first dielectric layer. The first insulating layer is arranged on the first dielectric layer and covers the first conductive line. The second conductive line is arranged in the second dielectric layer and partially overlaps the first conductive line in a vertical direction. The metal interconnection structure is arranged in the second dielectric layer and the first insulating layer, and physically contacts the top surface of the first conductive line, the top surface of the second conductive line, and the sidewall of one side of the second conductive line.

[0005] To achieve the above-mentioned purpose, an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising the following steps. A first conductive line is formed. A first dielectric layer is formed on both sides of the first conductive line. A first insulating layer is formed on the first dielectric layer to cover the first conductive line. A second conductive line is formed on the first insulating layer to partially overlap the first conductive line in a vertical direction. A second dielectric layer is formed on both sides of the second conductive line. A metal interconnection structure is formed in the second dielectric layer and the first insulating layer, and is physically in contact with the top surface of the first conductive line, the top surface of the second conductive line, and the sidewall of one side of the second conductive line. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings provide a deeper understanding of the embodiments of the present application and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and the relative sizes and proportions have been adjusted for the purpose of illustration and drawing convenience. The same symbols represent corresponding or similar features in different embodiments.

[0007] Figure 1 FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present application.

[0008] Figures 2 to 6 The figure is a schematic diagram of a method for manufacturing a semiconductor device according to a preferred embodiment of the present application, wherein:

[0009] Figure 2 is a schematic cross-sectional view of a semiconductor device after a first metal material layer is formed;

[0010] Figure 3 is a cross-sectional schematic diagram of a semiconductor device after a first conductive line is formed;

[0011] Figure 4 is a schematic cross-sectional view of a semiconductor device after a second metal material layer is formed;

[0012] Figure 5 is a schematic cross-sectional view of the semiconductor device after forming a second conductive line; and

[0013] Figure 6 It is a schematic cross-sectional view of a semiconductor device after a through hole is formed.

[0014] Figure 7 FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present application.

[0015] Figure 8 FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present application.

[0016] Fig. 9FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present application.

[0017] Fig.10 The figure is a cross-sectional schematic diagram of a semiconductor device according to the fifth embodiment of the present application. The reference numerals are explained as follows:

[0018] 10, 20, 30, 40, 50 semiconductor devices

[0019] 100 Substrate

[0020] 101 Shallow Trench Isolation

[0021] 103 Active area

[0022] 105 Doping region

[0023] 110 Gate structure

[0024] 111 Gate dielectric layer

[0025] 113 Semiconductor layer

[0026] 115 Barrier

[0027] 117 Metal Layer

[0028] 119 Covering layer

[0029] 120 Spacer structure

[0030] 121, 123, 125 gap wall

[0031] 130 Interlayer dielectric layer

[0032] 132 Plug

[0033] 140 First conductor

[0034] 140e Sidewall

[0035] 140t Top

[0036] 141 Barrier

[0037] 141a Barrier material layer

[0038] 143 Metal Layer

[0039] 143a First metal material layer

[0040] 151 first dielectric layer

[0041] 153 First insulation layer

[0042] 155 second dielectric layer

[0043] 157 Intermetallic Dielectric Layer

[0044] 157a, 157b Side wall

[0045] 160, 460, 560 Second conductor

[0046] 160e, 160f, 460e, 460f sidewall

[0047] 160t, 460t top surface

[0048] 161, 561 Barrier layer

[0049] 161a Barrier material layer

[0050] 163, 563 Metal layer

[0051] 163a Second metal material layer

[0052] 170, 270, 370, 470, 570 metal interconnect structures

[0053] 170a, 270a, 470a first side wall

[0054] 170b, 370b, 470b Second side wall

[0055] 171 Barrier

[0056] 173 Metal Layer

[0057] 180 Plug

[0058] 190, 410 connection structure

[0059] 459 Second insulation layer

[0060] 490 Capacitor Structure

[0061] 491 Bottom electrode layer

[0062] 493 Capacitor Dielectric Layer

[0063] 495 Top electrode layer

[0064] 560b bottom

[0065] D1 Horizontal direction

[0066] D2 vertical direction

[0067] O1, O2 through holes DETAILED DESCRIPTION

[0068] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0069] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0070] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0071] Please refer to Figure 1 As shown, Figure 1 FIG. 1 is a cross-sectional diagram of a semiconductor device 10 in the first embodiment of the present application. Figure 1 As shown, the semiconductor device 10 includes a first conductive line 140, a first insulating layer 153, a second conductive line 160, and a metal interconnection structure 170. The first conductive line 140 is disposed in a first dielectric layer 151. The first insulating layer 153 is disposed on the first dielectric layer 151 and covers the first conductive line 140. The second conductive line 160 is disposed in the second dielectric layer 155 and partially overlaps the first conductive line 140 in a vertical direction D2. In one embodiment, the second conductive line 160 includes a barrier layer 161 and a metal layer 163 stacked in sequence, wherein the barrier layer 161 includes, for example, conductive barrier materials such as titanium and / or titanium nitride (TiN), tantalum (Ta), and / or tantalum oxide (TaN), and the metal layer 163 includes, for example, copper (Cu), aluminum (Al), tungsten (W), or other suitable low-resistivity conductive materials, but is not limited thereto. The first dielectric layer 151, the first insulating layer 153, and the second dielectric layer 155 include, for example, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride, wherein the material of the first insulating layer 153 is preferably different from the materials of the first dielectric layer 151 and the second dielectric layer 155, but is not limited to this.

[0072] It should be particularly noted that the metal interconnection structure 170 is disposed in both the second dielectric layer 155 and the first insulating layer 153, and physically contacts the top surface 160t of the second conductive line 160, the side wall 160e of the second conductive line 160, and the top surface 140t of the first conductive line 140. In other words, by disposing the metal interconnection structure 170 at a position that at least partially overlaps the second conductive line 160 and the first conductive line 140, the metal interconnection structure 170 can electrically connect the second conductive line 160 located above the first insulating layer 153 and the first conductive line 140 located below the first insulating layer 153 at the same time. Under this arrangement, the metal interconnection structure 170 of the present embodiment can simultaneously connect the metal interconnection lines (i.e., the first conductive line 140 and the second conductive line 160) disposed at intervals from each other while saving space, which can not only improve the component performance and reliability, but also enable the semiconductor device 10 to achieve a more optimized operating performance.

[0073] Specifically, the metal interconnect structure 170 is simultaneously disposed in the first insulating layer 153, the second dielectric layer 155, and the intermetallic dielectric layer 157 covering the second conductive line 160, and has a relatively large extension height in the vertical direction D2. The metal interconnect structure 170 has a first sidewall 170a and a second sidewall 170b in the vertical direction D2. In one embodiment, the portion of the first sidewall 170a that physically contacts the first conductive line 140 in the vertical direction D2 preferably falls on the top surface 140t of the first conductive line 140, that is, the portion in the horizontal direction D1 does not fall beyond the sidewall 140e on one side of the first conductive line 140, such as Figure 1 However, other portions of the first sidewall 170a that are not in direct contact with the first conductive line 140 can be selectively extended outward, or even extended to a position beyond the sidewall 140e (not shown), so that the metal interconnect structure 170 can present a cross-sectional structure with a larger top and a smaller bottom as a whole, such as Figure 1 As shown, it is helpful to simplify the manufacturing process of the metal interconnect structure 170 and improve its component reliability. Similarly, the portion of the second sidewall 170b that physically contacts the second conductive line 160 in the vertical direction D2 also preferably falls on the top surface 160t of the second conductive line 160, that is, the landing point of the portion in the horizontal direction D1 does not exceed the sidewall 160f on the other side of the second conductive line 160, and other portions of the second sidewall 170b that do not directly contact the second conductive line 160 can also selectively extend outward, or even extend to a position beyond the sidewall 160f.

[0074] like Figure 1As shown, the semiconductor device 10 also includes a substrate 100, and the aforementioned first conductive line 140, first dielectric layer 151, first insulating layer 153, second conductive line 160, second dielectric layer 155 and metal interconnect structure 170 are all disposed on the substrate 100. In one embodiment, the substrate 100 is, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate composed of other suitable materials, but is not limited thereto. In addition, a plurality of shallow trench isolations (STI) 101 are also disposed in the substrate 100 to define a plurality of active regions 103 on the substrate 100. For example Figure 1 As shown, the semiconductor device 10 further includes a plurality of gate structures 110 and a plurality of plugs 132. The gate structures 110 are disposed on the substrate 100 in a mutually separated manner and are located below the first conductive line 140. The gate structure 110 includes a gate dielectric layer 111, a semiconductor layer 113, a barrier layer 115, a metal layer 117 and a cap layer 119, which are disposed in sequence. The gate dielectric layer 111 includes, for example, an insulating material such as silicon oxide, the semiconductor layer 113 includes, for example, a semiconductor material such as doped polysilicon or doped amorphous silicon, the barrier layer 115 includes, for example, a conductive barrier material such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, the metal layer 117 includes, for example, copper, aluminum, tungsten or other suitable low-resistivity conductive materials, and the cap layer 119 includes, for example, an insulating material such as silicon oxide, silicon nitride or silicon oxynitride, but is not limited thereto.

[0075] like Figure 1As shown, a spacer structure 120 is further disposed on the sidewalls on both sides of each gate structure 110, including a spacer 121, a spacer 123 and a spacer 125 stacked in sequence on the sidewalls. In one embodiment, the spacer 121 and the spacer 125 include, for example, the same insulating material, such as silicon nitride, silicon carbonitride, etc., and the spacer 123 includes, for example, an insulating material different from the spacers 121 and 125, such as silicon oxide, silicon oxynitride, etc., but is not limited thereto. Under this configuration, the gate structure 110 can form a transistor component (not shown) together with the doped regions 105 disposed on both sides of the gate structure 110 in the substrate 100. On the other hand, the plug 132 is disposed in the interlayer dielectric layer 130 on the substrate 100 and the gate structure 110, and physically contacts the metal layer 117 of the gate structure 110, or the doped region 105 on one side of the gate structure 110. In one embodiment, the semiconductor device 10 includes, for example, a plurality of first conductive lines 140 and a plurality of second conductive lines 160. The first conductive lines 140 are separately disposed in the first dielectric layer 151 and physically contact the plugs 132 respectively, while the second conductive lines 160 are separately disposed in the second dielectric layer 155. Preferably, each first conductive line 140 and each plug 132 are integrally formed and include a barrier layer 141 and a metal layer 143 stacked in sequence, such as Figure 1 As shown, but not limited thereto. The barrier layer 141 includes, for example, conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, and the metal layer 143 includes, for example, copper, aluminum, tungsten or other suitable low-resistivity conductive materials, but not limited thereto. It should be noted that the first conductive wire 140 and the second conductive wire 160 can be directly electrically connected through the metal interconnect structure 170, or the first conductive wire 140 and the second conductive wire 160 can be respectively connected through two plugs 180 disposed in the intermetallic dielectric layer 157, and then the first conductive wire 140 and the second conductive wire 160 are indirectly electrically connected by a connection structure 190 that simultaneously connects the two plugs 180. In one embodiment, the metal interconnect structure 170 and the plug 180 also include a barrier layer 171 and a metal layer 173 stacked in sequence, wherein the barrier layer 171 includes, for example, conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, and the metal layer 173 includes, for example, copper, aluminum, tungsten or other suitable low-resistivity conductive materials, but is not limited thereto.

[0076] like Figure 1As shown, according to the semiconductor device 10 of this embodiment, the metal interconnection structure 170 is arranged at a position that at least partially overlaps the second wire 160 and the first wire 140, so that the metal interconnection structure 170 can simultaneously electrically connect the second wire 160 located above the first insulating layer 153 and the first wire 140 located below the first insulating layer 153, thereby improving the configuration space and structural reliability of the metal interconnection line. As a result, the first wire 140 and the second wire 160 of the semiconductor device 10 can be directly electrically connected through the metal interconnection structure 170, thereby improving the component performance of the metal interconnection line while saving space, so that the semiconductor device 10 can achieve a more optimized operating performance.

[0077] In order to enable a person skilled in the art to which the present application belongs to easily understand the semiconductor device 10 of the present application, the manufacturing method of the semiconductor device 10 of the present application will be further described below.

[0078] See also Figures 2 to 6 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device 10 in a preferred embodiment of the present application. First, Figure 2As shown, a substrate 100 is provided, and a shallow trench isolation 101 is formed in the substrate 100 to define an active area 103. In one embodiment, the formation of the shallow trench isolation 101 is, for example, to first form a plurality of trenches (not shown) in the substrate 100 using an etching process, and then fill the trenches with at least one insulating material (such as silicon oxide, silicon nitride, etc.) to form a shallow trench isolation 101 whose surface is flush with the top surface of the substrate 100, but the invention is not limited thereto. Next, a gate structure 110 is formed on the substrate 100, and a spacer structure 120 is formed on the sidewall of the gate structure 110, and then a doped region 105 is formed in the substrate 100 on one side of the gate structure 110 and the spacer structure 120. The manufacturing process of the gate structure 110, for example, includes but is not limited to the following steps. First, a semiconductor material layer (not shown, for example, including semiconductor materials such as polycrystalline silicon and doped amorphous silicon), a barrier material layer (not shown, for example, including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide), a metal material layer (not shown, for example, including metal materials with low resistivity such as tungsten, aluminum or copper) and a capping material layer (not shown, for example, including insulating materials such as silicon oxide, silicon nitride or silicon oxynitride) are sequentially formed on the substrate 100, and finally a patterning process is performed to form a gate structure 110. The manufacturing process of the spacer structure 120, for example, includes sequentially forming a first spacer material layer (not shown, for example, including silicon nitride, silicon carbonitride), a second spacer material layer (not shown, for example, including silicon oxide, silicon oxynitride) and a third spacer material layer (not shown, for example, including silicon nitride, silicon carbonitride) to integrally cover the gate structure 110, and then performing a back etching process to form a spacer 121, a spacer 123 and a spacer 125 sequentially located on the side wall of the gate structure 110 to form the spacer structure 120.

[0079] Then, if Figure 2 As shown, a deposition process is performed to form an interlayer dielectric layer 130 on the substrate 100 to cover the gate structure 110 and the substrate 100 as a whole, and a plurality of openings (not shown) are formed in the interlayer dielectric layer 130 through a mask layer (not shown) to expose the metal layer 117 of the gate structure 110 and the doped region 105 on one side of the gate structure 110, respectively. In one embodiment, the interlayer dielectric layer 130 includes, for example, insulating materials such as silicon oxide and silicon oxide, but is not limited thereto. After the mask layer is completely removed, a deposition process is performed to form a barrier material layer 141a (for example, including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide) on the substrate 100, which is partially located in the openings and partially located outside the openings, as shown in FIG. Figure 2Then, another deposition process is performed to form a first metal material layer 143 a (eg, including copper, aluminum, tungsten or other suitable low-resistivity metal materials) on the substrate 100 , filling the remaining space of the opening and further covering the top surface of the interlayer dielectric layer 130 .

[0080] like Figure 3 As shown, Figure 2 The first metal material layer 143a and the barrier material layer 141a are subjected to a first photolithography process to simultaneously form a first conductive line 140 located in the horizontal direction D1 and a plug 132 located in the vertical direction D2. In this way, the first conductive line 140 and the plug 132 can be integrally formed, and together include a barrier layer 141 and a metal layer 143 stacked in sequence. Then, a deposition process and an etching back process are performed to form a first dielectric layer 151 whose top surface is aligned with the top surface 140t of the first conductive line 140, so that the first conductive line 140 is located in the first dielectric layer 151.

[0081] like Figure 4 As shown, multiple deposition processes are performed to sequentially form a first insulating layer 153, a barrier material layer 161a and a second metal material layer 163a on the first conductive line 140 and the first dielectric layer 151, wherein the first insulating layer 153, the barrier material layer 161a and the second metal material layer 163a all integrally cover the first conductive line 140 and the first dielectric layer 151.

[0082] like Figure 5 As shown, a second photolithography process is performed on the second metal material layer 163a and the barrier material layer 161a to form a second conductive line 160 located in the horizontal direction D1. Then, a deposition process and an etch-back process are performed again to form a second dielectric layer 155 whose top surface is aligned with the top surface 160t of the second conductive line 160, so that the second conductive line 160 is located in the second dielectric layer 155.

[0083] like Figure 6As shown, a deposition process is performed again to form an intermetallic dielectric layer 157 on the substrate 100, covering the second conductive line 160 and the second dielectric layer 155. In addition, a mask layer (not shown) and at least one second conductive line 160 are used as self-aligned masks, and a plurality of through holes O1 and O2 are formed in the intermetallic dielectric layer 157 by a self-aligned process. The through hole O1 sequentially penetrates the intermetallic dielectric layer 157, the second dielectric layer 155 and the first insulating layer 153 to simultaneously expose the top surface 160t and the sidewall 160e of the second conductive line 160 and the top surface 140t of the first conductive line 140, while the through hole O2 sequentially penetrates the intermetallic dielectric layer 157, the second dielectric layer 155 and / or the first insulating layer 153 to expose the top surface 160t of the second conductive line 160 or the top surface 140t of the first conductive line 140. It should be noted that, in another embodiment, the through holes O1 and O2 can be integrated with the manufacturing process of the connection structure electrically connecting other components, and have a relatively large length in the vertical direction D2, for example, about 10 to 20 times the length of the first conductive line 140 or the second conductive line 160, but not limited thereto. In addition, due to the load effect of etching, the through holes O1 and O2 have a cross-section that is small at the top and large at the bottom, such as Figure 6 As shown. The part where the side wall 157a of the through hole O1 in the vertical direction D2 physically contacts the first conductive line 140 preferably falls on the top surface 140t of the first conductive line 140, and does not exceed the side wall 140e of the first conductive line 140 in the horizontal direction D1. Similarly, the part where the side wall 157b of the through hole O1 in the vertical direction D2 physically contacts the second conductive line 160 also preferably falls on the top surface 160t of the second conductive line 160, and does not exceed the side wall 160f of the second conductive line 160 in the horizontal direction D1. Under this operation, it is helpful to simplify the manufacturing process of the through holes O1 and O2, avoid being affected by the critical size of the miniaturized through hole when manufacturing the through holes O1 and O2, and effectively improve the component reliability of the metal interconnect structure 170 formed subsequently.

[0084] Then, if Figure 6 As shown, after the mask layer is completely removed, a deposition process is performed again to sequentially form a barrier material layer (not shown, for example, including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide) and a metal material layer (not shown, for example, including copper, aluminum, tungsten or other suitable low-resistivity metal materials) on the substrate 100 to fill the through holes O1 and O2, so that the barrier material layer physically contacts the top surface 140t of the first conductive line 140 and the top surface 160t and sidewall 160e of the second conductive line 160, and then a planarization process is performed to form the through holes O1 and O2 as shown in FIG. Figure 1The metal interconnect structure 170 and the plug 180 are shown. In this way, the first wire 140 and the second wire 160 can be directly electrically connected through the metal interconnect structure 170, or a connection structure 190 that simultaneously connects the two plugs 180 is further formed on the intermetallic dielectric layer 157, so that the first wire 140 and the second wire 160 are indirectly electrically connected through the connection structure 190.

[0085] According to the manufacturing method of this embodiment, a through hole O1 is formed on the second conductive line 160 and the second dielectric layer 155, which penetrates the second dielectric layer 155 and the first insulating layer 153 at the same time, so that the through hole O1 has a cross section that is small at the top and large at the bottom in the vertical direction D2. In this way, a metal interconnection structure 170 that can electrically connect the second conductive line 160 located above the first insulating layer 153 and the first conductive line 140 located below the first insulating layer 153 is formed in the through hole O1. In this operation, the metal interconnection structure 170 has a cross-sectional structure that is small at the top and large at the bottom, and physically contacts the top surface 160t of the second conductive line 160, the side wall 160e on one side of the second conductive line 160, and the top surface 140t of the first conductive line 140, and the first side wall 170a and the second side wall 170b that contact the top surface 140t and the top surface 160t do not exceed the side wall 140e of the first conductive line 140 and the side wall 160e of the second conductive line 160. Therefore, the manufacturing method of this embodiment can form metal interconnects with improved device performance and reliable structure under the premise of simplifying the process, effectively save the installation space of the metal interconnects, and form a semiconductor device 10 with more optimized operating performance.

[0086] A person skilled in the art of the present application should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device and the method for manufacturing the same may also have other aspects and are not limited to the above. The following will further describe other embodiments or variations of the semiconductor device and the method for manufacturing the same of the present application. In order to simplify the description, the following description mainly describes the differences between the embodiments, and will not repeat the same aspects. In addition, the same components in the embodiments of the present application are marked with the same reference numerals to facilitate comparison between the embodiments.

[0087] Please refer to Figure 7, which is a cross-sectional schematic diagram of a semiconductor device 20 in the second embodiment of the present application. The structure of the semiconductor device 20 of the present embodiment is substantially the same as that of the semiconductor device 10 in the aforementioned embodiment, and the similarities are not repeated here. The main difference between the semiconductor device 20 of the present embodiment and the aforementioned embodiment is that the portion of the first sidewall 270a of the metal interconnect structure 270 that physically contacts the first wire 140 falls on the top surface 140t of the first wire 140 in the vertical direction D2 and just cuts the sidewall 140e of the first wire 140. In this way, the metal interconnect structure 270 can also present a cross-sectional structure with a larger top and a smaller bottom as a whole, which is beneficial to improve the reliability of its components under the premise of simplifying the manufacturing process of the metal interconnect structure 270.

[0088] The semiconductor device 20 of the present embodiment also sets the metal interconnection structure 270 at a position at least partially overlapping the second wire 160 and the first wire 140, and directly electrically connects the second wire 160 located above the first insulating layer 153 and the first wire 140 located below the first insulating layer 153 through the metal interconnection structure 270, thereby improving the configuration space and structural reliability of the metal interconnection line. Therefore, the semiconductor device 20 of the present embodiment can still improve the component performance of the metal interconnection line under the premise of space saving, and achieve more optimized operation performance.

[0089] Please refer to Figure 8 , which is a cross-sectional schematic diagram of a semiconductor device 30 in the third embodiment of the present application. The structure of the semiconductor device 30 in this embodiment is substantially the same as that of the semiconductor device 10 in the aforementioned embodiment, and the similarities are not repeated here. The main difference between the semiconductor device 30 in this embodiment and the aforementioned embodiment is that the portion of the second sidewall 370b of the metal interconnect structure 370 that physically contacts the second wire 160 falls on the top surface 160t of the second wire 160 in the vertical direction D2 and just cuts the sidewall 160f of the second wire 160. In this way, the metal interconnect structure 370 can also present a cross-sectional structure with a larger top and a smaller bottom as a whole, which is beneficial to improve the reliability of its components under the premise of simplifying the manufacturing process of the metal interconnect structure 370.

[0090] The semiconductor device 30 of the present embodiment also sets the metal interconnection structure 370 at a position at least partially overlapping the second wire 160 and the first wire 140, and directly electrically connects the second wire 160 located above the first insulating layer 153 and the first wire 140 located below the first insulating layer 153 through the metal interconnection structure 370, thereby improving the configuration space and structural reliability of the metal interconnection line. Therefore, the semiconductor device 30 of the present embodiment can still improve the component performance of the metal interconnection line under the premise of space saving, and achieve more optimized operation performance.

[0091] Please refer to Fig. 9, which is a cross-sectional schematic diagram of a semiconductor device 40 in a fourth embodiment of the present application. The structure of the semiconductor device 40 in this embodiment is substantially the same as that of the semiconductor device 10 in the aforementioned embodiment, and the similarities are not repeated here. The main difference between the semiconductor device 40 in this embodiment and the aforementioned embodiment is that the semiconductor device 40 further includes a capacitor structure 490, which is disposed on the second wire 460 and physically contacts the second wire 460.

[0092] Specifically, if Fig. 9 As shown, the second wire 460 of this embodiment can be arranged in the second dielectric layer 155 and located on the first insulating layer 153, and includes copper, aluminum, tungsten or other suitable low-resistivity conductive materials, but is not limited thereto. A second insulating layer 459 is also arranged on the second wire 460, at least partially covering the top surface 460t of the second wire 460, and the capacitor structure 490 partially penetrates the second insulating layer 459 to electrically connect the second wire 460. Among them, the capacitor structure 490 includes a plurality of bottom electrode layers 491, a capacitor dielectric layer 493, and a top electrode layer 495 arranged in sequence. Among them, each bottom electrode layer 491 has a U-shaped cross-sectional structure, and individually penetrates the second insulating layer 459 to physically contact and electrically connect the second wire 460 located below the second insulating layer 459.

[0093] It should be noted that the metal interconnection structure 470 of the present embodiment is disposed at a position that at least partially overlaps the second wire 460 and a first wire 140 that physically contacts the doped region 105. The metal interconnection structure 470 contacts the top surface 460t and the side wall 460e of the second wire 460 and the top surface 140t of the first wire 140, and can also directly electrically connect the first wire 140 and the second wire 460 under the premise of saving space. In addition, the metal interconnection structure 470 also has a first side wall 470a and a second side wall 470b in the vertical direction D2, and the portion thereof that physically contacts the top surface 140t and the top surface 460t is located in the horizontal direction D1 and does not exceed the side wall 140e on one side of the first wire 140 and the side wall 460f on the other side of the second wire 460, as shown in FIG. Fig. 9 In one embodiment, the first sidewall 470a and the second sidewall 470b of the metal interconnect structure 470 that physically contact the top surface 140t and the top surface 460t may also be selected to be aligned with the sidewall 140e on one side of the first wire 140 and the sidewall 460f on the other side of the second wire 460, but the invention is not limited thereto. In this way, the metal interconnect structure 470 may also present a cross-sectional structure that is larger at the top and smaller at the bottom, which is beneficial to simplifying its manufacturing process and improving component reliability.

[0094] In another embodiment, the metal interconnect structure 470 can be fabricated after the capacitor structure 490 is formed, and integrated with the fabrication process of the connection structure electrically connecting other components, and has a relatively large length in the vertical direction D2, for example, about 10 to 20 times the length of the first conductive line 140 or the second conductive line 460, but not limited thereto. Fig. 9 As shown, in the subsequent manufacturing process, a connection structure 410 may be additionally provided on the capacitor structure 490, and the capacitor structure 490 may be further electrically connected to different components through the connection structure 410 to form different devices to perform different operations.

[0095] Under this configuration, the semiconductor device 40 of the present embodiment can also directly electrically connect the second wire 460 located above the first insulating layer 153 and the first wire 140 located below the first insulating layer 153 through the metal interconnection structure 470, thereby simultaneously improving the configuration space and structural reliability of the metal interconnection line. In addition, the semiconductor device 40 of the present embodiment can further electrically connect the capacitor structure 490 disposed on the second wire 460 to the doped region 105 of the transistor component through the metal interconnection structure 470, so that the capacitor structure 490 and the transistor component together constitute the minimum memory cell of the memory device to receive voltage information from the bit line (not shown) and the word line (not shown). Moreover, the minimum memory cell can also be further electrically connected to a specific required component through the connection structure 410 disposed on the capacitor structure 490, so that the semiconductor device 40 can be used as a dynamic random access memory device (DRAM) to achieve a more optimized operation performance.

[0096] Please refer to Fig.10 , which is a cross-sectional schematic diagram of a semiconductor device 50 in the fifth embodiment of the present application. The structure of the semiconductor device 50 in this embodiment is substantially the same as that of the semiconductor device 10 in the aforementioned embodiment, and the similarities are not repeated here. The main difference between the semiconductor device 50 in this embodiment and the aforementioned embodiment is that the metal interconnect structure 570 is disposed between the first wire 140 and the second wire 560, and physically contacts the top surface 140t of the first wire 140 and the bottom surface 560b of the second wire 560.

[0097] Specifically, if Fig.10 As shown in FIG. 1 , the metal interconnection structure 570 of the present embodiment is disposed in the first insulating layer 153 and is located below the second conductive line 560. Furthermore, the metal interconnection structure 570 is preferably formed integrally with the second conductive line 560, and together comprises a barrier layer 561 and a metal layer 563 stacked in sequence, as shown in FIG. Fig.10As shown, but not limited thereto. The barrier layer 561 includes, for example, conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, and the metal layer 563 includes, for example, copper, aluminum, tungsten or other suitable low-resistivity conductive materials. In this way, the first conductive wire 140 and the second conductive wire 560 can also be directly electrically connected through the metal interconnect structure 570.

[0098] Under this setting, the semiconductor device 50 of this embodiment also sets the metal interconnection structure 570 at a position that at least partially overlaps the second wire 560 and the first wire 140, and directly electrically connects the second wire 560 located above the first insulating layer 153 and the first wire 140 located below the first insulating layer 153 through the metal interconnection structure 570, thereby improving the configuration space and structural reliability of the metal interconnection line. Therefore, the semiconductor device 50 of this embodiment can still improve the component performance of the metal interconnection line under the premise of space saving, and achieve more optimized operation performance.

[0099] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: A first conductive line disposed in the first dielectric layer; a first insulating layer, disposed on the first dielectric layer and covering the first conductive line; A second conductive line is disposed in the second dielectric layer and partially overlaps the first conductive line in a vertical direction; as well as The metal interconnection structure is disposed in the second dielectric layer and the first insulating layer and physically contacts the top surface of the second conductive line, the side wall of one side of the second conductive line, and the top surface of the first conductive line.

2. The semiconductor device according to claim 1, wherein: The portion where the first sidewall of the metal interconnect structure physically contacts the top surface of the first conductive line does not exceed the sidewall on one side of the first conductive line.

3. The semiconductor device according to claim 2, characterized in that The first sidewall of the metal interconnect structure is aligned with the sidewall of the first conductive line.

4. The semiconductor device according to claim 2, characterized in that The portion where the second sidewall of the metal interconnect structure physically contacts the top surface of the second conductive line does not exceed the sidewall on the other side of the second conductive line.

5. The semiconductor device according to claim 4, characterized in that The second sidewall of the metal interconnection structure is aligned with the sidewall on the other side of the second conductive line.

6. The semiconductor device according to claim 1, wherein: The metal interconnection structure includes a cross-sectional structure that is larger at the top and smaller at the bottom.

7. The semiconductor device according to claim 1, wherein: Also includes: A gate structure, disposed below the first conductive line; A plug is disposed on the gate structure and physically contacts the gate structure and the first conductive line.

8. The semiconductor device according to claim 1, wherein: Also includes: A gate structure, disposed below the first conductive line; as well as The plug is disposed below the first conductive line and physically contacts the doped region on one side of the gate structure and the first conductive line.

9. The semiconductor device according to claim 8, characterized in that Also includes: The capacitor structure is disposed on the second wire and physically contacts the second wire.

10. The semiconductor device according to claim 9, characterized in that Also includes: A second insulating layer is arranged on the second conductive line, wherein the capacitor structure further comprises a plurality of bottom electrode layers, capacitor dielectric layers and top electrode layers arranged in sequence, and the bottom electrode layer penetrates the second insulating layer and physically contacts the top surface of the second conductive line.

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