Array substrate, display panel and display device

Abstract

The utility model discloses an array substrate, a display panel and a display device. The array substrate comprises a substrate; the metal layer is arranged on the substrate and comprises a data line, a scanning line and a grid electrode, and the data line is disconnected in an area crossed with the scanning line; the first insulating layer covers the data line, the scanning line and the grid electrode; the active layer is arranged above the first insulating layer; the first transparent conducting layer is arranged above the first insulating layer and comprises a pixel electrode, a source electrode and a drain electrode; the second insulating layer covers the pixel electrode, the source electrode and the drain electrode, the first insulating layer and the second insulating layer are provided with contact holes in two end areas corresponding to each section of data line, and at least the data line is exposed out of the contact holes; the second transparent conducting layer is arranged above the second insulating layer and comprises a common electrode; the first transparent conductive layer and / or the second transparent conductive layer comprises bridging electrodes for conductively connecting the disconnected data lines. The array substrate is simple in structure, and only five mask processes are needed.

Description

Technical Field

[0001] The utility model relates to the technical field of displays, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] With the development of display technology, thin and light display panels are favored by consumers, especially thin and light liquid crystal display (LCD) panels.

[0003] An existing display device includes a thin film transistor array substrate (abbreviated as array substrate, Thin Film Transistor Array Substrate, TFT Array Substrate), a color filter substrate (Color Filter Substrate, CF Substrate) and liquid crystal molecules filled between the thin film transistor array substrate and the color filter substrate. When the above display device is working, a driving voltage is applied to the pixel electrode of the thin film transistor array substrate and the common electrode of the color filter substrate respectively, or a driving voltage is applied to the common electrode and the pixel electrode of the thin film transistor array substrate respectively, to control the rotation direction of the liquid crystal molecules between the two substrates to refract the backlight provided by the backlight module of the display device, thereby displaying a picture.

[0004] The structure and manufacturing sequence of each part of the existing array substrate are generally: base substrate → metal layer (including gate and scan line) → gate insulation layer → active layer → second metal layer (including data line, source, drain) → first transparent conductive layer (including pixel electrode) → flat layer → second transparent conductive layer (including common electrode), wherein the metal layer, active layer, second metal layer, first transparent conductive layer, flat layer and second transparent conductive layer each require a mask process, and a total of six mask processes are required. Although compared with the more conventional seven-mask process, one photomask can be saved, which can save costs, the six-mask process is still relatively complicated, the number of mask processes is large, and the manufacturing cost is high. Utility Model Content

[0005] In order to overcome the shortcomings and deficiencies in the prior art, the purpose of the present invention is to provide an array substrate, a display panel, and a display device to solve the problem that the array substrate in the prior art has a complex structure, resulting in a large number of mask processes and high production costs.

[0006] The purpose of the utility model is achieved through the following technical solutions:

[0007] The utility model provides an array substrate, comprising a base, a metal layer, a first insulating layer, a semiconductor layer, a first transparent conductive layer, a second insulating layer and a second transparent conductive layer.

[0008] A metal layer is disposed above the substrate, the metal layer comprising a data line and a scanning line and a gate which are conductively connected to each other, the gate and the scanning line are insulated from the data line, and the data line is disconnected in a region where it intersects with the scanning line;

[0009] A first insulating layer is disposed above the metal layer, and the first insulating layer covers the data line, the scan line and the gate;

[0010] A semiconductor layer is disposed above the first insulating layer, and the semiconductor layer includes an active layer corresponding to the gate;

[0011] A first transparent conductive layer is disposed above the first insulating layer, the first transparent conductive layer covers the active layer, the first transparent conductive layer comprises a pixel electrode, a source electrode and a drain electrode, the source electrode and the drain electrode are connected through the active layer, and the pixel electrode is conductively connected to the drain electrode;

[0012] A second insulating layer is disposed above the first transparent conductive layer, the second insulating layer covers the pixel electrode, the source electrode and the drain electrode, the first insulating layer and the second insulating layer are provided with contact holes at two end regions corresponding to each segment of the data line, and at least the data line is exposed in the contact hole;

[0013] A second transparent conductive layer is disposed above the second insulating layer, the second transparent conductive layer comprises a common electrode, and the common electrode is a comb-shaped electrode having slits in a region corresponding to the pixel electrode;

[0014] The first transparent conductive layer and / or the second transparent conductive layer further comprises a bridging electrode, which spans over the scanning line and conductively connects two adjacent disconnected sections of the data line, and conductively connects the source electrode to the data line.

[0015] Further, the bridging electrode includes a first bridging electrode, the first transparent conductive layer also includes the first bridging electrode, the first bridging electrode is conductively connected to the source electrode, and the first bridging electrode and the end of the data line are both exposed from the contact hole;

[0016] The second transparent conductive layer also includes a conductive column covering the contact hole, the conductive column corresponds to the contact hole one by one, the end of the first bridging electrode and the end of the data line are conductively connected through the conductive column, and the first bridging electrode spans the scan line and conductively connects two adjacent disconnected data lines.

[0017] Furthermore, projections of the first bridging electrode and the data line on the substrate partially overlap.

[0018] Furthermore, the bridging electrode includes a second bridging electrode, the second transparent conductive layer further includes the second bridging electrode covering the contact hole, each of the second bridging electrodes corresponds to the two contact holes on the upper and lower sides of the scanning line,

[0019] The ends of the source electrode and the data line are exposed from the contact hole, and the ends of the source electrode and the data line are conductively connected via the second bridging electrode, which spans over the scan line and conductively connects two adjacent disconnected sections of the data line.

[0020] Furthermore, projections of the source electrode and the data line on the substrate partially overlap.

[0021] Further, the bridging electrode includes a first bridging electrode and a second bridging electrode, the first transparent conductive layer also includes the first bridging electrode, the first bridging electrode is conductively connected to the source electrode, and the first bridging electrode and the end of the data line are both exposed from the contact hole; the second transparent conductive layer also includes the second bridging electrode covering the contact hole, and each of the second bridging electrodes corresponds to the two contact holes on the upper and lower sides of the scanning line;

[0022] The end of the first bridging electrode and the end of the data line are conductively connected via the second bridging electrode. Both the first bridging electrode and the second bridging electrode cross the scan line and conductively connect two adjacent disconnected sections of the data line.

[0023] Furthermore, a projection of the active layer on the substrate is located within a region of the scan line, and a region corresponding to the scan line and the active layer serves as the gate.

[0024] The present application also provides a display panel, comprising the array substrate as described above.

[0025] Furthermore, the display panel includes a color filter substrate arranged opposite to the array substrate and a liquid crystal layer located between the array substrate and the color filter substrate, an upper polarizer is provided on the color filter substrate, and a lower polarizer is provided on the array substrate, and a light transmission axis of the upper polarizer is perpendicular to the light transmission axis of the lower polarizer.

[0026] The present application also provides a display device, comprising the display panel as described above.

[0027] The beneficial effect of the utility model is that: by arranging the data line, the scan line and the gate in the same metal layer, the data line is disconnected in the area where it intersects with the scan line, and then by arranging a bridge electrode in the first transparent conductive layer and / or the second transparent conductive layer, the two adjacent disconnected data lines are conductively connected; the bridge electrode conductively connects the two adjacent disconnected data lines and at the same time, the source electrode is conductively connected to the data line. The array substrate in the present application has a simple structure and only requires five mask processes, which further reduces the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the planar structure of the array substrate in the first embodiment of the utility model;

[0029] Figure 2 The array substrate in the first embodiment of the utility model is along Figure 1 Schematic diagram of the cross section along the AA direction;

[0030] Figure 3 The array substrate in the first embodiment of the utility model is along Figure 1 Schematic diagram of the cross section along the BB direction;

[0031] Figure 4a-1 to Figure 4f-3 It is a structural schematic diagram of a method for manufacturing an array substrate in Embodiment 1 of the present utility model;

[0032] Figure 5 This is a schematic diagram of the planar structure of the array substrate in the second embodiment of the present utility model;

[0033] Figure 6 The array substrate in the second embodiment of the utility model is along Figure 5 Schematic diagram of the cross section in the CC direction;

[0034] Figure 7 This is a schematic diagram of the planar structure when the first transparent conductive layer is manufactured on the array substrate in the second embodiment of the present utility model;

[0035] Figure 8 It is a schematic diagram of the cross-sectional structure of the display device in the utility model when in a dark state;

[0036] Fig. 9 It is a schematic diagram of the cross-sectional structure of the display device of the utility model in a bright state. DETAILED DESCRIPTION

[0037] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined purpose of the present invention, the specific implementation methods, structures, features and effects of the array substrate, display panel and display device proposed by the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments:

[0038] [Example 1]

[0039] Figure 1 It is a schematic diagram of the planar structure of the array substrate in the first embodiment of the present utility model. Figure 2 The array substrate in the first embodiment of the utility model is along Figure 1 Schematic diagram of the cross section along the AA direction. Figure 3 The array substrate in the first embodiment of the utility model is along Figure 1 Schematic diagram of the cross section along the BB direction.

[0040] like Figures 1 to 3 As shown, an array substrate provided in Embodiment 1 of the present invention includes:

[0041] The substrate 10 may be made of glass, quartz, silicon, acrylic acid or polycarbonate. The substrate 10 may also be a flexible substrate. Suitable materials for the flexible substrate include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or a combination thereof.

[0042] The metal layer 11 is disposed on the substrate 10, and the metal layer 11 includes a data line 111 and a scanning line 112 and a gate that are conductively connected to each other. The gate and the scanning line 112 are insulated from the data line 111. The data line 111 is disconnected in the area where it intersects with the scanning line 112. The spacing between the data line 111 and the scanning line 112 is about 4um to prevent the data line 111 from short-circuiting with the scanning line 112. The metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0043] The first insulating layer 101 is disposed above the metal layer 11, and covers the data line 111, the scan line 112, and the gate. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0044] The semiconductor layer is disposed above the first insulating layer 101, and includes an active layer 12 corresponding to the gate. The material of the semiconductor layer is amorphous silicon (a-Si) and doped amorphous silicon.

[0045] A first transparent conductive layer 13 is provided on the first insulating layer 101, and the first transparent conductive layer 13 covers the active layer 12. The first transparent conductive layer 13 includes a pixel electrode 131, a source electrode 132, and a drain electrode 133. The source electrode 132 and the drain electrode 133 are connected through the active layer 12, and the pixel electrode 131 is conductively connected to the drain electrode 133. The material of the first transparent conductive layer 13 is indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0046] A second insulating layer 102 is disposed above the first transparent conductive layer 13, and the second insulating layer 102 covers the pixel electrode 131, the source electrode 132, and the drain electrode 133. The first insulating layer 101 and the second insulating layer 102 are provided with contact holes 103 at the two end regions corresponding to each segment of the data line 111, and the contact holes 103 penetrate the first insulating layer 101 and the second insulating layer 102, and at least the data line 111 is exposed in the contact holes 103. The second insulating layer 102 can be a flat layer, and the material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0047] The second transparent conductive layer 14 is disposed above the second insulating layer 102, and includes a common electrode 141. The common electrode 141 is a comb-shaped electrode with slits in the area corresponding to the pixel electrode 131, so that the array substrate can be applied to a display panel of a fringe field switching mode (Fringe Field Switching, FFS) or an in-plane switching mode (In-Plane Switching, IPS). The material of the second transparent conductive layer 14 is indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0048] The first transparent conductive layer 13 and / or the second transparent conductive layer 14 further include a bridging electrode, which spans the scanning line 112 and conductively connects two adjacent disconnected data lines 111, and conductively connects the source electrode 132 to the data line 111, that is, the bridging electrode conductively connects the two adjacent disconnected data lines 111, and also conductively connects the source electrode 132 to the data line 111.

[0049] like Figure 1 and Figure 3As shown, in this embodiment, the bridging electrode includes a first bridging electrode 134, and the first transparent conductive layer 13 also includes the first bridging electrode 134, that is, the pixel electrode 131, the source electrode 132, the drain electrode 133 and the first bridging electrode 134 are all arranged in the first transparent conductive layer 13. The first bridging electrode 134 is conductively connected to the source electrode 132, and the ends of the first bridging electrode 134 and the data line 111 are exposed from the contact hole 103. The second transparent conductive layer 14 also includes a conductive column 142 covering the contact hole 103, the conductive column 142 is insulated from the common electrode 141, and the conductive column 142 corresponds to the contact hole 103 one by one, that is, a conductive column 142 is arranged in each contact hole 103. The end of the first bridging electrode 134 and the end of the data line 111 are conductively connected through the conductive column 142, the first bridging electrode 134 crosses the scanning line 112 and conductively connects the two adjacent data lines 111 that are disconnected, and also conductively connects the source electrode 132 to the data line 111.

[0050] Furthermore, the projections of the first bridging electrode 134 and the data line 111 on the substrate 10 overlap, thereby facilitating the opening of the contact hole 103 and reducing the size of the contact hole 103, so that when the conductive column 142 is filled in the contact hole 103, the end of the first bridging electrode 134 and the end of the data line 111 can be conductively connected through the conductive column 142.

[0051] In this embodiment, the projection of the active layer 12 on the substrate 10 is located in the area of ​​the scan line 112, and the area corresponding to the scan line 112 and the active layer 12 is used as a gate, thereby increasing the aperture ratio of the sub-pixel. Of course, a branch electrode can also be made on the side of the scan line 112 to serve as a gate.

[0052] Figure 4a-1 to Figure 4f-3 Schematic diagram of the manufacturing method of the array substrate in the first embodiment of the present utility model. Figure 4a-1 , Figure 4b-1 , Figure 4c , Figure 4d-1 , Figure 4f-1 This is a schematic diagram of the planar structure of the array substrate during manufacture. Figure 4a-2 , Figure 4b-2 , Figure 4d-2 , Figure 4f-2 When making the array substrate Figure 1 Schematic diagram of the cross section along the AA direction. Figure 4b-3 , Figure 4d-3 , Figure 4e , Figure 4f-3 When making the array substrate Figure 1 Schematic diagram of the cross section along the BB direction. Figure 4a-1-4f-3 As shown, the method for manufacturing the array substrate includes:

[0053] like Figure 4a-1 and Figure 4a-2 As shown, a substrate 10 is provided, and a metal layer 11 is formed on the substrate 10. The substrate 10 can be made of materials such as glass, quartz, silicon, acrylic acid or polycarbonate. The substrate 10 can also be a flexible substrate. Suitable materials for the flexible substrate include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or a combination thereof. The metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0054] like Figure 4b-1 , Figure 4b-2 and Figure 4b-3 As shown, the metal layer 11 is etched by a first mask process to form a patterned data line 111 and a scan line 112 and a gate that are conductively connected to each other. The gate and the scan line 112 are insulated from the data line 111. The data line 111 is disconnected in the area where it intersects with the scan line 112. The spacing between the data line 111 and the scan line 112 is about 4um to prevent the data line 111 and the scan line 112 from short-circuiting.

[0055] A first insulating layer 101 is formed on the metal layer 11, and the first insulating layer 101 covers the data line 111, the scan line 112 and the gate. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0056] like Figure 4c As shown, a semiconductor layer is formed on the first insulating layer 101, and the semiconductor layer is etched by a second mask process to form a patterned active layer 12 on the semiconductor layer, and the active layer 12 corresponds to the gate. In this embodiment, the projection of the active layer 12 on the substrate 10 is located in the area of ​​the scan line 112, and the area corresponding to the scan line 112 and the active layer 12 is used as the gate, thereby increasing the aperture ratio of the sub-pixel. Among them, the material of the semiconductor layer is amorphous silicon (a-Si) and doped amorphous silicon.

[0057] like Figure 4d-1 , Figure 4d-2 and Figure 4d-3As shown, a first transparent conductive layer 13 is formed on the first insulating layer 101, and the first transparent conductive layer 13 covers the active layer 12. The first transparent conductive layer 13 is etched by a third mask process, and the first transparent conductive layer 13 forms a patterned pixel electrode 131, a source electrode 132, a drain electrode 133 and a first bridge electrode 134. The source electrode 132 and the drain electrode 133 are connected through the active layer 12, the pixel electrode 131 is conductively connected to the drain electrode 133, and the source electrode 132 is conductively connected to the first bridge electrode 134. Among them, the projection of the first bridge electrode 134 and the data line 111 on the substrate 10 overlap, so as to facilitate the subsequent opening of the contact hole 103 and reduce the size of the contact hole 103, so that when the conductive column 142 is filled in the contact hole 103, it is ensured that the end of the first bridge electrode 134 and the end of the data line 111 can be conductively connected through the conductive column 142. The material of the first transparent conductive layer 13 is indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0058] A second insulating layer 102 is formed on the first transparent conductive layer 13, and the second insulating layer 102 covers the pixel electrode 131, the source electrode 132, the drain electrode 133, and the first bridge electrode 134. The second insulating layer 102 may be a flat layer, and the material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0059] like Figure 4e As shown, the first insulating layer 101 and the second insulating layer 102 are etched simultaneously by a fourth mask process. The first insulating layer 101 and the second insulating layer 102 are provided with contact holes 103 at the two end regions corresponding to each segment of the data line 111. The contact holes 103 penetrate the first insulating layer 101 and the second insulating layer 102. The ends of the first bridging electrode 134 and the data line 111 are exposed from the contact holes 103, so that the ends of the first bridging electrode 134 and the data line 111 are conductively connected through the conductive pillars 142.

[0060] like Figure 4f-1 , Figure 4f-2 and Figure 4f-3As shown, a second transparent conductive layer 14 is formed on the second insulating layer 102, and the second transparent conductive layer 14 is etched by a fifth mask process, so that the second transparent conductive layer 14 forms a patterned common electrode 141 and a conductive column 142 covering the contact hole 103, the conductive column 142 and the common electrode 141 are insulated from each other, and the common electrode 141 is a comb-shaped electrode with slits in the area corresponding to the pixel electrode 131. The conductive column 142 corresponds to the contact hole 103 one by one, that is, a conductive column 142 is provided in each contact hole 103, and the end of the first bridging electrode 134 and the end of the data line 111 are conductively connected through the conductive column 142. The first bridging electrode 134 crosses the scanning line 112 and conductively connects the two adjacent data lines 111 that are disconnected, and also conductively connects the source electrode 132 and the data line 111.

[0061] Therefore, the array substrate in the present application has a simple structure and only requires five mask processes, further reducing the manufacturing cost.

[0062] [Example 2]

[0063] Figure 5 It is a schematic diagram of the planar structure of the array substrate in the second embodiment of the present utility model. Figure 6 The array substrate in the second embodiment of the utility model is along Figure 5 Schematic diagram of the cross section in the CC direction. Figure 5 and Figure 6 As shown, the array substrate provided in the second embodiment of the present invention is different from that in the first embodiment ( Figures 1 to 4f-3 ) are substantially the same, except that, in this embodiment:

[0064] The bridging electrode includes a second bridging electrode 143, and the second transparent conductive layer 14 also includes a second bridging electrode 143 covering the contact hole 103. The second bridging electrode 143 and the common electrode 141 are insulated from each other, that is, the second bridging electrode 143 and the common electrode 141 are both arranged in the second transparent conductive layer 14. Each second bridging electrode 143 corresponds to two contact holes 103 on the upper and lower sides of the scanning line 112. The ends of the source electrode 132 and the data line 111 are both exposed from the contact hole 103, and the ends of the source electrode 132 and the ends of the data line 111 are conductively connected through the second bridging electrode 143. The second bridging electrode 143 crosses the scanning line 112 and conductively connects the two adjacent data lines 111 that are disconnected. That is, in this embodiment, the second bridging electrode 143 not only plays a bridging role, conductively connecting the two adjacent data lines 111 that are disconnected, but also plays a role of a conductive column 142, conductively connecting the source electrode 132 and the data line 111. Therefore, in this embodiment, the first transparent conductive layer 13 does not need to be provided with the first bridging electrode 134 , and the second transparent conductive layer 14 does not need to be provided with the conductive pillar 142 .

[0065] Furthermore, the projections of the source electrode 132 and the data line 111 on the substrate 10 overlap, thereby facilitating the opening of the contact hole 103 and reducing the size of the contact hole 103, so that when the second bridging electrode 143 is filled in the contact hole 103, it is ensured that the end of the source electrode 132 and the end of the data line 111 can be conductively connected through the second bridging electrode 143.

[0066] In another embodiment, the bridging electrode includes a first bridging electrode 134 and a second bridging electrode 143. The first transparent conductive layer 13 also includes the first bridging electrode 134, which is conductively connected to the source electrode 132, and the ends of the first bridging electrode 134 and the data line 111 are exposed from the contact hole 103. The second transparent conductive layer 14 also includes a second bridging electrode 143 covering the contact hole 103, and each second bridging electrode 143 corresponds to two contact holes 103 on the upper and lower sides of the scanning line 112. The ends of the first bridging electrode 134 and the ends of the data line 111 are conductively connected through the second bridging electrode 143, and the first bridging electrode 134 and the second bridging electrode 143 both cross the scanning line 112 and conductively connect the two adjacent data lines 111 that are disconnected. At the same time, the first bridging electrode 134 and the second bridging electrode 143 act in parallel, thereby reducing the resistance of the bridging electrode to increase the conductivity of the entire data line 111.

[0067] refer to Figure 4a-1-4f-3 As shown, the method for manufacturing the array substrate includes:

[0068] refer to Figure 4a-1 and Figure 4a-2 As shown, a substrate 10 is provided, and a metal layer 11 is formed on the substrate 10. The substrate 10 can be made of materials such as glass, quartz, silicon, acrylic acid or polycarbonate. The substrate 10 can also be a flexible substrate. Suitable materials for the flexible substrate include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or a combination thereof. The metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0069] refer to Figure 4b-1 , Figure 4b-2 and Figure 4b-3As shown, the metal layer 11 is etched by a first mask process to form a patterned data line 111 and a scan line 112 and a gate that are conductively connected to each other. The gate and the scan line 112 are insulated from the data line 111. The data line 111 is disconnected in the area where it intersects with the scan line 112. The spacing between the data line 111 and the scan line 112 is about 4um to prevent the data line 111 and the scan line 112 from short-circuiting.

[0070] A first insulating layer 101 is formed on the metal layer 11, and the first insulating layer 101 covers the data line 111, the scan line 112 and the gate. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0071] refer to Figure 4c As shown, a semiconductor layer is formed on the first insulating layer 101, and the semiconductor layer is etched by a second mask process to form a patterned active layer 12 on the semiconductor layer, and the active layer 12 corresponds to the gate. In this embodiment, the projection of the active layer 12 on the substrate 10 is located in the area of ​​the scan line 112, and the area corresponding to the scan line 112 and the active layer 12 is used as the gate, so as to increase the aperture ratio of the sub-pixel. Among them, the material of the semiconductor layer is amorphous silicon (a-Si) and doped amorphous silicon.

[0072] like Figure 7 As shown, a first transparent conductive layer 13 is formed on the first insulating layer 101, and the first transparent conductive layer 13 covers the active layer 12. The first transparent conductive layer 13 is etched by a third mask process, and the first transparent conductive layer 13 forms a patterned pixel electrode 131, a source electrode 132 and a drain electrode 133, the source electrode 132 and the drain electrode 133 are connected through the active layer 12, and the pixel electrode 131 is conductively connected to the drain electrode 133. Among them, the projections of the source electrode 132 and the data line 111 on the substrate 10 overlap, so as to facilitate the subsequent opening of the contact hole 103 and reduce the size of the contact hole 103, so that when the second bridge electrode 143 is filled in the contact hole 103, it is ensured that the end of the source electrode 132 and the end of the data line 111 can be conductively connected through the second bridge electrode 143. The material of the first transparent conductive layer 13 is indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0073] A second insulating layer 102 is formed on the first transparent conductive layer 13, and the second insulating layer 102 covers the pixel electrode 131, the source electrode 132, and the drain electrode 133. The second insulating layer 102 may be a flat layer, and the material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0074] refer to Figure 4eAs shown, the first insulating layer 101 and the second insulating layer 102 are etched simultaneously by a fourth mask process, and the first insulating layer 101 and the second insulating layer 102 are provided with contact holes 103 at the two end regions corresponding to each segment of the data line 111, and the contact holes 103 penetrate the first insulating layer 101 and the second insulating layer 102, and the end portions of the source electrode 132 and the data line 111 are exposed from the contact holes 103, so that the end portions of the source electrode 132 and the end portions of the data line 111 are conductively connected through the second bridging electrode 143.

[0075] refer to Figure 4f-1 , Figure 4f-2 and Figure 4f-3 As shown, a second transparent conductive layer 14 is formed on the second insulating layer 102, and the second transparent conductive layer 14 is etched by a fifth mask process. The second transparent conductive layer 14 forms a patterned common electrode 141 and a second bridging electrode 143 covering the contact hole 103. The second bridging electrode 143 and the common electrode 141 are insulated from each other, and the common electrode 141 is a comb-shaped electrode with slits in the area corresponding to the pixel electrode 131. Each second bridging electrode 143 corresponds to two contact holes 103 on the upper and lower sides of the scanning line 112, that is, the two contact holes 103 on the upper and lower sides of the scanning line 112 share one second bridging electrode 143. The end of the source electrode 132 and the end of the data line 111 are conductively connected through the second bridging electrode 143. The second bridging electrode 143 crosses the scanning line 112 and conductively connects the two adjacent data lines 111 that are disconnected, and also conductively connects the source electrode 132 and the data line 111.

[0076] Therefore, the array substrate in the present application has a simple structure and only requires five mask processes, further reducing the manufacturing cost.

[0077] It should be understood by those skilled in the art that the rest of the structure and working principle of this embodiment are the same as those of the first embodiment and will not be described in detail here.

[0078] Figure 8 It is a schematic diagram of the cross-sectional structure of the display device in the utility model when it is in a dark state. Fig. 9 Schematic diagram of the cross-sectional structure of the display device in the present utility model when in bright state. Figure 8 and Fig. 9As shown, the present application also provides a display panel, including the array substrate as described above. The display panel includes a color filter substrate 20 arranged opposite to the array substrate and a liquid crystal layer 30 located between the array substrate and the color filter substrate 20, an upper polarizer 41 is provided on the color filter substrate 20, and a lower polarizer 42 is provided on the array substrate, and the light transmission axis of the upper polarizer 41 and the light transmission axis of the lower polarizer 42 are perpendicular to each other. Among them, the liquid crystal molecules in the liquid crystal layer 30 use positive liquid crystal molecules (liquid crystal molecules with positive dielectric anisotropy). In the initial state, the positive liquid crystal molecules are in a lying posture, and the alignment direction of the positive liquid crystal molecules close to the color filter substrate 20 is parallel to the alignment direction of the positive liquid crystal molecules close to the array substrate. It can be understood that the array substrate and the color filter substrate 20 are also provided with an alignment layer in a layer facing the liquid crystal layer 30, so as to align the positive liquid crystal molecules in the liquid crystal layer 30.

[0079] In this embodiment, a black matrix 21 and a color resist layer 22 are provided on the color filter substrate 20. The black matrix 21 corresponds to the scan line 131, the data line 111, the thin film transistor and the peripheral non-display area, and the black matrix 21 separates a plurality of color resist layers 22. The color resist layer 22 includes color resist materials of red (R), green (G) and blue (B), and correspondingly forms sub-pixels of red (R), green (G) and blue (B).

[0080] like Figure 8 and Fig. 9 As shown, the utility model further provides a display device, comprising the display panel as described above and a backlight module 50. The backlight module 50 is located below the display panel and is used to provide a backlight source for the display panel.

[0081] The backlight module 50 includes a backlight source 51 and an anti-peep layer 52, and the anti-peep layer 52 is used to narrow the range of the light emission angle. A brightness enhancement film 53 is also provided between the backlight source 51 and the anti-peep layer 52, and the brightness enhancement film 53 increases the brightness of the backlight module 50. Among them, the anti-peep layer 52 is equivalent to a miniature shutter structure, which can block light with a larger incident angle and allow light with a smaller incident angle to pass through, so that the angle range of light passing through the anti-peep layer 52 becomes smaller. The anti-peep layer 52 includes a plurality of parallel light-blocking walls and a light-transmitting hole located between two adjacent light-blocking walls, and light-absorbing materials are provided on both sides of the light-blocking walls. Of course, the backlight source 51 can also be a light-collecting backlight source, so there is no need to set the anti-peep layer 52, but the light-collecting backlight source is more expensive than the conventional backlight source.

[0082] The backlight module 50 can be an edge-type backlight module or a direct-type backlight module. Preferably, the backlight module 50 adopts a collimated backlight (CBL) mode, which can collect light and ensure the display effect.

[0083] In this document, the directional words such as up, down, left, right, front, and back are defined by the positions of the structures in the drawings and the positions of the structures relative to each other, just for the sake of clarity and convenience in expressing the technical solution. It should be understood that the use of the directional words should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second" used in this document are only used to distinguish names and are not used to limit quantity and order.

[0084] The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with the profession can make some changes or modifications to the technical contents disclosed above without departing from the scope of the technical solution of the present invention, which are equivalent embodiments of equivalent changes. However, any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. An array substrate, It is characterized in that It comprises a substrate (10), a metal layer (11), a first insulating layer (101), a semiconductor layer, a first transparent conductive layer (13), a second insulating layer (102) and a second transparent conductive layer (14), The metal layer (11) is arranged above the substrate (10), the metal layer (11) comprises a data line (111) and a scanning line (112) and a gate which are conductively connected to each other, the gate and the scanning line (112) are insulated from each other from the data line (111), and the data line (111) is disconnected in a region where it intersects with the scanning line (112); The first insulating layer (101) is disposed above the metal layer (11), and the first insulating layer (101) covers the data line (111), the scanning line (112) and the gate; The semiconductor layer is disposed above the first insulating layer (101), and the semiconductor layer comprises an active layer (12) corresponding to the gate; The first transparent conductive layer (13) is arranged above the first insulating layer (101), the first transparent conductive layer (13) covers the active layer (12), the first transparent conductive layer (13) comprises a pixel electrode (131), a source electrode (132) and a drain electrode (133), the source electrode (132) and the drain electrode (133) are connected via the active layer (12), and the pixel electrode (131) is conductively connected to the drain electrode (133); The second insulating layer (102) is arranged above the first transparent conductive layer (13), the second insulating layer (102) covers the pixel electrode (131), the source electrode (132) and the drain electrode (133), the first insulating layer (101) and the second insulating layer (102) are provided with contact holes (103) at the two end regions corresponding to each segment of the data line (111), and at least the data line (111) is exposed in the contact hole (103); The second transparent conductive layer (14) is arranged above the second insulating layer (102), the second transparent conductive layer (14) comprises a common electrode (141), and the common electrode (141) is a comb-shaped electrode with slits in a region corresponding to the pixel electrode (131); The first transparent conductive layer (13) and / or the second transparent conductive layer (14) further comprises a bridging electrode, which spans the scanning line (112) and conductively connects two adjacent disconnected sections of the data line (111), while conductively connecting the source electrode (132) to the data line (111).

2. The array substrate according to claim 1, It is characterized in that The bridging electrode comprises a first bridging electrode (134), the first transparent conductive layer (13) further comprises the first bridging electrode (134), the first bridging electrode (134) is conductively connected to the source electrode (132), and the ends of the first bridging electrode (134) and the data line (111) are both exposed from the contact hole (103); The second transparent conductive layer (14) further comprises a conductive column (142) covering the contact hole (103); the conductive column (142) corresponds to the contact hole (103) one by one; the end of the first bridging electrode (134) and the end of the data line (111) are conductively connected via the conductive column (142); the first bridging electrode (134) crosses the scanning line (112) and conductively connects two adjacent disconnected sections of the data line (111).

3. The array substrate according to claim 2, It is characterized in that Projections of the first bridging electrode (134) and the data line (111) on the substrate (10) partially overlap.

4. The array substrate according to claim 1, It is characterized in that The bridging electrode comprises a second bridging electrode (143), the second transparent conductive layer (14) further comprises the second bridging electrode (143) covering the contact hole (103), each of the second bridging electrodes (143) corresponding to two of the contact holes (103) on the upper and lower sides of the scanning line (112), The ends of the source electrode (132) and the data line (111) are both exposed from the contact hole (103); the ends of the source electrode (132) and the ends of the data line (111) are conductively connected via the second bridging electrode (143); the second bridging electrode (143) crosses the scanning line (112) and conductively connects two adjacent disconnected sections of the data line (111).

5. The array substrate according to claim 4, It is characterized in that Projections of the source electrode (132) and the data line (111) on the substrate (10) partially overlap.

6. The array substrate according to claim 1, It is characterized in that The bridging electrode comprises a first bridging electrode (134) and a second bridging electrode (143); the first transparent conductive layer (13) further comprises the first bridging electrode (134); the first bridging electrode (134) is conductively connected to the source electrode (132); ends of the first bridging electrode (134) and the data line (111) are both exposed from the contact hole (103); the second transparent conductive layer (14) further comprises the second bridging electrode (143) covering the contact hole (103); each of the second bridging electrodes (143) corresponds to two contact holes (103) on the upper and lower sides of the scanning line (112); The end of the first bridging electrode (134) and the end of the data line (111) are conductively connected via the second bridging electrode (143); the first bridging electrode (134) and the second bridging electrode (143) both cross the scanning line (112) and conductively connect two adjacent disconnected sections of the data line (111).

7. The array substrate according to any one of claims 1 to 6, It is characterized in that The projection of the active layer (12) on the substrate (10) is located in the area of ​​the scanning line (112), and the area corresponding to the scanning line (112) and the active layer (12) serves as the gate.

8. A display panel, It is characterized in that It comprises the array substrate as described in any one of claims 1 to 7.

9. The display panel according to claim 8, It is characterized in that The display panel comprises a color film substrate (20) arranged opposite to the array substrate and a liquid crystal layer (30) located between the array substrate and the color film substrate (20); an upper polarizer (41) is arranged on the color film substrate (20); a lower polarizer (42) is arranged on the array substrate; a light transmission axis of the upper polarizer (41) and a light transmission axis of the lower polarizer (42) are perpendicular to each other.

10. A display device, It is characterized in that Comprising a display panel as described in any one of claims 8 to 9.

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