Array substrate and display panel

Abstract

The utility model discloses an array substrate and a display panel, the array substrate comprises a scanning line, a main pixel electrode, a secondary pixel electrode, a data line, a switching circuit and a voltage dividing line, the data line is located between the main pixel electrode and the secondary pixel electrode, and the length direction of the data line is perpendicular to the length direction of the scanning line; the switching circuit is located between the main pixel electrode and the sub-pixel electrode and comprises a first thin film transistor, a second thin film transistor and a third thin film transistor, a source electrode of the first thin film transistor and a source electrode of the second thin film transistor are electrically connected with the data line, a drain electrode of the first thin film transistor is electrically connected with the main pixel electrode, and a drain electrode of the third thin film transistor is electrically connected with the sub-pixel electrode. The drain electrode of the second thin film transistor is electrically connected with the sub-pixel electrode, and the drain electrode of the third thin film transistor is electrically connected with the drain electrode of the second thin film transistor; the voltage dividing line is electrically connected with the source electrode of the third thin film transistor and extends in the length direction of the scanning line. The penetration rate of the array substrate can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Multi-domain Vertical Alignment LiquidCrystal Display (MVALCD) has been widely used in large-size display panels due to its advantages of high contrast and wide viewing angle. As the size of display panels evolves towards larger screens, multi-domain pixel design has gained attention in large-size display panels for its excellent viewing angle performance. Among them, the use of the traditional three-gate structure 4-domain array substrate is limited when applied to large-size display panels due to its small viewing angle.

[0003] Compared with the 4-domain array substrate of the three-gate structure, the traditional 1G1D structure 8-domain array substrate has a relatively larger viewing angle. However, since the voltage divider line (Sharebar) of the 8-domain array substrate of the 1G1D structure extends along the long axis direction of the sub-pixel, the voltage divider line overlaps with the electrode of the main pixel and the electrode of the sub-pixel respectively, making the length of the voltage divider line longer, resulting in difficulty for light to penetrate the area of ​​the array substrate where the voltage divider line is provided, resulting in reduced transmittance of the array substrate.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Utility Model Content

[0005] The purpose of the present application is to provide an array substrate and a display panel to improve the transmittance of the array substrate.

[0006] To solve the above problems, the technical solution of this application is as follows:

[0007] In a first aspect, the present application proposes an array substrate, comprising:

[0008] Scan line;

[0009] A main pixel electrode;

[0010] A sub-pixel electrode is arranged along the length direction of the scanning line and is spaced apart from the main pixel electrode;

[0011] A data line, located between the primary pixel electrode and the secondary pixel electrode, wherein a length direction of the data line is perpendicular to a length direction of the scan line;

[0012] a switch circuit, located between the primary pixel electrode and the secondary pixel electrode, the switch circuit comprising a first thin film transistor, a second thin film transistor and a third thin film transistor, a source of the first thin film transistor and a source of the second thin film transistor being electrically connected to the data line, a drain of the first thin film transistor being electrically connected to the primary pixel electrode, a drain of the second thin film transistor being electrically connected to the secondary pixel electrode, and a drain of the third thin film transistor being electrically connected to a drain of the second thin film transistor;

[0013] The voltage dividing line is electrically connected to the source electrode of the third thin film transistor, and the voltage dividing line extends along the length direction of the data line.

[0014] In an embodiment of the present application, the switch circuit is located between the data line and the main pixel electrode, and the voltage dividing line is located between the main pixel electrode and the switch circuit.

[0015] In an embodiment of the present application, the length of the voltage dividing line is greater than the width of the main pixel electrode.

[0016] In an embodiment of the present application, a plurality of the scan lines are arranged at intervals along the length direction of the data lines, and a voltage dividing line overlaps a portion of at least two adjacent scan lines.

[0017] In an embodiment of the present application, the array substrate further includes a gate layer, the gate layer is connected to the scan line, the gate layer partially overlaps with the switch circuit, and the gate layer does not overlap with the voltage divider line.

[0018] In one embodiment of the present application, the gate layer includes:

[0019] a first gate, the first gate being located between the voltage dividing line and the data line, the first gate overlapping with the source and the drain of the first thin film transistor, and the first gate overlapping with the source and the drain of the second thin film transistor;

[0020] The second gate is connected to the first gate and is located between the voltage dividing line and the data line. The second gate overlaps with the source and drain of the third thin film transistor.

[0021] In one embodiment of the present application, the array substrate further includes:

[0022] A main pixel wiring, located between the main pixel electrode and the data line, and connecting the main pixel electrode and the drain of the first thin film transistor;

[0023] a sub-pixel wiring, located between the sub-pixel electrode and the voltage dividing line, and connecting the sub-pixel electrode and the drain of the second thin film transistor; and

[0024] The shielding line overlaps with at least one of the scanning line, the gate layer, and the voltage dividing line.

[0025] In one embodiment of the present application, the length direction of the main pixel electrode is parallel to the length direction of the scan line, the width direction of the main pixel electrode is parallel to the length direction of the data line, the length direction of the sub-pixel electrode is parallel to the scan line, and the width direction of the sub-pixel electrode is parallel to the data line;

[0026] The width of the main pixel electrode is equal to the width of the sub-pixel electrode, the length of the main pixel electrode is smaller than the length of the sub-pixel electrode, and the width of the main pixel electrode is greater than or equal to the length of the voltage dividing line.

[0027] In an embodiment of the present application, the switch circuit is located between the data line and the main pixel electrode, and at least a portion of the voltage divider line overlaps with the main pixel electrode.

[0028] In one embodiment of the present application, the main pixel electrode includes:

[0029] A transverse trunk extending along the length direction of the scanning line;

[0030] A longitudinal trunk portion extending along the length direction of the data line, wherein the longitudinal trunk portion and the transverse trunk portion intersect at the center of the main pixel electrode; and

[0031] a branch portion, the branch portion being connected to at least one of the horizontal main trunk portion and the vertical main trunk portion;

[0032] Wherein, at least a portion of the voltage divider line overlaps with the longitudinal trunk portion.

[0033] In the second aspect, the present application proposes a display panel, which includes an array substrate, the array substrate including: a scan line; a main pixel electrode; a sub-pixel electrode, which is arranged at intervals from the main pixel electrode along the length direction of the scan line; a data line, which is located between the main pixel electrode and the sub-pixel electrode, and the length direction of the data line is perpendicular to the length direction of the scan line; a switching circuit, which is located between the main pixel electrode and the sub-pixel electrode, and the switching circuit includes a first thin film transistor, a second thin film transistor and a third thin film transistor, the source of the first thin film transistor and the source of the second thin film transistor are electrically connected to the data line, the drain of the first thin film transistor is electrically connected to the main pixel electrode, the drain of the second thin film transistor is electrically connected to the sub-pixel electrode, and the source of the third thin film transistor is electrically connected to the drain of the second thin film transistor; a voltage divider line, which is electrically connected to the drain of the third thin film transistor, and the voltage divider line extends along the length direction of the data line.

[0034] In the present application, since in a single sub-pixel of an 8-domain array substrate with a three-gate structure, the voltage divider line extends along the length direction of the data line, and the aspect ratio of the sub-pixel is greater than 1, compared to the solution in which the voltage divider line in the traditional 8-domain array substrate with a three-gate structure extends along the length direction of the scan line, in the present application, the voltage divider line extends along the length direction of the data line, so that the area occupied by the voltage divider line in the array substrate is relatively reduced, thereby improving the transmittance of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic diagram of a first embodiment of an array substrate of the present application;

[0036] Figure 2 yes Figure 1 Schematic diagram of the main pixel electrode and the sub-pixel electrode;

[0037] Figure 3 yes Figure 1 Schematic diagram of the scan line and gate layer;

[0038] Figure 4 yes Figure 1 Schematic diagram of the data line, switch circuit, and voltage divider line;

[0039] Figure 5 is a schematic diagram of a second embodiment of an array substrate of the present application;

[0040] Figure 6 yes Figure 5 Schematic diagram of the main pixel electrode and the sub-pixel electrode;

[0041] Figure 7 yes Figure 5 Schematic diagram of the scan line and gate layer;

[0042] Figure 8 yes Figure 5 Schematic diagram of the data line, switching circuit, and voltage divider line. DETAILED DESCRIPTION

[0043] The meanings of the terms used in this specification and claims correspond to the meanings commonly understood by those of ordinary skill in the art to which this application belongs. The terms used in this specification and claims are only for the purpose of facilitating the description and understanding of this application, and are not intended to limit this application to the narrow interpretation of the specific terms used in the specification and claims.

[0044] Reference Figures 1 to 4 , the present application proposes a display panel, the display panel is an LCD, and the display panel includes an array substrate 100 .

[0045] The present application proposes an array substrate 100, comprising:

[0046] Scan line 10;

[0047] A main pixel electrode 20;

[0048] The sub-pixel electrode 30 is disposed along the length direction X of the scanning line 10 and is spaced apart from the main pixel electrode 20 ;

[0049] The data line 40 is located between the primary pixel electrode 20 and the secondary pixel electrode 30 , and the length direction Y of the data line 40 is perpendicular to the length direction X of the scan line 10 ;

[0050] a switch circuit 50, located between the primary pixel electrode 20 and the secondary pixel electrode 30, the switch circuit 50 comprises a first thin film transistor T1, a second thin film transistor T2 and a third thin film transistor T3, a source S1 of the first thin film transistor T1 and a source S2 of the second thin film transistor T2 are electrically connected to the data line 40, a drain D1 of the first thin film transistor T1 is electrically connected to the primary pixel electrode 20, a drain D2 of the second thin film transistor T2 is electrically connected to the secondary pixel electrode 30, and a drain D3 of the third thin film transistor T3 is electrically connected to the drain D2 of the second thin film transistor T2;

[0051] The voltage dividing line 60 is electrically connected to the source electrode S3 of the third thin film transistor T3 , and the voltage dividing line 60 extends along the length direction Y of the data line 40 .

[0052] In the present application, since in a single sub-pixel of the 8-domain array substrate 100 with a three-gate structure, the voltage divider line 60 extends along the length direction Y of the data line 40, and the aspect ratio of the sub-pixel is greater than 1, compared with the solution in which the voltage divider line 60 in the traditional 8-domain array substrate 100 with a three-gate structure extends along the length direction X of the scan line 10, in the present application, the voltage divider line 60 extends along the length direction Y of the data line 40, so that the occupied area of ​​the voltage divider line 60 in the array substrate 100 is relatively reduced, thereby improving the transmittance of the array substrate 100.

[0053] In the 8-domain array substrate 100 of the tri-gate structure of the present application, the length direction X of the scan line 10 and the length direction Y of the data line 40 are perpendicular to each other, the main pixel electrode 20 and the sub-pixel electrode 30 extend along the length direction X of the scan line 10, the length direction of the main pixel electrode 20 is parallel to the length direction X of the scan line 10, the length direction of the sub-pixel electrode 30 is parallel to the length direction X of the scan line 10, the width direction of the main pixel electrode 20 is parallel to the length direction Y of the data line 40, and the width direction of the sub-pixel electrode 30 is parallel to the length direction Y of the data line 40.

[0054] In one embodiment, the main pixel electrode 20, the switch circuit 50, the data line 40, and the sub-pixel electrode 30 are arranged at intervals along the length direction X of the scan line 10. In another embodiment, the main pixel electrode 20, the data line 40, the switch circuit 50, and the sub-pixel electrode 30 are arranged at intervals along the length direction X of the scan line 10.

[0055] The width of the main pixel electrode 20 is similar to or equal to the width of the sub-pixel electrode 30, and the length of the main pixel electrode 20 is smaller than the length of the sub-pixel electrode 30. In the present application, the area occupied by the main pixel electrode 20 in the array substrate 100 is smaller than the area occupied by the sub-pixel electrode 30 in the array substrate 100.

[0056] The array substrate 100 also includes a substrate, on which the scan line 10, the main pixel electrode 20, the data line 40, the switch circuit 50, and the voltage divider line 60 are arranged. The area of ​​the orthographic projection of the main pixel electrode 20 on the substrate is smaller than the area of ​​the orthographic projection of the sub-pixel electrode 30 on the substrate.

[0057] In the 8-domain array substrate 100 with a three-gate structure, the ratio of the length of the main pixel electrode 20 to the length of the sub-pixel electrode 30 is in the range of 1.1 to 3, and the length of the main pixel electrode 20 to the length of the sub-pixel electrode 30 is one of 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, and 3.

[0058] In a single sub-pixel of an 8-domain array substrate 100 of a conventional three-gate structure, the length direction of the main pixel electrode 20 and the length direction of the sub-pixel electrode 30 both extend along the length direction X of the scan line 10. Since the voltage divider line 60 extends along the length direction X of the scan line 10, a portion of the voltage divider line 60 overlaps with the main pixel electrode 20 and the sub-pixel electrode 30. Therefore, in the conventional three-gate structure of the 8-domain array substrate 100, the length of the voltage divider line 60 is relatively long, the area occupied by the voltage divider line 60 in the array substrate 100 is relatively large, and the transmittance of the array substrate 100 is relatively low.

[0059] In a single sub-pixel of the array substrate 100 of the present application, since the voltage dividing line 60 extends along the length direction Y of the data line 40, the voltage dividing line 60 only overlaps with the main pixel electrode 20; or, the voltage dividing line 60 of the present application only overlaps with the sub-pixel electrode 30; or, the voltage dividing line 60 does not overlap with the main pixel electrode 20 or the sub-pixel electrode 30. Compared with the traditional array substrate 100, the length of the voltage dividing line 60 of the present application is shortened by at least one time, the area occupied by the voltage dividing line 60 in the array substrate 100 is relatively small, and the transmittance of the array substrate 100 is improved.

[0060] In the present application, the data line 40, the voltage divider line 60, the source S1 and the drain D1 of the first thin film transistor T1, the source S2 and the drain D2 of the second thin film transistor T2, and the source S3 and the drain D3 of the third thin film transistor T3 share the same metal layer, and the first thin film transistor T1 and the second thin film transistor T2 share the same source.

[0061] Reference Figures 1 to 4 In one embodiment of the present application, the switch circuit 50 is located between the data line 40 and the main pixel electrode 20 , and the voltage divider line 60 is located between the main pixel electrode 20 and the switch circuit 50 .

[0062] The main pixel electrode 20 , the voltage dividing line 60 , the switch circuit 50 , and the sub-pixel electrode 30 are arranged at intervals along the length direction X of the scan line 10 .

[0063] The array substrate 100 also includes a main pixel line 81, a sub-pixel line 82 and a shielding line 83, wherein the main pixel line 81 is located between the main pixel electrode 20 and the data line 40, the main pixel line 81 connects the main pixel electrode 20 and the drain D1 of the first thin film transistor T1, and a portion of the main pixel line 81 overlaps with the voltage divider line 60.

[0064] The sub-pixel wiring 82 is located between the sub-pixel electrode 30 and the voltage dividing line 60 . The sub-pixel wiring 82 connects the sub-pixel electrode 30 and the drain electrode D2 of the second thin film transistor T2 . A portion of the sub-pixel wiring 82 overlaps the data line 40 .

[0065] The shielding wiring 83 partially overlaps with the scanning line 10 and the gate layer 70 , so as to reduce the parasitic capacitance between the sub-pixel and the scanning line 10 and the gate layer 70 .

[0066] The main pixel electrode 20, the sub-pixel electrode 30, the main pixel wiring 81, the sub-pixel wiring 82, and the shielding wiring 83 share the same metal layer. The main pixel electrode 20, the sub-pixel electrode 30, the main pixel wiring 81, the sub-pixel wiring 82, and the shielding wiring 83 are made of indium tin oxide.

[0067] In one embodiment, the length of the voltage divider line 60 is less than the width of the main pixel electrode 20, and the voltage dividing performance of the voltage divider line 60 is relatively weak; in another embodiment, the length of the voltage divider line 60 is greater than or equal to the width of the main pixel electrode 20, and the voltage dividing performance of the voltage divider line 60 is relatively strong.

[0068] Reference Figures 1 to 4 In one embodiment of the present application, the length of the voltage dividing line 60 is greater than the width of the main pixel electrode 20 .

[0069] When the length of the voltage dividing line 60 is greater than the width of the main pixel electrode 20 , the voltage dividing performance of the voltage dividing line 60 is improved, thereby improving the viewing angle of the display panel.

[0070] In one embodiment, the length of the voltage dividing line 60 is greater than the width of the main pixel electrode 20 , and the length of the voltage dividing line 60 is less than the interval between two adjacent scanning lines 10 .

[0071] In another embodiment, the length of the voltage dividing line 60 is greater than the width of the main pixel electrode 20 , and the length of the voltage dividing line 60 is equal to the interval between two adjacent scan lines 10 , and the voltage dividing line 60 partially overlaps with the two adjacent scan lines 10 .

[0072] In another embodiment, the length of the voltage dividing line 60 is greater than the width of the main pixel electrode 20, and the length of the voltage dividing line 60 is greater than the spacing between two adjacent scanning lines 10. In this embodiment, a portion of the voltage dividing line 60 overlaps with a plurality of scanning lines 10. Multiple sub-pixels share one voltage dividing line 60, and the length of the voltage dividing line 60 is longer, thereby improving the voltage dividing performance.

[0073] Reference Figures 1 to 4 In one embodiment of the present application, a plurality of the scan lines 10 are arranged at intervals along the length direction Y of the data line 40 , and a voltage divider line 60 overlaps a portion of at least two adjacent scan lines 10 .

[0074] The length of the voltage dividing line 60 is greater than the width of the main pixel electrode 20, and the length of the voltage dividing line 60 is greater than the spacing between two adjacent scanning lines 10. In this embodiment, a portion of the voltage dividing line 60 overlaps with a plurality of scanning lines 10. Multiple sub-pixels share one voltage dividing line 60, and the length of the voltage dividing line 60 is longer, thereby improving the voltage dividing performance.

[0075] Reference Figures 1 to 4 In one embodiment of the present application, the array substrate 100 further includes a gate layer 70 , the gate layer 70 is connected to the scan line 10 , the gate layer 70 partially overlaps with the switch circuit 50 , and the gate layer 70 does not overlap with the voltage divider line 60 .

[0076] The gate layer 70 and the scan line 10 share the same metal layer, so the gate layer 70 and the scan line 10 are electrically connected, a first semiconductor layer and a first gate insulating layer are provided between the gate layer 70 and the source S1 and the drain D1 of the first thin film transistor T1, a second semiconductor layer and a second gate insulating layer are provided between the gate layer 70 and the source S2 and the drain D2 of the second thin film transistor T2, and a third semiconductor layer and a third gate insulating layer are provided between the gate layer 70 and the source S3 and the drain D3 of the third thin film transistor T3.

[0077] When the scan line 10 is powered on, the gate layer 70 controls the channels of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer to open, thereby connecting the source S1 and the drain D1 of the first thin film transistor T1, while respectively connecting the source S2 and the drain D2 of the second thin film transistor T2, and connecting the source S3 and the drain D3 of the third thin film transistor T3, thereby realizing power supply to the main pixel electrode 20 and the sub-pixel electrode 30.

[0078] The gate layer 70 does not overlap with the voltage dividing line 60 , so as to avoid excessive reflectivity of the overlapping portion to light when the gate layer 70 overlaps with the voltage dividing line 60 , thereby improving the transmittance of the array substrate 100 .

[0079] Reference Figures 1 to 4 In one embodiment of the present application, the gate layer 70 includes:

[0080] a first gate 71, the first gate 71 being located between the voltage dividing line 60 and the data line 40, the first gate 71 overlapping with the source S1 and the drain D1 of the first thin film transistor T1, and the first gate 71 overlapping with the source S2 and the drain D2 of the second thin film transistor T2;

[0081] The second gate 72 is connected to the first gate 71 and is located between the voltage dividing line 60 and the data line 40 . The second gate 72 overlaps with the source S3 and the drain D3 of the third thin film transistor T3 .

[0082] The first gate 71 , the second gate 72 and the scan line 10 share the same metal layer, and the first gate 71 , the second gate 72 and the scan line 10 are integrally formed.

[0083] The first gate 71 is connected to the scan line 10. Since the first thin film transistor T1 and the second thin film transistor T2 share the same source, the first gate 71 overlaps with the source S1 and the drain D1 of the first thin film transistor T1, and the first gate 71 overlaps with the source S2 and the drain D2 of the second thin film transistor T2. When the scan line 10 is powered on, the first gate 71 controls the channels of the first semiconductor layer and the second semiconductor layer to open, thereby connecting the source S1 and the drain D1 of the first thin film transistor T1, and connecting the source S2 and the drain D2 of the second thin film transistor T2.

[0084] The second gate 72 is connected to the first gate 71 and overlaps with the source S3 and the drain D3 of the third thin film transistor T3. When the scan line 10 is powered on, the channel from the second gate 72 to the third semiconductor layer is opened, thereby connecting the source S3 and the drain D3 of the third thin film transistor T3.

[0085] The first gate 71 and the second gate 72 are located between the voltage divider line 60 and the data line 40. The first gate 71 and the second gate 72 do not overlap with the voltage divider line 60 and the data line 40, thereby preventing excessive reflectivity due to the overlap of the gate layer 70 and the voltage divider line 60 and the data line 40, thereby improving the transmittance of the array substrate 100.

[0086] In one embodiment of the present application, the array substrate further includes:

[0087] A main pixel wiring 81 is located between the main pixel electrode 20 and the data line 40 and connects the main pixel electrode 20 and the drain electrode D1 of the first thin film transistor T1;

[0088] A sub-pixel wiring 82 is located between the sub-pixel electrode 30 and the voltage dividing line 60 and connects the sub-pixel electrode 30 and the drain electrode D2 of the second thin film transistor T2; and

[0089] The shielding line 83 overlaps with at least one of the scan line 10 , the gate layer 70 , and the voltage dividing line 60 .

[0090] The shielding wiring 83 is used to reduce the parasitic capacitance between the sub-pixel and the scanning line 10 , the gate layer 70 , and the voltage dividing line 60 .

[0091] The main pixel electrode 20, the sub-pixel electrode 30, the main pixel wiring 81, the sub-pixel wiring 82, and the shielding wiring 83 share the same metal layer. The main pixel electrode 20, the sub-pixel electrode 30, the main pixel wiring 81, the sub-pixel wiring 82, and the shielding wiring 83 are made of indium tin oxide.

[0092] In one embodiment of the present application, the length direction of the main pixel electrode 20 is parallel to the length direction X of the scan line 10, the width direction of the main pixel electrode 20 is parallel to the length direction Y of the data line 40, the length direction of the sub-pixel electrode 30 is parallel to the scan line 10, and the width direction of the sub-pixel electrode 30 is parallel to the data line 40;

[0093] The width of the main pixel electrode 20 is equal to that of the sub-pixel electrode 30 , the length of the main pixel electrode 20 is smaller than that of the sub-pixel electrode 30 , and the width of the main pixel electrode 20 is smaller than that of the voltage dividing line 60 .

[0094] In an embodiment of the present application, the switch circuit 50 is located between the data line 40 and the main pixel electrode 20 , and at least a portion of the voltage dividing line 60 overlaps with the main pixel electrode 20 .

[0095] See also Figures 5 to 8The main pixel electrode 20, the switch circuit 50, and the data line 40 are arranged at intervals along the length direction X of the scan line 10, wherein the main pixel electrode 20 partially overlaps with the voltage dividing line 60. Since the main stem of the main pixel electrode 20 corresponds to the non-luminous area of ​​the main pixel, when the voltage dividing line 60 overlaps with the main stem of the main pixel electrode 20, the voltage dividing line 60 does not affect the luminescence of the main pixel, and the voltage dividing line 60 is integrated in the non-luminous area of ​​the main pixel electrode 20, which increases the area of ​​the opening area, thereby increasing the aperture ratio of the array substrate 100.

[0096] See also Figures 5 to 8 In one embodiment of the present application, the main pixel electrode 20 includes:

[0097] A transverse trunk portion 21 extending along a length direction X of the scanning line 10;

[0098] A longitudinal trunk portion 22 extends along a length direction Y of the data line 40 , wherein the longitudinal trunk portion 22 intersects with the transverse trunk portion 21 at the center of the main pixel electrode 20 ; and

[0099] A branch portion 23, wherein the branch portion 23 is connected to at least one of the horizontal trunk portion 21 and the vertical trunk portion 22;

[0100] Wherein, at least a portion of the voltage dividing line 60 overlaps with the longitudinal trunk portion 22 .

[0101] The horizontal trunk portion 21 and the vertical trunk portion 22 of the main pixel electrode 20 correspond to the non-luminous region of the main pixel, and the branch portion 23 of the main pixel electrode 20 corresponds to the luminous region of the main pixel.

[0102] Since the vertical trunk portion 22 of the main pixel electrode 20 does not emit light, when the voltage dividing line 60 overlaps the vertical trunk portion 22 , the voltage dividing line 60 does not affect the light emission of the main pixel and improves the aperture ratio of the main pixel opening area.

[0103] The above is a detailed description of the specific implementation of the present application. The above implementation disclosed in the present application is only the preferred implementation of the present application. For ordinary technicians in this field, many modifications and improvements can be made without departing from the concept of the present application. These modifications and improvements all fall within the scope of protection defined by the claims of the present application.

Claims

1. An array substrate, characterized in that: include: Scan line; A main pixel electrode; A sub-pixel electrode is arranged along the length direction of the scanning line and is spaced apart from the main pixel electrode; A data line, located between the primary pixel electrode and the secondary pixel electrode, wherein a length direction of the data line is perpendicular to a length direction of the scan line; a switch circuit, located between the primary pixel electrode and the secondary pixel electrode, the switch circuit comprising a first thin film transistor, a second thin film transistor and a third thin film transistor, a source of the first thin film transistor and a source of the second thin film transistor being electrically connected to the data line, a drain of the first thin film transistor being electrically connected to the primary pixel electrode, a drain of the second thin film transistor being electrically connected to the secondary pixel electrode, and a drain of the third thin film transistor being electrically connected to a drain of the second thin film transistor; The voltage dividing line is electrically connected to the source electrode of the third thin film transistor, and the voltage dividing line extends along the length direction of the data line.

2. The array substrate according to claim 1, characterized in that: The switch circuit is located between the data line and the main pixel electrode, and the voltage dividing line is located between the main pixel electrode and the switch circuit.

3. The array substrate according to claim 2, characterized in that: A plurality of the scanning lines are arranged at intervals along the length direction of the data lines, and a voltage dividing line overlaps a portion of at least two adjacent scanning lines.

4. The array substrate according to claim 2, characterized in that: The array substrate further includes a gate layer, the gate layer is connected to the scan line, the gate layer partially overlaps with the switch circuit, and the gate layer does not overlap with the voltage dividing line.

5. The array substrate according to claim 4, characterized in that: The gate layer comprises: a first gate, the first gate being located between the voltage dividing line and the data line, the first gate overlapping with the source and the drain of the first thin film transistor, and the first gate overlapping with the source and the drain of the second thin film transistor; The second gate is connected to the first gate and is located between the voltage dividing line and the data line. The second gate overlaps with the source and drain of the third thin film transistor.

6. The array substrate according to claim 4, characterized in that: The array substrate further includes: A main pixel wiring, located between the main pixel electrode and the data line, and connecting the main pixel electrode and the drain of the first thin film transistor; a sub-pixel wiring, located between the sub-pixel electrode and the voltage dividing line, and connecting the sub-pixel electrode and the drain of the second thin film transistor; and The shielding line overlaps with at least one of the scanning line, the gate layer, and the voltage dividing line.

7. The array substrate according to claim 1, wherein: The length direction of the main pixel electrode is parallel to the length direction of the scan line, the width direction of the main pixel electrode is parallel to the length direction of the data line, the length direction of the sub-pixel electrode is parallel to the scan line, and the width direction of the sub-pixel electrode is parallel to the data line; The width of the main pixel electrode is equal to the width of the sub-pixel electrode, the length of the main pixel electrode is smaller than the length of the sub-pixel electrode, and the width of the main pixel electrode is smaller than the length of the voltage dividing line.

8. The array substrate according to claim 1, wherein: The switch circuit is located between the data line and the main pixel electrode, and at least a portion of the voltage dividing line overlaps with the main pixel electrode.

9. The array substrate according to claim 8, characterized in that: The main pixel electrode comprises: A transverse trunk extending along the length direction of the scanning line; A longitudinal trunk portion extending along the length direction of the data line, wherein the longitudinal trunk portion and the transverse trunk portion intersect at the center of the main pixel electrode; and a branch portion, the branch portion being connected to at least one of the horizontal main trunk portion and the vertical main trunk portion; Wherein, at least a portion of the voltage divider line overlaps with the longitudinal trunk portion.

10. A display panel, characterized in that: It comprises an array substrate as described in any one of claims 1 to 9.

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