Nand test structure, test assembly and test device
By introducing the corresponding connection between the main control chip and the test bits in the NAND test structure, the problem of long-term analysis of NAND Flash chip characteristics in the prior art is solved, and rapid testing efficiency improvement is achieved.
Patent Information
- Application Number
- CN202420629643.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-28
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2034-03-28
AI Technical Summary
In the analysis of the characteristics of NAND Flash chips, it is necessary to design EMMC chip substrate circuits, board production and sample verification, resulting in a long time and affecting the analysis progress.
Design a NAND test structure including a test base and a main control chip. The test base is equipped with a test bit for installing a NAND chip, and read and write tests are performed through the main control chip. The main control chip and the test points of the test bit are one by one. Connect, reduce signal transmission distance and improve test efficiency.
By adding the main control chip, it is possible to quickly open and read and write tests on the NAND chip, shorten the characteristic analysis time and improve the testing efficiency.
Smart Images
Figure CN222213741U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of storage test technology, and in particular to a Nand test structure, a test component and a test device. Background Art
[0002] With the rapid development of digital transformation of enterprises, data is showing an explosive growth trend. The development of emerging technologies such as big data, cloud computing, and AI has made data sources and structures more complex and diverse. We have conducted comprehensive exploration and innovation on NAND Flash reliability testing. Nand Flash does not lose data after power failure and can be used as external storage. It has large capacity and fast rewrite speed, and is suitable for storing large amounts of data. Therefore, it is widely used in the industry. When using NandFlash, it is necessary to analyze the impact of Nand's physical properties on data, and analyze and test Nand Flash's high and low temperature resistance, data retention capacity, lifespan, read and write speed and other characteristics.
[0003] At present, the designed EMMC chip is mainly used to perform Nand characteristic analysis. It is necessary to design the EMMC chip substrate circuit first, then send out the board for board manufacturing, and then make proofs to verify the results. This method takes a long time and affects the progress of the analysis. Utility Model Content
[0004] The purpose of this application is to provide a Nand test structure, a test component and a test device, which can speed up the test and analysis time of Nand chips.
[0005] The present application discloses a Nand test structure, which includes a test socket and a main control chip connected to each other. A test position is provided in the test socket, and the test position is used to install a Nand chip. A plurality of first test points are provided in the test position, and the first test points are used to connect with pads on the Nand chip in the test position; a plurality of second test points are provided on the main control chip, and a plurality of the second test points are connected with a plurality of the first test points in a one-to-one correspondence, and the main control chip is used to perform read and write tests on the Nand chip in the test position.
[0006] Optionally, the test socket includes a test base plate and a test cover plate, the test position is arranged in the test base plate, one end of the test cover plate is connected to one end of the test base plate by a hinge, and the other end of the test cover plate is snap-connected to the other end of the test base plate, and the test cover plate is used to press and fix the Nand chip in the test position; the main control chip is fixed on a side of the test base plate away from the test cover plate.
[0007] Optionally, the test socket is an integrally formed structure, the test position is an open cavity in the test socket, and the main control chip is fixed on a side of the test socket away from the opening of the test position; a pressure head is provided in the test position, and the pressure head is arranged on the side wall of the test position and connected to the test socket, for pressing and fixing the Nand chip in the test position.
[0008] Optionally, the type of the main control chip includes SM2730, and the type of the Nand chip includes BGA132Nand.
[0009] Optionally, the test socket and the main control chip are fixed by screws.
[0010] The present application also discloses a test component, which includes a substrate and at least two Nand test structures as described above, and all the Nand test structures are mounted on the substrate.
[0011] Optionally, the main control chips in all the Nand test structures are integrated on a printed circuit board, and the printed circuit board is simultaneously connected to the first connection points in all the test positions; the printed circuit board is arranged on the back side of the substrate, and the test sockets in the Nand test structure are all arranged on the front side of the substrate; the second test point of the main control chip and the first test point of the corresponding test position are connected by punching a hole in the substrate.
[0012] Optionally, a charging interface is provided on the substrate, and the charging interface is simultaneously connected to all the main control chips; wherein the charging interface is a type c interface.
[0013] Optionally, the test component includes two Nand test structures, and the two Nand test structures are respectively used to test different types of Nand chips.
[0014] The present application discloses a testing device, which includes a motherboard and the testing components as described above. The motherboard is provided with a plurality of fixing positions, and the testing components are arranged one by one at the fixing positions. The motherboard is provided with a charging terminal, and the charging terminal is simultaneously connected to the main control chips in all the testing components.
[0015] The beneficial effects of the present application are as follows: the current card opening fixtures are all card opening fixtures for the entire EMMC. The fixture itself does not have a control chip, and the EMMC main control is required to complete the test. The Nand test structure in the present application can open the card for the Nand chip by adding a main control chip; moreover, when performing read and write tests on the Nand chip, since the control line length between the Nand core in the test position and the internal circuit of the main control chip is in the shortest state, this can increase the signal transmission speed, while shortening the time for characteristic analysis and improving the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:
[0017] Figure 1 is a schematic diagram of a Nand test structure provided in an embodiment of the present application;
[0018] Figure 2 is a schematic diagram of a test socket provided in an embodiment of the present application;
[0019] Figure 3 is a schematic diagram of another test socket provided in an embodiment of the present application;
[0020] Figure 4 is a three-dimensional schematic diagram of a test assembly provided in an embodiment of the present application;
[0021] Figure 5 is a front schematic diagram of a test assembly provided in an embodiment of the present application;
[0022] Figure 6 It is a schematic diagram of the reverse side of a test assembly provided in an embodiment of the present application;
[0023] Figure 7 is a three-dimensional schematic diagram of another test assembly provided in an embodiment of the present application;
[0024] Figure 8 It is a schematic diagram of a testing device provided in an embodiment of the present application.
[0025] Among them, 10, test device; 11, motherboard; 20, test component; 21, substrate; 22, charging interface; 100, Nand test structure; 110, test socket; 111, test position; 112, test base plate; 113, test cover; 114, pressure head; 115, first test point; 120, main control chip; 121, second test point. DETAILED DESCRIPTION
[0026] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative, but the present application can be implemented in many alternative forms and should not be construed as being limited to only the embodiments described herein.
[0027] In the description of the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating relative importance or implicitly indicating the number of the indicated technical features. In addition, terms such as "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicating orientation or positional relationship are described based on the orientation or relative positional relationship shown in the accompanying drawings, and are only simplified descriptions for the convenience of describing the present application, rather than indicating that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the present application.
[0028] Combination Figure 1 and Figure 2 As shown, an embodiment of the present application provides a Nand test structure 100, the Nand test structure 100 includes a test socket 110 and a main control chip 120, the test socket 110 is provided with a test position 111, the test position 111 is used to install a Nand chip, and a plurality of first test points 115 are provided in the test position 111, the first test points 115 are used to connect with the pads on the Nand chip in the test position 111; a plurality of second test points 121 are provided on the main control chip 120, and a plurality of the second test points 121 are connected to a plurality of the first test points 115 in a one-to-one correspondence, and the main control chip 120 is used to perform read and write tests on the Nand chip in the test position 111.
[0029] It should be noted that the Nand test structure 100 in the embodiment of the present application can perform card opening, aging test, high and low temperature test or other read and write tests on the Nand chip.
[0030] The current card opening fixtures are all for the entire EMMC card opening fixture. The fixture itself does not have a control chip, and the EMMC main control is required to complete the test. The Nand test structure 100 in the embodiment of the present application can open the card for the Nand chip by adding a main control chip 120. Moreover, when performing read and write tests on the Nand chip, since the control line length between the Nand core in the test position 111 and the internal line of the main control chip 120 is in the shortest state, this can increase the signal transmission speed, shorten the time of characteristic analysis, and improve the test efficiency.
[0031] In one embodiment, if Figure 2As shown, the test seat 110 includes a test base plate 112 and a test cover plate 113 that can be opened and closed. The test position 111 is arranged in the test base plate 112, and one end of the test cover plate 113 is connected to one end of the test base plate 112 by a hinge, specifically by a shaft rod plus a torsion spring. The hinge connection enables one end of the test cover plate 113 and one end of the test base plate 112 to open automatically without being affected by external force, so as to facilitate the installation of the Nand chip.
[0032] The other end of the test cover 113 is engaged with the other end of the test base 112. When the test cover 113 is placed on the test base 112, the test cover 113 will press and fix the Nand chip in the test position 111. In addition, a button is provided on the test cover 113. When the test cover 113 needs to be opened to take out the Nand chip in the test position 111, the button only needs to be pressed, and the engagement structure of the test cover 113 and the test base 112 will be separated, and the test cover 113 will open automatically under the action of the torsion spring.
[0033] In this embodiment, the main control chip 120 is fixed to one end of the test base plate 112 away from the test cover plate 113, specifically by drilling holes at the edge of the main control chip 120 and the edge of the main control chip 120 and fixing them with screws.
[0034] In this embodiment, a soft rubber pad is provided on the inner wall and the bottom of the test position 111, and an elastic pressing plate is provided at the bottom of the test cover 113. When the Nand chip is pressed and fixed, the soft rubber pad and the elastic pressing plate can provide a buffering effect to avoid affecting the circuit structure in the Nand chip.
[0035] In another embodiment, Figure 3 As shown, the test socket 110 is an integrally formed structure, and the test position 111 is an open cavity in the test socket 110, that is, the top of the test socket 110 is hollow. When the Nand chip installed in the test position 111 is fixed, the surface of the Nand chip is exposed. Through this design, it is also convenient to replace the Nand chip.
[0036] At the same time, the main control chip 120 is fixed to a side of the test socket 110 away from the opening of the test position 111 by means of screws or welding.
[0037] A pressing head 114 is provided in the test position 111 . The pressing head 114 is disposed on a side wall of the test position 111 and connected to the test socket 110 for pressing and fixing the Nand chip in the test position 111 .
[0038] In the embodiment of the present application, the type of the main control chip 120 is SM2730, and the type of the Nand chip is BGA132 Nand. Of course, in other embodiments, the main control chip 120 and the Nand chip can also be of other types.
[0039] Combination Figure 4 , Figure 5 and Figure 6 As shown, the embodiment of the present application further provides a test assembly 20 , which includes a substrate 21 and the Nand test structure 100 as described above, and all the Nand test structures 100 are mounted on the substrate 21 .
[0040] As an implementation method of an embodiment of the present application, the main control chip 120 in all the Nand test structures 100 is integrated on a printed circuit board, and the printed circuit board is simultaneously connected to the first connection points in all the test positions 111; the printed circuit board is arranged on the back side of the substrate 21, and the test sockets 110 in the Nand test structure 100 are all arranged on the front side of the substrate 21; the second test point 121 of the main control chip 120 and the first test point 115 of the corresponding test position 111 are connected by punching a hole in the substrate 21.
[0041] Through the above design, this embodiment can reduce the number of main control chips 120 and improve the integration of driver chips, which is beneficial to reducing the overall volume of the test component 20.
[0042] like Figure 7 As shown, as another implementation of the embodiment of the present application, each Nand test structure 100 in the test component 20 is independently configured, and the main control chips 120 in different Nand test structures 100 are not integrated.
[0043] In this embodiment, the main control chip 120 and the test socket 110 in all Nand test structures 100 are located on the same side of the substrate 21 , and the main control chip 120 is located between the substrate 21 and the test socket 110 .
[0044] Through the above design, this embodiment can fix a suitable number of Nand test structures 100 on a substrate 21 as needed, and test multiple Nand chips at the same time, so as to improve the test efficiency.
[0045] In the embodiment of the present application, a charging interface 22 is provided on the substrate 21, and the charging interface 22 is connected to the printed circuit board, or is simultaneously connected to all the main control chips 120. Among them, the charging interface 22 is a type C interface. Of course, in other embodiments, the charging interface 22 can also use other types of interfaces.
[0046] In one embodiment, the test assembly 20 includes two Nand test structures 100, and the two Nand test structures 100 are respectively used to test different types of Nand chips. Correspondingly, the test positions 111 in the test socket 110 can be made into different sizes to test Nand chips of different sizes; or the main control chip 120 can be made into different types to test different types of Nand chips or test them under different conditions.
[0047] like Figure 8 As shown, the embodiment of the present application further provides a test device 10, the test device 10 includes a motherboard 11 and the test component 20 as described above, the motherboard 11 is provided with a plurality of fixed positions, the test components 20 are arranged one by one at the fixed positions, the motherboard 11 is provided with a charging terminal, and the charging terminal is simultaneously connected to the main control chip 120 in all the test components 20. The test device 10 can test a large number of Nands at one time to further improve the test efficiency.
[0048] Moreover, since there is a charging terminal on the motherboard 11 and each test component 20 also has a separate charging interface 22, when using one of the test components 20 alone, there is no need to plug the power into the motherboard 11 and use the motherboard 11 for power supply. Instead, the type-c interface is used to power one test component 20 alone, making the test device 10 more flexible to use.
[0049] In addition, the inventive concept of the present application can form a large number of embodiments, but the length of the application document is limited and it is impossible to list them one by one. Therefore, under the premise of no conflict, the embodiments or technical features described above can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effects will be enhanced.
[0050] The above content is a further detailed description of the present application in combination with specific optional implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.
Claims
1. A Nand test structure, characterized in that: It comprises a test socket and a main control chip connected to each other, wherein a test position is provided in the test socket, the test position is used to install a Nand chip, and a plurality of first test points are provided in the test position, the first test points are used to connect with pads on the Nand chip in the test position; The main control chip is provided with a plurality of second test points, and the plurality of second test points are connected with the plurality of first test points in a one-to-one correspondence. The main control chip is used to perform a read and write test on the Nand chip in the test position.
2. The Nand test structure according to claim 1, characterized in that: The test seat comprises a test base plate and a test cover plate, the test position is arranged in the test base plate, one end of the test cover plate is connected to one end of the test base plate by a hinge, the other end of the test cover plate is connected to the other end of the test base plate by snapping, and the test cover plate is used to press and fix the Nand chip in the test position; The main control chip is fixed on an end of the test base plate away from the test cover plate.
3. The Nand test structure according to claim 1, characterized in that: The test seat is an integrally formed structure, the test position is an open cavity in the test seat, and the main control chip is fixed on a side of the test seat away from the opening of the test position; A pressing head is provided in the test position. The pressing head is arranged on the side wall of the test position and connected to the test socket for pressing and fixing the Nand chip in the test position.
4. The Nand test structure according to any one of claims 1 to 3, characterized in that: The type of the main control chip includes SM2730, and the type of the Nand chip includes BGA132Nand.
5. The Nand test structure according to any one of claims 1 to 3, characterized in that: The test socket and the main control chip are fixed by screws.
6. A test component, characterized in that: The method comprises a substrate and at least two Nand test structures according to any one of claims 1 to 5, wherein all the Nand test structures are mounted on the substrate.
7. The test assembly according to claim 6, characterized in that All the main control chips in the Nand test structure are integrated on a printed circuit board, and the printed circuit board is simultaneously connected to the first connection points in all the test positions; The printed circuit board is arranged on the back side of the substrate, and the test sockets in the Nand test structure are all arranged on the front side of the substrate; The second test point of the main control chip and the first test point of the corresponding test position are connected by punching a hole on the substrate.
8. The test assembly according to claim 6, characterized in that The substrate is provided with a charging interface, and the charging interface is simultaneously connected to all the main control chips; Among them, the charging interface is a type c interface.
9. The test assembly according to claim 6, characterized in that The test component includes two Nand test structures, and the two Nand test structures are respectively used to test different types of Nand chips.
10. A testing device, characterized in that: It comprises a motherboard and a test component as described in any one of claims 6-9, wherein the motherboard is provided with a plurality of fixing positions, the test components are arranged one by one at the fixing positions, and the motherboard is provided with a charging terminal, and the charging terminal is simultaneously connected to the main control chips in all the test components.