Multi-channel alignment interface based on FPGA
By designing a fixed base and snap structure on the FPGA interface and combining the dust-proof cover, the problem of loosening and dust accumulation in long-term use is solved, the stability and cleaning are improved, and the reliability of signal transmission is ensured. and long-term health status of interfaces.
Patent Information
- Application Number
- CN202420999959.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-09
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2034-05-09
AI Technical Summary
The alignment interface of existing FPGAs is easily worn and loose during long connections, resulting in unstable signal connections, which may cause data transmission errors and system crashes, and may easily accumulate dust when not in use, affecting the quality of the interface.
A multi-channel alignment interface based on FPGA is designed, and a fixed connection device is fixed with a fixed base and snap-on structure. Combined with a dust-proof cover structure, it ensures that the signal connection line does not loosen or fall when it is not in use, and prevents dust. Enter.
The fixed base and snap structure ensure a stable connection of the signal connection line, reduce distortion and interruption of signal transmission, improve the stability and reliability of the system, and reduce the pollution and accumulation of the interface through the dust cover, maintaining the Good working condition.
Smart Images
Figure CN222214713U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of FPGA interface, in particular to a multi-channel alignment interface based on FPGA. Background Art
[0002] FPGA can connect and communicate with various external devices and interfaces. FPGA has some general pins that can be configured as input or output and exchange digital signals with external devices. These pins can be used to control external devices, receive sensor data, communicate with other digital circuits, etc. FPGA also supports various serial communication interfaces, such as SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit), UART (Universal Asynchronous Receiver / Transmitter) and USB (Universal Serial Bus), etc. These interfaces can be used to exchange data and communicate with external devices. At the same time, FPGA supports various high-speed serial interfaces, such as Gigabit Ethernet, HDMI (High Definition Multimedia Interface), DisplayPort and SATA (Serial ATA), etc., these interfaces can be used for high-speed data transmission and communication with external devices. Through the FPGA interface, various external devices and systems can be connected and communicated, thereby realizing various application requirements. However, the existing FPGA alignment interface may cause wear and looseness of the interface during long-term connection work, thereby affecting the stability of the signal connection and the transmission quality. Once the interface connection is unstable, it may cause data transmission errors, system crashes or performance degradation. In addition, the FPGA alignment interface is prone to dust accumulation when not in use, which affects the quality degradation and unstable connection of the FPGA alignment interface. Therefore, those skilled in the art provide a multi-channel alignment interface based on FPGA to solve the problems raised in the above background technology. Utility Model Content
[0003] The purpose of the utility model is to provide a multi-channel alignment interface based on FPGA to solve the problems raised in the above background technology.
[0004] In order to achieve the above purpose, the utility model provides the following technical solutions:
[0005] An FPGA-based multi-channel alignment interface comprises a fixed base, a connecting device is fixedly connected to the front end of the fixed base, a snap-fit structure is arranged at the upper end of the connecting device, a dustproof structure is arranged at the lower end of the connecting device, an FPGA alignment interface is arranged in the middle of the connecting device, a button movable groove is arranged at the inner end of the snap-fit structure, and a snap-fit groove is arranged between the FPGA alignment interface and the button movable groove.
[0006] Preferably, a fixing rod is provided at the inner end of the buckle groove, a rotating buckle is rotatably connected to the outer side of the fixing rod, an adjusting spring is fixedly connected to the rear end of the rotating buckle, a button is fixedly connected to the front end of the rotating buckle, and a fixed card block is provided at a position corresponding to the rotating buckle on the lower side of the inner end of the FPGA alignment interface.
[0007] Preferably, a dust cover is provided at the inner end of the FPGA alignment interface near the front side, a protrusion is fixedly connected to the front end surface of the dust cover near the upper side, moving blocks are fixedly connected to the left and right sides of the dust cover, a moving block adjusting rod is slidably connected to the inner side of the moving block, and a spring is provided on the outer side of the lower end of the moving block corresponding to the moving block adjusting rod.
[0008] Preferably, a dust cover groove is provided at the lower end of the dust cover, a signal connection line plug is plugged into the inner end of the FPGA alignment interface, a signal connection line is provided at one end of the signal connection line plug, a signal connection head is provided at the other end of the signal connection line plug, a clamping ring is fixedly connected to the outer surface of the signal connection line plug, and an FPGA alignment interface device is fixedly connected to the rear end of the fixed base.
[0009] By adopting the above technical solution,
[0010] Compared with the prior art, the beneficial effects of the utility model are:
[0011] 1. Fix the connection device on the surface of the FPGA alignment interface device through the fixing base to prevent it from falling. Install the signal connection line plug on the front end of the signal connection line, and then insert the signal connection line plug into the FPGA alignment interface. The clamping ring on the outer surface of the signal connection line plug is clamped by the fixed clamping block and the rotating buckle to prevent the signal connection line at the inner end of the FPGA alignment interface from loosening or falling in the working state. When the signal connection line needs to be removed, press the button, and the button drives the rotating buckle to rotate on the fixed rod. At the same time, the rotating buckle compresses the adjusting spring. The rotating buckle loosens the clamping ring on the surface of the signal connection line plug, and then the signal connection line plug can be removed. Release the button, adjust the spring to release the elastic force, adjust the spring to drive the rotating buckle to return to its position, and the rotating buckle drives the button to return to its position By fixing the base and the clamping ring, a stable connection between the signal cable plug and the FPGA alignment interface is ensured, which can reduce distortion and interruption during signal transmission and ensure the stability and reliability of the system. The mechanical structure of pressing the button to rotate the buckle makes it easy and effective to remove the signal cable. The user only needs to press the button and rotate the buckle to release the signal cable plug. No additional tools or complicated operating steps are required. The fixed card block and the rotating buckle are clamped to ensure that the signal cable plug will not accidentally loosen or fall off in the working state, which helps to prevent data loss or system failure caused by accidental disconnection and improves the safety of the equipment. The spring and return mechanism are adjusted so that the rotating buckle and button can automatically return to their original position after operation and maintain good working condition.
[0012] 2. When the FPGA alignment interface is not in use, the dust cover prevents dust from entering the FPGA alignment interface. When the FPGA alignment interface is to be used, push the bump downward by hand, and the bump drives the dust cover to move downward into the dust cover slot. At the same time, the dust cover drives the moving blocks on the left and right sides to slide downward on the moving block adjustment rod. The moving block compresses the spring on the outside of the lower moving block adjustment rod, so that the signal connection line plug can be inserted into the FPGA alignment interface. When the signal connection line plug is unplugged, the spring releases the elastic force to drive the moving block to move upward, and the moving block drives the dust cover to return to its place to cover the FPGA alignment interface, which can effectively prevent dust and other impurities from entering the FPGA alignment interface, thereby reducing the pollution and accumulation inside the interface, keeping the interface clean and in good working condition, and reducing connection problems or failures caused by dust. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.
[0014] Figure 1 It is a structural diagram of the multi-channel alignment interface based on FPGA.
[0015] Figure 2 It is a schematic diagram of the structure of the connection device in the FPGA-based multi-channel alignment interface.
[0016] Figure 3 Schematic diagram of the structure of the snap-in structure in the FPGA-based multi-channel alignment interface.
[0017] Figure 4 Schematic diagram of the dust-proof structure in the FPGA-based multi-channel alignment interface.
[0018] Figure 5 It is a structural schematic diagram of the signal connection lines in the FPGA-based multi-channel alignment interface.
[0019] In the figure: 1. fixed base, 2. connecting device, 3. buckle structure, 4. dustproof structure, 5. FPGA alignment interface, 6. buckle slot, 7. fixed rod, 8. rotating buckle, 9. adjustment spring, 10. button, 11. fixed block, 12. dust cover, 13. bump, 14. moving block, 15. moving block adjustment rod, 16. spring, 17. dust cover slot, 18. signal connecting line, 19. signal connecting line plug, 20. snap ring, 21. signal connector, 22. FPGA alignment interface device, 23. button movable slot.
[0020] The realization of the purpose, functional features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. The above-mentioned drawings have shown clear embodiments of this application, which will be described in more detail later. These drawings and textual descriptions are not intended to limit the scope of the concept of this application in any way, but to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION
[0021] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.
[0022] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.
[0023] It should be understood that, although the terms first, second, third, etc. may be used to describe various information in this article, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this article, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination". Furthermore, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate that there are the described features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or", "and / or", "including at least one of the following" etc. used in this application can be interpreted as inclusive, or mean any one or any combination. For example, “comprising at least one of the following: A, B, C” means “any of the following: A; B; C; A and B; A and C; B and C; A and B and C”, and for another example, “A, B or C” or “A, B and / or C” means “any of the following: A; B; C; A and B; A and C; B and C; A and B and C”. An exception to this definition will only occur when a combination of elements, functions, steps or operations are inherently mutually exclusive in some manner.
[0024] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0025] See also Figures 1 to 4 In the embodiment of the utility model, the multi-channel alignment interface based on FPGA includes a fixed base 1. The rear end of the fixed base 1 is fixedly connected with an FPGA alignment interface device 22. The fixed base can help fix the multi-channel alignment interface, and the connecting device is fixed to the surface of the FPGA alignment interface device 22 through the fixed base to prevent it from falling.
[0026] The front end of the fixed base 1 is fixedly connected with a connecting device 2. The connecting device 2 arranged on the fixed base 1 can prevent the signal connecting wire at the inner end of the FPGA alignment interface from loosening or falling off in the working state, ensure the stable connection between the signal connecting wire plug and the FPGA alignment interface, reduce the distortion and interruption during signal transmission, ensure the stability and reliability of the system, and make it easy and effective to remove the signal connecting wire.
[0027] Exemplarily, a snap-fit structure 3 is provided at the upper end of the connecting device 2 , a dustproof structure 4 is provided at the lower end of the connecting device 2 , and an FPGA alignment interface 5 is provided in the middle of the connecting device 2 .
[0028] Exemplarily, a button movable groove 23 is opened at the inner end of the buckle structure 3, a buckle groove 6 is opened between the FPGA alignment interface 5 and the button movable groove 23, a fixing rod 7 is arranged at the inner end of the buckle groove 6, a rotating buckle 8 is rotatably connected to the outer side of the fixing rod 7, an adjusting spring 9 is fixedly connected to the rear end of the rotating buckle 8, and a button 10 is fixedly connected to the front end of the rotating buckle 8.
[0029] Exemplarily, a fixed block 11 is provided at a position corresponding to the rotating buckle 8 on the lower side of the inner end of the FPGA alignment interface 5. A dust cover 12 is provided near the front side of the inner end of the FPGA alignment interface 5. A dust cover groove 17 is provided at the lower end of the dust cover 12.
[0030] The clamping ring on the outer surface of the signal connection line plug is clamped by the fixed clamping block 11 and the rotating buckle 8, which can prevent the signal connection line at the inner end of the FPGA alignment interface from loosening or falling off in the working state. When the FPGA alignment interface 5 is not in use, the dust cover 12 prevents dust from entering the FPGA alignment interface 5.
[0031] Exemplarily, a protrusion 13 is fixedly connected to the front surface of the dust cover 12 near the upper side, and a moving block 14 is fixedly connected to the left and right sides of the dust cover 12. When the FPGA alignment interface 5 is to be used, the protrusion is pushed downward by hand, and the protrusion drives the dust cover 12 to move downward into the dust cover slot. When the signal connection line plug is unplugged, the moving block 14 drives the dust cover 12 to return to its original position to cover the FPGA alignment interface 5, which can effectively prevent dust and other impurities from entering the FPGA alignment interface 5, thereby reducing pollution and accumulation inside the interface, keeping the interface clean and in good working condition, and reducing connection problems or failures caused by dust.
[0032] Exemplarily, the inner side of the moving block 14 is slidably connected with a moving block adjusting rod 15 , and the outer side of the lower end of the moving block 14 corresponding to the moving block adjusting rod 15 is sleeved with a spring 16 .
[0033] When the signal connection line needs to be removed, press the button, the button drives the rotating buckle 8 to rotate on the fixing rod 7, and at the same time, the rotating buckle 8 compresses the adjusting spring 9, and the rotating buckle 8 loosens the signal connection line plug, so that the signal connection line plug can be removed, release the button, and the adjusting spring 9 releases the elastic force. The adjusting spring 9 can drive the rotating buckle 8 to return to its original position, and the rotating buckle 8 drives the button to return to its original position.
[0034] Exemplarily, the inner end of the FPGA alignment interface 5 is used to plug the signal connection line plug 19. A signal connection line 18 can be set at one end of the signal connection line plug 19, and a signal connector 21 can be set at the other end of the signal connection line plug 19. A clamping ring 20 is fixedly connected to the outer surface of the signal connection line plug 19. By locking the fixed base 1 and the clamping ring 20, a stable connection between the signal connection line plug 19 and the FPGA alignment interface 5 is ensured.
[0035] The working principle of the utility model is: the connection device is fixed on the surface of the FPGA alignment interface device through a fixed base to prevent it from falling. The front end of the signal connection line is installed with a signal connection line plug, and then the signal connection line plug is inserted into the FPGA alignment interface. The clamping ring on the outer surface of the signal connection line plug is clamped by a fixed clamping block and a rotating clamping buckle to prevent the signal connection line at the inner end of the FPGA alignment interface from loosening or falling in the working state.
[0036] When the signal cable needs to be removed, press the button, which drives the rotating buckle to rotate on the fixed rod. At the same time, the rotating buckle compresses the adjusting spring. The rotating buckle loosens the clamping ring on the surface of the signal cable plug, and the signal cable plug can be removed.
[0037] Release the button, adjust the spring to release the elastic force, adjust the spring to drive the rotating buckle to return to its original position, and rotate the buckle to drive the button to return to its original position. By fixing the base and the clamp ring, a stable connection between the signal cable plug and the FPGA alignment interface is ensured, which can reduce distortion and interruption during signal transmission and ensure the stability and reliability of the system.
[0038] The mechanical structure of pressing a button to rotate the buckle makes it easy and effective to remove the signal cable. The user only needs to press a button and rotate the buckle to release the signal cable plug, without the need for additional tools or complicated operating steps. The fixed card block and rotating buckle are clamped to ensure that the signal cable plug will not accidentally loosen or fall off in the working state, which helps prevent data loss or system failure caused by accidental disconnection and improves the safety of the equipment. The spring and return mechanism are adjusted so that the rotating buckle and button can automatically return to their original position after operation and maintain good working condition.
[0039] When the FPGA alignment interface is not in use, the dust cover prevents dust from entering the FPGA alignment interface; when the FPGA alignment interface is to be used, push the bump downward by hand, and the bump drives the dust cover to move downward into the dust cover slot. At the same time, the dust cover drives the moving blocks on the left and right sides to slide downward on the moving block adjustment rod, and the moving block compresses the spring on the outside of the lower moving block adjustment rod, so that the signal connection line plug can be inserted into the FPGA alignment interface. When the signal connection line plug is unplugged, the spring releases the elastic force to drive the moving block to move upward, and the moving block drives the dust cover to return to its position to cover the FPGA alignment interface, which can effectively prevent dust and other impurities from entering the FPGA alignment interface, thereby reducing the pollution and accumulation inside the interface, keeping the interface clean and in good working condition, and reducing connection problems or failures caused by dust.
[0040] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be regarded as exemplary and non-restrictive from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.
[0041] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
Claims
1. A multi-channel alignment interface based on FPGA, comprising a fixed base (1), characterized in that: The front end of the fixed base (1) is fixedly connected to a connecting device (2); the upper end of the connecting device (2) is provided with a buckle structure (3); the lower end of the connecting device (2) is provided with a dustproof structure (4); an FPGA alignment interface (5) is provided in the middle of the connecting device (2); a button movable groove (23) is provided at the inner end of the buckle structure (3); and a buckle groove (6) is provided between the FPGA alignment interface (5) and the button movable groove (23).
2. The FPGA-based multi-channel alignment interface according to claim 1, characterized in that: A fixing rod (7) is provided at the inner end of the buckle groove (6); a rotating buckle (8) is rotatably connected to the outer side of the fixing rod (7); an adjusting spring (9) is fixedly connected to the rear end of the rotating buckle (8); and a button (10) is fixedly connected to the front end of the rotating buckle (8).
3. The FPGA-based multi-channel alignment interface according to claim 1, characterized in that: A fixed clamping block (11) is provided at a position corresponding to the rotating buckle (8) on the lower side of the inner end of the FPGA alignment interface (5), and a dust cover (12) is provided at the inner end of the FPGA alignment interface (5) near the front side.
4. The FPGA-based multi-channel alignment interface according to claim 3, characterized in that: A protrusion (13) is fixedly connected to the front end surface of the dust cover (12) near the upper side, and moving blocks (14) are fixedly connected to the left and right sides of the dust cover (12).
5. The FPGA-based multi-channel alignment interface according to claim 4, characterized in that: The inner side of the moving block (14) is slidably connected with a moving block adjusting rod (15), and the outer side of the lower end of the moving block (14) corresponding to the moving block adjusting rod (15) is sleeved with a spring (16).
6. The FPGA-based multi-channel alignment interface according to claim 3, characterized in that: A dust cover groove (17) is provided at the lower end of the dust cover (12), and a signal connection line plug (19) is plugged into the inner end of the FPGA alignment interface (5).
7. The FPGA-based multi-channel alignment interface according to claim 6, characterized in that: One end of the signal connection line plug (19) is provided with a signal connection line (18), and the other end of the signal connection line plug (19) is provided with a signal connector (21).
8. The FPGA-based multi-channel alignment interface according to claim 7, characterized in that: A clamping ring (20) is fixedly connected to the outer surface of the signal connection line plug (19), and an FPGA alignment interface device (22) is fixedly connected to the rear end of the fixed base (1).