PCB (Printed Circuit Board) with multiple MOS (Metal Oxide Semiconductor) transistors sealed in pair and battery management system
By optimizing the pad layout of multiple MOS tube-to-tube-sealed PCB boards, the problems of pad layout limitations and low production efficiency in the prior art are solved, and higher heat dissipation and overcurrent capabilities and production efficiency are achieved.
Patent Information
- Application Number
- CN202323668860.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2033-12-29
AI Technical Summary
The pad layout of existing multi-MOS tubes on the parallel tube PCB boards has problems such as drain pad unit position limitation, source pad unit is too dispersed, complex welding process and low production efficiency, resulting in insufficient heat dissipation and overcurrent capability. Restricted.
By optimizing the pad unit layout, the second source pad unit is merged, the drain pad unit is adjusted to connect the pin to the side, adopting a chip pin, and connecting the source and gate of the MOS tube through the solder wire , increase the number and thickness of bonded wires, and improve the parallel welding capability of MOS pipes.
It achieves higher heat dissipation and overcurrent capabilities, reduces MOS usage, reduces costs, and improves production efficiency through automated patch operations.
Smart Images
Figure CN222216052U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of MOS tube-to-tube sealing, in particular to a PCB board and a battery management system for sealing a plurality of MOS tubes. Background Art
[0002] The existing single MOS has weak heat dissipation capacity, which limits the overcurrent capacity. When the current is large, the heat generated by the MOS cannot be dissipated in time, the temperature rises, and the MOS on-resistance increases with the temperature. Then the temperature rises again, increasing the conduction loss of the MOS.
[0003] There are some high current application modules such as BMS (Battery Management System), such as Figure 1 As shown, the temperature rise problem can be solved by using multiple MOS pairs in parallel, that is, increasing the number of connections between the MOS source and the source pad of the PCB board and increasing the thickness of the connections. Figure 2 The existing PCB pad unit layout for multiple MOS tubes in parallel has the following problems:
[0004] First, the drain pad unit D is located in the middle of the second source pad unit S2, which limits the number and thickness of the connection lines from the MOS source to the pad;
[0005] Second, there are multiple source pad units (S1 and S2), which are too dispersed, which is not conducive to the wiring of the overall PCB board, limiting the number and thickness of the connectable wires of the source pad units, thereby limiting the product's current capacity;
[0006] Third, the second source pad unit S2 is divided into two areas, which need to be connected by external welding wires, and three pins need to be welded, which makes the preparation process complicated;
[0007] Fourthly, each drain pad unit D, gate pad unit (G1 and G2), and source pad unit (S1 and S2) has external plug-in pins, which require manual soldering later, thus reducing production efficiency.
[0008] The purpose of the present invention is to design a PCB board and a battery management system with multiple MOS tubes sealed together to solve the above problems in the prior art. Utility Model Content
[0009] The purpose of the utility model is to overcome the deficiencies of the prior art and provide a PCB board and a battery management system with multiple MOS tubes sealed together, which can solve the above-mentioned technical problems.
[0010] The utility model provides a PCB board with multiple MOS tubes sealed together, comprising:
[0011] A PCB body, a pad unit arranged on the PCB body, the pad unit being used for welding a plurality of groups of MOS tubes, each group of the MOS tubes being a group of parallel-connected MOS tubes, the pad unit comprising: a first source pad unit, a first gate pad unit, a drain pad unit, a second source pad unit, and a second gate pad unit;
[0012] The first source pad unit and the second source pad unit are symmetrically arranged on both sides of the PCB board body, and are used to connect the source electrodes of the MOS tubes closest to each group of MOS tubes through welding wires, respectively, and connect each group of MOS tubes in parallel;
[0013] The drain pad unit is arranged between the first source pad unit and the second source pad unit, and a plurality of groups of MOS tubes are placed above the drain pad unit to connect the drains of each group of MOS tubes;
[0014] A first gate pad unit is arranged between the first source pad unit and the drain pad unit, and a second gate pad unit is arranged between the second source pad unit and the drain pad unit, which are used to connect the gates of the nearest MOS tubes in each group of MOS tubes through welding wires.
[0015] Further, the first source pad unit area is larger than the first gate pad unit area, and the second source pad unit area is larger than the second gate pad unit area.
[0016] Furthermore, the drain pad unit is a first drain pad unit and a second drain pad unit, and the first drain pad unit and the second drain pad unit are connected via a bonding wire.
[0017] Furthermore, the first drain pad unit is used for external pins, and the second drain pad unit is used for welding the drain of the MOS tube.
[0018] Furthermore, the distances between the first source pad unit, the first gate pad unit, the drain pad unit, the second source pad unit, and the second gate pad unit are 0.6±0.02 mm.
[0019] Furthermore, three groups of MOS tubes are welded above the drain pad, and each group of MOS tubes is arranged in parallel.
[0020] Furthermore, the pad unit is externally connected to a surface mount pin.
[0021] The utility model provides a battery management system, comprising: a PCB board on which a plurality of MOS tubes are sealed.
[0022] The utility model has the following advantages:
[0023] First, by adjusting the layout of the pad unit on the PCB board, the second source pad unit is merged, and the part of the drain pad unit connected to the pin is adjusted to the side, so that the drain pad unit will not affect the welding wire connection between the MOS tube and the second source pad unit, ensuring that the welding wire connection of the MOS tube source is no longer restricted by the frame.
[0024] Second, the drain pad unit can accommodate 6 MOS tubes, realize the joint welding of 6 MOS tubes, and improve the overall current capacity of the PCB board. This PCB board can improve the heat dissipation capacity of the product using the PCB board, reduce the amount of MOS tubes, and thus achieve the effect of reducing costs. The welding wires connecting the source of each MOS tube to the source pad unit are 6 20mil welding wires, which can optimize the on-resistance parameters of the MOS tube, while improving the heat dissipation capacity and the single pulse avalanche breakdown energy impact resistance.
[0025] Third, by centrally arranging the first source pad unit and the second source pad unit without separation, there is no need for additional welding wires to connect the separated separation pad units, thereby reducing the number of pins welded for each pad unit.
[0026] Fourth, the use of surface-mount pins facilitates the subsequent automated surface-mount operations, eliminating the need for manual soldering and improving production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0028] Figure 1 It is the equivalent circuit diagram of multiple MOS tubes connected in parallel.
[0029] Figure 2 This is a PCB diagram of a pair of MOS tubes packaged together.
[0030] Figure 3 This is the PCB diagram of the first embodiment.
[0031] Figure 4 It is the PCB board dimension diagram of embodiment 1.
[0032] Figure 5 This is the PCB diagram of the second embodiment. DETAILED DESCRIPTION
[0033] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It is particularly noted that the following embodiments are only used to illustrate the present invention, but do not limit the scope of the present invention. Similarly, the following embodiments are only partial embodiments of the present invention rather than all embodiments. All other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0034] Embodiment 1
[0035] like Figure 3 As shown, this solution provides a PCB board for sealing multiple MOS tubes, including:
[0036] A PCB body, a pad unit arranged on the PCB body, the pad unit being used to weld a plurality of groups of MOS tubes, each group of the MOS tubes being a group of parallel-connected MOS tubes, the pad unit comprising: a first source pad unit S1, a first gate pad unit G1, a drain pad unit D, a second source pad unit S2, and a second gate pad unit G2;
[0037] The first source pad unit S1 and the second source pad unit S2 are symmetrically arranged on both sides of the PCB board body, and are used to connect the source electrodes of the MOS tubes closest to each group of MOS tubes through welding wires, respectively, and connect each group of MOS tubes in parallel;
[0038] The drain pad unit D is disposed between the first source pad unit S1 and the second source pad unit S2, and a plurality of groups of MOS transistors are placed above the drain pad unit D to connect the drains of each group of MOS transistors;
[0039] A first gate pad unit G1 is arranged between the first source pad unit S1 and the drain pad unit D, and a second gate pad unit G2 is arranged between the second source pad unit S1 and the drain pad unit D, which are used to connect the gates of the MOS tubes closest to each group of MOS tubes through welding wires.
[0040] In this embodiment, by adjusting the layout of the pad unit on the PCB board, the second source pad unit is merged, and the part of the drain pad unit connected to the pin is adjusted to the side, so that the drain pad unit will not affect the wire connection between the MOS tube and the second source pad unit, ensuring that the wire connection of the source of the MOS tube is no longer restricted by the frame. In this solution, the wires connecting the source of each MOS tube to the source pad unit are 6 20mil wires, which can optimize the on-resistance parameters of the MOS tube, while improving the heat dissipation capacity and the single pulse avalanche breakdown energy impact resistance.
[0041] Further, the area of the first source pad unit S1 is larger than the area of the first gate pad unit G1, and the area of the second source pad unit S2 is larger than the area of the second gate pad unit G2.
[0042] Further, the distances among the first source pad unit S1, the first gate pad unit G1, the drain pad unit D, the second source pad unit S2, and the second gate pad unit G2 are 0.6±0.02 mm.
[0043] Furthermore, three groups of MOS tubes are welded above the drain pad D, and each group of MOS tubes is arranged in parallel.
[0044] In this embodiment, the size of each pad unit is as follows: Figure 4 As shown, the drain pad unit can accommodate 3 groups of MOS tubes, realize parallel welding of 3 groups of MOS tubes, and improve the overall current capacity of the PCB board. This PCB board can improve the heat dissipation capacity of the product using the PCB board, reduce the amount of MOS tubes, and thus achieve the effect of reducing costs.
[0045] Furthermore, the pad unit is externally connected to a surface mount pin.
[0046] In this embodiment, SMD pins are used to facilitate the subsequent automated SMD operation, eliminating the need for manual soldering and improving production efficiency.
[0047] Embodiment 2
[0048] like Figure 5 As shown, the difference between this embodiment and the first embodiment is that the drain pad unit is a first drain pad unit D1 and a second drain pad unit D2, and the first drain pad unit D1 and the second drain pad unit D2 are connected by a bonding wire.
[0049] Furthermore, the first drain pad unit D1 is used for external pins, and the second drain pad unit D2 is used for welding the drain of the MOS tube.
[0050] In this embodiment, the drain pad unit area of this embodiment is smaller than the drain pad unit area of the first embodiment, which can save pad area and achieve the same technical effect as the embodiment.
[0051] The present solution also provides a battery management system, including the above-mentioned PCB board with multiple MOS tubes sealed together.
[0052] The above descriptions are only some embodiments of the present invention, and do not limit the protection scope of the present invention. Any equivalent device or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A PCB board with multiple MOS tubes sealed together, characterized in that: include: A PCB body, a pad unit arranged on the PCB body, the pad unit being used for welding a plurality of groups of MOS tubes, each group of the MOS tubes being a group of parallel-connected MOS tubes, the pad unit comprising: a first source pad unit, a first gate pad unit, a drain pad unit, a second source pad unit, and a second gate pad unit; The first source pad unit and the second source pad unit are symmetrically arranged on both sides of the PCB board body, and are used to connect the source electrodes of the MOS tubes closest to each group of MOS tubes through welding wires, respectively, and connect each group of MOS tubes in parallel; The drain pad unit is arranged between the first source pad unit and the second source pad unit, and a plurality of groups of MOS tubes are placed above the drain pad unit to connect the drains of each group of MOS tubes; A first gate pad unit is arranged between the first source pad unit and the drain pad unit, and a second gate pad unit is arranged between the second source pad unit and the drain pad unit, which are used to connect the gates of the nearest MOS tubes in each group of MOS tubes through welding wires.
2. The PCB board with multiple MOS tubes sealed together according to claim 1, characterized in that: The first source pad unit area is larger than the first gate pad unit area, and the second source pad unit area is larger than the second gate pad unit area.
3. The PCB board with multiple MOS tubes sealed together according to claim 1, characterized in that: The drain pad unit includes a first drain pad unit and a second drain pad unit, and the first drain pad unit and the second drain pad unit are connected via a bonding wire.
4. The PCB board with multiple MOS tubes sealed together according to claim 3, characterized in that: The first drain pad unit is used for external pins, and the second drain pad unit is used for welding the drain of the MOS tube.
5. The PCB board with multiple MOS tubes sealed together according to claim 1, characterized in that: The distances between the first source pad unit, the first gate pad unit, the drain pad unit, the second source pad unit, and the second gate pad unit are 0.6±0.02 mm.
6. The PCB board with multiple MOS tubes sealed together according to claim 1, characterized in that: Three groups of MOS tubes are welded above the drain pad, and each group of MOS tubes is arranged in parallel.
7. The PCB board with multiple MOS tubes sealed together according to claim 1, characterized in that: The pad unit is externally connected to a surface mount pin.
8. A battery management system, characterized in that: A PCB board comprising a plurality of MOS tubes sealed together as described in any one of claims 1 to 7.