Perovskite cell structure and perovskite crystalline silicon ore laminated cell

Abstract

The utility model belongs to the technical field of solar cells, and particularly provides a perovskite cell structure and a perovskite crystalline silicon ore laminated cell, and the perovskite cell structure comprises a conductive substrate. A nickel oxide hole transport layer, a cesium bromide buffer layer, a perovskite light absorption layer, an electron transport layer and an electrode layer are sequentially stacked on the conductive substrate. The solar cell can relieve interface stress, and has high cell open-circuit voltage, charge extraction effect, structural stability and photoelectric conversion efficiency.

Description

Technical Field

[0001] The utility model belongs to the technical field of solar cells and relates to a perovskite cell structure and a perovskite crystal silicon ore laminated cell. Background Art

[0002] Perovskite solar cells have attracted widespread attention due to their rapid development in power conversion efficiency. They have the advantages of simple manufacturing, low cost, and the ability to produce transparent, flexible and laminated devices, making them a research hotspot in the field of renewable energy.

[0003] In the manufacturing process of perovskite solar cells, the selection of appropriate materials and components is crucial to achieve efficient and stable power conversion. Nickel oxide has attracted much attention in perovskite solar cells due to its easy preparation, low cost and good mechanical stability. Nickel oxide, as a P-type semiconductor material with a wide bandgap (3.6-4.0 eV), has been successfully used in the inverse structure of perovskite solar cells and the perovskite crystalline silicon stacked cell structure.

[0004] The study found that the overcoordinated Ni ≥ 3+ sites can react with the perovskite precursor through an electron transfer-proton transfer mechanism to form a PbI-rich nanostructured structure at the NiO / perovskite interface. 2-x Br x The hole extraction barrier is usually eliminated by introducing excess A-site cations in the perovskite precursor to offset the loss of organic cations. In addition, nickel vacancies are considered to be the main reason for the dominant P-type conductivity in undoped nickel oxide. Since the internal P-type conductivity is limited, the Ni vacancies in undoped nickel oxide have a large ionization energy, and external dopants with shallow acceptor levels are usually used to increase the conductivity.

[0005] In addition, due to the interface contact between the P-type semiconductor material and the perovskite layer, it is easy to cause the energy band mismatch inside the battery, resulting in reflection and loss at the interface. The mismatch in thermal expansion coefficients of different materials will also cause stress concentration at the interface, reducing the photoelectric conversion rate of the battery. Therefore, how to effectively alleviate the problem of interface stress is crucial to improving battery performance. Utility Model Content

[0006] In view of the shortcomings of the prior art, the purpose of the utility model is to provide a perovskite battery structure and a perovskite silicon ore stacked battery, which have a higher battery open circuit voltage, charge extraction effect and structural stability. At the same time, it can also relieve interface stress, which is beneficial to improve the photoelectric conversion efficiency of the battery.

[0007] To achieve this purpose, the utility model adopts the following technical solutions:

[0008] In a first aspect, the utility model provides a perovskite battery structure, which includes a conductive substrate, on which a nickel oxide hole transport layer, a cesium bromide buffer layer, a perovskite light absorption layer, an electron transport layer and an electrode layer are sequentially stacked.

[0009] The nickel oxide hole transport layer in the utility model has a high resistivity, and its low conductivity will intensify the recombination of charge carriers and reduce hole extraction, thereby improving the charge separation effect of the battery and enhancing the photoelectric conversion efficiency of the battery; at the same time, by introducing a cesium bromide buffer layer, the reflection and loss of holes at the interface are reduced, the open circuit voltage of the battery can be significantly improved, the interface stress is effectively relieved, the structural stability of the battery is enhanced, the performance degradation caused by stress is reduced, the photoelectric conversion efficiency of the battery is further improved, and multi-faceted interface regulation and battery performance improvement are achieved.

[0010] As a preferred technical solution of the present invention, the thickness of the cesium bromide buffer layer is 1 to 8 nm, for example, it can be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm or 8 nm, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0011] The cesium bromide buffer layer of the utility model can be prepared by evaporation. By introducing the evaporated cesium bromide buffer layer between the nickel oxide hole transport layer and the perovskite light absorption layer, it is helpful to adjust the interface contact between the two, reduce the band mismatch inside the battery, thereby reducing the reflection and loss of electrons at the interface, improving the electron transmission efficiency of the battery, and then improving the open circuit voltage. Secondly, the cesium bromide buffer layer can alleviate the problem of stress concentration at the interface caused by the mismatch of thermal expansion coefficients of different materials in the battery, which helps to improve the structural stability of the battery and reduce the performance degradation caused by stress. In addition, the cesium bromide buffer layer also optimizes the band structure between the nickel oxide layer and the perovskite layer, making it easier for electrons and holes to be separated and extracted at the interface, thereby reducing the possibility of charge recombination, not only improving the quality of perovskite films with large grain sizes, but also effectively enhancing the charge extraction efficiency.

[0012] As a preferred technical solution of the present invention, the thickness of the nickel oxide hole transport layer is 10 to 15 nm, for example, it can be 10 nm, 11 nm, 12 nm, 13 nm, 14 nm or 15 nm, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0013] The thickness of the perovskite light absorbing layer is 350 to 600 nm, for example, it can be 350 nm, 360 nm, 380 nm, 400 nm, 430 nm, 450 nm, 460 nm, 480 nm, 500 nm, 520 nm, 550 nm, 580 nm or 600 nm, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0014] The thickness of the electron transport layer is 25 to 40 nm, for example, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, 32 nm, 35 nm, 36 nm, 38 nm or 40 nm, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0015] The thickness of the electrode layer is 800-1000 nm, for example, it can be 800 nm, 820 nm, 830 nm, 840 nm, 850 nm, 860 nm, 880 nm, 900 nm, 920 nm, 940 nm, 950 nm, 960 nm, 980 nm or 1000 nm, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0016] As a preferred technical solution of the utility model, the electron transport layer includes a first electron transport layer and a second electron transport layer which are stacked in sequence from the perovskite light absorbing layer to the electrode layer.

[0017] The thickness of the first electron transport layer is 15 to 25 nm, for example, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm or 25 nm, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0018] The thickness of the second electron transport layer is 10-15 nm, for example, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm or 15 nm, but is not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0019] As a preferred technical solution of the utility model, the first electron transport layer is a C60 electron transport layer, and the second electron transport layer is a SnO2 electron transport layer.

[0020] In a second aspect, the utility model provides a perovskite-crystalline silicon ore stacked battery, wherein the perovskite-crystalline silicon ore stacked battery comprises a first battery layer and a second battery layer stacked in layers, wherein the first battery layer comprises the perovskite battery structure described in the first aspect, and the conductive substrate is connected to the second conductive layer.

[0021] The nickel oxide hole transport layer of the laminated battery in the utility model has a high resistivity, and its low conductivity will intensify the recombination of charge carriers and reduce hole extraction, thereby improving the charge separation effect of the battery, and thus enhancing the photoelectric conversion efficiency of the battery. By introducing a buffer layer, the reflection and loss of electrons at the interface are reduced, the open circuit voltage of the battery can be significantly improved, the interface stress is effectively relieved, the structural stability of the battery is enhanced, the performance degradation caused by stress is reduced, the photoelectric conversion efficiency of the battery is further improved, and multi-faceted interface regulation and battery performance improvement are achieved.

[0022] The nickel oxide hole transport layer in the utility model is used as a P-type semiconductor material for the reverse plate of the battery, introduces a PN heterojunction, improves the charge separation effect of the battery, and thus enhances the photoelectric conversion efficiency. At the same time, it has a resistivity of up to 108Ω, which is beneficial to the recombination of charge carriers and reduces hole extraction.

[0023] As a preferred technical solution of the utility model, the second battery layer includes an N-type amorphous silicon layer, a first intrinsic amorphous silicon layer, a silicon wafer, a second intrinsic amorphous silicon layer, a P-type amorphous silicon layer and a back electrode layer which are stacked in sequence in a direction away from the first battery layer.

[0024] As a preferred technical solution of the utility model, a first transparent conductive layer is arranged between the electrode layer of the first battery layer and the electron transport layer, and a second transparent conductive layer is arranged between the back electrode layer of the second battery layer and the P-type amorphous silicon layer.

[0025] As a preferred technical solution of the present invention, the thickness of the back electrode layer is 800-1000nm, for example, it can be 800nm, 820nm, 830nm, 840nm, 850nm, 860nm, 880nm, 900nm, 920nm, 940nm, 950nm, 960nm, 980nm or 1000nm, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0026] The thickness of the first transparent conductive layer and the second transparent conductive layer are independently 100 to 130 nm, for example, 100 nm, 102 nm, 105 nm, 106 nm, 108 nm, 110 nm, 115 nm, 118 nm, 120 nm, 122 nm, 125 nm, 126 nm, 128 nm or 130 nm, but are not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0027] It should be noted that, in the present invention, the thickness of the first transparent conductive layer and the second transparent conductive layer are independently 100-130 nm, which means that the thickness of the first transparent conductive layer is 100-130 nm, and the thickness of the second transparent conductive layer is 100-130 nm, and the thickness of the first transparent conductive layer and the second transparent conductive layer can be the same or different.

[0028] The thickness of the conductive substrate is 20 to 30 nm, for example, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm or 30 nm, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0029] The conductive substrate includes a tunnel junction layer, a metal layer or a transparent electrode layer, and is located between the two end battery layers, and is used for electronic recombination of the first battery layer and the second battery layer.

[0030] The numerical range described in the present invention not only includes the point values ​​listed above, but also includes any point values ​​between the above numerical ranges that are not listed. Due to space limitations and for the sake of simplicity, the present invention no longer exhaustively lists the specific point values ​​included in the range.

[0031] Compared with the prior art, the beneficial effects of the utility model are:

[0032] The utility model provides a perovskite battery structure and a perovskite-silicon ore stacked battery, in which the nickel oxide hole transport layer used has high resistivity, and its low conductivity will intensify the recombination of charge carriers and reduce hole extraction, thereby improving the charge separation effect of the battery, thereby enhancing the photoelectric conversion efficiency of the battery. By introducing a buffer layer, the reflection and loss of electrons at the interface are reduced, the open circuit voltage of the battery can be significantly improved, the interface stress is effectively relieved, the structural stability of the battery is enhanced, the performance degradation caused by stress is reduced, the photoelectric conversion efficiency of the battery is further improved, and multi-faceted interface regulation and battery performance improvement are achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the structure of a perovskite crystalline silicon stacked battery structure provided in Example 1 of the utility model;

[0034] Figure 2 A schematic diagram of the structure of a perovskite crystalline silicon stacked battery structure provided in Example 2 of the utility model;

[0035] Figure 3 A schematic diagram of the structure of a perovskite crystalline silicon stacked battery structure provided in Comparative Example 1 of the present utility model;

[0036] Figure 4A scanning electron microscope image of the perovskite crystalline silicon stacked cell structure provided in Example 2 of the utility model;

[0037] Figure 5 A scanning electron microscope image of the perovskite crystalline silicon stacked cell structure provided in Comparative Example 1 of the present utility model;

[0038] Figure 6 Steady-state fluorescence spectrum (PL) test diagram of the perovskite crystalline silicon stacked cell structure provided in Example 2 of the utility model and Comparative Example 1;

[0039] Figure 7 This is a trend diagram of the photoelectric conversion efficiency of the perovskite crystalline silicon stacked cell structure provided in Example 2 of the utility model and Comparative Example 1.

[0040] Among them, 1011-conductive substrate (Ⅰ); 1021-nickel oxide hole transport layer (Ⅰ); 1031-cesium bromide buffer layer (Ⅰ); 1041-perovskite light absorption layer (Ⅰ); 1051-C60 electron transport layer (Ⅰ); 1061-SnO2 electron transport layer (Ⅰ); 1071-electrode layer; 101-back electrode; 102-second ITO conductive layer; 103-P-type amorphous silicon layer; 104-second Intrinsic amorphous silicon layer; 105-silicon wafer; 106-first intrinsic amorphous silicon layer; 107-N-type amorphous silicon layer; 108-conductive substrate (Ⅱ); 109-nickel oxide hole transport layer (Ⅱ); 110-perovskite light absorption layer (Ⅱ); 111-C60 electron transport layer (Ⅱ); 112-SnO2 electron transport layer (Ⅱ); 113-first ITO conductive layer; 114-front electrode; 115-cesium bromide buffer layer (Ⅱ). DETAILED DESCRIPTION

[0041] It should be understood that, in the description of the present utility model, the terms "center", "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present utility model, unless otherwise specified, "multiple" means two or more.

[0042] The technical solution of the utility model is further explained below with reference to the accompanying drawings and through specific implementation methods.

[0043] All materials used in the following contents are commercially available products known to those skilled in the art.

[0044] In a specific embodiment, the utility model provides a perovskite battery structure, including a conductive substrate, on which a nickel oxide hole transport layer, a cesium bromide buffer layer, a perovskite light absorption layer, an electron transport layer and an electrode layer are sequentially stacked.

[0045] The cesium bromide buffer layer of the utility model can be prepared by evaporation. By introducing the evaporated cesium bromide buffer layer between the nickel oxide hole transport layer and the perovskite light absorption layer, it is helpful to adjust the interface contact between the two, reduce the band mismatch inside the battery, thereby reducing the reflection and loss of electrons at the interface, improving the electron transmission efficiency of the battery, and then improving the open circuit voltage. Secondly, the cesium bromide buffer layer can alleviate the problem of stress concentration at the interface caused by the mismatch of thermal expansion coefficients of different materials in the battery, which helps to improve the structural stability of the battery and reduce the performance degradation caused by stress. In addition, the cesium bromide buffer layer also optimizes the band structure between the nickel oxide layer and the perovskite layer, making it easier for electrons and holes to be separated and extracted at the interface, thereby reducing the possibility of charge recombination, not only improving the quality of perovskite films with large grain sizes, but also effectively enhancing the charge extraction efficiency.

[0046] In some embodiments, the thickness of the nickel oxide hole transport layer is 10 to 15 nm, the thickness of the cesium bromide buffer layer is 1 to 8 nm, the thickness of the perovskite light absorption layer is 350 to 600 nm, the thickness of the electron transport layer is 25 to 40 nm, and the thickness of the electrode layer is 800 to 1000 nm.

[0047] The perovskite light-absorbing layer in the utility model can be produced by co-evaporation technology, specifically including:

[0048] Lead iodide, cesium iodide, and lead bromide are evaporated on the cesium bromide buffer layer, wherein the evaporation rate of lead iodide is The evaporation rate of cesium lead iodide is The evaporation rate of lead bromide is Then, a mixed organic solution of methylamine iodide, methylamine bromide, methylamine iodide and methylamine chloride dissolved in isopropanol is spin-coated on the evaporated film layer at a concentration of 1.0 to 1.5 M, and annealed at a temperature of 100 to 150° C. for 10 to 15 minutes to prepare the perovskite light-absorbing layer.

[0049] In some embodiments, the electron transport layer includes a first electron transport layer and a second electron transport layer stacked in sequence from the perovskite light absorbing layer to the electrode layer. Specifically, the first electron transport layer is a C60 electron transport layer, the thickness of the first electron transport layer is 15 to 25 nm, and the second electron transport layer is a SnO2 electron transport layer, the thickness of the second electron transport layer is 10 to 15 nm.

[0050] In another specific embodiment, the utility model provides a perovskite crystal silicon ore stacked battery, including a first battery layer and a second battery layer stacked, the first battery layer includes a perovskite battery structure described in a specific embodiment, and the conductive substrate is connected to the second battery layer. The second battery layer includes an N-type amorphous silicon layer, a first intrinsic amorphous silicon layer, a silicon wafer, a second intrinsic amorphous silicon layer, a P-type amorphous silicon layer and a back electrode layer stacked in sequence in a direction away from the first battery layer. A first transparent conductive layer is arranged between the electrode layer of the first battery layer and the electron transport layer, and a second transparent conductive layer is arranged between the back electrode layer of the second battery layer and the P-type amorphous silicon layer. The conductive substrate in the utility model includes a tunnel junction layer, a metal layer or a transparent electrode layer, which is located between the battery layers at both ends and is used for electronic recombination of the first battery layer and the second battery layer. Specifically, the conductive substrate is a TCO (transparent conductive oxide coating, Transparent Conductive Oxides) transparent electrode, and its material can be ITO (indium tin oxide), FTO (fluorine-doped SnO2), or AZO (aluminum-doped ZnO).

[0051] In the present invention, the front electrode can be connected to the surface of the first transparent conductive layer by evaporation, and the back electrode can be connected to the surface of the second transparent conductive layer by screen printing or evaporation.

[0052] In the utility model, the nickel oxide hole transport layer is used as a P-type semiconductor material for the reverse plate of the battery, and a PN heterojunction is introduced to improve the charge separation effect of the battery, thereby enhancing the photoelectric conversion efficiency. At the same time, it has a resistivity of up to 108Ω, which is conducive to the recombination of charge carriers and reduces hole extraction.

[0053] Illustratively, a perovskite crystalline silicon ore stacked battery of the utility model is a front electrode layer, a second electron transport layer, a first electron transport layer, a perovskite light absorption layer, a cesium bromide buffer layer, a nickel oxide hole transport layer, a conductive substrate, an N-type amorphous silicon layer, a first intrinsic amorphous silicon layer, a silicon wafer, a second intrinsic amorphous silicon layer, a P-type amorphous silicon layer and a back electrode layer stacked in sequence from top to bottom.

[0054] In some embodiments, the thickness of the conductive substrate is 20 to 30 nm, the thickness of the back electrode layer is 800 to 1000 nm, and the thickness of the first transparent conductive layer and the second transparent conductive layer are independently 100 to 130 nm.

[0055] In order to help those skilled in the art better understand the overall technical solution and working process of the present invention, the present invention exemplarily provides the following specific preparation methods for the first battery layer and the second battery layer.

[0056] The preparation method of the first battery layer specifically comprises the following steps:

[0057] (1) forming a nickel oxide hole transport layer on the surface of a conductive substrate by sputtering using a magnetron method;

[0058] (2) forming a cesium bromide buffer layer by evaporating the upper surface of the nickel oxide hole transport layer;

[0059] (3) using a co-evaporation technique to form a calcium perovskite light-absorbing layer on the upper surface of the cesium bromide buffer layer;

[0060] (4) forming a C60 electron transport layer on the upper surface of the perovskite light absorbing layer by an evaporation method;

[0061] (5) forming a SnO2 electron transport layer on the upper surface of the C60 electron transport layer by atomic deposition;

[0062] (6) A first conductive layer is formed by sputtering on the upper surface of the SnO2 electron transport layer using magnetron technology to obtain a first battery layer.

[0063] The manufacturing method of the second battery layer includes: forming a P-type amorphous silicon layer, a second intrinsic amorphous silicon layer, a silicon wafer, a first intrinsic amorphous silicon layer and an N-type amorphous silicon layer on the surface of the second transparent conductive layer in sequence to obtain the second battery layer, and then connecting an electrode to a surface of a side of the second transparent conductive layer away from the P-type amorphous silicon layer to form a back electrode layer. In addition, a commercially available semi-finished heterojunction battery known to those skilled in the art can also be used as the second battery layer.

[0064] Example 1

[0065] This embodiment provides a perovskite battery structure, such as Figure 1 As shown, it includes a conductive substrate (I) 1011, a nickel oxide hole transport layer (I) 1021, a cesium bromide buffer layer (I) 1031, a perovskite light absorption layer (I) 1041, a C60 electron transport layer (I) 1051, a SnO2 electron transport layer (I) 1061 and an electrode layer 1071 which are stacked in sequence.

[0066] The method for preparing the perovskite battery structure in this embodiment includes the following steps:

[0067] (1) Providing a conductive substrate (I) 1011;

[0068] (2) forming a nickel oxide hole transport layer 1021 on the surface of the conductive substrate (I) 1011 by sputtering using a magnetron method;

[0069] (3) forming a cesium bromide buffer layer (I) 1031 on the surface of the nickel oxide hole transport layer (I) 1021 by evaporation;

[0070] (4) Using a co-evaporation technique, lead iodide, cesium iodide, and lead bromide are evaporated on the cesium bromide buffer layer (I) 1031, wherein the evaporation rate of lead iodide is The evaporation rate of cesium lead iodide is The evaporation rate of lead bromide is Then, a mixed organic solution of methylamine iodide, methylamine bromide, methylamine iodide and methylamine chloride dissolved in isopropanol was spin-coated on the evaporated film layer at a concentration of 1.2 M, and annealed at a temperature of 120° C. for 15 min to prepare a perovskite light absorbing layer (I) 1041;

[0071] (5) preparing a C60 electron transport layer (I) 1051 on the perovskite light absorbing layer (I) 1041 by an evaporation method;

[0072] (6) using an atomic deposition technique, depositing a SnO2 electron transport layer (I) 1061 on the upper surface of the C60 electron transport layer (I) 1051;

[0073] (7) A silver metal electrode layer 1071 is evaporated on the surface of the SnO2 electron transport layer (I) 1061 to obtain a perovskite cell structure.

[0074] Example 2

[0075] This embodiment provides a perovskite crystalline silicon stacked battery, such as Figure 2As shown, it includes a first battery layer and a second battery layer stacked from top to bottom. The first battery layer includes a nickel oxide hole transport layer (II) 109, a cesium bromide buffer layer (II) 115, a perovskite light absorption layer (II) 110, a C60 electron transport layer (II) 111, a SnO2 electron transport layer (II) 112 and a first ITO conductive layer 113 stacked on one side surface of a conductive substrate (II) 108. The thickness of the nickel oxide hole transport layer (II) 109 is 15nm, the thickness of the cesium bromide buffer layer (II) 115 is 1nm, the thickness of the perovskite light absorption layer (II) 110 is 400nm, the thickness of the C60 electron transport layer (II) 111 is 20nm, the thickness of the SnO2 electron transport layer (II) 112 is 15nm, and the thickness of the first ITO conductive layer 113 is 120nm. A front electrode 114 with a thickness of 900 nm is also arranged on the first ITO conductive layer 113, and the front electrode 114 is a silver metal electrode. The conductive substrate (II) 108 is an ITO composite layer with a thickness of 20 nm, which is used for electronic recombination of the first battery layer and the second battery layer. The second battery layer includes an N-type amorphous silicon layer 107, a first intrinsic amorphous silicon layer 106, a silicon wafer 105, a second intrinsic amorphous silicon layer 104, a P-type amorphous silicon layer 103 and a second ITO conductive layer 102 stacked in sequence on the other side surface of the conductive substrate (II) 108, and a back electrode 101 is also arranged on the second ITO conductive layer 102, and the back electrode 101 is a silver metal electrode.

[0076] The method for preparing the perovskite crystalline silicon stacked cell structure in this embodiment includes the following steps:

[0077] (1) Providing a semi-finished heterojunction cell as the second cell layer;

[0078] (2) depositing an ITO composite layer on the N-type amorphous silicon layer 107 of the second battery layer;

[0079] (3) forming a nickel oxide hole transport layer (II) 109 on the surface of the ITO composite layer by sputtering in a magnetron manner;

[0080] (4) forming a cesium bromide buffer layer (II) 115 on the surface of the nickel oxide hole transport layer (II) 109 by evaporation;

[0081] (5) Using a co-evaporation technique, lead iodide, cesium iodide, and lead bromide are evaporated on the cesium bromide buffer layer (II) 115, wherein the evaporation rate of lead iodide is The evaporation rate of cesium lead iodide is The evaporation rate of lead bromide is Then, a mixed organic solution of methylamine iodide, methylamine bromide, methylamine iodide and methylamine chloride dissolved in isopropanol was spin-coated on the evaporated film layer at a concentration of 1.2 M, and annealed at a temperature of 120° C. for 15 min to prepare a perovskite light absorbing layer (II) 110;

[0082] (6) preparing a C60 electron transport layer (II) 111 on the perovskite light absorbing layer (II) 110 by an evaporation method;

[0083] (7) using an atomic deposition technique, depositing a SnO2 electron transport layer (II) 112 on the upper surface of the C60 electron transport layer (II) 111;

[0084] (8) forming a first ITO conductive layer 113 by sputtering on the surface of the SnO2 electron transport layer (II) 112 using magnetron technology;

[0085] (9) A layer of silver metal electrode is evaporated on the surface of the first ITO conductive layer 113 to obtain a perovskite crystalline silicon stacked cell.

[0086] Example 3

[0087] The present embodiment provides a perovskite crystalline silicon stacked battery, including a first battery layer and a second battery layer stacked in sequence from top to bottom. The first battery layer includes a nickel oxide hole transport layer (II) 109, a cesium bromide buffer layer (II) 115, a perovskite light absorption layer (II) 110, a C60 electron transport layer (II) 111, a SnO2 electron transport layer (II) 112 and a first ITO conductive layer stacked in sequence on a side surface of a conductive substrate (II) 108. The thickness of the nickel oxide hole transport layer (II) 109 is 10nm, the thickness of the cesium bromide buffer layer (II) 115 is 2nm, the thickness of the perovskite light absorption layer (II) 110 is 350nm, the thickness of the C60 electron transport layer (II) 111 is 15nm, the thickness of the SnO2 electron transport layer (II) 112 is 10nm, and the thickness of the first ITO conductive layer 113 is 100nm. A front electrode 114 with a thickness of 800 nm is also arranged on the first ITO conductive layer 113, and the front electrode 114 is a silver metal electrode. The conductive substrate (II) 108 is an ITO composite layer with a thickness of 25 nm, which is used for electronic recombination of the first battery layer and the second battery layer. The second battery layer includes an N-type amorphous silicon layer 107, a first intrinsic amorphous silicon layer 106, a silicon wafer 105, a second intrinsic amorphous silicon layer 104, a P-type amorphous silicon layer 103 and a second ITO conductive layer 102 stacked in sequence on the other side surface of the conductive substrate (II) 108, and a back electrode 101 is also arranged on the second ITO conductive layer 102, and the back electrode 101 is a silver metal electrode.

[0088] The preparation method of the perovskite crystalline silicon stacked cell structure provided in this embodiment is the same as that in Example 2.

[0089] Example 4

[0090] The present embodiment provides a perovskite crystalline silicon stacked battery, including a first battery layer and a second battery layer stacked in sequence from top to bottom. The first battery layer includes a nickel oxide hole transport layer (II) 109, a cesium bromide buffer layer (II) 115, a perovskite light absorption layer (II) 110, a C60 electron transport layer (II) 111, a SnO2 electron transport layer (II) 112 and a first ITO conductive layer stacked in sequence on one side surface of a conductive substrate (II) 108. The thickness of the nickel oxide hole transport layer (II) 109 is 12nm, the thickness of the cesium bromide buffer layer (II) 115 is 4nm, the thickness of the perovskite light absorption layer (II) 110 is 600nm, the thickness of the C60 electron transport layer (II) 111 is 25nm, the thickness of the SnO2 electron transport layer (II) 112 is 12nm, and the thickness of the first ITO conductive layer 113 is 130nm. A front electrode 114 with a thickness of 1000 nm is also arranged on the first ITO conductive layer 113, and the front electrode 114 is a silver metal electrode. The conductive substrate (II) 108 is an ITO composite layer with a thickness of 30 nm, which is used for electronic recombination of the first battery layer and the second battery layer. The second battery layer includes an N-type amorphous silicon layer 107, a first intrinsic amorphous silicon layer 106, a silicon wafer 105, a second intrinsic amorphous silicon layer 104, a P-type amorphous silicon layer 103 and a second ITO conductive layer 102 stacked in sequence on the other side surface of the conductive substrate (II) 108, and a back electrode 101 is also arranged on the second ITO conductive layer 102, and the back electrode 101 is a silver metal electrode.

[0091] The preparation method of the perovskite crystalline silicon stacked cell structure provided in this embodiment is the same as that in Example 2.

[0092] Example 5

[0093] This embodiment provides a perovskite crystalline silicon stacked cell, which differs from Embodiment 2 in that the thickness of the cesium bromide buffer layer (II) 115 is 3 nm, and the remaining structures, dimensional parameters and preparation methods are the same as those of Embodiment 2.

[0094] Example 6

[0095] This embodiment provides a perovskite crystalline silicon stacked cell, which differs from Embodiment 2 in that the thickness of the cesium bromide buffer layer (II) 115 is 5 nm, and the remaining structures, dimensional parameters and preparation methods are the same as those of Embodiment 2.

[0096] Example 7

[0097] This embodiment provides a perovskite crystalline silicon stacked cell, which differs from Embodiment 2 in that the thickness of the cesium bromide buffer layer (II) 115 is 8 nm, and the remaining structures, dimensional parameters and preparation methods are the same as those of Embodiment 2.

[0098] Comparative Example 1

[0099] This comparative example provides a perovskite crystalline silicon stacked cell, which differs from Example 2 in that: Figure 3 As shown, the cesium bromide buffer layer (II) 115 is not provided, that is, the first battery layer of this comparative example includes a nickel oxide hole transport layer (II) 109, a perovskite light absorption layer (II) 110, a C60 electron transport layer (II) 111, a SnO2 electron transport layer (II) 112 and a first ITO conductive layer 113 stacked in sequence on one side surface of a conductive substrate (II) 108, a front electrode 114 is provided on the first ITO conductive layer 113, and the rest of the structure, size parameters and preparation method are the same as those in Example 2.

[0100] The utility model tests the open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF) and photoelectric conversion efficiency (PEC) of the battery structure obtained in Examples 2 to 7 and Comparative Example 1 under AM 1.5G illumination using IV testing equipment. The results are shown in Table 1.

[0101] Table 1

[0102] serial number Voc(V) <![CDATA[Jsc(mA·cm -2 )]]> FF(%) PCE(%) Example 2 1.83 19.51 80.44 28.72 Example 3 1.84 19.63 80.49 29.07 Example 4 1.85 19.61 80.73 29.29 Example 5 1.86 19.72 80.64 29.58 Example 6 1.85 19.52 80.52 29.08 Example 7 1.83 19.56 80.58 28.84 Comparative Example 1 1.81 19.15 80.14 27.78

[0103] It is not difficult to see from Table 1 that Examples 2 to 7 modify the battery structure by introducing a cesium bromide buffer layer, and obtain higher open circuit voltage, short circuit current density, fill factor and photoelectric conversion efficiency. When the buffer layer thickness is 3nm, the photoelectric conversion efficiency of the battery is as high as 29.58%. This is mainly because the cesium bromide buffer layer can reduce the reflection and loss of electrons at the interface, improve the transmission efficiency, and thus improve the open circuit voltage. At the same time, it can alleviate the problem of stress concentration at the interface, which helps to improve the structural stability of the battery. After modification, electrons and holes are more easily separated and extracted at the interface, which effectively enhances the charge extraction efficiency.

[0104] The utility model performs scanning electron microscope tests on the perovskite light absorbing layer of the battery structure provided in Example 2 and Comparative Example 1, as shown in FIG. Figure 4 and Figure 5 As shown, compared with the battery structure of comparative example 1 without a buffer layer, embodiment 2 introduces a buffer layer to perform interface modification, so that the perovskite grains become larger, which is more conducive to the crystallization of the perovskite film.

[0105] The utility model performs steady-state fluorescence spectrum (PL) tests on the perovskite light-absorbing layer of the battery structure provided in Example 2 and Comparative Example 1, and the results are as follows: Figure 6 shown.

[0106] Depend on Figure 6 It can be seen that the PL peak after the buffer layer modification in Example 2 has a blue shift, indicating that the quality and crystallinity of the perovskite film have been improved, and the trap state has been effectively passivated. x When a film is formed on NiOx / CsBr, the PL peak decreases, indicating that it has a stronger PL quenching effect. It is not difficult to see that compared with the interface not modified with CsBr in Comparative Example 1, Example 2 is modified by introducing a buffer layer, so that the hole extraction rate of the NiOx / perovskite interface is faster.

[0107] The utility model stores the battery structure provided by Example 2 and Comparative Example 1 in air with a humidity of 30% ± 10%, and tests the photoelectric conversion efficiency when the storage time is 200h, 400h, 600h, 800h, 1000h, and 1200h respectively. The results are as follows: Figure 7 shown.

[0108] Depend on Figure 7 It can be observed that the battery structure of Example 2 still maintains an efficiency of more than 87% after being stored for 1000 hours, while the photoelectric conversion efficiency of the battery structure of Comparative Example 1 drops to 75% after being stored for 1000 hours, indicating that the introduction of the buffer layer can effectively improve the stability of the battery.

[0109] The applicant declares that the above is only a specific implementation method of the present utility model, but the protection scope of the present utility model is not limited thereto. The technicians in the relevant technical field should understand that any changes or substitutions that can be easily thought of by the technicians in the relevant technical field within the technical scope disclosed in the present utility model fall within the protection scope and disclosure scope of the present utility model.

Claims

1. A perovskite battery structure, characterized in that: The perovskite cell structure comprises a conductive substrate, on which a nickel oxide hole transport layer, a cesium bromide buffer layer, a perovskite light absorption layer, an electron transport layer and an electrode layer are sequentially stacked.

2. The perovskite battery structure according to claim 1, characterized in that: The thickness of the cesium bromide buffer layer is 1-8 nm.

3. The perovskite battery structure according to claim 1, characterized in that: The thickness of the nickel oxide hole transport layer is 10 to 15 nm; The thickness of the perovskite light absorbing layer is 350-600 nm; The thickness of the electron transport layer is 25 to 40 nm; The thickness of the electrode layer is 800-1000 nm.

4. The perovskite battery structure according to claim 1, characterized in that: The electron transport layer comprises a first electron transport layer and a second electron transport layer which are sequentially stacked from the perovskite light absorbing layer to the electrode layer; The thickness of the first electron transport layer is 15 to 25 nm; The thickness of the second electron transport layer is 10-15 nm.

5. The perovskite battery structure according to claim 4, characterized in that: The first electron transport layer is a C60 electron transport layer, and the second electron transport layer is a SnO2 electron transport layer.

6. A perovskite silicon ore stacked battery, characterized in that: The perovskite crystalline silicon ore stacked battery comprises a first battery layer and a second battery layer which are stacked, the first battery layer comprises the perovskite battery structure according to any one of claims 1 to 5, and the conductive substrate is connected to the second battery layer.

7. The perovskite crystalline silicon ore stacked cell according to claim 6, characterized in that: The second battery layer includes an N-type amorphous silicon layer, a first intrinsic amorphous silicon layer, a silicon wafer, a second intrinsic amorphous silicon layer, a P-type amorphous silicon layer and a back electrode layer which are sequentially stacked in a direction away from the first battery layer.

8. The perovskite crystalline silicon ore stacked cell according to claim 7, characterized in that: A first transparent conductive layer is arranged between the electrode layer and the electron transport layer of the first battery layer, and a second transparent conductive layer is arranged between the back electrode layer and the P-type amorphous silicon layer of the second battery layer.

9. The perovskite crystalline silicon ore stacked cell according to claim 8, characterized in that: The thickness of the back electrode layer is 800-1000 nm; The thickness of the first transparent conductive layer and the second transparent conductive layer are independently 100 to 130 nm.

10. The perovskite crystalline silicon ore stacked cell according to claim 6, characterized in that: The thickness of the conductive substrate is 20 to 30 nm; The conductive substrate includes a tunnel junction layer, a metal layer or a transparent electrode layer.

Images