Frequency multiplier circuit with adjustable duty ratio, integrated circuit and electronic equipment
The inverting unit and the pulse unit generate pulse signals aligned with the clock signal, and the frequency doubling unit generates a frequency doubling clock signal with adjustable duty cycles, solving the problem of high complexity of the phase-locked loop circuit and difficult to modulate the duty cycle. A simple and low-cost frequency multiplication clock signal output is realized.
Patent Information
- Application Number
- CN202420659731.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-01
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2034-04-01
AI Technical Summary
The existing clock signal frequency multiplication circuit requires a phase-locked loop structure, which makes it difficult to modulate the duty cycle of the frequency multiplication clock signal.
The inverting unit and the pulse unit are used to generate an upper pulse signal and a lower pulse signal based on the clock signal and the inverting signal. The frequency multiplication clock signal with adjustable duty cycle is generated through the frequency multiplication unit, which eliminates the phase-locked loop circuit structure.
The frequency multiplication clock signal output with adjustable duty cycle is realized, which simplifies the circuit structure, reduces the silicon wafer area and cost, and improves practicality.
Smart Images
Figure CN222234820U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of clock circuits, in particular to a frequency multiplication circuit with adjustable duty cycle, an integrated circuit and electronic equipment. Background Art
[0002] In the target integrated circuit system, it is often necessary to multiply the frequency of the clock signal, for example, to double the frequency of the input clock signal and provide it to the corresponding components.
[0003] At present, the conventional solution to achieve clock signal frequency multiplication is to use a phase-locked loop circuit, which has high speed and high precision performance. However, the phase-locked loop circuit structure requires many components, which is relatively complex to implement, consumes silicon chip area and cost, and the duty cycle of the generated frequency-multiplied clock signal is difficult to modulate. If it is necessary to generate a frequency-multiplied clock signal with a modulatable duty cycle, an additional circuit structure is required to achieve it, which further increases the overall complexity of the circuit structure as well as the silicon chip area and cost.
[0004] Therefore, there is an urgent need to propose a circuit structure that does not require a phase-locked loop circuit structure, is easier to implement, and generates a frequency-multiplied clock signal with an adjustable duty cycle. Utility Model Content
[0005] In view of the above problems, the utility model provides a frequency multiplication circuit, an integrated circuit and an electronic device with adjustable duty cycle, which better solve the above problems.
[0006] The embodiment of the utility model provides a frequency multiplication circuit with adjustable duty cycle, and the frequency multiplication circuit with adjustable duty cycle includes: an inverting unit, a pulse unit, and a frequency multiplication unit;
[0007] The inverting unit is electrically connected to the pulse unit, and the inverting unit is used to generate an inverted signal of the clock signal and output it to the pulse unit;
[0008] The pulse unit is electrically connected to the frequency multiplication unit, and the pulse unit is used to generate an up pulse signal and a down pulse signal based on the clock signal and the inverse signal, and output the up pulse signal and the down pulse signal to the frequency multiplication unit;
[0009] The frequency multiplication unit is used to generate a frequency multiplication clock signal with an adjustable duty cycle according to the upper pulse signal and the lower pulse signal;
[0010] The upper pulse signal is aligned with the rising edge of the clock signal and has a preset width, and the lower pulse signal is aligned with the falling edge of the clock signal and has the preset width.
[0011] Optionally, the pulse unit includes: a first pulse unit and a second pulse unit;
[0012] One end of the first pulse unit receives the clock signal, and the other end is electrically connected to the frequency multiplication unit, and the first pulse unit is used to generate the upper pulse signal based on the clock signal;
[0013] One end of the second pulse unit is electrically connected to the inverting unit to receive the inverted signal;
[0014] The other end of the second pulse unit is electrically connected to the frequency multiplication unit, and the second pulse unit is used to generate the lower pulse signal based on the inverted signal.
[0015] Optionally, the first pulse unit and the second pulse unit both include: an inversion structure, a signal structure, and a pulse structure;
[0016] The inversion structure is used to invert the received clock signal or the inverse signal to obtain two negative signals, one negative signal is output to the pulse structure, and the other negative signal is output to the signal structure;
[0017] The signal structure is used to generate a delayed signal according to the received non-signal and output it to the pulse structure;
[0018] The pulse structure is used to generate a pulse signal according to the non-signal and the delayed signal, and the pulse signal includes: the upper pulse signal and the lower pulse signal.
[0019] Optionally, the inversion structure includes: a first inverter and a second inverter; the signal structure includes: a first current source, a first control switch, and a capacitor; the pulse structure includes: a NOR gate;
[0020] The first end of the first inverter and the first end of the second inverter both receive the clock signal or the inverse signal, and the first inverter is used to invert the received clock signal or the inverse signal to obtain a first negation signal and output it to the first end of the NOR gate;
[0021] The second end of the first inverter is electrically connected to the first end of the NOR gate;
[0022] The second end of the second inverter is electrically connected to the control end of the first control switch, and the second inverter is used to invert the received clock signal or the inverse signal to obtain a second negation signal and output it to the control end of the first control switch;
[0023] The first end of the first control switch is electrically connected to the second end of the first current source, the first end of the capacitor, and the second end of the NOR gate, respectively, and the first control switch is used to open or close according to the second NOR signal;
[0024] A first end of the first current source receives a power supply voltage, and the first current source is used to charge the capacitor when the first control switch is disconnected, and to be grounded when the first control switch is closed;
[0025] The second end of the first control switch and the second end of the capacitor are both grounded, and the capacitor is used to receive charging and generate a delayed rising capacitor voltage when the first control switch is disconnected, and to discharge to the ground and generate a delayed falling capacitor voltage when the first control switch is closed, wherein the delayed rising capacitor voltage corresponds to the delayed rising delay signal, and the delayed falling capacitor voltage corresponds to the delayed falling delay signal;
[0026] The third end of the NOR gate is electrically connected to the frequency multiplication unit, and the NOR gate is used to generate the up pulse signal or the down pulse signal according to the first NOT signal and the delay signal.
[0027] Optionally, the preset width of the pulse signal is determined by the current of the first current source and the capacitance of the capacitor.
[0028] Optionally, the frequency multiplication unit includes: a voltage generation structure and a clock signal structure;
[0029] The voltage generating structure is used to generate different voltages according to the conditions of the up pulse signal and the down pulse signal and transmit them to the clock signal structure;
[0030] The clock signal generating structure is used to generate the frequency-multiplied clock signal with adjustable duty cycle according to the different voltages and the preset voltage.
[0031] Optionally, the voltage generation structure includes: a second current source, a second control switch, and a third control switch; the clock signal structure includes: a comparator;
[0032] A first end of the second current source receives a power supply voltage, a second end of the second current source is electrically connected to a first end of the second control switch, a first end of the third control switch, and a first end of the comparator, and the second current source is used to transmit the power supply voltage to the comparator when the second control switch and the third control switch are both disconnected, and to be grounded when either the second control switch or the third control switch is closed;
[0033] The control end of the second control switch is electrically connected to the first pulse unit, and the second control switch is used to open or close according to the condition of the upper pulse signal;
[0034] The control end of the third control switch is electrically connected to the second pulse unit, and the third control switch is used to open or close according to the condition of the lower pulse signal;
[0035] The second end of the second control switch and the second end of the third control switch are both grounded;
[0036] The second end of the comparator receives a preset voltage, and the third end outputs the duty cycle adjustable multiplied clock signal. The comparator is used to generate the duty cycle adjustable multiplied clock signal according to the power supply voltage and the preset voltage, and the preset voltage is less than the power supply voltage.
[0037] Optionally, the second control switch, the third control switch, and the first control switch in the pulse unit all include: N-type field effect transistors.
[0038] An embodiment of the utility model further provides an integrated circuit, comprising: a frequency multiplier circuit with adjustable duty cycle as described above, wherein the frequency multiplier circuit with adjustable duty cycle is used to generate the frequency multiplier clock signal with adjustable duty cycle.
[0039] The embodiment of the utility model further provides an electronic device, the electronic device comprising: a power receiving unit and the integrated circuit as described above;
[0040] The integrated circuit is used to provide a frequency-multiplied clock signal with an adjustable duty cycle to the power receiving unit.
[0041] The utility model provides a frequency multiplication circuit with adjustable duty cycle, comprising: an inverting unit, a pulse unit, and a frequency multiplication unit. The inverting unit is electrically connected to the pulse unit, and the inverting unit is used to generate an inverse signal of a clock signal and output it to the pulse unit; the pulse unit is electrically connected to the frequency multiplication unit, and the pulse unit generates an upper pulse signal and a lower pulse signal based on the clock signal and the inverse signal, and outputs them to the frequency multiplication unit.
[0042] The frequency multiplication unit is used to generate a frequency multiplication clock signal with adjustable duty cycle according to an upper pulse signal and a lower pulse signal, wherein the upper pulse signal is aligned with the rising edge of the clock signal and has a preset width, and the lower pulse signal is aligned with the falling edge of the clock signal and has a preset width.
[0043] The frequency multiplication circuit with adjustable duty cycle proposed in the utility model creatively eliminates the traditional phase-locked loop circuit structure. The pulse unit generates two pulse signals with preset widths aligned with the rising and falling edges of the clock signal based on the clock signal and the inverse signal of the clock signal, thereby generating a voltage that changes with the pulse signal. The frequency multiplication unit generates a frequency-multiplied clock signal by combining this voltage with the preset voltage. At the same time, the preset width of the pulse signal generated by the pulse unit can be adjusted to adjust the duty cycle of the output frequency-multiplied clock signal. Its overall structure is simpler than that of the traditional phase-locked loop circuit structure, and the silicon chip area and cost are relatively low, so it has high practicality. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] By reading the detailed description of the preferred embodiment below, various other advantages and benefits will become clear to those of ordinary skill in the art. The accompanying drawings are only used for the purpose of illustrating the preferred embodiment and are not considered to be limiting of the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:
[0045] Figure 1 It is an overall architecture diagram of a clock frequency multiplication circuit with adjustable duty cycle according to an embodiment of the utility model;
[0046] Figure 2 It is an overall architecture diagram of a clock frequency multiplication circuit with adjustable duty ratio including two pulse units in an embodiment of the utility model;
[0047] Figure 3 This is a circuit structure diagram of a preferred pulse unit in the embodiment of the utility model;
[0048] Figure 4 This is a circuit structure diagram of a better frequency multiplication unit in the embodiment of the utility model;
[0049] Figure 5 It is a timing diagram of a clock signal, an inverted signal, a first negative signal, a second negative signal, an up pulse signal, and a down pulse signal in an embodiment of the utility model. DETAILED DESCRIPTION
[0050] In order to make the above-mentioned purposes, features and advantages of the utility model more obvious and easy to understand, the utility model is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. It should be understood that the specific embodiments described here are only used to explain the utility model, are only part of the embodiments of the utility model, not all of the embodiments, and are not used to limit the utility model.
[0051] The duty cycle adjustable frequency multiplication circuit of the utility model refers to Figure 1 The overall structural schematic diagram shown includes: an inversion unit, a pulse unit, and a frequency doubling unit.
[0052] The inverting unit is electrically connected to the pulse unit, and the inverting unit is used to generate the inverse signal of the clock signal and output it to the pulse unit; the pulse unit is electrically connected to the frequency multiplication unit, and the pulse unit is used to generate an up pulse signal and a down pulse signal based on the clock signal and the inverse signal, and output them to the frequency multiplication unit. That is, the pulse unit not only receives the inverse signal of the clock signal, but also needs to receive the clock signal itself.
[0053] The frequency multiplication unit is used to generate a frequency multiplication clock signal with adjustable duty cycle according to an upper pulse signal and a lower pulse signal, wherein the upper pulse signal is aligned with the rising edge of the clock signal and has a preset width, and the lower pulse signal is aligned with the falling edge of the clock signal and has a preset width.
[0054] There are many ways to implement the pulse unit. In a preferred embodiment, the pulse unit includes: a first pulse unit and a second pulse unit; one end of the first pulse unit receives a clock signal, and the other end is electrically connected to the frequency multiplication unit. The first pulse unit is used to generate an upper pulse signal based on the clock signal, and the upper pulse signal is a pulse signal aligned with the rising edge of the clock signal and has a preset width.
[0055] One end of the second pulse unit is electrically connected to the inverting unit to receive the inverted signal; the other end of the second pulse unit is electrically connected to the frequency multiplication unit, and the second pulse unit is used to generate a lower pulse signal based on the inverted signal. The lower pulse signal is a pulse signal aligned with the falling edge of the clock signal and has a preset width. The architecture of the two pulse units can refer to Figure 2 shown.
[0056] For the specific first pulse unit and the second pulse unit, the structures of the two can be exactly the same or different, as long as the two can generate the above-mentioned upper pulse signal and lower pulse signal. In a preferred embodiment, the two have the same structure, and the first pulse unit and the second pulse unit both include: an inverting structure, a signal structure, and a pulse structure.
[0057] The inverting structure is used to invert the received clock signal or the inverse signal to obtain two negative signals, one of which is output to the pulse structure, and the other is output to the signal structure.
[0058] The signal structure is used to generate a delayed signal according to the received non-signal and output it to the pulse structure; the pulse structure receives two signals: a non-signal and a delayed signal, and is used to generate a pulse signal according to the non-signal and the delayed signal.
[0059] In order to understand the circuit structure of the pulse unit more clearly, refer to Figure 3 The circuit structure shown, Figure 3 A preferred circuit structure diagram of a pulse unit is shown in FIG. 1 using specific components as an example. It should be noted that: Figure 3The specific components and their connection structures are shown as examples, which does not mean that the pulse unit can only be of this structure and can only use these components. Based on the above description and the functions of each circuit shown, those skilled in the art can propose other circuit structures to achieve the corresponding functions through simple reasoning.
[0060] The inversion structure includes: a first inverter and a second inverter; the signal structure includes: a first current source, a first control switch, and a capacitor; and the pulse structure includes: a NOR gate. Figure 3 a first control switch as shown in FIG. 1 , and Figure 4 The second control switch and the third control switch shown in the figure are both shown by taking an N-type field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, abbreviated as MOSFET, often abbreviated as MOS tube, Chinese: Metal-Oxide Semiconductor Field Effect Transistor, abbreviated as MOSFET) as an example.
[0061] The first end of the first inverter and the first end of the second inverter both receive the clock signal or its inverse signal, and the first inverter is used to invert the received clock signal or its inverse signal to obtain a first negative signal and output it to the first end of the NOR gate. The second end of the first inverter is electrically connected to the first end of the NOR gate.
[0062] The second end of the second inverter is electrically connected to the control end of the first control switch, and the second inverter is used to invert the received clock signal or its inverse signal to obtain a second negative signal and output it to the control end of the first control switch (i.e., the gate end of the N-type field effect transistor).
[0063] The first end of the first control switch (i.e., the drain end of the N-type field effect transistor) is electrically connected to the second end of the first current source, the first end of the capacitor, and the second end of the NOR gate, respectively. The first control switch is used to open or close according to the situation of the second NOR signal.
[0064] A first terminal of the first current source receives a power supply voltage. The first current source is used to charge the capacitor when the first control switch is opened, and is grounded when the first control switch is closed.
[0065] The second end of the first control switch (i.e., the source end of the N-type field effect transistor) and the second end of the capacitor are both grounded. The capacitor is used to receive charge and generate a delayed rising capacitor voltage when the first control switch is disconnected, and to discharge to the ground and generate a delayed falling capacitor voltage when the first control switch is closed, wherein the delayed rising capacitor voltage corresponds to a delayed rising delay signal, and the delayed falling capacitor voltage corresponds to a delayed falling delay signal.
[0066] The third end of the NOR gate is electrically connected to the frequency multiplication unit, and the NOR gate is used to generate an up pulse signal or a down pulse signal according to the first NOT signal and a delay signal (a delayed rising delay signal or a delayed falling delay signal).
[0067] The first pulse unit receives a clock signal and generates an up pulse signal, and the second pulse unit receives an inverse signal of the clock signal and generates a down pulse signal. Regardless of the up pulse signal or the down pulse signal, the preset width is determined by the current of the first current source and the capacitance of the capacitor. The larger the current of the first current source and the smaller the capacitance of the capacitor, the smaller the preset width; the smaller the current of the first current source and the larger the capacitance of the capacitor, the larger the preset width. In actual applications, the specific width is determined based on the required duty cycle, and then the current of the first current source and the capacitance of the capacitor are inferred.
[0068] There are also multiple ways to implement the frequency multiplication unit. A preferred frequency multiplication unit includes: a voltage generation structure and a clock signal structure.
[0069] The voltage generating structure is used to generate different voltages according to the upper pulse signal and the lower pulse signal and transmit them to the clock signal structure; the clock signal generating structure is used to generate a frequency-multiplied clock signal with adjustable duty cycle according to different voltages and preset voltages.
[0070] In order to understand the circuit structure of the frequency multiplication unit more clearly, refer to Figure 4 The circuit structure shown, Figure 4 A preferred circuit structure diagram of a frequency multiplication unit is shown in FIG. 1 using specific components as an example. Figure 3 Same situation, Figure 4 The specific components and their connection structures are used as examples, which does not mean that the frequency multiplication unit can only be of this structure and can only use these components. Based on the above description and the functions of each circuit shown, those skilled in the art can propose other circuit structures to achieve the corresponding functions through simple reasoning.
[0071] Figure 4 In the embodiment, the voltage generating structure includes: a second current source, a second control switch, and a third control switch; and the clock signal structure includes: a comparator.
[0072] The first end of the second current source receives the power supply voltage, and the second end of the second current source is electrically connected to the first end of the second control switch (i.e., the drain end of the N-type field effect transistor), the first end of the third control switch (i.e., the drain end of the N-type field effect transistor), and the first end of the comparator (i.e., the inverting end of the comparator). The second current source is used to transmit the power supply voltage to the comparator when the second control switch and the third control switch are both disconnected, and to be grounded when either the second control switch or the third control switch is closed.
[0073] The control end of the second control switch (i.e., the gate end of the N-type field effect transistor) is electrically connected to the first pulse unit, that is, it receives the upper pulse signal, and the second control switch is used to open or close according to the situation of the upper pulse signal; the control end of the third control switch (i.e., the gate end of the N-type field effect transistor) is electrically connected to the second pulse unit, that is, it receives the lower pulse signal, and the third control switch is used to open or close according to the situation of the lower pulse signal.
[0074] The second end of the second control switch (ie, the source end of the N-type field effect transistor) and the second end of the third control switch (ie, the source end of the N-type field effect transistor) are both grounded.
[0075] The second end of the comparator (i.e., the in-phase end of the comparator) receives a preset voltage, and the third end (i.e., the output end of the comparator) outputs a double-frequency clock signal with an adjustable duty cycle. The comparator is used to generate a double-frequency clock signal with an adjustable duty cycle according to the power supply voltage and the preset voltage, and the preset voltage is less than the power supply voltage. For example: the preset voltage is half of the power supply voltage, that is, the preset voltage = power supply voltage / 2, then the comparator outputs a 2-fold clock signal with an adjustable duty cycle.
[0076] The working principle of the clock frequency multiplication circuit with adjustable duty cycle proposed in the utility model is combined with Figure 5 The timing diagram of the clock signal, the anti-signal, the first non-signal, the second non-signal, the upper pulse signal, the lower pulse signal, and the frequency-multiplied clock signal shown in the figure, taking the rising edge of a clock signal cycle as an example, can be understood as follows: at the beginning of the rising edge, the NOR gate in the first pulse unit receives the first non-signal as a low level, and at the same time, the second non-signal low level causes the first control switch in the first pulse unit to be disconnected, and the first current source begins to charge the capacitor, which generates a delayed rising capacitor voltage. Before the capacitor voltage rises to a certain voltage value, it can be considered that the corresponding delay signal is also a low level at this time, then the NOR gate receives the low-level delay signal, and its output is a high level, that is, the upper pulse signal is a high level. The width of the upper pulse signal is from the beginning of the rising edge until the capacitor voltage rises to a certain voltage value. It can be considered that the corresponding delay signal becomes a high level at this time, then the NOR gate receives the high-level delay signal, and its output becomes a low level, that is, the upper pulse signal becomes a low level.
[0077] During the period from the rising edge to the falling edge in this cycle, due to the existence of the inverting unit, the second pulse unit receives the inverse signal of the clock signal, which is a low level, and the NOR gate in the first pulse unit receives the first non-signal as a high level. At the same time, the high level of the second non-signal causes the first control switch in the second pulse unit to close, the first current source to ground, and the capacitor to discharge, which generates a delayed falling capacitor voltage. However, no matter whether the capacitor voltage is discharged to a certain voltage value or to 0, the corresponding delay signal changes from a high level to a low level, which does not affect the NOR gate to always output a low level, that is, the lower pulse signal is always a low level and will not be a high level.
[0078] At the beginning of the falling edge of the cycle, due to the existence of the inverting unit, the inverting signal received by the second pulse unit is at a high level, then the NOR gate in the second unit receives the first non-signal as a low level, and at the same time, the low level of the second non-signal causes the first control switch in the second pulse unit to be disconnected, and the first current source begins to charge the capacitor, which generates a delayed rising capacitor voltage. Before the capacitor voltage rises to a certain voltage value, it can be considered that the corresponding delay signal is also at a low level at this time, then the NOR gate receives the low-level delay signal, and its output is high level, that is, the lower pulse signal is high level. The width of the lower pulse signal is from the beginning of the upper falling edge until the capacitor voltage rises to a certain voltage value. It can be considered that the corresponding delay signal becomes high level at this time, then the NOR gate receives the high-level delay signal, and its output becomes low level, that is, the lower pulse signal becomes low level.
[0079] During the period from the falling edge of the cycle to the rising edge of the next cycle, since the first pulse unit is the received clock signal and the circuit structure of the first pulse unit is exactly the same as the circuit structure of the second pulse unit, it can be concluded based on the above similar reasoning that during this period, the upper pulse signal is always at a low level and will not be at a high level.
[0080] During the period when either the upper pulse signal or the lower pulse signal is at a high level, the second control switch or the third control switch in the frequency multiplication unit will be closed, the current of the second current source will flow directly to the ground, and the voltage at the inverting end of the comparator will be 0, which is definitely lower than the preset voltage at the in-phase end, so the comparator outputs a clock signal. During the period when both the upper pulse signal and the lower pulse signal are at a low level, the second control switch and the third control switch in the frequency multiplication unit are both disconnected, and the current of the second current source is directly transmitted to the inverting end of the comparator. The voltage at the inverting end of the comparator is the power supply voltage. Since the preset voltage is less than the power supply voltage, the voltage at the inverting end of the comparator must be higher than the preset voltage at the in-phase end, and the comparator does not output a clock signal. Through such a working principle, the frequency multiplication of the clock signal is realized, and at the same time, the duty cycle of the output clock signal is controlled by the preset bandwidth of the upper pulse signal and the lower pulse signal, that is, its duty cycle can be modulated, and finally a frequency multiplication clock signal with adjustable duty cycle is obtained.
[0081] Through the above circuit structure, the traditional phase-locked loop circuit structure is no longer used, but the inverting unit is used to generate the inverse signal of the clock signal, and then the pulse unit generates two pulse signals with preset widths aligned with the rising edge and falling edge of the clock signal based on the clock signal and the inverse signal of the clock signal. The two pulse signals control the voltage transmitted to the signal structure, and the changing voltage and the preset voltage use the signal structure to generate a multiplied clock signal, and because the preset width of the pulse signal can be modulated, the duty cycle of the output multiplied clock signal can also be modulated. The components used in the entire circuit are relatively fewer than those in the phase-locked loop circuit structure, the circuit structure is relatively simple, and the silicon chip area and cost are relatively low.
[0082] Based on the above-mentioned clock multiplier circuit with adjustable duty cycle, an embodiment of the utility model further proposes an integrated circuit, which includes: a clock multiplier circuit with adjustable duty cycle as described above; the clock multiplier circuit with adjustable duty cycle can generate a multiplied clock signal with adjustable duty cycle.
[0083] Based on the above-mentioned clock multiplication circuit with adjustable duty cycle, an embodiment of the utility model further proposes an electronic device, which includes: a power receiving unit and the above-mentioned integrated circuit; the integrated circuit is used to provide a multiplication clock signal with adjustable duty cycle to the power receiving unit.
[0084] In summary, the duty cycle adjustable frequency multiplication circuit of the utility model comprises: an inverting unit, a pulse unit, and a frequency multiplication unit. The inverting unit is electrically connected to the pulse unit, and the inverting unit is used to generate an inverse signal of the clock signal and output it to the pulse unit; the pulse unit is electrically connected to the frequency multiplication unit, and the pulse unit generates an upper pulse signal and a lower pulse signal based on the clock signal and the inverse signal, and outputs them to the frequency multiplication unit.
[0085] The frequency multiplication unit is used to generate a frequency multiplication clock signal with adjustable duty cycle according to an upper pulse signal and a lower pulse signal, wherein the upper pulse signal is aligned with the rising edge of the clock signal and has a preset width, and the lower pulse signal is aligned with the falling edge of the clock signal and has a preset width.
[0086] The duty cycle adjustable frequency multiplication circuit proposed in the utility model creatively eliminates the traditional phase-locked loop circuit structure, and instead uses an inverting unit to generate an inverse signal of a clock signal, and then a pulse unit generates two pulse signals aligned with the rising edge and the falling edge of the clock signal and having a preset width based on the clock signal and the inverse signal of the clock signal. The two pulse signals control the voltage transmitted to the signal structure, and the changing voltage and the preset voltage use the signal structure to generate a frequency-multiplied clock signal, and because the preset width of the pulse signal can be modulated, the duty cycle of the output frequency-multiplied clock signal can also be modulated. The entire circuit uses fewer components than the phase-locked loop circuit structure, the circuit structure is relatively simple, the silicon chip area and cost are relatively low, and it has high practicality.
[0087] Although the preferred embodiments of the utility model embodiments have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the utility model embodiments.
[0088] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.
[0089] The embodiments of the present invention are described above in conjunction with the accompanying drawings and introduced in detail. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.
Claims
1. A frequency multiplication circuit with adjustable duty cycle, characterized in that: The frequency multiplication circuit with adjustable duty cycle comprises: an inversion unit, a pulse unit, and a frequency multiplication unit; The inverting unit is electrically connected to the pulse unit, and the inverting unit is used to generate an inverted signal of the clock signal and output it to the pulse unit; The pulse unit is electrically connected to the frequency multiplication unit, and the pulse unit is used to generate an up pulse signal and a down pulse signal based on the clock signal and the inverse signal, and output the up pulse signal and the down pulse signal to the frequency multiplication unit; The frequency multiplication unit is used to generate a frequency multiplication clock signal with an adjustable duty cycle according to the upper pulse signal and the lower pulse signal; The upper pulse signal is aligned with the rising edge of the clock signal and has a preset width, and the lower pulse signal is aligned with the falling edge of the clock signal and has the preset width.
2. The frequency multiplication circuit with adjustable duty cycle according to claim 1, characterized in that: The pulse unit comprises: a first pulse unit and a second pulse unit; One end of the first pulse unit receives the clock signal, and the other end is electrically connected to the frequency multiplication unit, and the first pulse unit is used to generate the upper pulse signal based on the clock signal; One end of the second pulse unit is electrically connected to the inverting unit to receive the inverted signal; The other end of the second pulse unit is electrically connected to the frequency multiplication unit, and the second pulse unit is used to generate the lower pulse signal based on the inverted signal.
3. The frequency multiplication circuit with adjustable duty cycle according to claim 2, characterized in that: The first pulse unit and the second pulse unit both include: an inversion structure, a signal structure, and a pulse structure; The inversion structure is used to invert the received clock signal or the inverse signal to obtain two negative signals, one negative signal is output to the pulse structure, and the other negative signal is output to the signal structure; The signal structure is used to generate a delayed signal according to the received non-signal and output it to the pulse structure; The pulse structure is used to generate a pulse signal according to the non-signal and the delayed signal, and the pulse signal includes: the upper pulse signal and the lower pulse signal.
4. The frequency multiplication circuit with adjustable duty cycle according to claim 3, characterized in that: The inversion structure includes: a first inverter and a second inverter; the signal structure includes: a first current source, a first control switch, and a capacitor; the pulse structure includes: a NOR gate; The first end of the first inverter and the first end of the second inverter both receive the clock signal or the inverse signal, and the first inverter is used to invert the received clock signal or the inverse signal to obtain a first negation signal and output it to the first end of the NOR gate; The second end of the first inverter is electrically connected to the first end of the NOR gate; The second end of the second inverter is electrically connected to the control end of the first control switch, and the second inverter is used to invert the received clock signal or the inverse signal to obtain a second negation signal and output it to the control end of the first control switch; The first end of the first control switch is electrically connected to the second end of the first current source, the first end of the capacitor, and the second end of the NOR gate, respectively, and the first control switch is used to open or close according to the second NOR signal; A first end of the first current source receives a power supply voltage, and the first current source is used to charge the capacitor when the first control switch is disconnected, and to be grounded when the first control switch is closed; The second end of the first control switch and the second end of the capacitor are both grounded, and the capacitor is used to receive charging and generate a delayed rising capacitor voltage when the first control switch is disconnected, and to discharge to the ground and generate a delayed falling capacitor voltage when the first control switch is closed, wherein the delayed rising capacitor voltage corresponds to the delayed rising delay signal, and the delayed falling capacitor voltage corresponds to the delayed falling delay signal; The third end of the NOR gate is electrically connected to the frequency multiplication unit, and the NOR gate is used to generate the up pulse signal or the down pulse signal according to the first NOT signal and the delay signal.
5. The frequency multiplication circuit with adjustable duty cycle according to claim 4, characterized in that: The preset width of the pulse signal is determined by the current of the first current source and the capacitance of the capacitor.
6. The frequency multiplication circuit with adjustable duty cycle according to claim 2, characterized in that: The frequency multiplication unit comprises: a voltage generation structure and a clock signal structure; The voltage generating structure is used to generate different voltages according to the conditions of the up pulse signal and the down pulse signal and transmit them to the clock signal structure; The clock signal generating structure is used to generate the frequency-multiplied clock signal with adjustable duty cycle according to the different voltages and the preset voltage.
7. The frequency multiplication circuit with adjustable duty cycle according to claim 6, characterized in that: The voltage generation structure includes: a second current source, a second control switch, and a third control switch; the clock signal structure includes: a comparator; A first end of the second current source receives a power supply voltage, a second end of the second current source is electrically connected to a first end of the second control switch, a first end of the third control switch, and a first end of the comparator, and the second current source is used to transmit the power supply voltage to the comparator when the second control switch and the third control switch are both disconnected, and to be grounded when either the second control switch or the third control switch is closed; The control end of the second control switch is electrically connected to the first pulse unit, and the second control switch is used to open or close according to the condition of the upper pulse signal; The control end of the third control switch is electrically connected to the second pulse unit, and the third control switch is used to open or close according to the condition of the lower pulse signal; The second end of the second control switch and the second end of the third control switch are both grounded; The second end of the comparator receives a preset voltage, and the third end outputs the duty cycle adjustable multiplied clock signal. The comparator is used to generate the duty cycle adjustable multiplied clock signal according to the power supply voltage and the preset voltage, and the preset voltage is less than the power supply voltage.
8. The frequency multiplication circuit with adjustable duty cycle according to claim 7, characterized in that: The second control switch, the third control switch, and the first control switch in the pulse unit all include: an N-type field effect transistor.
9. An integrated circuit, characterized in that: The integrated circuit comprises: a frequency multiplier circuit with adjustable duty cycle as described in any one of claims 1 to 8, wherein the frequency multiplier circuit with adjustable duty cycle is used to generate the frequency multiplier clock signal with adjustable duty cycle.
10. An electronic device, characterized in that: The electronic device comprises: a power receiving unit and the integrated circuit as claimed in claim 9; The integrated circuit is used to provide a frequency-multiplied clock signal with an adjustable duty cycle to the power receiving unit.