Digital phase-locked loop circuit

Abstract

A digital phase-locked loop (PLL) circuit is provided, comprising: a synchronization control module configured to generate an input characterization signal representing the periodic change of the input periodic signal relative to the base clock signal based on a base clock signal and an input periodic signal; a counting control module configured to generate a clock counting result representing the multiple relationship between the period of the input characterization signal and the period of the base clock signal based on the base clock signal and the input characterization signal; an arithmetic control module configured to generate a base clock control variable based on a preset multiplication factor between the frequency of the output clock signal and the frequency of the input periodic signal, and to generate an output clock control variable based on the clock counting result; and an output control module configured to generate an output control signal based on the base clock control variable and the output clock control variable, and to generate an output clock signal based on the output control signal and the base clock signal.

Description

Technical Field

[0001] This invention relates to the field of circuits, and more specifically to a digital phase-locked loop circuit. Background Technology

[0002] A phase-locked loop (PLL) circuit is a common circuit that can be used to generate an output clock signal that is synchronized with the input periodic signal (in both frequency and phase). Figure 1 A schematic block diagram of a traditional analog phase-locked loop circuit is shown. (For example...) Figure 1 As shown, the analog phase-locked loop circuit consists of three parts: a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). When the frequency of the input periodic signal Sin changes, the loop filter cannot quickly adjust the voltage supplied to the VCO in response to the frequency change of the input periodic signal Sin. As a result, the frequency of the output clock signal Sout generated by the VCO will oscillate significantly and requires a long adjustment time to synchronize with the frequency of the input periodic signal Sin. In addition, due to the limitations of the loop filter's filtering parameters, the analog phase-locked loop circuit is not suitable for situations where the frequency range of the input periodic signal is wide. Summary of the Invention

[0003] A digital phase-locked loop circuit according to an embodiment of the present invention includes: a synchronization control module configured to generate an input characterization signal representing the periodic change of the input periodic signal relative to the base clock signal based on a base clock signal and an input periodic signal; a counting control module configured to generate a clock counting result representing the multiple relationship between the period of the input characterization signal and the period of the base clock signal based on the base clock signal and the input characterization signal; an arithmetic control module configured to generate a base clock control variable based on a preset multiplication factor between the frequency of the output clock signal and the frequency of the input periodic signal, and to generate an output clock control variable based on the clock counting result; and an output control module configured to generate an output control signal based on the base clock control variable and the output clock control variable, and to generate an output clock signal based on the output control signal and the base clock signal.

[0004] The digital phase-locked loop circuit according to the present invention can achieve synchronization between the output clock signal and the input periodic signal (synchronization in both frequency and phase) with a much shorter adjustment time than the analog phase-locked loop circuit, and does not have the loop oscillation problem of the analog phase-locked loop circuit. Attached Figure Description

[0005] The invention can be better understood from the following description of specific embodiments of the invention in conjunction with the accompanying drawings, wherein:

[0006] Figure 1 A schematic block diagram of a traditional analog phase-locked loop circuit is shown.

[0007] Figure 2 A schematic block diagram of a digital phase-locked loop circuit according to an embodiment of the present invention is shown.

[0008] Figure 3 It shows Figure 2 The diagram shows an example implementation of the synchronization control module.

[0009] Figure 4 It shows the relationship with Figure 3 The waveform diagrams of multiple signals related to the synchronization control module are shown below;

[0010] Figure 5 It shows Figure 2 The diagram shows an example implementation of the counting control module.

[0011] Figure 6 It shows Figure 2 The diagram shows a partial example implementation of the operation control module.

[0012] Figure 7 It shows Figure 2 The diagram shows a partial example implementation of the operation control module.

[0013] Figure 8 It shows Figure 2 The diagram shows an example implementation of the output control module.

[0014] Figure 9 A control flowchart of a digital phase-locked loop circuit according to an embodiment of the present invention is shown;

[0015] Figure 10 It shows the relationship with Figure 8 The waveform diagrams shown are of several signals related to the output control module. Detailed Implementation

[0016] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention. The invention is by no means limited to any specific configurations and algorithms presented below, but covers any modifications, substitutions, and improvements to elements, components, and algorithms without departing from the spirit of the invention. Well-known structures and techniques are not shown in the drawings and the following description in order to avoid unnecessarily obscuring the invention.

[0017] In view of one or more problems existing in traditional analog phase-locked loop circuits, a digital phase-locked loop circuit is proposed, which can achieve fast phase-locked control through digital calculation, and can improve the signal frequency range of the phase-locked loop circuit and greatly reduce the circuit complexity of the phase-locked loop circuit.

[0018] Figure 2 A schematic block diagram of a digital phase-locked loop circuit 200 according to an embodiment of the present invention is shown. Figure 2 As shown, the digital phase-locked loop circuit 200 includes a synchronization control module 202, a counting control module 204, an arithmetic control module 206, and an output control module 208. Specifically: the synchronization control module 202 is configured to generate an input characterization signal Sin_start, representing the periodic change of the input periodic signal Sin relative to the base clock signal OSC_CLK, based on the base clock signal OSC_CLK and the input periodic signal Sin; the counting control module 204 is configured to generate a characterization signal Sin_start, representing the period between the period of the input characterization signal Sin_start and the period of the base clock signal OSC_CLK, based on the base clock signal OSC_CLK and the input characterization signal Sin_start. The clock counting result Nsin is a multiple of the frequency; the operation control module 206 is configured to generate a basic clock control variable OSC_SUM based on a preset multiplication factor Nset between the frequency of the output clock signal DPLL_CLK and the frequency of the input periodic signal Sin, and to generate an output clock control variable DPLL_SUM based on the clock counting result Nsin; the output control module 208 is configured to generate an output control signal DPLL_PASS based on the basic clock control variable OSC_SUM and the output clock control variable DPLL_SUM, and to generate an output clock signal DPLL_CLK based on the output control signal DPLL_PASS and the basic clock signal OSC_CLK.

[0019] Here, we assume that the frequency of the base clock signal OSC_CLK is Fosc, the frequency of the input periodic signal Sin is Fin, and the frequency of the output clock signal DPLL_CLK is Fout = Nset × Fin. The base clock signal OSC_CLK is usually a high-frequency clock signal (e.g., a high-frequency oscillation signal) with a frequency much higher than that of the input periodic signal.

[0020] Figure 3 It shows Figure 2 The diagram shows an example implementation of the synchronization control module 202. Figure 2As shown, in some embodiments, the synchronization control module 202 may be further configured to: generate a first characterization signal Q1 using a D flip-flop T1 based on the falling edge of the base clock signal OSC_CLK and the input period signal Sin; generate a second characterization signal Q2 using a D flip-flop T2 based on the falling edge of the base clock signal OSC_CLK and the first characterization signal Q1; and generate an input characterization signal Sin_start using an AND gate AND1 based on the inverted signal of the second characterization signal Q2 and the first characterization signal Q1.

[0021] Figure 4 It shows the relationship with Figure 3 The diagram shows waveforms of multiple signals related to the synchronization control module 202. It should be noted that... Figure 4 The waveform shown is Figure 3 The waveform diagram shown is generated by the synchronization control module 202 with the rising edge of the input periodic signal Sin as the valid edge and the falling edge of the basic clock signal OSC_CLK as the valid edge.

[0022] Figure 5 It shows Figure 2 The diagram shows an example implementation of the counting control module 204. Figure 5 As shown, in some embodiments, the counting control module 204 may be further configured to: count the number of cycles of the basic clock signal OSC_CLK using a clock counter when the input characterization signal Sin_start is at an inactive level (e.g., low level); and update the clock counter to the clock count result Nsin and clear the clock counter when the input characterization signal Sin_start is at an active level (e.g., high level).

[0023] Specifically, in Figure 5 In the example implementation of the counting control module 204 shown, a 2-way selector U1, a D flip-flop T3, and an adder (+1 operation) constitute a clock counter. The input characterization signal Sin_start is used as the output control signal of the 2-way selector U1. When the input characterization signal Sin_start is logic 0, it is the signal received at output terminal 0 of the 2-way selector U1. When the input characterization signal Sin_start is logic 1, it is the signal received at output terminal 1 of the 2-way selector U1. A 2-way selector U2 and a D flip-flop T4 constitute a counting output device, used to update the clock counter's counting result to the clock counting result Nsin and output it externally. The input characterization signal Sin_start is used as the output control signal of the 2-way selector U2. When the input characterization signal Sin_start is logic 0, it is the signal received at output terminal 0 of the 2-way selector U2. When the input characterization signal Sin_start is logic 1, it is the signal received at output terminal 1 of the 2-way selector U2.

[0024] Figure 6 It shows Figure 2 The diagram shows a partial example implementation of the arithmetic control module 206. (See attached diagram.) Figure 6 As shown, in some embodiments, the operation control module 206 can be further configured to: initialize the basic clock control variable OSC_SUM based on a preset multiplication factor Nset between the frequency Fout of the output clock signal DPLL_CLK and the frequency Fin of the input period signal Sin when the input characterization signal Sin_start is at an active level (e.g., high level). For example, the value of the basic clock control variable OSC_SUM can be initialized to OSC. SUM =1.5×N set .

[0025] like Figure 6 As shown, in some embodiments, the operation control module 206 can be further configured to: update the basic clock control variable OSC_SUM based on a preset multiplication factor Nset between the frequency Fout of the output clock signal DPLL_CLK and the frequency Fin of the input periodic signal Sin when the input characterization signal Sin_start is at an inactive level (e.g., low level). For example, the updated variable value of the basic clock control variable OSC_SUM can be calculated based on the variable value updated when the previous valid edge of the basic clock signal OSC_CLK arrives and the preset multiplication factor Nset between the frequency Fout of the output clock signal DPLL_CLK and the frequency Fin of the input periodic signal Sin, and the calculated updated variable value can be used to update the basic clock control variable OSC_SUM when the current valid edge of the basic clock signal OSC_CLK arrives. For example, the variable value of the basic clock control variable OSC_SUM can be updated to OSC_SUM = OSC_SUM + N. Set .

[0026] Specifically, in Figure 6In a partial example implementation of the arithmetic control module 206 shown, a 2-way selector U3, a D flip-flop T5, and an adder (+Nset operation) constitute the first arithmetic unit, used to initialize and update the basic clock control variable OSC_SUM. The input characterization signal Sin_start is used as the output control signal of the 2-way selector U3. When the input characterization signal Sin_start is logic 0, the signal received at output terminal 0 of the 2-way selector U3 is (i.e., the sum of the variable value of the basic clock control variable OSC_SUM updated at the previous valid edge of the basic clock signal OSC_CLK and the preset multiplication factor Nset). When the input characterization signal Sin_start is logic 1, the signal received at output terminal 1 of the 2-way selector U3 is (i.e., 1.5*Nset).

[0027] Figure 7 It shows Figure 2 The diagram shows a partial example implementation of the arithmetic control module 206. (See attached diagram.) Figure 7 As shown, in some embodiments, the operation control module 206 can be further configured to initialize the output clock control variable DPLL_SUM based on the clock counting result Nsin when the input characterization signal Sin_start is at an active level (e.g., high level). For example, the value of the output clock control variable DPLL_SUM can be initialized to DPLL_SUM = Nsin. Sin .

[0028] like Figure 7 As shown, in some embodiments, the operation control module 206 can be further configured to update the output clock control variable DPLL_SUM based on the clock count result Nsin when the input characterization signal Sin_start is at an inactive level (e.g., low level). For example, the updated variable value of the output clock control variable DPLL_SUM can be calculated based on the variable value updated by the output clock control variable DPLL_SUM at the previous valid edge of the base clock signal OSC_CLK, the clock count result Nsin, and the output control signal DPLL_PASS. The calculated updated variable value is then used to update the output clock control variable DPLL_SUM at the current valid edge of the base clock signal OSC_CLK. The output control signal DPLL_PASS characterizes the magnitude comparison between the variable values ​​updated by the base clock control variable OSC_SUM and the output clock control variable DPLL_SUM at the previous valid edge of the base clock signal. For example, the variable value of the output clock control variable DPLL_SUM can be updated to DPLL_SUM = DPLL_SUM + DPLL_PASS * N. Sin .

[0029] Specifically, in Figure 7 In a partial example implementation of the arithmetic control module 206 shown, the two-way selectors U4 and U5, the D flip-flop T6, and the adder constitute the second arithmetic unit, used to initialize and update the output clock control variable DPLL_SUM. The output control signal DPLL_PASS is used as the output control signal for the two-way selector U4. When the output control signal DPLL_PASS is logic 0, the signal received at output terminal 0 of the two-way selector U4 is logic 0; when the output control signal DPLL_PASS is logic 1, the signal received at output terminal 1 of the two-way selector U4 is logic 1. The clock count result Nsin), the input characterization signal Sin_start is used as the output control signal of the 2-way selector U5. When the input characterization signal Sin_start is logic 0, the signal received at output terminal 0 of the 2-way selector U5 is (i.e., the result of adding the value of the output clock control variable DPLL_SUM updated at the previous valid edge of the base clock signal OSC_CLK with the output signal of the 2-way selector U4). When the input characterization signal Sin_start is logic 1, the signal received at output terminal 1 of the 2-way selector U5 is (i.e., the clock count result Nsin).

[0030] Figure 8 It shows Figure 2 The diagram shows an example implementation of the output control module 208. Figure 8 As shown, in some embodiments, the output control module 208 can be further configured to: generate a variable comparison signal SUM_COMP using a comparator based on the base clock control variable OSC_SUM and the output clock control variable DPLL_SUM; generate an output control signal DPLL_PASS using a D flip-flop T7 based on the falling edge of the base clock signal OSC_CLK and the variable comparison signal SUM_COMP; and generate an output clock signal DPLL_CLK using an AND gate AND2 based on the base clock signal OSC_CLK and the output control signal DPLL_PASS. Here, when the base clock control variable OSC_SUM is greater than the output clock control variable DPLL_SUM, the output control signal DPLL_PASS is logic 1, and the next pulse of the output base clock signal OSC_CLK is used as one pulse of the output clock signal DPLL_CLK; when the base clock control variable OSC_SUM is not greater than the output clock control variable DPLL_SUM, the output control signal SUM_COMP is logic 0, and the output clock signal DPLL_CLK is logic 0.

[0031] In some embodiments, the counting control module 204 and the arithmetic control module 206 take the rising edge of the base clock signal OSC_CLK as the valid edge, and the synchronization control module 202 and the output control module 208 take the falling edge of the base clock signal OSC_CLK as the valid edge; alternatively, the counting control module 204 and the arithmetic control module 206 take the falling edge of the base clock signal OSC_CLK as the valid edge, and the synchronization control module 202 and the output control module 208 take the rising edge of the base clock signal OSC_CLK as the valid edge.

[0032] Figure 9 A control flowchart of a digital phase-locked loop circuit according to an embodiment of the present invention is shown. Figure 9 As shown, the control flow of the digital phase-locked loop circuit according to an embodiment of the present invention includes: when the effective edge of the base clock signal OSC_CLK arrives, determining whether the effective edge of the input period signal Sin has arrived (i.e., whether the input characterization signal Sin_start is at an effective level (e.g., high level)); when the effective edge of the input period signal Sin arrives (i.e., when the input characterization signal Sin_start is at an effective level), updating the clock count result Nsin, clearing the clock counter, initializing the output clock control variable DPLL_SUM, and initializing the base clock control variable OSC_SUM; when the effective edge of the input period signal Sin does not arrive (i.e., when the input characterization signal Sin_start is at an ineffective level (e.g., low level)), the clock counter stops counting. Increment the count by 1, accumulating the output clock control variable DPLL_SUM and the base clock control variable OSC_SUM; determine if the base clock control variable OSC_SUM is greater than the output clock control variable DPLL_SUM; if the base clock control variable OSC_SUM is greater than the output clock control variable DPLL_SUM, then the output control signal DPLL_PASS is logic 1, and the next pulse of the output base clock signal OSC_CLK is used as the output clock signal DPLL_CLK; if the base clock control variable OSC_SUM is not greater than the output clock control variable DPLL_SUM, then the output control signal DPLL_PASS is logic 0, and the next pulse of the base clock signal OSC_CLK is masked, i.e., the output clock signal DPLL_CLK is logic 0. Here, the steps in box 1 correspond to the rising edge of the base clock signal OSC_CLK, and the steps in box 2 correspond to the falling edge of the base clock signal OSC_CLK.

[0033] Figure 10 It shows the relationship with Figure 8 The diagram shows waveforms of multiple signals related to the output control module 208. Specifically, Figure 10The following example illustrates waveforms of multiple signals associated with the output control module 208: Based on a 10MHz base clock signal OSC_CLK and a 1kHz input periodic signal Sin, an output clock signal DPLL_CLK is generated with a frequency 3000 times that of the input periodic signal Sin; the clock count result Nsin is 10,000, and the preset multiplication factor Nset between the frequency of the output clock signal DPLL_CLK and the frequency of the input periodic signal Sin is 3,000; when the rising edge of the input periodic signal Sin arrives (i.e., Sin_start is at...), the output clock signal DPLL_CLK is generated with a frequency 3000 times that of the input periodic signal Sin. When the active level is active, the base clock control variable OSC_SUM and the output clock control variable DPLL_SUM are initialized to 4500 (1.5Nset) and 10,000 (Nsin) respectively at the rising edge of the base clock signal OSC_CLK. The output control signal DPLL_PASS is updated to logic 0 at the falling edge of the base clock signal OSC_CLK, masking the next pulse of the base clock signal OSC_CLK, and so on. The subsequent correspondence between the base clock control signal OSC_CLK and the output clock signal DPLL_CLK is as follows:

[0034] Table 1 Examples of Novel Digital Phase-Locked Loops

[0035]

[0036] from Figure 10 It can be seen that the output clock signal DPLL_CLK is synchronized with the clock edge of the base clock signal OSC_CLK. Since the frequency of the base clock signal OSC_CLK (10MHz) and the frequency of the output clock signal DPLL_CLK (3MHz) are not integer multiples of each other, the output clock signal DPLL_CLK is not uniformly distributed. Its maximum counting / timing deviation is 0.5 cycles (50ns) of the base clock signal OSC_CLK. Over a long period, when the output clock signal DPLL_CLK is used for counting and timing functions, the error is 50ns / 1s (5 / 100 million) per second and 50ns / 1ms (0.05 / 10,000) per second. These errors are almost negligible, and their error can be further reduced by increasing the frequency of the base clock signal OSC_CLK.

[0037] The following is a mathematical derivation of the effects achieved by the digital phase-locked loop circuit according to an embodiment of the present invention:

[0038] Assuming that when the input characterization signal Sin_start is at an active level, any rising edge of the output clock signal DPLL_CLK is the Nth... DPLLThe rising edge, and the Nth rising edge of the base clock signal OSC_CLK corresponding to the output clock signal DPLL_CLK. DPLL The rising edge of the Nth rising edge is the rising edge of the Nth rising edge. OSC One rising edge.

[0039] When the Nth time of the base clock signal OSC_CLK OSC When the rising edge arrives, the base clock control variable OSC_SUM will output the following calculated updated variable value:

[0040]

[0041] When the Nth time of the base clock signal OSC_CLK OSC When the rising edge arrives, the output clock control variable DPLL_SUM will output the following calculated updated variable value:

[0042]

[0043] As can be seen from the working mechanism of the digital phase-locked loop circuit according to the embodiments of the present invention:

[0044]

[0045] Combining (1), (2), and (3), we can obtain:

[0046]

[0047] That is, the Nth time of the output clock signal DPLL_CLK DPLL The pulse needs to be in the first pulse of the base clock signal OSC_CLK. The pulse is generated at time N. OSC To The result after rounding.

[0048] Continuing with the example above:

[0049] Theoretically, the first pulse of the output clock signal DPLL_CLK should be generated at the time of the 3.33rd pulse of the base clock signal OSC_CLK, but in reality it is generated at the time of the 3rd pulse of the base clock signal OSC_CLK.

[0050] The second pulse of the output clock signal DPLL_CLK should theoretically be generated at the 6th and 67th pulse of the base clock signal OSC_CLK, but it is actually generated at the 7th pulse of the base clock signal OSC_CLK.

[0051] Theoretically, the third pulse of the output clock signal DPLL_CLK should be generated at the time of the tenth pulse of the base clock signal OSC_CLK, but in reality, it is generated at the time of the tenth pulse of the base clock signal OSC_CLK.

[0052] And so on:

[0053] The 30th pulse of the output clock signal DPLL_CLK should theoretically be generated at the 100th pulse of the base clock signal OSC_CLK, but in reality it is generated at the 100th pulse of the base clock signal OSC_CLK.

[0054] The 3000th (Nset) pulse of the output clock signal DPLL_CLK should theoretically be generated at the moment of the 10000th (Nsin) pulse of the base clock signal OSC_CLK, at which time the next pulse of the corresponding input characterization signal Sin_start arrives, and one cycle ends.

[0055] The digital phase-locked loop circuit according to embodiments of the present invention can guarantee the generation of an output clock signal DPLL_CLK of approximately Nset cycles within one cycle of the input periodic signal Sin, thereby achieving Nset frequency multiplication of the input periodic signal Sin. Although the frequency of the base clock signal OSC_CLK will affect the operation process of the digital phase-locked loop circuit according to embodiments of the present invention, it will not have a significant impact on the output clock signal DPLL_CLK. Using base clock signals OSC_CLK of different frequencies (as long as their frequency is higher than the expected frequency of the output clock signal DPLL_CLK), the Nset frequency multiplication effect of the input periodic signal Sin can be achieved, therefore the frequency accuracy requirement of the base clock signal OSC_CLK is not high. Furthermore, when the frequency of the input periodic signal Sin changes, the clock counting result Nsin will be updated immediately at the end of one cycle of the input periodic signal Sin, so its response lags by only one cycle, which is much faster than that of analog phase-locked loop circuits, and it does not suffer from the oscillation problem caused by the loop filter in analog phase-locked loop circuits. In addition, for cases where the frequency of the input periodic signal Sin is low, it is only necessary to ensure that the bit width of the corresponding variables (e.g., Nsin, OSC_SUM, DPLL_SUM) is sufficient and that no overflow occurs. This allows the digital phase-locked loop circuit according to the embodiment of the present invention to work normally even when the frequency range of the input periodic signal Sin is wide.

[0056] In summary, the digital phase-locked loop circuit according to the embodiments of the present invention only requires adders, comparators, flip-flops and other components to achieve synchronization of the input periodic signal and the output clock signal (synchronization in both frequency and phase), without the need for multiplication and division units, which greatly simplifies the computation and circuit design complexity.

[0057] This invention can be implemented in other specific forms without departing from its spirit and essential characteristics. For example, the algorithm described in a particular embodiment can be modified without departing from the basic spirit of the invention. Therefore, the present embodiments are to be regarded as exemplary rather than limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and all changes falling within the meaning and scope of the claims and their equivalents are thus included within the scope of the invention.

Claims

1. A digital phase-locked loop circuit, comprising: The synchronization control module is configured to generate an input characterization signal that characterizes the periodic variation of the input periodic signal relative to the base clock signal, based on a base clock signal and an input periodic signal. The counting control module is configured to generate a clock counting result based on the base clock signal and the input characterization signal, representing the multiple relationship between the period of the input characterization signal and the period of the base clock signal. The operation control module is configured to generate a basic clock control variable based on a preset multiplication factor between the frequency of the output clock signal and the frequency of the input periodic signal, and to generate an output clock control variable based on the clock counting result. as well as The output control module is configured to generate an output control signal based on the base clock control variable and the output clock control variable, and to generate the output clock signal based on the output control signal and the base clock signal, wherein... The counting control module and the arithmetic control module take the rising edge of the base clock signal as the valid edge, and the synchronization control module and the output control module take the falling edge of the base clock signal as the valid edge, or The counting control module and the arithmetic control module take the falling edge of the base clock signal as the valid edge, while the synchronization control module and the output control module take the rising edge of the base clock signal as the valid edge.

2. The digital phase-locked loop circuit according to claim 1, wherein, The synchronization control module is further configured to: Based on the base clock signal and the input period signal, a first characterization signal is generated using a first D flip-flop; Based on the base clock signal and the first characterization signal, a second characterization signal is generated using a second D flip-flop; as well as The input representation signal is generated using a first AND gate based on the inverted signal of the second representation signal and the first representation signal.

3. The digital phase-locked loop circuit according to claim 1, wherein, The counting control module is further configured to: When the input representation signal is at an inactive level, a clock counter is used to count the number of cycles of the basic clock signal. When the input representation signal is at an active level, the clock counter's count result is updated to the clock count result and the clock counter is cleared to zero.

4. The digital phase-locked loop circuit according to claim 1, wherein, The computation control module is further configured as follows: When the input characterization signal is at an active level, the basic clock control variable is initialized based on a preset multiplication factor between the frequency of the output clock signal and the frequency of the input periodic signal; as well as When the input characterization signal is at an inactive level, the basic clock control variable is updated based on a preset multiplication factor between the frequency of the output clock signal and the frequency of the input periodic signal.

5. The digital phase-locked loop circuit according to claim 4, wherein, The computation control module is further configured as follows: The updated variable value of the basic clock control variable is calculated based on the variable value updated when the preceding effective edge of the basic clock signal arrives and the preset multiplication factor between the frequency of the output clock signal and the frequency of the input periodic signal. as well as When the current valid edge of the base clock signal arrives, the base clock control variable is updated using the calculated update variable value.

6. The digital phase-locked loop circuit according to claim 1, wherein, The computation control module is further configured as follows: When the input characterization signal is at an active level, the output clock control variable is initialized based on the clock counting result; and When the input representation signal is at an inactive level, the output clock control variable is updated based on the clock counting result.

7. The digital phase-locked loop circuit according to claim 6, wherein, The computation control module is further configured as follows: Based on the updated value of the output clock control variable at the preceding valid edge of the base clock signal, the clock counting result, and the output control signal, the updated value of the output clock control variable is calculated, wherein the output control signal represents the magnitude comparison between the updated value of the base clock control variable and the updated value of the output clock control variable at the preceding valid edge of the base clock signal; and When the current valid edge of the base clock signal arrives, the output clock control variable is updated using the calculated update variable value.

8. The digital phase-locked loop circuit according to claim 7, wherein, The output control signal is logic 1 when the base clock control variable is greater than the output clock control variable, and logic 0 when the base clock control variable is not greater than the output clock control variable.

9. The digital phase-locked loop circuit according to claim 1, wherein, The output control module is further configured to: Based on the basic clock control variable and the output clock control variable, a comparator is used to generate a variable comparison signal; Based on the basic clock signal and the variable comparison signal, the output control signal is generated using a third D flip-flop. as well as The output clock signal is generated using a second AND gate based on the base clock signal and the output control signal.

10. A control method implemented by a digital phase-locked loop circuit, comprising: Based on a base clock signal and an input periodic signal, an input characterization signal is generated that characterizes the periodic variation of the input periodic signal relative to the base clock signal. Based on the base clock signal and the input characterization signal, a clock counting result is generated that represents the multiple relationship between the period of the input characterization signal and the period of the base clock signal. A basic clock control variable is generated based on a preset multiplication factor between the frequency of the output clock signal and the frequency of the input periodic signal, and an output clock control variable is generated based on the clock counting result. as well as An output control signal is generated based on the base clock control variable and the output clock control variable, and an output clock signal is generated based on the output control signal and the base clock signal, wherein... The processing for generating the clock counting result and the processing for generating the basic clock control variable and the output clock control variable take the rising edge of the basic clock signal as the valid edge; the processing for generating the input characterization signal and the processing for generating the output clock signal take the falling edge of the basic clock signal as the valid edge, or... The processing for generating the clock count result and the processing for generating the basic clock control variable and the output clock control variable take the falling edge of the basic clock signal as the valid edge. The processing for generating the input characterization signal and the processing for generating the output clock signal take the rising edge of the basic clock signal as the valid edge.

11. The control method according to claim 10, wherein, The process of generating the input representation signal includes: Based on the base clock signal and the input period signal, a first characterization signal is generated using a first D flip-flop; Based on the fundamental clock signal and the first characterization signal, a second characterization signal is generated using a second D flip-flop; and The input representation signal is generated using a first AND gate based on the inverted signal of the second representation signal and the first representation signal.

12. The control method according to claim 10, wherein, The process for generating the clock count result includes: When the input representation signal is at an inactive level, a clock counter is used to count the number of cycles of the basic clock signal. When the input representation signal is at an active level, the clock counter's count result is updated to the clock count result and the clock counter is cleared to zero.

13. The control method according to claim 10, wherein, The process of generating the basic clock control variable includes: When the input characterization signal is at an active level, the basic clock control variable is initialized based on a preset multiplication factor between the frequency of the output clock signal and the frequency of the input periodic signal; and When the input characterization signal is at an inactive level, the basic clock control variable is updated based on a preset multiplication factor between the frequency of the output clock signal and the frequency of the input periodic signal.

14. The control method according to claim 13, wherein, The process of updating the basic clock control variables includes: Based on the updated value of the basic clock control variable at the arrival of the preceding valid edge of the basic clock signal and the preset multiplication factor between the frequency of the output clock signal and the frequency of the input periodic signal, the updated value of the basic clock control variable is calculated; and When the current valid edge of the base clock signal arrives, the base clock control variable is updated using the calculated update variable value.

15. The control method according to claim 10, wherein, The process of generating the output clock control variable includes: When the input characterization signal is at an active level, the output clock control variable is initialized based on the clock counting result; and When the input representation signal is at an inactive level, the output clock control variable is updated based on the clock counting result.

16. The control method according to claim 15, wherein, The process of updating the output clock control variable includes: Based on the updated value of the output clock control variable at the preceding valid edge of the base clock signal, the clock counting result, and the output control signal, the updated value of the output clock control variable is calculated, wherein the output control signal represents the magnitude comparison between the updated value of the base clock control variable and the updated value of the output clock control variable at the preceding valid edge of the base clock signal; and When the current valid edge of the base clock signal arrives, the output clock control variable is updated using the calculated update variable value.

17. The control method according to claim 16, wherein, The output control signal is logic 1 when the base clock control variable is greater than the output clock control variable, and logic 0 when the base clock control variable is not greater than the output clock control variable.

18. The control method according to claim 10, wherein, The process of generating the output clock signal includes: Based on the basic clock control variable and the output clock control variable, a comparator is used to generate a variable comparison signal; Based on the fundamental clock signal and the variable comparison signal, the output control signal is generated using a third D flip-flop; and The output clock signal is generated using a second AND gate based on the base clock signal and the output control signal.

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