Display device

Abstract

A display device is provided. The display device includes: a substrate including a display area and a peripheral area outside the display area; a scan driver disposed in a central portion of the display area and extending in a first direction; and a first signal line connected to the scan driver and extending at one side in a second direction crossing the first direction, in which the first signal line has a first width in the first direction, and the first width continuously decreases from the scan driver toward the peripheral region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0039039 filed on March 24, 2023 and Korean Patent Application No. 10-2023-0077063 filed on June 15, 2023 and all rights derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device, and more particularly to a display device having improved reliability and resolution. Background Art

[0004] The display device visually displays data. The display device may provide an image by using a light emitting diode. The use of the display device has been diversified, and various attempts have been made to develop designs to improve the quality of the display device. Utility Model Content

[0005] One or more embodiments include a display device with improved reliability and resolution.

[0006] According to one or more embodiments, a display device includes: a substrate including a display area and a peripheral area outside the display area; a scan driver, which is arranged in a central part of the display area and extends in a first direction; and a first signal line, which is connected to the scan driver and extends on one side of the display area in a second direction intersecting the first direction, wherein the first signal line has a first width in the first direction, and the first width continuously decreases as the first signal line extends from the scan driver toward the peripheral area.

[0007] In an embodiment, the display device may further include: a first initialization voltage driver, which is arranged on one side of the peripheral area and extends in a first direction; and a first initialization voltage line, which is connected to the first initialization voltage driver and extends in a second direction, wherein the first initialization voltage line may have a second width in the first direction, and the second width may continuously decrease from the first initialization voltage driver toward the scan driver.

[0008] In an embodiment, the first width of the first signal line may be continuously increased from the peripheral area toward the scan driver.

[0009] In an embodiment, the second width of the first initialization voltage line may be continuously increased from the scan driver toward the first initialization voltage driver.

[0010] In an embodiment, when the display device is viewed in a direction perpendicular to the substrate, a sum of a first width of the first signal line and a second width of the first initialization voltage line may be constant at any point of the substrate in the second direction.

[0011] In an embodiment, the display device may further include a wiring portion including a first signal line and a first initialization voltage line.

[0012] In an embodiment, the plurality of wiring portions may be disposed to be separated from each other at regular intervals in the first direction.

[0013] In an embodiment, the display device may further include a second signal line connected to the scan driver and extending on the other side in the second direction, wherein the second signal line may have a third width in the first direction, wherein the third width may continuously decrease from the scan driver toward the peripheral area.

[0014] In an embodiment, the display device may further include: a second initialization voltage driver, which is arranged on the other side of the peripheral area and extends in the first direction; and a second initialization voltage line, which is connected to the second initialization voltage driver and extends in the second direction, wherein the second initialization voltage line may have a fourth width in the first direction, wherein the fourth width may continuously decrease from the second initialization voltage driver toward the scan driver.

[0015] In an embodiment, the third width of the second signal line may be continuously increased from the peripheral area toward the scan driver.

[0016] In an embodiment, the fourth width of the second initialization voltage line may be continuously increased from the scan driver toward the second initialization voltage driver.

[0017] In an embodiment, when the display device is viewed in a direction perpendicular to the substrate, a sum of the third width of the second signal line and the fourth width of the second initialization voltage line may be constant at any point of the substrate in the second direction.

[0018] In an embodiment, the display device may further include: a first organic light emitting diode arranged above the scan driver; and a first sub-pixel circuit electrically connected to the first organic light emitting diode and arranged to be adjacent to the scan driver in the display area.

[0019] In an embodiment, the first sub-pixel circuit may include a first semiconductor layer and a first thin film transistor insulated from the first semiconductor layer.

[0020] In an embodiment, the first organic light emitting diode may include a sub-pixel electrode disposed on a substrate, an emission layer disposed on the sub-pixel electrode, and an opposing electrode disposed on the emission layer.

[0021] In an embodiment, the first sub-pixel circuit may be electrically connected to the first signal line.

[0022] In an embodiment, the first sub-pixel circuit may be electrically connected to a first initialization voltage line.

[0023] According to one or more embodiments, a display device includes: a substrate including a display area and a peripheral area outside the display area; a scan driver, which is arranged in a central portion of the display area and extends in a first direction; a first initialization voltage driver, which is arranged in the peripheral area and extends in the first direction; a first signal line, which is connected to the scan driver, extends in a second direction intersecting the first direction, and has a first width in the first direction; and a first initialization voltage line, which is connected to the first initialization voltage driver, extends in the second direction, and has a second width in the first direction, wherein, when the display device is viewed in a direction perpendicular to the substrate, the sum of the first width and the second width is constant at any point of the substrate in the second direction.

[0024] In an embodiment, the first width of the first signal line may be gradually reduced from the scan driver toward the peripheral area.

[0025] In an embodiment, the second width of the first initialization voltage line may be continuously reduced from the first initialization voltage driver toward the scan driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a perspective view of a display device according to an embodiment;

[0028] Figure 2 is a schematic cross-sectional view of a display device according to an embodiment;

[0029] Figure 3 is a schematic equivalent circuit diagram of a sub-pixel circuit electrically connected to a sub-pixel according to an embodiment;

[0030] Figure 4 is a schematic plan view of a display panel according to an embodiment; and

[0031] Figure 5is a schematic enlarged view of a portion of a plan view of a display panel according to an embodiment. DETAILED DESCRIPTION

[0032] The embodiments illustrated in the accompanying drawings will now be referred to in detail, wherein similar reference numerals refer to similar elements throughout. In this regard, embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, embodiments are described below only by reference to the figures to illustrate aspects of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout the present disclosure, the expression "at least one of a, b or c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or their variants.

[0033] Since the present disclosure contemplates various changes and numerous embodiments, specific embodiments are illustrated in the drawings and described in the written description. The effects and features of the embodiments and methods for implementing them will be explained with reference to the embodiments described in detail below with reference to the drawings. However, the present disclosure is not limited to the following embodiments and may be embodied in various forms.

[0034] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. When describing the embodiments with reference to the accompanying drawings, the same or corresponding elements are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0035] In the following embodiments, terms such as "first" and "second" may be used to describe various elements, but such elements should not be limited to the above terms. The above terms are used to distinguish one element from another element.

[0036] In the following embodiments, expressions using the singular include expressions in the plural unless they have apparently different meanings herein.

[0037] In the following embodiments, terms such as “include” or “comprising” may be interpreted as indicating specific characteristics or elements or any combination thereof, but may not be interpreted as excluding the possibility of the existence or addition of one or more other characteristics, elements and / or any combination thereof.

[0038] In the following embodiments, when a layer, region, and / or element is referred to as being “on” another layer, region, or element, it can be directly or indirectly on another layer, region, or element. That is, for example, intervening layers, regions, or elements may exist.

[0039] For the convenience of description, the size of the elements in the drawings may be exaggerated or reduced. For example, since the size and thickness of the elements in the drawings are arbitrarily illustrated for the convenience of description, the present disclosure is not limited thereto.

[0040] When the embodiment can be implemented differently, a specific process order may be performed in a different order than described. For example, two processes described in succession may be performed substantially at the same time, or may be performed in an order opposite to the described order.

[0041] As used herein, "A and / or B" means A, B, or A and B. In addition, "at least one of A and B" means A, B, or A and B.

[0042] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0043] In the following embodiments, when a layer, region, and / or element is referred to as being "connected" to another layer, region, and / or element, it may be "directly connected" to the other layer, region, or element, and / or may be "indirectly connected" to the other layer, region, and / or element, with one or more intervening layers, regions, and / or elements therebetween. For example, when a layer, region, and / or element is referred to as being "electrically connected" to another layer, region, and / or element, it may be "directly electrically connected" to the other layer, region, and / or element, and / or may be "indirectly electrically connected" to the other layer, region, and / or element, with one or more intervening layers, regions, and / or elements therebetween.

[0044] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may refer to different directions that are not orthogonal to each other.

[0045] Figure 1 is a perspective view of a display device 1 according to the embodiment.

[0046] The display device 1 according to the embodiment as a device for displaying moving images or static images can be used as a display screen of various products such as televisions, laptop computers, monitors, billboards and / or Internet of Things (IOT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMP), navigation devices and / or ultra-mobile personal computers (UMPC). In addition, the display device 1 according to the embodiment can be used in wearable devices such as smart watches, watch phones, glasses-type displays and / or head-mounted displays (HMD). In addition, the display device 1 according to the embodiment can be used as an instrument panel of a vehicle, a central information display (CID) arranged on the central dashboard and / or instrument panel of the vehicle, an interior mirror display instead of a side mirror of the vehicle, and / or a display arranged on the rear surface of the front seat as an entertainment device for the rear seat of the vehicle.

[0047] In the examples and with reference to Figure 1 , the display device 1 may have an edge in a first direction and an edge in a second direction. Here, the first direction and the second direction may intersect each other. For example, the first direction and the second direction may form an acute angle with each other. As another example, the first direction and the second direction may form an obtuse angle with each other or be orthogonal to each other. In the following, the case where the first direction and the second direction are orthogonal to each other is mainly described in detail. For example, the first direction may be an x ​​direction or a -x direction, and the second direction may be a y direction or a -y direction. A third direction perpendicular to the first direction and the second direction may be a z direction or a -z direction.

[0048] In an embodiment, the display device 1 may include a display area DA and a peripheral area PA outside the display area DA. The display device 1 may provide a specific image by using light emitted from a plurality of sub-pixels PX disposed in the display area DA. The peripheral area PA is disposed outside the display area DA and may be a type of a non-display area in which no sub-pixels are disposed. The display area DA may be completely surrounded by the peripheral area PA.

[0049] In the following, an organic light-emitting display device is described as an example of a display device 1 according to an embodiment, but the display device 1 of the present disclosure is not limited thereto. In another embodiment, the display device 1 of the present disclosure may be an inorganic light-emitting display device (or an inorganic electroluminescent (EL) display device) or a quantum dot light-emitting display device. For example, in an embodiment, the emission layer of the display element included in the display device 1 may include an organic material or an inorganic material. In addition, in an embodiment, the display device 1 may include an emission layer and quantum dots located on the path of light emitted from the emission layer.

[0050] Figure 2is a schematic cross-sectional view of a display device 1 according to an embodiment. Specifically, Figure 2 According to the embodiment Figure 1 Schematic cross-sectional view of the display area DA of the display device 1 taken along line II′ in FIG.

[0051] In the examples and with reference to Figure 2 , the display panel 10 may include a substrate 100, an inorganic insulating layer IIL, an organic insulating layer OIL, a sub-pixel circuit PC, a connection electrode CM, an organic light emitting diode OLED, a pixel defining layer 118, a spacer 119, and an encapsulation layer 300. That is, the substrate 100, the inorganic insulating layer IIL, the organic insulating layer OIL, the sub-pixel circuit PC, the connection electrode CM, the organic light emitting diode OLED, the pixel defining layer 118, the spacer 119, and the encapsulation layer 300 may be disposed in the display area DA of the display panel 10.

[0052] In an embodiment, the substrate 100 may include a first base layer 100a, a first barrier layer 100b, a second base layer 100c, and a second barrier layer 100d. In an embodiment, the first base layer 100a, the first barrier layer 100b, the second base layer 100c, and the second barrier layer 100d may be sequentially stacked in a thickness direction of the substrate 100.

[0053] In an embodiment, at least one of the first substrate layer 100a and the second substrate layer 100c may include a polymer resin such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, and / or cellulose acetate propionate.

[0054] In an embodiment, the first barrier layer 100b and the second barrier layer 100d are barrier layers for preventing penetration of external foreign substances, and may include a material including silicon nitride (SiN x ), silicon oxide (SiO 2 ) and / or silicon oxynitride (SiON) in an inorganic material.

[0055] In an embodiment, a buffer layer 111 may be disposed on the substrate 100. The buffer layer 111 may include a layer such as SiN x , SiON and / or SiO 2 and an inorganic insulating material, and includes a single layer or a plurality of layers containing the above-mentioned inorganic insulating material.

[0056] In an embodiment, the inorganic insulating layer IIL may be disposed on the buffer layer 111. The inorganic insulating layer IIL may include a first inorganic insulating layer 112, a second inorganic insulating layer 113, and a third inorganic insulating layer 114.

[0057] In an embodiment, the sub-pixel circuit PC may be disposed in the display area DA. The sub-pixel circuit PC may include a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0058] In an embodiment, the semiconductor layer Act may be disposed on the buffer layer 111. The semiconductor layer Act may include polycrystalline silicon. Alternatively, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, an organic semiconductor, etc. The semiconductor layer Act may include a channel region, a drain region and a source region respectively disposed on both sides of the channel region.

[0059] In an embodiment, the gate electrode GE may be arranged on the semiconductor layer Act. The gate electrode GE may overlap the channel region. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and include a single layer or multiple layers including the above materials.

[0060] In an embodiment, the first inorganic insulating layer 112 may be disposed between the semiconductor layer Act and the gate electrode GE. The first inorganic insulating layer 112 may include a layer such as SiO 2 、SiN x , SiON, Alumina (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and / or inorganic insulating materials of zinc oxide (ZnO).

[0061] In an embodiment, the second inorganic insulating layer 113 may be disposed on the gate electrode GE. The second inorganic insulating layer 113 may cover the gate electrode GE. The second inorganic insulating layer 113 may include a silicon-based material such as SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 and / or an inorganic insulating material of ZnO.

[0062] In an embodiment, the upper electrode CE2 of the storage capacitor Cst may be arranged on the second inorganic insulating layer 113. The upper electrode CE2 may overlap the gate electrode GE thereunder. In this case, the gate electrode GE and the upper electrode CE2 overlapping each other (the second inorganic insulating layer 113 is between the gate electrode GE and the upper electrode CE2) may form a storage capacitor Cst. That is, the gate electrode GE may serve as the lower electrode CE1 of the storage capacitor Cst.

[0063] In the embodiment and as described above, the storage capacitor Cst may overlap with the thin film transistor TFT. However, the present disclosure is not limited thereto. For example, the storage capacitor Cst may not overlap with the thin film transistor TFT. That is, the lower electrode CE1 of the storage capacitor Cst may be disposed to be separated from the gate electrode GE of the thin film transistor TFT as an element separated from the gate electrode GE of the thin film transistor TFT.

[0064] In an embodiment, the upper electrode CE2 may include Al, platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), Mo, Ti, tungsten (W) and / or Cu, and include a single layer or multiple layers containing the above materials.

[0065] In an embodiment, the third inorganic insulating layer 114 may be disposed on the upper electrode CE2. The third inorganic insulating layer 114 may cover the upper electrode CE2. The third inorganic insulating layer 114 may include SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 and / or ZnO. The third inorganic insulating layer 114 may include a single layer or a plurality of layers including the above-mentioned inorganic insulating materials.

[0066] In an embodiment, each of the drain electrode DE and the source electrode SE may be disposed on the third inorganic insulating layer 114. Each of the drain electrode DE and the source electrode SE may be connected to the semiconductor layer Act via a contact hole included in the first inorganic insulating layer 112, the second inorganic insulating layer 113, and the third inorganic insulating layer 114. The drain electrode DE and the source electrode SE may include a material having high conductivity. The drain electrode DE and the source electrode SE may include a conductive material including Mo, Al, Cu, Ti, etc., and include a single layer or a plurality of layers including the above materials. For example, the drain electrode DE and the source electrode SE may have a multilayer structure of Ti / Al / Ti.

[0067] In an embodiment, the organic insulating layer OIL may be disposed on the inorganic insulating layer IIL. The organic insulating layer OIL may include a first organic insulating layer 115 and a second organic insulating layer 116. Figure 2 An embodiment in which two organic insulating layers OIL are provided is illustrated, but the present disclosure is not limited thereto. In an embodiment, three or four organic insulating layers OIL may be provided.

[0068] In an embodiment, the first organic insulating layer 115 may cover the drain electrode DE and the source electrode SE. The first organic insulating layer 115 may include an organic insulating material such as a general polymer (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenol group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a paraxylene-based polymer, a vinyl alcohol-based polymer, and / or a mixture thereof.

[0069] In an embodiment, the connection electrode CM may be arranged on the first organic insulating layer 115. In this embodiment, the connection electrode CM may be connected to the drain electrode DE or the source electrode SE via a contact hole of the first organic insulating layer 115. The connection electrode CM may include a material having high conductivity. The connection electrode CM may include a conductive material including Mo, Al, Cu, Ti, etc., and include a single layer or a plurality of layers including the above materials. For example, the connection electrode CM may have a multilayer structure of Ti / Al / Ti.

[0070] In an embodiment, the second organic insulating layer 116 may be disposed on the connection electrode CM. The second organic insulating layer 116 may cover the connection electrode CM. The second organic insulating layer 116 may include the same material as that of the first organic insulating layer 115 or include a material different from that of the first organic insulating layer 115.

[0071] In an embodiment, a light emitting diode may be disposed on the second organic insulating layer 116. For example, an organic light emitting diode OLED may be disposed on the second organic insulating layer 116. Alternatively, although not shown, an inorganic light emitting diode or the like may be disposed on the second organic insulating layer 116.

[0072] In an embodiment, the organic light emitting diode OLED may emit red light, green light or blue light, or emit red light, green light, blue light or white light. The organic light emitting diode OLED may include a sub-pixel electrode 211, an emission layer 212b, a functional layer 212f, an opposing electrode 213 and a capping layer 215.

[0073] In an embodiment, the sub-pixel electrode 211 may be disposed on the second organic insulating layer 116. The sub-pixel electrode 211 may be electrically connected to the connection electrode CM via a contact hole defined in the second organic insulating layer 116. The sub-pixel electrode 211 may include an indium tin oxide (ITO), indium zinc oxide (IZO), ZnO, indium oxide (In 2 O 3 ), indium gallium oxide (IGO) and / or aluminum zinc oxide (AZO). In an embodiment, the sub-pixel electrode 211 may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and / or compounds thereof. In an embodiment, the sub-pixel electrode 211 may further include a conductive oxide including ITO, IZO, ZnO and / or In above / below the reflective layer. 2 O 3 For example, the sub-pixel electrode 211 may have a multi-layer structure of ITO / Ag / ITO.

[0074] In an embodiment, a pixel defining layer 118 having an opening exposing at least a portion of the sub-pixel electrode 211 may be disposed on the sub-pixel electrode 211. An emission region of light emitted from the organic light emitting diode OLED may be defined by the opening defined in the pixel defining layer 118. For example, in an embodiment, a width of the opening may correspond to a width of the emission region.

[0075] In an embodiment, the pixel defining layer 118 may include an organic insulating material. Alternatively, in an embodiment, the pixel defining layer 118 may include an organic insulating material such as SiN x , SiON or SiO 2 Inorganic insulating material. Alternatively, in another embodiment, the pixel defining layer 118 may include an organic insulating material and an inorganic insulating material. In an embodiment, the pixel defining layer 118 may include a shading material. The shading material may include carbon black, carbon nanotubes, a resin and / or paste containing a black dye, metal particles (e.g., Ni, Al, Mo and / or their alloys), metal oxide particles (e.g., chromium oxide) and / or metal nitride particles (e.g., chromium nitride). When the pixel defining layer 118 includes a shading material, external light reflection caused by a metal structure arranged below the pixel defining layer 118 can be reduced.

[0076] In an embodiment, the spacer 119 may be disposed on the pixel defining layer 118. The spacer 119 may include an organic insulating material such as polyimide. Alternatively, in an embodiment, the spacer 119 may include an organic insulating material such as SiN x or SiO 2 of inorganic insulating materials, or including organic insulating materials and inorganic insulating materials.

[0077] In an embodiment, the spacer 119 may include the same material as that of the pixel defining layer 118. In this embodiment, the pixel defining layer 118 and the spacer 119 may be formed together in a mask process using a half-tone mask, etc. Alternatively, in an embodiment, the spacer 119 may include a material different from that of the pixel defining layer 118.

[0078] In an embodiment, the emission layer 212b may be disposed in the opening of the pixel defining layer 118. The emission layer 212b may include a polymer or a low molecular weight organic material that emits light of a specific color.

[0079] In an embodiment, the functional layer 212f may include a first functional layer 212a and a second functional layer 212c. The first functional layer 212a may be disposed between the subpixel electrode 211 and the emission layer 212b, and the second functional layer 212c may be disposed between the emission layer 212b and the counter electrode 213. However, at least one of the first functional layer 212a and the second functional layer 212c may be omitted. Hereinafter, an embodiment in which the first functional layer 212a and the second functional layer 212c are disposed will be described in detail.

[0080] In an embodiment, the first functional layer 212a may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer 212c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer 212a and / or the second functional layer 212c may be a common layer formed to completely cover the substrate 100, like the counter electrode 213 to be described below.

[0081] In an embodiment, the counter electrode 213 may be arranged on the functional layer 212f. The counter electrode 213 may include a conductive material having a low work function. For example, the counter electrode 213 may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), Ca and / or their alloys. Alternatively, in an embodiment, the counter electrode 213 may further include a (semi) transparent layer including ITO, IZO, ZnO and / or In on the (semi) transparent layer including the above materials. 2 O 3 layer.

[0082] In embodiments, the capping layer 215 may be disposed on the counter electrode 213. The capping layer 215 may include an inorganic material such as lithium fluoride (LiF) and / or an organic material.

[0083] In an embodiment, the encapsulation layer 300 may be disposed on the organic light emitting diode OLED. The encapsulation layer 300 may cover the organic light emitting diode OLED. The encapsulation layer 300 may be disposed on the counter electrode 213 and / or the capping layer 215. In an embodiment, the encapsulation layer 300 may include at least one inorganic layer and at least one organic layer. Figure 2 It is illustrated that the encapsulation layer 300 includes a first inorganic encapsulation layer 310 , an organic encapsulation layer 320 , and a second inorganic encapsulation layer 330 which are sequentially stacked.

[0084] In an embodiment, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 、ZnO、SiO 2 、SiN x The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include a single layer or multiple layers containing the above materials. The organic encapsulation layer 320 may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide, polyethylene, etc. In an embodiment, the organic encapsulation layer 320 may include acrylate.

[0085] In an embodiment, the input sensing layer 48 may be disposed on the encapsulation layer 300. The input sensing layer 48 may include a first touch insulating layer 410, a second touch insulating layer 420, a first conductive layer 430, a third touch insulating layer 440, a second conductive layer 450, and a planarization layer 460.

[0086] In an embodiment, the first touch insulating layer 410 may be disposed on the second inorganic encapsulation layer 330, and the second touch insulating layer 420 may be disposed on the first touch insulating layer 410. In an embodiment, the first touch insulating layer 410 and the second touch insulating layer 420 may include an inorganic insulating material and / or an organic insulating material. For example, the first touch insulating layer 410 and the second touch insulating layer 420 may include an inorganic insulating material such as SiO 2 、SiN x and / or SiON inorganic insulating material.

[0087] In an embodiment, at least one of the first touch insulating layer 410 and the second touch insulating layer 420 may be omitted. For example, the first touch insulating layer 410 may be omitted. In this embodiment, the second touch insulating layer 420 may be disposed on the second inorganic encapsulation layer 330, and the first conductive layer 430 may be disposed on the second touch insulating layer 420.

[0088] In an embodiment, the first conductive layer 430 may be disposed on the second touch insulating layer 420, and the third touch insulating layer 440 may be disposed on the first conductive layer 430. In an embodiment, the third touch insulating layer 440 may include an inorganic insulating material and / or an organic insulating material. For example, the third touch insulating layer 440 may include an inorganic insulating material such as SiO 2 、SiN x and / or SiON inorganic insulating material.

[0089] In an embodiment, the second conductive layer 450 may be arranged on the third touch insulating layer 440. The touch electrode TE of the input sensing layer 48 may have a structure in which the first conductive layer 430 and the second conductive layer 450 are connected to each other. Alternatively, in an embodiment, the touch electrode TE may be formed on any one of the first conductive layer 430 and the second conductive layer 450, and include a metal wire contained in the corresponding conductive layer. Each of the first conductive layer 430 and the second conductive layer 450 may include at least one of Al, Cu, Ti, Mo and ITO, and include a single layer or multiple layers containing the above materials. For example, each of the first conductive layer 430 and the second conductive layer 450 may have a three-layer structure of Ti layer / Al layer / Ti layer.

[0090] In an embodiment, the planarization layer 460 may cover the second conductive layer 450. The planarization layer 460 may include an organic insulating material.

[0091] Figure 3 is a schematic equivalent circuit diagram of a sub-pixel circuit PC electrically connected to a sub-pixel according to an embodiment.

[0092] In the examples and with reference to Figure 3 , the sub-pixel may emit light through the organic light emitting diode OLED, and the organic light emitting diode OLED may be electrically connected to the sub-pixel circuit PC.

[0093] In an embodiment, the sub-pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0094] In an embodiment, the first transistor T1 as a driving thin film transistor can be connected to the driving voltage line PL and the storage capacitor Cst, and is configured to control the driving current flowing from the driving voltage line PL to the organic light emitting diode OLED in response to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with a specific brightness according to the driving current. The second electrode (e.g., cathode) of the organic light emitting diode OLED can receive the common voltage ELVSS.

[0095] In an embodiment, the second transistor T2 as a switching thin film transistor can be connected to the signal line SL and the data line DL, and is configured to send the data voltage (or data signal) Dm received via the data line DL to the first transistor T1 based on the scan signal (or scan voltage, switching voltage or switching signal) Sn received via the signal line SL.

[0096] In an embodiment, a storage capacitor Cst may be connected to a driving voltage line PL and a first transistor T1. One electrode of the storage capacitor Cst may be connected to the driving voltage line PL, and the other electrode of the storage capacitor Cst may be connected to a gate electrode of the first transistor T1. The storage capacitor Cst may store a difference between a driving voltage ELVDD applied to the driving voltage line PL and a gate voltage of the first transistor T1, and maintain the gate voltage of the first transistor T1.

[0097] In an embodiment, the third transistor T3 is a compensation thin film transistor, and the gate electrode of the third transistor T3 may be connected to the signal line SL. The source electrode (or drain electrode) of the third transistor T3 may be connected to the drain electrode (or source electrode) of the first transistor T1, and connected to the first electrode (e.g., anode) of the organic light emitting diode OLED via the sixth transistor T6. The drain electrode (or source electrode) of the third transistor T3 may be connected to the other electrode of the storage capacitor Cst, the source electrode (or drain electrode) of the fourth transistor T4, and the gate electrode of the first transistor T1. The third transistor T3 may be turned on according to the scan signal Sn received via the signal line SL, and the gate electrode and the drain electrode of the first transistor T1 are connected to each other so that the first transistor T1 is diode-connected.

[0098] In an embodiment, the fourth transistor T4 is an initialization thin film transistor, and the gate electrode of the fourth transistor T4 may be connected to the previous signal line SL-1. The drain electrode (or source electrode) of the fourth transistor T4 may be connected to the initialization voltage line VL. The source electrode (or drain electrode) of the fourth transistor T4 may be connected to the other electrode of the storage capacitor Cst, the drain electrode (or source electrode) of the third transistor T3, and the gate electrode of the first transistor Tl. The fourth transistor T4 may be turned on according to the previous scan signal Sn-1 received via the previous signal line SL-1, and is configured to send the initialization voltage Vint to the gate electrode of the first transistor T1 to perform an initialization operation of initializing the voltage of the gate electrode of the first transistor T1.

[0099] In an embodiment, the fifth transistor T5 is an operation control thin film transistor, and the gate electrode of the fifth transistor T5 may be connected to the emission control line EL. The source electrode (or drain electrode) of the fifth transistor T5 may be connected to the driving voltage line PL. The drain electrode (or source electrode) of the fifth transistor T5 may be connected to the source electrode (or drain electrode) of the first transistor T1 and the drain electrode (or source electrode) of the second transistor T2.

[0100] In an embodiment, the sixth transistor T6 is an emission control thin film transistor, and the gate electrode of the sixth transistor T6 may be connected to the emission control line EL. The source electrode (or drain electrode) of the sixth transistor T6 may be connected to the drain electrode (or source electrode) of the first transistor T1 and the source electrode (or drain electrode) of the third transistor T3. The drain electrode (or source electrode) of the sixth transistor T6 may be electrically connected to the first electrode of the organic light emitting diode OLED. The fifth transistor T5 and the sixth transistor T6 may be turned on simultaneously according to the emission control signal En received via the emission control line EL, so that the driving voltage ELVDD is sent to the organic light emitting diode OLED and the driving current flows in the organic light emitting diode OLED.

[0101] In an embodiment, the seventh transistor T7 may be an initialization thin film transistor for initializing the first electrode of the organic light emitting diode OLED. The gate electrode of the seventh transistor T7 may be connected to the next signal line SL+1. The source electrode (or drain electrode) of the seventh transistor T7 may be connected to the first electrode of the organic light emitting diode OLED. The drain electrode (or source electrode) of the seventh transistor T7 may be connected to the initialization voltage line VL. The seventh transistor T7 may be turned on according to the next scan signal Sn+1 received via the next signal line SL+1, and initialize the first electrode of the organic light emitting diode OLED.

[0102] although Figure 3 An embodiment is illustrated in which the fourth transistor T4 and the seventh transistor T7 are connected to the previous signal line SL-1 and the next signal line SL+1, respectively, but in an embodiment, both the fourth transistor T4 and the seventh transistor T7 can be connected to the previous signal line SL-1 and driven according to the previous scan signal Sn-1.

[0103] In an embodiment, one electrode of the storage capacitor Cst may be connected to the driving voltage line PL. The other electrode of the storage capacitor Cst may be connected to the gate electrode of the first transistor T1, the drain electrode (or source electrode) of the third transistor T3, and the source electrode (or drain electrode) of the fourth transistor T4.

[0104] In an embodiment, the second electrode of the organic light emitting diode OLED may receive the common voltage ELVSS. The organic light emitting diode OLED may receive the driving current from the first transistor T1 to emit light.

[0105] In an embodiment, all of the first to seventh transistors T1 to T7 may include a semiconductor layer including silicon, respectively. However, the present disclosure is not limited thereto.

[0106] In an embodiment, at least one transistor among the first to seventh transistors T1 to T7 may include a semiconductor layer including oxide, and the remaining transistors may include a semiconductor layer including silicon. Specifically, the first transistor T1 directly affecting the brightness of the display panel 10 may include a silicon semiconductor including polycrystalline silicon having high reliability, and therefore, a display panel 10 having high resolution may be implemented.

[0107] In an embodiment, since an oxide semiconductor has high carrier mobility and low leakage current, a voltage drop may not be large even when the driving time is long. That is, since the color change of an image according to a voltage drop is not large even during low-frequency driving, low-frequency driving is possible. As described above, since an oxide semiconductor has an advantage of low leakage current, at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 may include an oxide semiconductor so as to prevent leakage current that may flow to the gate electrode of the first transistor T1 and simultaneously reduce power consumption. In this embodiment, a signal line and / or a voltage line may be added to Figure 3 In addition, transistors other than the third transistor T3 and the fourth transistor T4 may include a semiconductor layer including an oxide. For example, the seventh transistor T7 may include a semiconductor layer including an oxide semiconductor.

[0108] Figure 4 is a schematic plan view of a display panel 10 according to an embodiment.

[0109] In the examples and with reference to Figure 4 The display panel 10 may include a scan driver SDRV, a terminal portion PAD, a data driver 32, and power lines disposed on a substrate 100. The power lines may include a driving voltage supply line 11 and a common voltage supply line 13.

[0110] In an embodiment, the substrate 100 (see Figure 2) may include a display area DA and a peripheral area PA outside the display area DA. A portion of the peripheral area PA may extend in one direction (e.g., the y direction). The terminal portion PAD, the driving voltage supply line 11, the common voltage supply line 13, the initialization voltage driver 15, etc. may be disposed in the peripheral area PA. In an embodiment, the width of the extended portion of the peripheral area PA in the x direction may be smaller than the width of the display area DA in the x direction. Unlike the initialization voltage driver 15, the driving voltage supply line 11, the common voltage supply line 13, etc., the scan driver SDRV may be disposed in the central portion of the display area DA to extend in a second direction (e.g., the y direction). When the scan driver SDRV is disposed in the central portion of the display area DA, the area of ​​the peripheral area PA (i.e., the area in which the sub-pixel PX is not disposed in the display device 1) may be reduced, thereby positively affecting the resolution of the display device 1, etc.

[0111] In an embodiment, a plurality of sub-pixels PX may be disposed in the display area DA. Each of the plurality of sub-pixels PX may be implemented by a display element such as an organic light emitting diode OLED. Each of the plurality of sub-pixels PX may emit, for example, red light, green light, blue light, and / or white light.

[0112] In detail, in an embodiment, the first subpixel PX1 may be disposed at one side of the display area DA. The second subpixel PX2 may be disposed at the other side of the display area DA. The third subpixel PX3 may be disposed to overlap the scan driver SDRV disposed in the central portion of the display area DA.

[0113] In an embodiment, each of the first subpixel circuit PC1, the second subpixel circuit PC2, and the third subpixel circuit PC3 for driving the first subpixel PX1, the second subpixel PX2, and the third subpixel PX3, respectively, may be disposed in the display area DA. The first subpixel circuit PC1 may be disposed in the display area DA to overlap with the first subpixel PX1, and the second subpixel circuit PC2 may be disposed in the display area DA to overlap with the second subpixel PX2. The third subpixel circuit PC3 may be disposed around the scan driver SDRV in the display area DA. In other words, the third subpixel circuit PC3 may be disposed so as not to overlap with the third subpixel PX3.

[0114] In an embodiment, each of the plurality of sub-pixel circuits PC driving the sub-pixels PX in the display area DA may be connected to a signal line or voltage line configured to control on / off, brightness, etc. of a display element such as a light emitting diode OLED. Figure 4A first signal line SL1 and a second signal line SL2 extending in a first direction (e.g., x direction or -x direction) and a data line DL extending in a second direction (e.g., y direction or -y direction) are illustrated as signal lines, and a driving voltage line PL is illustrated as a voltage line. In detail, the first signal line SL1 extends at one side of the display area DA in the first direction (e.g., x direction or -x direction), and the second signal line SL2 extends at the other side of the display area DA in the first direction (e.g., x direction or -x direction). In addition, the sub-pixel circuit PC may be connected to the initialization voltage driver 15 and to the initialization voltage line VL extending in the first direction (e.g., x direction or -x direction). In detail, the initialization voltage line VL may include a first initialization voltage line VL1 extending in the first direction (e.g., x direction or -x direction) at one side of the display area DA and a second initialization voltage line VL2 extending in the first direction (e.g., x direction or -x direction) at the other side of the display area DA.

[0115] In an embodiment, the sub-pixel circuit PC driving the sub-pixel PX may be electrically connected to an external circuit disposed in the peripheral area PA or the display area DA. The scan driver SDRV may be disposed in the central portion of the display area DA to extend in the second direction (e.g., the y direction or the -y direction). The terminal portion PAD, the data driver 32, the driving voltage supply line 11, the common voltage supply line 13, and the initialization voltage driver 15 may be disposed in the peripheral area PA.

[0116] In an embodiment, a scan driver SDRV disposed in a central portion of the display area DA may generate a scan signal and transmit the scan signal to each sub-pixel circuit PC via a signal line SL. In detail, the scan driver SDRV may provide a scan signal to a first sub-pixel circuit PC1 disposed at one side of the display area DA via a first signal line SL1. In addition, the scan driver SDRV may provide a scan signal to a second sub-pixel circuit PC2 disposed at the other side of the display area DA via a second signal line SL2.

[0117] In an embodiment, a terminal portion PAD may be provided at one side of the substrate 100. The terminal portion PAD is exposed without being covered by an insulating layer, and may be electrically connected to a controller such as a display circuit board 30. Control signals of the controller may be provided to a scan driver SDRV, a data driver 32, a driving voltage supply line 11, and a common voltage supply line 13 via the terminal portion PAD, respectively. In addition, the data driver 32 may be disposed on the display circuit board 30. The data driver 32 generates a data signal and transmits the data signal to each sub-pixel circuit PC via a fan-out line FW and a data line DL connected to the fan-out line FW.

[0118] In an embodiment, the driving voltage supply line 11 may be disposed in the peripheral area PA. The driving voltage supply line 11 may be configured to provide a driving voltage ELVDD to each sub-pixel PX. The driving voltage supply line 11 may be disposed in the peripheral area PA and connected to a plurality of driving voltage lines PL extending to the display area DA in a second direction (e.g., y direction).

[0119] In an embodiment, the common voltage supply line 13 may be disposed in the peripheral area PA and configured to supply a common voltage ELVSS to each sub-pixel PX.

[0120] In an embodiment, the initialization voltage driver 15 may include a first initialization voltage driver 15a extending in a second direction (e.g., y direction or -y direction) at one side of the peripheral area PA and a second initialization voltage driver 15b extending in the second direction (e.g., y direction or -y direction) at the other side of the peripheral area PA. The initialization voltage may be supplied to the first sub-pixel circuit PC1 via a first initialization voltage line VL1 connected from the first initialization voltage driver 15a and extending in a first direction (e.g., x direction or -x direction). The initialization voltage may be supplied to the second sub-pixel circuit PC2 via a second initialization voltage line VL2 connected from the second initialization voltage driver 15b and extending in the first direction (e.g., x direction or -x direction).

[0121] Figure 5 1 is a schematic enlarged view of a portion of a plan view of a display panel 10 according to an embodiment. In detail, Figure 5 The scan driver SDRV, the initialization voltage driver 15 , the signal lines SL, and the initialization voltage lines VL included in the display panel 10 are schematically illustrated.

[0122] In the examples and with reference to Figure 5 , the scan driver SDRV may be disposed in the central portion of the display area DA to extend in the second direction (e.g., the y direction or the −y direction). The first initialization voltage driver 15a may be disposed at one side of the peripheral area PA to extend in the second direction (e.g., the y direction or the −y direction). The second initialization voltage driver 15b may be disposed on the other side of the peripheral area PA to extend in the second direction (e.g., the y direction or the −y direction).

[0123] In an embodiment, the sub-pixel circuit PC (see FIG. 1 ) is configured to send a scan signal to the sub-pixel circuit PC disposed at one side of the display area DA. Figure 4The first signal line SL1 of the display area DA may be connected from the scan driver SDRV and extend in a first direction (eg, x direction or -x direction). The first signal line SL1 of the display area DA may be connected from the scan driver SDRV and extend in a first direction (eg, x direction or -x direction). Figure 4 ) may be connected from the scan driver SDRV and extend in a first direction (eg, an x ​​direction or a −x direction).

[0124] In an embodiment, the initialization voltage is sent to the sub-pixel circuit PC (see FIG. 1 ) disposed at one side of the display area DA. Figure 4 The first initialization voltage line VL1 of the display area DA may be connected from the first initialization voltage driver 15a and extend in a first direction (eg, x direction or -x direction). The initialization voltage is configured to be transmitted to the sub-pixel circuit PC (see FIG. Figure 4 ) may be connected from the second initialization voltage driver 15b and extend in the first direction (eg, the x direction or the −x direction).

[0125] In an embodiment, the first initialization voltage line VL1 and the first signal line SL1 may be disposed adjacent to each other, and the second initialization voltage line VL2 and the second signal line SL2 may be disposed adjacent to each other.

[0126] In an embodiment, the first signal line SL1 may have a first width t1 in the second direction (e.g., the y direction or the −y direction). The first width t1 of the first signal line SL1 may be continuously reduced from the scan driver SDRV toward the peripheral area PA. In other words, the first width t1 of the first signal line SL1 may be continuously increased from the peripheral area PA toward the scan driver SDRV. Since a portion of the first signal line SL1 adjacent to the scan driver SDRV has a large number of carriers emitted from the scan driver SDRV, in order to effectively transmit the carriers to the sub-pixel circuit PC (see Figure 4 ), the first width t1 of the portion of the first signal line SL1 adjacent to the scan driver SDRV may be greater than the first width t1 of the portion of the first signal line SL1 separated from the scan driver SDRV. In other words, in order to effectively transmit the carriers emitted from the scan driver SDRV to the sub-pixel circuit PC of the display area DA (see Figure 4 ), the first width t1 of the first signal line SL1 may be continuously reduced from the scan driver SDRV toward the peripheral area PA.

[0127] In an embodiment, the first initialization voltage line VL1 may have a second width t2 in a second direction (e.g., the y direction or the −y direction). The second width t2 of the first initialization voltage line VL1 may be continuously reduced from the first initialization voltage driver 15a toward the scan driver SDRV. In other words, the second width t2 of the first initialization voltage line VL1 may be continuously increased from the scan driver SDRV toward the first initialization voltage driver 15a. Since a portion of the first initialization voltage line VL1 adjacent to the first initialization voltage driver 15a has a large number of carriers emitted from the first initialization voltage driver 15a, in order to effectively send the carriers to the sub-pixel circuit PC (see Figure 4 ), the second width t2 of the portion of the first initialization voltage line VL1 adjacent to the first initialization voltage driver 15a may be greater than the second width t2 of the portion of the first initialization voltage line VL1 separated from the first initialization voltage driver 15a. In other words, in order to effectively transmit the carriers emitted from the first initialization voltage driver 15a to the sub-pixel circuit PC of the display area DA (see Figure 4 ), the second width t2 of the first initialization voltage line VL1 may be continuously reduced from the first initialization voltage driver 15a toward the scan driver SDRV.

[0128] In an embodiment, when the substrate 100 (see Figure 4 ) viewing the display device 1 in the vertical direction (see Figure 1 ), the first width t1 of the first signal line SL1 and the second width t2 of the first initialization voltage line VL1 (the first signal line SL1 and the first initialization voltage line VL1 are adjacent to each other) can be constant at any point in the first direction (e.g., the x direction or the -x direction) of the display device 1. This is because the amount of carriers emitted from the first initialization voltage driver 15a and the amount of carriers emitted from the scan driver SDRV are the same.

[0129] In an embodiment, the first wiring portion L1 may include a first signal line SL1 and a first initialization voltage line VL1. A plurality of first wiring portions L1 may be disposed in one line at one side of the display area DA, spaced apart from each other at regular intervals.

[0130] In an embodiment, a second initialization voltage line VL2 extending from the second initialization voltage driver 15b in a first direction (e.g., x direction or -x direction) and a second signal line SL2 extending from the scan driver SDRV in a first direction (e.g., x direction or -x direction) may be disposed at the other side of the display area DA. The second signal line SL2 may have a third width t3 in a second direction (e.g., y direction or -y direction). The third width t3 of the second signal line SL2 may be continuously reduced from the scan driver SDRV toward the peripheral area PA. In other words, the third width t3 of the second signal line SL2 may be continuously increased from the peripheral area PA toward the scan driver SDRV.

[0131] In an embodiment, the second initialization voltage line VL2 may have a fourth width t4 in the second direction (e.g., the y direction or the -y direction). The fourth width t4 of the second initialization voltage line VL2 may be continuously reduced from the second initialization voltage driver 15b toward the scan driver SDRV. In other words, the fourth width t4 of the second initialization voltage line VL2 may be continuously increased from the scan driver SDRV toward the second initialization voltage driver 15b.

[0132] In an embodiment, when the substrate 100 (see Figure 4 ) viewing the display device 1 in the vertical direction (see Figure 1 ), the third width t3 of the second signal line SL2 and the fourth width t4 of the second initialization voltage line VL2 (the second signal line SL2 and the second initialization voltage line VL2 are adjacent to each other) can be constant at any point in the first direction (for example, the x direction or the -x direction) of the display device 1.

[0133] In an embodiment, the second wiring portion L2 may include a second signal line SL2 and a second initialization voltage line VL2. A plurality of second wiring portions L2 may be disposed in one line at the other side of the display area DA, spaced apart from each other at regular intervals.

[0134] In the embodiment of the switching transistor, with the gate electrode GE (see Figure 2 ) overlapping semiconductor layers Act (see Figure 2 ) increases the ratio of the length to the width, and the switching capability of the switching transistor can be improved. In the embodiment of the switching transistor provided separately from the scan driver SDRV, since the signal line SL provided separately from the scan driver SDRV has a small width in the second direction (for example, the y direction or the -y direction), the semiconductor layer Act (see Figure 2 ) with the substrate 100 (see Figure 2) in order to improve the switching capability of the switching transistor without increasing the thickness in the direction perpendicular to the substrate 100. In other words, the width of the semiconductor layer Act of the switching transistor disposed separately from the scan driver SDRV in the direction perpendicular to the substrate 100 may be smaller than the width of the semiconductor layer Act of the switching transistor disposed adjacent to the scan driver SDRV in the direction perpendicular to the substrate 100.

[0135] In an embodiment, the resolution of the display device 1 may be improved by disposing the scan driver SDRV at the center of the display area DA to reduce the area of ​​the peripheral area PA where the subpixels PX are not disposed.

[0136] In addition, in an embodiment, the width of the signal line SL connected from the scan driver SDRV in the second direction (for example, the y direction or the -y direction) can be continuously reduced from the scan driver SDRV toward the peripheral area PA, and the width of the initialization voltage line VL connected from the initialization voltage driver 15 in the second direction (for example, the y direction or the -y direction) can be continuously reduced from the initialization voltage driver 15 toward the scan driver SDRV.

[0137] In an embodiment, since the portions of the signal line SL and the initialization voltage line VL respectively set to be adjacent to the scan driver SDRV and the initialization voltage driver 15 have a large number of carriers emitted from the scan driver SDRV and the initialization voltage driver 15, respectively, when the width of the portions of the signal line SL and the initialization voltage line VL respectively set to be adjacent to the scan driver SDRV and the initialization voltage driver 15 in the second direction (for example, the y direction or the -y direction) is greater than the width of the portions of the signal line SL and the initialization voltage line VL respectively set to be separated from the scan driver SDRV and the initialization voltage driver 15 in the second direction (for example, the y direction or the -y direction), the carriers can be effectively sent to the sub-pixel circuit PC, and therefore, the reliability and resolution of the display device 1 can be improved.

[0138] According to one or more embodiments as described above, a display device with improved reliability and resolution may be implemented.

[0139] It should be understood that the embodiments described herein should be considered in a descriptive sense only, and not for the purpose of limitation. The description of the features or aspects within each embodiment should generally be considered as other similar features or aspects that can be used in other embodiments. Although one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims. Therefore, the scope of the various embodiments of the present disclosure should be interpreted as including all changes or modifications obtained from the technical ideas of the various embodiments of the present disclosure in addition to the embodiments disclosed herein. In addition, embodiments or parts of embodiments may be combined in whole or in part without departing from the scope of the present disclosure.

Claims

1. A display device, characterized in that: include: a substrate including a display area and a peripheral area outside the display area; a scan driver disposed in a central portion of the display area and extending in a first direction; as well as a first signal line connected to the scan driver and extending on one side of the display area in a second direction crossing the first direction, The first signal line has a first width in the first direction, wherein the first width decreases as the first signal line extends from the scan driver toward the peripheral area.

2. The display device according to claim 1, characterized in that Further including: a first initialization voltage driver disposed on one side of the peripheral area and extending in the first direction; as well as a first initialization voltage line connected to the first initialization voltage driver and extending in the second direction, The first initialization voltage line has a second width in the first direction, wherein the second width decreases as the first initialization voltage line extends from the first initialization voltage driver toward the scan driver.

3. The display device according to claim 2, characterized in that: The first width of the first signal line increases as the first signal line extends from the peripheral area toward the scan driver, and wherein the second width of the first initialization voltage line increases as the first initialization voltage line extends from the scan driver toward the first initialization voltage driver.

4. The display device according to claim 2, characterized in that: When the display device is viewed in a direction perpendicular to the substrate, a sum of the first width of the first signal line and the second width of the first initialization voltage line is constant at any point of the substrate in the second direction.

5. The display device according to claim 1, characterized in that Further including: a second signal line connected to the scan driver and extending on the other side of the display area in the second direction, The second signal line has a third width in the first direction, and the third width decreases as the second signal line extends from the scan driver toward the peripheral area.

6. The display device according to claim 5, characterized in that: Further including: a second initialization voltage driver disposed on the other side of the peripheral area and extending in the first direction; as well as a second initialization voltage line connected to the second initialization voltage driver and extending in the second direction, The second initialization voltage line has a fourth width in the first direction, wherein the fourth width decreases as the second initialization voltage line extends from the second initialization voltage driver toward the scan driver.

7. The display device according to claim 6, characterized in that: The third width of the second signal line increases as the second signal line extends from the peripheral area toward the scan driver, and The fourth width of the second initialization voltage line increases continuously as the second initialization voltage line extends from the scan driver toward the second initialization voltage driver.

8. The display device according to claim 6, characterized in that: When the display device is viewed in a direction perpendicular to the substrate, a sum of the third width of the second signal line and the fourth width of the second initialization voltage line is constant at any point of the substrate in the second direction.

9. A display device, characterized in that: include: a substrate including a display area and a peripheral area outside the display area; a scan driver disposed in a central portion of the display area and extending in a first direction; a first initialization voltage driver disposed in the peripheral region and extending in the first direction; a first signal line connected to the scan driver, extending in a second direction crossing the first direction, and having a first width in the first direction; as well as a first initialization voltage line, the first initialization voltage line being connected to the first initialization voltage driver, extending in the second direction and having a second width in the first direction, When the display device is viewed in a direction perpendicular to the substrate, a sum of the first width and the second width is constant at any point of the substrate in the second direction.

10. The display device according to claim 9, characterized in that: The first width of the first signal line decreases as the first signal line extends from the scan driver toward the peripheral area, and The second width of the first initialization voltage line decreases continuously as the first initialization voltage line extends from the first initialization voltage driver toward the scan driver.

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