Universal processor interface test equipment supporting master-slave mode

Abstract

The utility model discloses a general processor interface test device supporting a master-slave mode, which comprises a general processor interface test device, an interface circuit and a configuration power supply, and is characterized in that the general processor interface test device is an ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array) or CPLD (Complex Programmable Logic Device) integrated circuit module, and the interface circuit comprises an upper computer interface and a to-be-tested board interface; wherein the universal processor interface test equipment is connected to the interface circuit through a pin or a cable, and the configuration power supply is connected to the universal processor interface test equipment and the interface circuit through a pin or a cable. Wherein the upper computer is connected to the upper computer terminal, and the to-be-tested board interface is connected to the processor, the PCB single board or the ASIC / FPGA integrated circuit. According to the circuit, a read-write communication instruction is sent through the upper computer, data communication between the general processor interface test equipment and the processor / single board is achieved, and therefore the function test of the processor / single board data communication interface is completed.

Description

Technical Field

[0001] The utility model belongs to the technical field of avionics, and in particular relates to a universal processor interface testing device supporting a master-slave mode. Background Art

[0002] With the continuous increase in the output and complexity of aircraft platform circuit equipment, the requirements for ground test accuracy, comprehensiveness and test efficiency of airborne equipment are constantly increasing. Traditional airborne computer / single board port communication testing develops separate port communication test equipment based on the unique port communication timing of each device. This method is costly, has poor reusability, and cannot test port communication boundary timing parameters, which brings practical difficulties to ground testing of airborne equipment. Summary of the invention

[0003] The purpose of the present invention is to provide a universal processor interface test device supporting master-slave mode to solve the problems of poor reusability and single test of existing computer / single board port data communication test devices.

[0004] The present invention is implemented by adopting the following technical scheme.

[0005] The present invention provides a general processor interface test device supporting a master-slave mode, the test device comprising: a general processor interface test integrated circuit module 1, an interface circuit 2 and a configuration power supply 3, the interface circuit 2 comprising a host computer interface 4 and a board to be tested interface 5;

[0006] The universal processor interface test integrated circuit module 1 is connected to the host computer interface 4 and the test board interface 5 respectively, and the power supply 3 is configured to provide voltage for the universal processor interface test integrated circuit module 1, the host computer interface 4 and the test board interface 5.

[0007] Furthermore, the universal processor interface test integrated circuit module 1 comprises a host computer communication port with fixed timing and a board-to-be-tested communication port with timing parameters configurable by registers.

[0008] Furthermore, the host computer communication port is connected to the host computer outside the general processor interface test device through the host computer interface 4; the board under test communication port is connected to the board under test outside the general processor interface test device through the board under test interface 5.

[0009] Furthermore, the timing parameters of the host computer communication port in the universal processor interface test integrated circuit module 1 are not configurable, and the external host computer needs to use a parallel communication protocol with a specific timing to communicate with the universal processor interface test integrated circuit module 1 .

[0010] Furthermore, the communication port of the board under test in the universal processor interface test integrated circuit module 1 has two working modes, corresponding to the board under test working in the host computer mode and the slave computer mode respectively, and the timing parameters of the two working modes are configurable.

[0011] Furthermore, the universal processor interface test integrated circuit module 1 is an ASIC or FPGA or CPLD integrated circuit module.

[0012] Compared with the prior art, the beneficial effects of the present invention are: the processor interface test equipment can realize computer / single board port data communication tests with different timing requirements through the method of timing parameter configuration; the computer / single board port data communication tests in different working states can be realized through the method of working mode configuration, which can solve the problems of poor reusability and single test of existing computer / single board port data communication test equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a structural schematic diagram of a general processor interface testing device supporting master-slave mode of the present invention;

[0014] Figure 2 Write mode timing diagram for the host computer;

[0015] Figure 3 It is the timing diagram of the upper machine reading mode;

[0016] Figure 4 Write mode timing diagram for the lower computer;

[0017] Figure 5 This is the timing diagram of the lower machine reading mode. DETAILED DESCRIPTION

[0018] The following will provide a clear and complete description with reference to the accompanying drawings in the embodiments of the present invention.

[0019] Combination Figure 1 The present invention provides a universal processor interface test device supporting a master-slave mode, comprising a universal processor interface test integrated circuit module 1, an interface circuit 2 and a configuration power supply 3, wherein the universal processor interface test device 1 is an ASIC or FPGA or CPLD integrated circuit module, and the interface circuit 2 comprises a host computer interface 4 and a board-to-be-tested interface 5;

[0020] The universal processor interface test integrated circuit module 1 is connected to the interface circuit 2 , and the power supply 3 is configured to provide voltage to the test board interface 1 and the interface circuit 2 .

[0021] The general processor interface test integrated circuit module 1 is an ASIC or FPGA or CPLD integrated circuit module, and the integrated circuit module includes a host computer communication port with fixed timing and a communication port of the board to be tested whose timing parameters can be configured by registers. In the integrated circuit module, the host computer communication port is connected to the host computer interface 4 in the interface circuit 2, and the communication port of the board to be tested is connected to the interface 5 of the board to be tested.

[0022] The timing parameters of the host computer communication port in the integrated circuit module cannot be configured. The external host computer needs to use a parallel communication protocol with a specific timing to communicate with the general processor interface test integrated circuit module 1. There are two working modes for the communication port of the board under test in the integrated circuit module, corresponding to the board under test working in the host computer mode and the slave computer mode respectively, and the timing parameters of the two working modes are configurable. The interface signal and timing are shown in the attached Figure 2 , 3, 4, 5.

[0023] The method of using the universal processor interface test equipment in master-slave mode is as follows:

[0024] (1) Turn on the power of the general processor interface test equipment;

[0025] (2) External host computer configures timing parameter registers;

[0026] (3) External host computer configures the working status register;

[0027] (4) The external host computer inputs read and write instructions to control the processor interface test device (1) to communicate with the board under test, and determines whether the port of the board under test is normal based on the read and write test results.

[0028] Compared with the prior art, the beneficial effects of the present invention are: the processor interface test equipment can realize computer / single board port data communication tests with different timing requirements through the method of timing parameter configuration; the computer / single board port data communication tests in different working states can be realized through the method of working mode configuration, which can solve the problems of poor reusability and single test of existing computer / single board port data communication test equipment.

Claims

1. A general processor interface test device supporting master-slave mode, characterized in that: The test equipment comprises: a general processor interface test integrated circuit module (1), an interface circuit (2) and a configuration power supply (3); the interface circuit (2) comprises a host computer interface (4) and a test board interface (5); The universal processor interface test integrated circuit module (1) is connected to the host computer interface (4) and the interface of the board to be tested (5) respectively, and a power supply (3) is configured to provide voltage to the universal processor interface test integrated circuit module (1), the host computer interface (4) and the interface of the board to be tested (5); The universal processor interface test integrated circuit module (1) comprises a host computer communication port with fixed timing and a test board communication port with register-configurable timing parameters; The host computer communication port is connected to a host computer outside the general processor interface test device via a host computer interface (4); the test board communication port is connected to a test board outside the general processor interface test device via a test board interface (5).

2. A general processor interface test device supporting master-slave mode according to claim 1, characterized in that: The timing parameters of the host computer communication port in the universal processor interface test integrated circuit module (1) are not configurable, and the external host computer needs to use a parallel communication protocol with a specific timing to communicate with the universal processor interface test integrated circuit module (1).

3. A general processor interface test device supporting master-slave mode according to claim 2, characterized in that: The communication port of the board under test in the universal processor interface test integrated circuit module (1) has two working modes, corresponding to the board under test working in the upper computer mode and the lower computer mode respectively, and the timing parameters of the two working modes are configurable.

4. A general processor interface test device supporting master-slave mode according to claim 3, characterized in that: The universal processor interface test integrated circuit module (1) is an ASIC or FPGA or CPLD integrated circuit module.

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