Lead frame structure and semiconductor packaging structure

Abstract

A lead frame structure and a semiconductor package structure wherein the lead frame structure comprises: a lead frame formed by a graphical etching process, the lead frame comprising a first surface and a second surface opposite to each other, the first surface and the second surface are rough surfaces formed by electroplating treatment before the graphical etching process; the electroplated layers are positioned on the first surface and the second surface; and the through holes are exposed out of the surface of the side wall of the lead frame. According to the lead frame structure, the side wall part of the lead frame is exposed by adopting the graphical etching process, so that the tightness of connection between the lead frame and the plastic package layer is improved, and the use performance and the yield of the lead frame are improved.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor packaging, in particular to a lead frame structure and a semiconductor packaging structure. Background Art

[0002] As the chip carrier of integrated circuits, the lead frame is a key structural component that uses bonding materials to achieve electrical connection between the internal circuit lead ends of the chip and the external leads to form an electrical circuit. It serves as a bridge to connect with external wires. Lead frames are required in most semiconductor integrated blocks and are an important basic material in the electronic information industry.

[0003] At present, the electroplating layer in the lead frame is formed on the surface of the lead frame after the graphic etching process, so the subsequently formed plastic sealing layer is formed on the surface of the electroplating layer. However, the connection tightness between the plastic sealing layer and the electroplating layer is not high, and then the lead frame and the plastic sealing layer will be delaminated during the operation, which reduces the tightness of the connection between the lead frame and the plastic sealing layer and affects the performance. Utility Model Content

[0004] The technical problem solved by the utility model is to provide a lead frame structure and a semiconductor packaging structure so as to make the connection between the lead frame and the electroplating layer and between the lead frame and the plastic sealing layer tighter.

[0005] In order to solve the above technical problems, an embodiment of the utility model provides a lead frame structure, including: a lead frame formed by a graphic etching process, the lead frame including a first surface and a second surface relative to each other, the first surface and the second surface are rough surfaces formed by electroplating treatment before the graphic etching process; an electroplating layer located on the first surface and the second surface; and a plurality of through holes, the through holes exposing the side wall surface of the lead frame.

[0006] Optionally, the roughness range of the first surface is 2 to 7, and the roughness is the ratio of the surface area of ​​the first surface before the electroplating treatment to that after the electroplating treatment; the roughness range of the second surface is 2 to 7, and the roughness is the ratio of the area of ​​the second surface before the electroplating treatment to that after the electroplating treatment.

[0007] Optionally, the electroplating layer includes a third surface and a fourth surface opposite to each other, and the third surface is in contact with the first surface.

[0008] Optionally, the roughness range of the fourth surface is 2 to 7, and the roughness of the fourth surface is the ratio of the area of ​​the fourth surface before the electroplating treatment to the area of ​​the fourth surface after the electroplating treatment.

[0009] Optionally, the electroplating layer includes a single-layer electroplating layer or a multi-layer electroplating layer.

[0010] Optionally, the number of layers of the electroplating layer ranges from 1 to 4 layers.

[0011] Optionally, the single-layer electroplated layer is one of a copper-plated layer, a nickel-plated layer, a palladium-plated layer, a gold-plated layer and a silver-plated layer.

[0012] Optionally, the multi-layer electroplating layer is a combination of multiple ones of a copper plating layer, a nickel plating layer, a palladium plating layer, a gold plating layer and a silver plating layer.

[0013] Optionally, the multi-layer electroplating layer includes: a nickel-plated layer, a silver-plated layer, a combination of a nickel-plated layer and a palladium-plated layer, a combination of a nickel-plated layer and a gold-plated layer, a combination of a nickel-plated layer, a palladium-plated layer and a gold-plated layer, and a combination of a nickel-plated layer, a palladium-plated layer, a silver-plated layer and a gold-plated layer.

[0014] Optionally, the lead frame includes a copper frame.

[0015] Optionally, the lead frame further includes a plurality of through holes.

[0016] Optionally, the roughness of the side wall surface of the through hole in the lead frame ranges from 1.1 to 4, and the roughness of the side wall surface of the through hole in the lead frame is the ratio of the area of ​​the side wall surface of the through hole before the electroplating treatment to that after the electroplating treatment.

[0017] Optionally, the roughness of the first surface and the second surface is greater than or equal to the roughness of the side wall surface of the through hole in the lead frame; the roughness of the fourth surface is greater than or equal to the roughness of the side wall surface of the through hole in the lead frame.

[0018] The utility model also provides a semiconductor packaging structure, comprising: a lead frame, the lead frame comprising a first surface and a second surface relative to each other, the first surface and the second surface being rough surfaces formed by electroplating before a graphic etching process; an electroplating layer located on the first surface and the second surface; a chip located on the surface of the electroplating layer, the chip being electrically connected to the lead frame; and a plastic sealing layer located on the surface of the electroplating layer and the surface of the chip.

[0019] Optionally, the electroplating layer includes a third surface and a fourth surface opposite to each other, and the third surface is in contact with the first surface.

[0020] Optionally, the roughness range of the first surface is 2 to 7, and the roughness is the ratio of the surface area of ​​the first surface before the electroplating treatment to that after the electroplating treatment; the roughness range of the second surface is 2 to 7, and the roughness is the ratio of the area of ​​the second surface before the electroplating treatment to that after the electroplating treatment.

[0021] Optionally, the roughness of the fourth surface ranges from 2 to 7, and the roughness is the ratio of the area of ​​the fourth surface before the electroplating treatment to the area of ​​the fourth surface after the electroplating treatment.

[0022] Optionally, the roughness of the side wall surface of the through hole in the lead frame ranges from 1.1 to 4, and the roughness is the ratio of the area of ​​the side wall surface of the through hole before the electroplating treatment to that after the electroplating treatment.

[0023] Optionally, the roughness of the first surface and the second surface is greater than or equal to the roughness of the side wall surface of the through hole in the lead frame; the roughness of the fourth surface is greater than or equal to the roughness of the side wall surface of the through hole in the lead frame.

[0024] Optionally, the electroplating layer includes a single-layer electroplating layer or a multi-layer electroplating layer.

[0025] Optionally, the number of layers of the electroplating layer ranges from 1 to 4 layers.

[0026] Optionally, the single-layer electroplated layer is one of a copper-plated layer, a nickel-plated layer, a palladium-plated layer and a gold-plated layer.

[0027] Optionally, the multi-layer electroplating layer is a combination of multiple ones of a copper plating layer, a nickel plating layer, a palladium plating layer, a gold plating layer and a silver plating layer.

[0028] Optionally, the multi-layer electroplating layer includes: a nickel-plated layer, a silver-plated layer, a combination of a nickel-plated layer and a palladium-plated layer, a combination of a nickel-plated layer and a gold-plated layer, a combination of a nickel-plated layer, a palladium-plated layer and a gold-plated layer, and a combination of a nickel-plated layer, a palladium-plated layer, a silver-plated layer and a gold-plated layer.

[0029] Optionally, the semiconductor packaging structure further includes: a plurality of interconnect structures located between the chip surface and the electroplating layer, the interconnect structures being electrically connected to the chip and the electroplating layer respectively.

[0030] Compared with the prior art, the technical solution of the embodiment of the utility model has the following beneficial effects:

[0031] In the lead frame structure provided by the utility model, the rough surfaces of the first surface and the second surface are formed by electroplating before the graphic etching process, so that the connection between the electroplating layer and the first surface and the second surface is tighter, and the risk of process deformation of the lead frame is reduced and the uniformity of the roughening of the first surface and the second surface is ensured; after the graphic etching process, the side wall portion of the lead frame is exposed, which increases the tightness of the connection between the lead frame and the subsequently formed plastic sealing layer, and improves the performance and yield of the lead frame.

[0032] Furthermore, the utility model uses electroplating to form a rough surface on the side wall surface of the lead frame, thereby increasing the contact area between the lead frame and the subsequently formed plastic encapsulation layer, thereby increasing the tightness of the connection between the lead frame and the plastic encapsulation layer, and improving the performance and yield of the lead frame.

[0033] In the semiconductor packaging structure provided by the utility model, the rough surfaces of the first surface and the second surface are formed by electroplating before the graphic etching process, so that the connection between the electroplating layer and the first surface and the second surface is tighter, and the risk of process deformation of the lead frame is reduced and the uniformity of the roughening of the first surface and the second surface is ensured; after the graphic etching process, the side wall portion of the lead frame is exposed, the area of ​​the lead frame and the subsequently formed plastic sealing layer is increased, thereby increasing the tightness of the connection between the lead frame and the plastic sealing layer, and improving the performance and yield of the lead frame.

[0034] Furthermore, the technical solution of the utility model adopts electroplating to form the rough surface of the side wall of the lead frame, thereby increasing the contact area between the lead frame and the subsequently formed plastic encapsulation layer, thereby increasing the tightness of the connection between the lead frame and the plastic encapsulation layer, and improving the performance and yield of the lead frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic diagram of a semiconductor packaging structure;

[0036] Figures 2 to 13 It is a structural schematic diagram of the formation process of the lead frame structure in one embodiment of the utility model;

[0037] Figures 14 to 16 is a structural schematic diagram of a formation process of a semiconductor packaging structure in another embodiment of the present invention;

[0038] Figures 17 to 20 It is a planar structural diagram of the first surface or the second surface before and after the electroplating treatment in one embodiment of the utility model. DETAILED DESCRIPTION

[0039] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0040] As described in the background art, it is necessary to make the connection between the frame and the electroplating layer and between the lead frame and the mold tighter.

[0041] Please refer to Figure 1 The semiconductor packaging structure includes: a lead frame 100; and an electroplating layer 101 located on the surface of the lead frame.

[0042] In the above scheme, the electroplating layer 101 is formed directly on the surface of the lead frame 100. Since the lead frame 100 is mostly made of metal material and its surface is relatively smooth, directly forming the electroplating layer 101 on the surface of the lead frame 100 will cause the electroplating layer 101 to be loosely connected to the surface of the lead frame 100, and then stratification will occur during operation, affecting the performance.

[0043] In addition, the electroplating layer in the above scheme covers the surface of the lead frame, and the subsequently formed plastic sealing layer is formed on the surface of the electroplating layer, but the connection tightness between the plastic sealing layer and the electroplating layer is not high, and then during the operation, the lead frame and the plastic sealing layer will be delaminated, which reduces the tightness of the connection between the lead frame and the plastic sealing layer and affects the performance.

[0044] In order to solve the above-mentioned technical problems, in the lead frame structure and the semiconductor packaging structure provided by the technical solution of the utility model, the surface area of ​​the frame is increased by roughening the first surface and / or the second surface of the frame, thereby improving the tightness of the connection between the electroplating layer and the frame, the performance of the lead frame and the yield of the lead frame; and after the graphic etching process, the side wall portion of the lead frame is exposed, thereby increasing the tightness of the connection between the lead frame and the plastic packaging layer, and improving the performance and yield of the lead frame.

[0045] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0046] Figures 2 to 10 It is a structural schematic diagram of a lead frame structure in one embodiment of the utility model.

[0047] Please refer to Figure 2 , an initial lead frame 200 is provided, wherein the initial lead frame 200 includes an initial first surface A and an initial second surface B.

[0048] The initial lead frame 200 is used to provide a material basis for a subsequently formed electroplating layer 206 .

[0049] The thickness of the initial lead frame 200 ranges from 0.1 mm to 2 mm.

[0050] The initial lead frame 200 includes a copper frame.

[0051] Please refer to Figure 3 , performing a first roughening treatment on the initial first surface A and the initial second surface B to form a first surface 201 and a second surface 202 .

[0052] In this embodiment, after the first roughening treatment, a plurality of protrusions raised relative to the reference plane and depressions located between the protrusions are formed on the first surface 201; a plurality of protrusions raised relative to the reference plane and depressions located between the protrusions are also formed on the second surface 202; the reference plane is a plane parallel to the initial first surface A or the initial second surface B.

[0053] In one embodiment, the top dimension of the recess is larger than the bottom dimension, and the side wall of the recess is inclined relative to the reference plane; in another embodiment, the top dimension of the recess is smaller than the bottom dimension, and the side wall of the recess is inclined relative to the reference plane; in other embodiments, the top dimension of the recess is equal to the bottom dimension, and the side wall of the recess is perpendicular to the reference plane.

[0054] The first roughening treatment method includes electroplating.

[0055] The roughness of the first surface 201 is in the range of 2 to 7.

[0056] The roughness of the first surface 201 is the ratio of the surface area of ​​the first surface 201 before the electroplating treatment to the surface area of ​​the first surface 201 after the electroplating treatment.

[0057] The roughness of the second surface 202 is in the range of 2 to 7.

[0058] The roughness of the second surface 202 is the ratio of the area of ​​the second surface 202 before the electroplating process to the area of ​​the second surface 202 after the electroplating process.

[0059] The following will be combined Figures 17 to 20 The roughness in this embodiment is described. Specifically, Figures 17 to 20 for Figure 3 A partial enlarged view of area C in the middle, wherein area C is a partial enlarged view of any cross section of the initial lead frame perpendicular to the reference plane, Fig. 20 The structure of the rough surface in region C. The curve only represents the rough surface. For the specific shape of the rough surface, please refer to Figures 17 to 19 .

[0060] Please refer to Fig.17 In one embodiment, the top dimension of the recess is larger than the bottom dimension, the sidewall of the recess is inclined relative to the reference plane, and the first surface is Fig.17 The first surface is shown as line A1, and the reference surface is shown as line B. In this embodiment, the roughness of the first surface is the ratio of the length of line A1 to the length of line B.

[0061] Please refer to Fig.18In another embodiment, the top dimension of the recess is equal to the bottom dimension, the sidewall of the recess is perpendicular to the reference plane, and the first surface is Fig.18 The first surface is shown as line A2, and the reference surface is shown as line B. In this embodiment, the roughness of the first surface is the ratio of the length of line A2 to the length of line B.

[0062] Please refer to Fig.19 In other embodiments, the top dimension of the recess is smaller than the bottom dimension, the sidewall of the recess is inclined relative to the reference plane, and the first surface is Fig.19 The first surface is shown as line A3, and the reference surface is shown as line B. In this embodiment, the roughness of the first surface is the ratio of the length of line A3 to the length of line B.

[0063] Please refer to Figure 4 , a photoresist layer 203 is formed on the first surface 201 and the second surface 202 .

[0064] Please refer to Figure 5 , performing exposure and development processing on the photoresist layer 203; removing the unexposed photoresist layer 203 until the first surface 201 is exposed, forming a region to be electroplated 205 and a first mask layer 204.

[0065] The photoresist layer 203 is used to form electroplating mask patterns on the first surface 201 and the second surface 202 .

[0066] Please refer to Figure 6 , using the first mask layer 204 as a mask, forming an electroplating layer 206 on the area to be electroplated 205 .

[0067] The electroplating layer 206 includes a third surface and a fourth surface 2061 opposite to each other, and the third surface contacts the first surface 201 .

[0068] The roughness of the fourth surface 2061 is in the range of 2 to 7.

[0069] The roughness of the fourth surface 2061 is characterized by the ratio of the surface area of ​​the fourth surface 2061 after roughening to the surface area of ​​the fourth surface 2061 before roughening.

[0070] The roughness of the fourth surface 2061 is consistent with the roughness of the first surface 201 or the second surface 202 .

[0071] In the above scheme, the description of the roughness of the fourth surface 2061 is consistent with the description of the roughness of the first surface or the second surface 202 mentioned above, and will not be repeated here.

[0072] The electroplating layer 206 includes a single-layer electroplating layer 206 or a multi-layer electroplating layer 206 .

[0073] The single-layer electroplating layer 206 is one of a copper-plated layer, a nickel-plated layer, a palladium-plated layer, a gold-plated layer and a silver-plated layer.

[0074] The number of layers of the electroplating layer 206 ranges from 1 layer to 4 layers.

[0075] In this embodiment, the number of layers of the electroplating layer 206 is 1.

[0076] In other embodiments, the number of layers of the electroplating layer 206 is 2 or 3.

[0077] The multi-layer electroplating layer 206 is a combination of a copper plating layer, a nickel plating layer, a palladium plating layer, a gold plating layer and a silver plating layer.

[0078] The multi-layer electroplating layer 206 includes: a nickel-plated layer, a silver-plated layer, a combination of a nickel-plated layer and a palladium-plated layer, a combination of a nickel-plated layer and a gold-plated layer, a combination of a nickel-plated layer, a palladium-plated layer and a gold-plated layer, and a combination of a nickel-plated layer, a palladium-plated layer, a silver-plated layer and a gold-plated layer.

[0079] In this embodiment, the multi-layer electroplating layer 206 is a combination of a nickel-plated layer, a palladium-plated layer and a gold-plated layer.

[0080] In other embodiments, the multi-layer electroplating layer 206 is a combination of a nickel plating layer, a palladium plating layer, a silver plating layer, and a gold plating layer.

[0081] The thickness of the electroplating layer 206 is in a range of 0.05 micrometers to 5 micrometers.

[0082] Please refer to Figure 7 , remove the first mask layer 204 until the first surface 201 and the second surface 202 are exposed.

[0083] Please refer to Figure 8 , forming a second mask layer (not shown in the figure) on the surface of the electroplating layer 206, wherein the second mask layer (not shown in the figure) exposes a portion of the first surface 201 and the second surface 202; using the second mask layer (not shown in the figure) as a mask, etching the first surface 201 or the second surface 202 to form a plurality of through holes 208 and a lead frame 207; performing a second roughening treatment on the side wall surface 209 of the through hole 208; and removing the second mask layer (not shown in the figure).

[0084] The second mask layer (not shown in the figure) is used to form a protective pattern of an etching mask to prevent the electroplating layer 206 from being damaged in subsequent etching steps.

[0085] The method for forming the through holes 208 includes: using the second mask layer (not shown in the figure) as a mask, etching the first surface 201 to form a plurality of through holes 208, wherein the openings of the through holes 208 face the first surface 201; and the through holes 208 expose the side wall surface 209 of the lead frame.

[0086] The method for forming the through holes 208 further includes: using the second mask layer (not shown) as a mask, etching the second surface 202 to form a plurality of through holes 208 , wherein the openings of the through holes 208 face the second surface 202 .

[0087] The opening diameter of the through hole 208 on the first surface 201 is different from the opening diameter of the through hole 208 on the second surface 202 .

[0088] In this embodiment, the range of etching the through hole 208 from the first surface 201 and the second surface 202 is different from the range of the to-be-electroplated area 205 .

[0089] Please refer to Fig. 9 as well as Fig.10 , Fig.10 is a top view of 9. Fig. 9 yes Fig.10 A schematic structural diagram along the section line AA1 shows that the side wall surface 209 of the through hole 208 is subjected to a second roughening treatment.

[0090] The second roughening treatment method includes electroplating.

[0091] The roughness of the sidewall surface 209 of the through hole 208 is in the range of 1.1 to 4.

[0092] The roughness of the side wall surface 209 of the through hole 208 is the ratio of the surface area before the electroplating process to the surface area after the electroplating process.

[0093] In this embodiment, the roughness of the first surface 201 and the second surface 202 is greater than the roughness of the side wall surface 209 of the through hole 208 .

[0094] In this embodiment, the roughness of the fourth surface 2061 is greater than the roughness of the sidewall surface 209 of the through hole 208 .

[0095] Please continue to refer to Fig. 9The technical solution of the utility model also provides a lead frame 207 structure, including: a lead frame 207 formed by a graphic etching process, the lead frame 207 includes a first surface 201 and a second surface 202 relative to each other, the first surface 201 and the second surface 202 are rough surfaces formed by electroplating treatment before the graphic etching process; an electroplating layer 206 located on the first surface 201 and the second surface 202; a plurality of through holes 208, the through holes 208 exposing the side wall surface 209 of the lead frame.

[0096] In this embodiment, the lead frame 207 is used to provide a material basis for the subsequently formed electroplating layer 206 .

[0097] In this embodiment, the thickness of the lead frame 207 ranges from 0.1 mm to 2 mm.

[0098] In this embodiment, the lead frame 207 includes a copper frame.

[0099] In this embodiment, the chip 300 includes a functional surface a and a non-functional surface b opposite to each other. The functional surface a exposes a conductive pad 301 , and an interconnection structure is provided on the conductive pad 301 .

[0100] In this embodiment, the roughness range of the first surface 201 is 2 to 7, and the roughness is the ratio of the surface area of ​​the first surface 201 before the electroplating treatment to that after the electroplating treatment; the roughness range of the second surface 202 is 2 to 7, and the roughness is the ratio of the area of ​​the second surface 202 before the electroplating treatment to that after the electroplating treatment.

[0101] In this embodiment, the electroplating layer 206 includes a third surface and a fourth surface 2061 opposite to each other, and the third surface is in contact with the first surface 201 .

[0102] In this embodiment, the roughness of the fourth surface 2061 ranges from 2 to 7, and the roughness of the fourth surface 2061 is the ratio of the area of ​​the fourth surface 2061 before the electroplating treatment to the area of ​​the fourth surface 2061 after the electroplating treatment.

[0103] In this embodiment, the roughness of the fourth surface 2061 is consistent with the roughness of the first surface 201 or the second surface 202 .

[0104] The electroplating layer 206 includes a single-layer electroplating layer 206 or a multi-layer electroplating layer 206 .

[0105] The single-layer electroplating layer 206 is one of a copper-plated layer, a nickel-plated layer, a palladium-plated layer, a gold-plated layer and a silver-plated layer.

[0106] The number of layers of the electroplating layer 206 ranges from 1 layer to 4 layers.

[0107] In this embodiment, the number of layers of the electroplating layer 206 is 1.

[0108] In other embodiments, the number of layers of the electroplating layer 206 is 2 or 3.

[0109] In this embodiment, the multi-layer electroplating layer 206 is a combination of multiple layers selected from the group consisting of a nickel plating layer, a palladium plating layer, a gold plating layer and a silver plating layer.

[0110] The multi-layer electroplating layer 206 includes: a copper plated layer, a nickel plated layer, a silver plated layer, a combination of a nickel plated layer and a palladium plated layer, a combination of a nickel plated layer and a gold plated layer, a combination of a nickel plated layer, a palladium plated layer and a gold plated layer, and a combination of a nickel plated layer, a palladium plated layer, a silver plated layer and a gold plated layer.

[0111] In this embodiment, the multi-layer electroplating layer 206 is a combination of a nickel-plated layer, a palladium-plated layer and a gold-plated layer.

[0112] In other embodiments, the multi-layer electroplating layer 206 is a combination of a nickel plating layer, a palladium plating layer, a silver plating layer, and a gold plating layer.

[0113] The thickness of the electroplating layer 206 is in a range of 0.05 micrometers to 5 micrometers.

[0114] The lead frame 207 structure further includes a plurality of through holes 208 .

[0115] The roughness of the sidewall surface 209 of the through hole 208 in the lead frame 207 is in the range of 1.1 to 4.

[0116] The roughness of the side wall surface 209 of the through hole 208 in the lead frame 207 is the ratio of the area of ​​the side wall surface 209 of the through hole 208 before the electroplating process to the area of ​​the side wall surface 209 of the through hole 208 after the electroplating process.

[0117] In this embodiment, the roughness of the first surface 201 and the second surface 202 is greater than or equal to the roughness of the side wall surface 209 of the through hole 208 in the lead frame 207; the roughness of the fourth surface 2061 is greater than or equal to the roughness of the side wall surface 209 of the through hole 208 in the lead frame 207.

[0118] Figures 11 to 13 It is a structural schematic diagram of the formation process of a semiconductor packaging structure in another embodiment of the present invention.

[0119] The utility model provides Fig. 9The lead frame 207 shown in the figure includes a first surface 201 and a second surface 202 relative to each other, wherein the first surface 201 and the second surface 202 are rough surfaces formed by electroplating before the patterning etching process, and the first surface 201 and the second surface 202 have an electroplating layer 206; and a plurality of through holes 208, wherein the through holes 208 expose the side wall surface 209 of the lead frame.

[0120] Figures 11 to 13 It is a structural schematic diagram of the semiconductor packaging structure described in one embodiment of the utility model.

[0121] Please Figure 8 Based on reference Fig.11 , a chip 300 is provided, wherein the chip 300 includes a functional surface a and a non-functional surface b opposite to each other, wherein the functional surface a exposes a conductive pad 301 , and an interconnection structure is provided on the conductive pad 301 .

[0122] The interconnect structure includes solder balls 302 and copper pillars.

[0123] In this embodiment, the interconnection structure is a solder ball 302 .

[0124] In other embodiments, the interconnect structure is a copper pillar.

[0125] Please refer to Fig.12 , the chip 300 is fixed on the lead frame 207 .

[0126] In this embodiment, the lead frame 207 is fixed to the functional surface a of the chip 300 .

[0127] The method of fixing the lead frame 207 to the functional surface a of the chip 300 includes: reflow soldering of the solder balls 302 and copper pillar welding processes.

[0128] In this embodiment, the lead frame 207 and the chip 300 are electrically connected after welding.

[0129] The method of fixing the lead frame 207 to the functional surface a of the chip 300 further includes: bonding the lead frame 207 and the chip 300 or performing a heat pressing process.

[0130] In this embodiment, the chip 300 needs to form a conductive structure connected to the lead frame 207 on the functional surface a.

[0131] Please refer to Fig.13 , the plastic packaging layer 303 is formed on the surface of the chip 300 and the surface of the lead frame 207 .

[0132] In this embodiment, the plastic sealing layer 303 includes an epoxy resin layer.

[0133] In this embodiment, the plastic packaging layer 303 exposes the electroplating layer 206 on the surface of the lead frame 207 .

[0134] Please continue to refer to Fig.13 The technical solution of the utility model also provides a semiconductor packaging structure, including: a lead frame 207, the lead frame 207 includes a first surface 201 and a second surface 202 relative to each other, the first surface 201 and the second surface 202 are rough surfaces formed by electroplating before the graphic etching process; an electroplating layer 206 located on the first surface 201 and the second surface 202; a plurality of through holes 208, the through holes 208 exposing the side wall surface 209 of the lead frame; a chip 300 located on the surface of the electroplating layer 206, the chip 300 is electrically connected to the lead frame 207; and a plastic packaging layer 303 located on the surface of the lead frame 207 and the surface of the chip 300.

[0135] The chip 300 includes a functional surface a and a non-functional surface b opposite to each other. The functional surface a exposes a conductive pad 301 , and an interconnection structure is provided on the conductive pad 301 .

[0136] In this embodiment, the electroplating layer 206 includes a third surface and a fourth surface 2061 opposite to each other, and the third surface is in contact with the first surface 201 .

[0137] In this embodiment, the roughness range of the first surface 201 is 2 to 7, and the roughness is the ratio of the surface area of ​​the first surface 201 before the electroplating treatment to that after the electroplating treatment; the roughness range of the second surface 202 is 2 to 7, and the roughness is the ratio of the area of ​​the second surface 202 before the electroplating treatment to that after the electroplating treatment.

[0138] In this embodiment, the roughness of the fourth surface 2061 ranges from 2 to 7, and the roughness is the ratio of the area of ​​the fourth surface 2061 before the electroplating treatment to the area of ​​the fourth surface 2061 after the electroplating treatment.

[0139] In this embodiment, the electroplating layer 206 includes a single-layer electroplating layer 206 or a multi-layer electroplating layer 206 .

[0140] In this embodiment, the number of layers of the electroplating layer 206 ranges from 1 layer to 4 layers.

[0141] In this embodiment, the single-layer electroplating layer 206 is one of a copper-plated layer, a nickel-plated layer, a palladium-plated layer, a gold-plated layer and a silver-plated layer.

[0142] In this embodiment, the multi-layer electroplating layer 206 is a combination of a copper plating layer, a nickel plating layer, a palladium plating layer, a gold plating layer and a silver plating layer.

[0143] In this embodiment, the multi-layer electroplating layer 206 includes: a nickel-plated layer, a silver-plated layer, a combination of a nickel-plated layer and a palladium-plated layer, a combination of a nickel-plated layer and a gold-plated layer, a combination of a nickel-plated layer, a palladium-plated layer and a gold-plated layer, and a combination of a nickel-plated layer, a palladium-plated layer, a silver-plated layer and a gold-plated layer.

[0144] In this embodiment, the semiconductor packaging structure also includes a plurality of through holes 208; the roughness range of the side wall surface 209 of the through hole 208 in the lead frame 207 is 1.1 to 4, and the roughness is the ratio of the area of ​​the side wall surface 209 of the through hole 208 before the electroplating treatment to that after the electroplating treatment.

[0145] In this embodiment, the semiconductor packaging structure further includes: a plurality of interconnect structures located between the surface of the chip 300 and the electroplating layer 206 , wherein the interconnect structures are electrically connected to the chip 300 and the electroplating layer 206 , respectively.

[0146] The interconnect structure includes solder balls 302 and copper pillars.

[0147] In this embodiment, the interconnection structure is a solder ball 302 .

[0148] In other embodiments, the interconnect structure is a copper pillar.

[0149] In the above scheme, the rough surfaces of the first surface 201 and the second surface 202 are formed by electroplating before the graphic etching process, so that the connection between the electroplating layer and 206 of the first surface 201 and the second surface 202 is tighter, and the risk of process deformation of the lead frame 207 is reduced and the uniformity of the roughening of the first surface 201 and the second surface 202 is ensured; the graphic etching process is used to expose the side wall portion of the lead frame 207, which increases the tightness of the connection between the lead frame 207 and the subsequently formed plastic encapsulation layer, thereby improving the performance and yield of the lead frame 207.

[0150] Figures 14 to 16 It is a structural schematic diagram of a semiconductor packaging structure in another embodiment of the utility model.

[0151] Please Figure 8 Based on reference Fig.14 , a chip 400 is provided, wherein the chip 400 includes a relative functional surface a and a non-functional surface b.

[0152] The interconnect structure includes metal conductive lines.

[0153] Please refer to Fig.15, the chip 400 is fixed on the lead frame 207 .

[0154] In this embodiment, the lead frame 207 is fixed to the functional surface b of the chip 400 .

[0155] In this embodiment, the lead frame 207 is also fixed to the functional surface a of the chip 400 .

[0156] The method of fixing the lead frame 207 to the functional surface a of the chip 400 includes: connecting with a metal wire 401 .

[0157] In this embodiment, the lead frame 207 and the chip 400 are electrically connected after welding.

[0158] The method of fixing the lead frame 207 to the non-functional surface b of the chip 400 further includes: bonding the lead frame 207 and the chip 400 or performing a heat-pressing process.

[0159] In this embodiment, the chip 400 needs to form a conductive structure connected to the lead frame 207 on the functional surface a.

[0160] Please refer to Fig.16 , the plastic packaging layer 402 is formed on the surface of the chip 400 and the surface of the lead frame 207 .

[0161] In this embodiment, the plastic sealing layer 402 includes an epoxy resin layer.

[0162] In this embodiment, the plastic packaging layer 402 exposes the electroplating layer 206 on the surface of the lead frame 207 .

[0163] Please continue to refer to Fig.16 The utility model also provides a semiconductor packaging structure. Fig.13 The semiconductor packaging structure is the same as that of Fig.16 The functional surface a of the chip 400 of the semiconductor package structure is connected to the lead frame 207 by a metal wire 401 .

[0164] Although the utility model is disclosed as above, the utility model is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the utility model. Therefore, the protection scope of the utility model shall be subject to the scope defined by the claims.

Claims

1. A lead frame structure, characterized in that: include: A lead frame formed by a patterned etching process, the lead frame comprising a first surface and a second surface opposite to each other, the first surface and the second surface being rough surfaces formed by electroplating before the patterned etching process; an electroplated layer located on the first surface and the second surface; The electroplating layer includes a third surface and a fourth surface opposite to each other, the third surface is in contact with the first surface, the roughness of the fourth surface ranges from 2 to 7, and the roughness of the fourth surface is the ratio of the area of ​​the fourth surface before the electroplating treatment to the area of ​​the fourth surface after the electroplating treatment; A plurality of through holes, wherein the through holes expose the side wall surface of the lead frame, the roughness of the side wall surface of the through hole in the lead frame ranges from 1.1 to 4, and the roughness of the side wall surface of the through hole in the lead frame is the ratio of the area of ​​the side wall surface of the through hole before the electroplating treatment to that after the electroplating treatment.

2. The lead frame structure according to claim 1, characterized in that: The roughness of the first surface ranges from 2 to 7, and the roughness is the ratio of the surface area of ​​the first surface before the electroplating treatment to the surface area of ​​the first surface after the electroplating treatment; The roughness of the second surface ranges from 2 to 7, where the roughness is the ratio of the area of ​​the second surface before the electroplating treatment to the area of ​​the second surface after the electroplating treatment.

3. The lead frame structure according to claim 1, characterized in that: The electroplating layer includes a single-layer electroplating layer or a multi-layer electroplating layer.

4. The lead frame structure according to claim 3, characterized in that: The number of layers of the electroplating layer ranges from 1 to 4 layers.

5. The lead frame structure according to claim 3, characterized in that: The single-layer electroplated layer is one of a copper-plated layer, a nickel-plated layer, a palladium-plated layer, a gold-plated layer and a silver-plated layer.

6. The lead frame structure according to claim 3, characterized in that: The multi-layer electroplating layer is a combination of multiple layers selected from the group consisting of a copper plating layer, a nickel plating layer, a palladium plating layer, a gold plating layer and a silver plating layer.

7. The lead frame structure according to claim 6, characterized in that: The multi-layer electroplating layer includes: a nickel-plated layer, a silver-plated layer, a combination of a nickel-plated layer and a palladium-plated layer, a combination of a nickel-plated layer and a gold-plated layer, a combination of a nickel-plated layer, a palladium-plated layer and a gold-plated layer, and a combination of a nickel-plated layer, a palladium-plated layer, a silver-plated layer and a gold-plated layer.

8. The lead frame structure according to claim 1, wherein: The lead frame includes a copper frame.

9. The lead frame structure according to claim 1, wherein: The roughness of the first surface and the second surface is greater than or equal to the roughness of the side wall surface of the through hole in the lead frame; the roughness of the fourth surface is greater than or equal to the roughness of the side wall surface of the through hole in the lead frame.

10. A semiconductor packaging structure, characterized in that: include: A lead frame, the lead frame comprising a first surface and a second surface opposite to each other, wherein the first surface and the second surface are rough surfaces formed by electroplating before a patterning etching process; an electroplated layer on the first surface and the second surface; A chip located on the surface of the electroplating layer, wherein the chip is electrically connected to the lead frame; A plastic sealing layer is located on the surface of the electroplating layer and the surface of the chip.

11. The semiconductor package structure according to claim 10, wherein: The electroplating layer includes a third surface and a fourth surface opposite to each other, and the third surface contacts the first surface.

12. The semiconductor package structure according to claim 11, wherein: The roughness of the first surface ranges from 2 to 7, and the roughness is the ratio of the surface area of ​​the first surface before the electroplating treatment to the surface area of ​​the first surface after the electroplating treatment; The roughness of the second surface ranges from 2 to 7, where the roughness is the ratio of the area of ​​the second surface before the electroplating treatment to the area of ​​the second surface after the electroplating treatment.

13. The semiconductor package structure according to claim 12, wherein: The roughness of the fourth surface ranges from 2 to 7, and the roughness is the ratio of the area of ​​the fourth surface before the electroplating treatment to the area of ​​the fourth surface after the electroplating treatment.

14. The semiconductor package structure according to claim 13, wherein: It also includes a plurality of through holes; the roughness of the side wall surface of the through hole in the lead frame ranges from 1.1 to 4, and the roughness is the ratio of the area of ​​the side wall surface of the through hole before the electroplating treatment to the area after the electroplating treatment.

15. The semiconductor package structure according to claim 14, wherein: The roughness of the first surface and the second surface is greater than or equal to the roughness of the side wall surface of the through hole in the lead frame; the roughness of the fourth surface is greater than or equal to the roughness of the side wall surface of the through hole in the lead frame.

16. The semiconductor package structure according to claim 14, wherein: The electroplating layer includes a single-layer electroplating layer or a multi-layer electroplating layer.

17. The semiconductor package structure according to claim 16, wherein: The number of layers of the electroplating layer ranges from 1 to 4 layers.

18. The semiconductor package structure according to claim 16, wherein: The single-layer electroplated layer is one of a copper-plated layer, a nickel-plated layer, a palladium-plated layer and a gold-plated layer.

19. The semiconductor package structure according to claim 16, wherein: The multi-layer electroplating layer is a combination of multiple layers selected from the group consisting of a copper plating layer, a nickel plating layer, a palladium plating layer, a gold plating layer and a silver plating layer.

20. The semiconductor package structure according to claim 19, wherein: The multi-layer electroplating layer includes: a nickel-plated layer, a silver-plated layer, a combination of a nickel-plated layer and a palladium-plated layer, a combination of a nickel-plated layer and a gold-plated layer, a combination of a nickel-plated layer, a palladium-plated layer and a gold-plated layer, and a combination of a nickel-plated layer, a palladium-plated layer, a silver-plated layer and a gold-plated layer.

21. The semiconductor package structure according to claim 10, wherein: Also includes: A plurality of interconnect structures are located between the chip surface and the electroplating layer, wherein the interconnect structures are electrically connected to the chip and the electroplating layer respectively.

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