Semiconductor device and semiconductor structure

Abstract

The utility model provides a semiconductor device and a semiconductor structure. The semiconductor device comprises a first protection layer and a redistribution layer. The first protective layer is over the substrate and contains an embedded metal-insulator-metal capacitor. A redistribution layer is formed over the first protection layer, the redistribution layer including a first redistribution layer structure and a second redistribution layer structure, the first redistribution layer structure being separated from the second redistribution layer structure by a dielectric filled opening, where the dielectric filled opening is over a portion of the metal-insulator-metal capacitor. Wherein a sidewall of each of the first redistribution layer structure and the second redistribution layer structure has a convex profile defining a dielectric filled opening separating the first redistribution layer structure from the second redistribution layer structure.

Description

Technical Field

[0001] The present disclosure relates to an apparatus and method for profile control of stress relaxation. Background Art

[0002] In today's electronics industry, there is a growing demand for smaller, faster electronic devices that can simultaneously support more and more complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by reducing the size of semiconductor integrated circuits (e.g., minimum feature size) to improve production efficiency and reduce related costs. However, this change in the size of integrated circuits has also correspondingly increased the complexity of semiconductor processes. Therefore, the continued optimization of semiconductor integrated circuits and devices requires the joint advancement of semiconductor processes and technologies to achieve. Utility Model Content

[0003] One aspect of the present disclosure describes a semiconductor device comprising a first protective layer and a redistribution layer. The first protective layer is located above a substrate and contains an embedded metal-insulator-metal capacitor. The redistribution layer is formed on the first protective layer, the redistribution layer comprising a first redistribution layer structure and a second redistribution layer structure, the first redistribution layer structure is separated from the second redistribution layer structure by a dielectric-filled opening, wherein the dielectric-filled opening is located above a portion of the metal-insulator-metal capacitor. The sidewalls of each of the first redistribution layer structure and the second redistribution layer structure have a convex profile, and the convex profile defines a dielectric-filled opening separating the first redistribution layer structure from the second redistribution layer structure.

[0004] Another aspect of the present disclosure describes a semiconductor structure including a first protection layer and a redistribution layer. The first protection layer is located above a substrate, and the first protection layer contains an embedded metal-insulator-metal capacitor. The redistribution layer includes a first redistribution layer structure and a second redistribution layer structure, which are located above the first protection layer, wherein a sidewall of each of the first redistribution layer structure and the second redistribution layer structure has a convex profile.

[0005] Another aspect of the present disclosure describes a semiconductor structure including a substrate and a redistribution layer. The substrate has an interconnect structure in a dielectric layer above it, and has a first protective layer above the dielectric layer, the first protective layer having a first sublayer, a second sublayer above the first sublayer, and a metal-insulator-metal capacitor between the first sublayer and the second sublayer. The redistribution layer is located above the first protective layer and in the first protective layer above a top metal structure in the interconnect structure, wherein the redistribution layer has a first redistribution layer structure and a second redistribution layer structure, the first redistribution layer structure is not connected to the top metal structure, the second redistribution layer structure is connected to the top metal structure, and the sidewalls of each of the first redistribution layer structure and the second redistribution layer structure have a convex profile. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of these features may be arbitrarily increased or reduced based on the clarity of the discussion.

[0007] Figure 1 is a cross-sectional view of a portion of a semiconductor device at a stage in an integrated circuit process according to one or more embodiments;

[0008] Figure 2 A flowchart illustrating an example of a semiconductor manufacturing method including forming a convex profile on an end of a redistribution layer structure according to one or more embodiments;

[0009] Figures 3 to 14 illustrative cross-sectional views of a semiconductor structure at various stages of fabrication according to one or more embodiments.

[0010]

Explanation of symbols

[0011] 100:Semiconductor device

[0012] 102:Substrate

[0013] 104: Top metal pad

[0014] 106: Top interlayer dielectric layer

[0015] 108,308: First protective layer

[0016] 108-1,308a: First sublayer

[0017] 108-2,308b: Second sublayer

[0018] 110,310: Metal-insulator-metal capacitors

[0019] 112,312: Heavy cloth layer

[0020] 112a,706a: The first layer structure

[0021] 112b,706b: Second layer structure

[0022] 114: Undoped silicon glass plus high-density plasma layer

[0023] 115,1402: Second protection layer

[0024] 116: Silicon nitride layer

[0025] 118: The third protective layer

[0026] 120: Bump structure

[0027] 122: Under Bump Metal Layer

[0028] 124,1408: Conductive column

[0029] 126,1410:Solder layer

[0030] 128,130a,130b,704a,704b: Box

[0031] 132: Dielectric filling opening

[0032] 134: Crack

[0033] 200: Method

[0034] 202,204,206,208,210,212,214,216,218,220,222: Blocks

[0035] 300:Semiconductor structure

[0036] 302:Substrate

[0037] 304: Interconnection structure

[0038] 306: Dielectric layer

[0039] 414: Photoresist layer

[0040] 514: Patterned photoresist layer

[0041] 516: Opening

[0042] 602: First Depth

[0043] 702: Second Depth

[0044] 706a: first heavy layer structure

[0045] 706b: Second layer structure

[0046] 708: Top size

[0047] 710: Bottom size

[0048] 712: minimum size

[0049] 714: Barrel height

[0050] 716: Heavy cloth layer thickness

[0051] 902: Bottom contour angle

[0052] 904: Redistribution layer horizontal boundary

[0053] 906: Extend the edge upward

[0054] 1002, 1102: first dielectric layer

[0055] 1202: second dielectric layer

[0056] 1302: Bump opening

[0057] 1404: Bump structure

[0058] 1406: Under Bump Metal Layer DETAILED DESCRIPTION

[0059] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0060] It is understood that, although the terms first, second, third, etc. may be used in the present disclosure to describe each element, component, region, layer, part and / or fragment, these elements, components, regions, layers, parts and / or fragments should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, part and / or fragment from another element, component, region, layer, part and / or fragment. Therefore, without departing from the teaching of the present disclosure, the first element, component, region, layer, part and / or fragment discussed below may be referred to as the second element, component, region, layer, part and / or fragment.

[0061] For the sake of brevity of description, conventional techniques related to conventional semiconductor device manufacturing may not be described in detail in this disclosure. In addition, the various operations and processes described in this disclosure may be incorporated into a broader program or process with additional functions that are not described in detail in this disclosure. In particular, each process in semiconductor device manufacturing is well known, so for the sake of brevity of description, many conventional processes will only be briefly mentioned here or will be completely omitted without providing well-known process details. The content disclosed in this disclosure is obvious to those of ordinary skill in the art who have read this disclosure in its entirety, and the structure disclosed in this disclosure can be used with a variety of technologies and can be incorporated into a variety of semiconductor devices and products. In addition, it is worth noting that the semiconductor device structure includes different numbers of elements, and the single element shown in the accompanying drawings may be representative of multiple elements.

[0062] In addition, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or other) elements or features, as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In addition, unless expressly stated otherwise, each element having the same reference number and / or letter is assumed to have the same material composition and have a thickness within the same thickness range.

[0063] It is worth noting that references to "one embodiment", "an embodiment", "an exemplary embodiment", "exemplary", "example", etc. in the specification indicate that the described embodiment may include specific features, structures or characteristics, but each embodiment does not necessarily include specific features, structures or characteristics. In addition, such terms do not necessarily refer to the same embodiment. In addition, when describing specific features, structures or characteristics in conjunction with an embodiment, whether or not explicitly described, the features, structures or characteristics affected by the combination with other embodiments must be within the knowledge of a person of ordinary skill in the art.

[0064] In one or more embodiments of the present disclosure, a "material layer" is a layer comprising an identified material in a concentration of at least 50% by weight, such as a layer comprising an identified material in a concentration of at least 60% by weight, a layer comprising an identified material in a concentration of at least 75% by weight, a layer comprising an identified material in a concentration of at least 90% by weight, a layer comprising an identified material in a concentration of at least 95% by weight, or a layer comprising an identified material in a concentration of at least 99% by weight, and a layer as a "material" comprises an identified material in a concentration of at least 50% by weight, such as a layer comprising an identified material in a concentration of at least 60% by weight, a layer comprising an identified material in a concentration of at least 75% by weight, a layer comprising an identified material in a concentration of at least 90% by weight, a layer comprising an identified material in a concentration of at least 95% by weight, or a layer comprising at least 99% by weight. For example, in some embodiments, each aluminum layer comprises at least 50 weight percent, at least 60 weight percent, at least 75 weight percent, at least 90 weight percent, at least 95 weight percent, or at least 99 weight percent aluminum.

[0065] Some embodiments of the present disclosure will now be described with reference to the accompanying drawings, wherein the same reference numerals are generally used to represent the same elements throughout the present disclosure. In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of the subject matter for which protection is to be applied. However, it is apparent that the subject matter for which protection is to be applied can be implemented without these specific details. In other cases, structures and devices are represented in the form of block diagrams to facilitate the description of the subject matter for which protection is to be applied.

[0066] Additional operations may be provided before, during, and / or after the stages described in these embodiments. In different embodiments, some of the stages described may be replaced or removed. Additional features may be added to the semiconductor device structure. In different embodiments, some of the features described below may be replaced or removed. Although some embodiments discuss performing operations in a particular order, these operations may also be performed in another logical order.

[0067] As used herein, a "layer" refers to a region, such as a region including any boundaries, and not necessarily a region of uniform thickness. For example, a layer may include at least some regions of varying thickness.

[0068] Stress migration is a phenomenon that can occur in integrated circuits. Stress migration can cause voids and / or cracks to form in conductors, which can reduce the performance of the integrated circuit. For example, under stress migration, factors such as vacancy migration and hydrostatic stress gradients can cause voids to form in conductors. Voids or cracks in conductors can cause open circuits or increased resistance, which can affect the performance of the integrated circuit.

[0069] When materials with different thermal expansion coefficients are formed in an interconnect structure, stress migration occurs due to the stress formed between the different materials. Various thermal processes in semiconductor processing, such as high pressure annealing, can cause plastic deformation vacancies (e.g., small gaps) or cracks to form in the interconnect structure. These small gaps can be driven by stress migration caused by hydrostatic stress gradients to gather in high stress gradient areas in the interconnect structure and nucleate or form large gaps. Large gaps can reduce or eliminate electrical contact between metal layers. Therefore, stress migration may cause reduced electrical contact between conductive materials, resulting in increased resistivity and possible device failure.

[0070] As semiconductor device geometries continue to shrink, stress migration reliability issues become more severe. Stress migration effects are minimized by forming a convex profile on the sidewalls of a redistribution layer region in a structure that is separated into multiple redistribution layers (e.g., AlCu redistribution layers). Additionally, in one or more embodiments of the present disclosure, crack formation on or across a metal-insulator-metal capacitor located near the sidewalls of the separated redistribution layers is minimized due to the profile of the sidewalls. The profile of the sidewalls can further improve film adhesion and protect pads by preventing voids formed by stress migration.

[0071] The present disclosure presents one or more embodiments of semiconductor structures and methods of forming semiconductor structures having sidewall profiles that reduce the occurrence of problems associated with stress migration. In some embodiments, stress migration is mitigated by including a convex sidewall profile for a redistribution layer structure. In some exemplary embodiments, the sidewall profile is formed using a lateral etching operation.

[0072] Figure 11 is a cross-sectional view of a portion of a semiconductor device 100 at an exemplary stage in an integrated circuit process according to an embodiment. A portion of a semiconductor device 100 having circuits formed in and / or on a substrate 102 is shown. The substrate 102 may be one of a variety of types of semiconductor substrates commonly used in semiconductor integrated circuit manufacturing, and integrated circuits may be formed therein and / or on it. The semiconductor substrate may be any structure including semiconductor materials, including but not limited to bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials may be used, including Group III, Group IV, and / or Group V semiconductors. Although not shown, it should be understood that the substrate 102 may further include a plurality of isolation features, such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features. The isolation features may isolate each microelectronic element formed in and / or on the substrate 102. Examples of the types of microelectronic components that may be formed in the substrate 102 include, but are not limited to, components such as metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel field effect transistors (PFETs) and / or n-channel field effect transistors (NFETs), resistors, diodes, capacitors, inductors, fuses, and / or other suitable components. Various processes are performed to form various microelectronic components, including, but not limited to, one or more of deposition, etching, implantation, lithography, annealing, and other suitable processes. The microelectronic components are interconnected to form integrated circuit devices, which may include logic devices, memory devices (e.g., static random access memory (SRAM)), radio frequency (RF) devices, input / output (I / O) devices, system-on-chip (SoC) devices, and other suitable types of devices.

[0073] The example semiconductor device 100 also includes an interconnect structure covering the substrate 102. The interconnect structure includes an interlayer dielectric layer and a metallization structure covering the microelectronic element. The interlayer dielectric layer in the metallization structure may include one or more of a low-k dielectric material, undoped silicate glass (USG), silicon nitride (SiN), silicon oxynitride (SiON), and other commonly used materials. The dielectric constant of the low-k dielectric material may be less than about 3.9 or less than about 2.8. The metal lines in the metallization structure may be formed of copper or a copper alloy. A top metal pad 104 is formed and patterned in and / or on the top interlayer dielectric layer 106. The top metal pad 104 provides electrical connection for external circuits. The top metal pad 104 may be formed of any suitable conductive material, including one or more of copper, tungsten, aluminum, aluminum-copper alloy, silver, or the like.

[0074] An exemplary first protective layer 108 is formed and patterned over the top metal pad 104 and the top interlayer dielectric layer 106. In various embodiments, the first protective layer 108 may be formed of a non-organic material, such as undoped silicate glass, silicon nitride, silicon oxynitride, silicon oxide, or a combination thereof. The first protective layer 108 may be formed by any suitable method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In other embodiments, the first protective layer 108 may be formed of a polymer layer, such as epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), etc., although other relatively soft, typically organic dielectric materials may also be used. The first protective layer 108 may include any number of sub-layers, including a first sub-layer 108-1 covering a second sub-layer 108-2.

[0075] The exemplary first protection layer 108 includes an embedded metal-insulator-metal capacitor 110. The metal-insulator-metal capacitor 110 can be used for various functions, such as a decoupling capacitor, a high-frequency noise filtering capacitor in mixed-signal applications, an oscillator, a phase shift network, a bypass filter, a coupling capacitor in a radio frequency application, or other functions. In various embodiments, the metal-insulator-metal capacitor is formed above the first sublayer 108-1 of the first protection layer 108 and below the second sublayer 108-2.

[0076] The exemplary semiconductor device 100 further includes a redistribution layer 112 disposed above the first protective layer 108 and in the opening in the first protective layer 108. Portions of the redistribution layer 112 are coupled to the top metal pad 104 to reroute the electrical connection at the top metal pad 104 to a desired location, such as an under bump metallurgy (UBM) structure, a solder bump, and / or a copper pillar bump to facilitate external electrical connection. In this embodiment, the redistribution layer 112 reroutes the connection at the top metal pad 104 to a bump structure 120 located at a different location on the chip. The ability to reroute points can achieve a higher contact density.

[0077] In various embodiments, the redistribution layer 112 is formed of aluminum copper (AlCu). In various embodiments, the redistribution layer 112 includes multiple layers, such as a barrier layer, a diffusion layer disposed on the barrier layer, and an aluminum copper alloy layer disposed on the diffusion layer. The barrier layer may also include a tantalum film and a tantalum nitride film disposed on the tantalum film. The diffusion layer is a metal oxide. In various embodiments, the diffusion layer includes tantalum, oxygen, aluminum, and nitrogen.

[0078] The exemplary redistribution layer 112 includes a first redistribution layer structure 112a and a second redistribution layer structure 112b. The first redistribution layer structure 112a is separated from the second redistribution layer structure 112b by a dielectric-filled opening 132 (e.g., filled with undoped silicon glass plus a high density plasma (HDP) layer 114), wherein the dielectric-filled opening 132 is located above a portion of the metal-insulator-metal capacitor 110. Each of the first redistribution layer structure 112a and the second redistribution layer structure 112b has a convex profile on the sidewall of the opening 132 (as shown in boxes 130a and 130b), and the convex profile defines the dielectric-filled opening 132 that separates the first redistribution layer structure 112a from the second redistribution layer structure 112b. The convex profile located on the end (as shown in boxes 130a and 130b) has a shape that resists stress migration from the redistribution layer 112 to the metal-insulator-metal capacitor 110, so as to resist cracks 134 formed within or across the metal-insulator-metal capacitor 110 due to stress migration from the redistribution layer to the metal-insulator-metal capacitor 110.

[0079] The exemplary semiconductor device 100 further includes a second protective layer 115 including undoped silicon glass plus a high density plasma layer 114 and a silicon nitride layer 116 disposed thereon. A third protective layer 118 is disposed on the silicon nitride layer 116.

[0080] The exemplary semiconductor device 100 further includes a bump structure 120, which includes an under bump metallization layer 122 formed on the third protection layer 118 and electrically connected to the redistribution layer 112 through an opening in the second protection layer 115, a conductive pillar 124, and a solder layer 126. The exemplary under bump metallization layer 122 is formed on the surface of the third protection layer 118 and the exposed portion of the redistribution layer 112. In various embodiments, the under bump metallization layer 122 includes a diffusion barrier layer or a glue layer, which may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc., formed by physical vapor deposition or sputtering. In various embodiments, the under bump metallization layer 122 also includes a seed layer formed on the diffusion barrier layer by physical vapor deposition or sputtering. The seed layer may be formed of copper (Cu) or aluminum (Al), chromium (Cr), nickel (Ni), tin (Sn), gold (Au) or a combination thereof. In some embodiments, the UBM layer 122 includes a titanium layer and a copper seed layer.

[0081] The exemplary conductive pillar 124 is formed on the underbump metallization layer 122. In various embodiments, the conductive pillar 124 includes a copper layer. The copper layer includes pure elemental copper, copper containing inevitable impurities, and / or a copper alloy containing a small amount of elements such as tantalum, indium (In), tin, zinc (Zn), manganese (Mn), chromium, titanium, germanium (Ge), strontium (Sr), platinum (Pt), magnesium (Mg), aluminum, or zirconium (Zr). The conductive pillar 124 can be formed by sputtering, printing, electroplating, electroless plating (electro-less plating), electrochemical deposition (electrochemical deposition; ECD), molecular beam epitaxy (molecular beam epitaxy; MBE), atomic layer deposition (atomic layer deposition; ALD) and / or a commonly used chemical vapor deposition method. In various embodiments, the copper layer is formed by electrochemical plating (electro-chemical plating; ECP).

[0082] An exemplary solder layer 126 is formed on the conductive pillar 124. The solder layer 126 may be made of a lead-free solder, such as Sn, SnAg, Sn-Pb, SnAgCu (wherein the weight percentage of Cu is less than 0.3%), SnAgZn, SnZn, SnBi-In, Sn-In, Sn-Au, SnPb, SnCu, SnZnIn, SnAgSb, and other similar suitable materials, by an electroplating method. In various embodiments, the solder layer 126 is formed to have a controlled volume.

[0083] In various embodiments, the solder reflow process is performed at a temperature equal to or higher than the melting temperature of the solder. After the solder reflow process, the solder layer 126 is melted to become a reflowed solder layer 126, and the thickness and surface shape of the reflowed solder layer 126 may be changed after the reflow process. For example, the reflowed solder layer 126 may have a Figure 1 The spherical surface shown.

[0084] Figure 2 is a process flow diagram illustrating an exemplary method 200 of semiconductor manufacturing, which includes forming a convex profile on an end of a redistribution layer structure, the convex profile having a shape that resists stress migration from the redistribution layer to the metal-insulator-metal capacitor, so as to resist cracks formed within or across the metal-insulator-metal capacitor due to stress migration from the redistribution layer to the metal-insulator-metal capacitor. According to some embodiments, Figure 2 Combination Figure 3-14 The semiconductor structure 300 is shown in various stages of manufacture. Figure 1 The method 200 is merely an example and is not intended to limit the present disclosure beyond what is expressly recited in the claims. Additional steps may be provided before, during, and after the method 200, and the steps described may be moved, replaced, or eliminated for additional embodiments of the method 200. Additional features may be added to the semiconductor structure 300 depicted in the figure, and some of the features described below may be replaced, modified, or deleted in other embodiments.

[0085] As with other method embodiments and exemplary devices discussed herein, it should be understood that portions of the semiconductor structure may be fabricated by typical semiconductor technology processes, and therefore some processes are only briefly described herein. In addition, the exemplary semiconductor structure may include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, dials, fuses, and / or other logic devices, etc., which are simplified for a better understanding of the concepts disclosed herein.

[0086] At block 202, the exemplary method 200 includes providing a substrate having an interconnect structure in a dielectric layer above the substrate, and providing a first protective layer above the dielectric layer, wherein a metal-insulator-metal capacitor is formed in the first protective layer. In various embodiments, the first protective layer has a first sublayer and a second sublayer located above the first sublayer, and the metal-insulator-metal capacitor is formed between the first sublayer and the second sublayer.

[0087] At block 204, the exemplary method 200 includes forming a redistribution layer above the first protection layer. Figure 3In the example of the embodiment of blocks 202 and 204, a substrate 302 is depicted, which has an interconnect structure 304 in a dielectric layer 306 on the substrate 302 and a first protection layer 308 on the dielectric layer 306, wherein a metal-insulator-metal capacitor 310 is formed in the first protection layer between a first sublayer 308a and a second sublayer 308b. A redistribution layer 312 is formed on the first protection layer 308.

[0088] At block 206, the exemplary method 200 includes forming a photoresist layer on the redistribution layer. Figure 4 As an example, in the embodiment of block 206 , a photoresist layer 414 is formed on the redistribution layer 312 .

[0089] At block 208, the exemplary method 200 includes patterning the photoresist layer to form a photoresist pattern having an opening in the photoresist layer above the metal-insulator-metal capacitor. The photoresist is patterned to expose a selected portion of the underlying redistribution layer above the metal-insulator-metal capacitor during a semiconductor process, such as an etching operation, while protecting an overlying portion of the underlying redistribution layer during the semiconductor process. The photoresist pattern can be formed by exposing and developing the photoresist layer using methods commonly used in the art. Figure 5 In the example of block 208 , a patterned photoresist layer 514 is formed over the redistribution layer 312 and has an opening 516 over the metal-insulator-metal capacitor 310 .

[0090] At block 210, the exemplary method 200 includes removing a portion of a redistribution layer below the opening to a first depth. The redistribution layer may be etched using the patterned photoresist layer as an etch mask to transfer the photoresist pattern to the redistribution layer. The redistribution layer may be etched using an anisotropic etching operation. Figure 6 In the example of block 210 , a portion of the redistribution layer 312 below the opening is removed to a first depth 602 .

[0091] At block 212, the exemplary method 200 includes removing a portion of the redistribution layer below the opening to a second depth at a top of the first protective layer using a trim process that forms a convex profile on the sidewalls of the redistribution layer in the opening. The trim process may involve etching the redistribution layer using a lateral etching operation to form a convex profile on the sidewalls. The redistribution layer may be etched using an isotropic etching operation to form a convex profile on the sidewalls. The opening separates the redistribution layer into a first redistribution layer structure and a second redistribution layer structure. The trim process may involve low voltage (e.g., 6-12 mT), low bias power (e.g., 50-200 W), a chemically lean region (e.g., Cl 2 / BCl 3ratio of 1:2, 1:1, 2:1, 3:1) and produces less byproducts in the plasma etching chamber (such as Al 2 O 3 , CCl 4 CF 4 , AlF 3 ).

[0092] Reference Figure 7 In the embodiment of block 212, the portion of the redistribution layer 312 below the opening 516 is removed to a second depth 702 at the top of the first protection layer 308 in a manner to form a convex profile on the sidewalls (as shown in blocks 704a and 704b). The opening 516 divides the redistribution layer 312 into a first redistribution layer structure 706a and a second redistribution layer structure 706b.

[0093] At block 214, the exemplary method 200 includes removing the photoresist layer. The photoresist layer may be removed using an ashing operation. Figure 8 For example, in the embodiment of block 214 , the photoresist layer has been removed from above the redistribution layer 312 .

[0094] Fig. 9 1 is a cross-sectional view of a semiconductor structure according to some embodiments, which depicts exemplary characteristics of a portion of an end portion of a redistribution layer after the redistribution layer portion is separated into different redistribution layer structures. In various embodiments, a bottom profile angle (θ) 902 defined by a first protection layer to redistribution layer horizontal boundary 904 and an upwardly extending edge 906 of an end portion of a redistribution layer structure (706a or 706b) is between about 90 degrees and about 120 degrees.

[0095] In various embodiments, the opening 516 between the first redistribution layer structure 706a and the second redistribution layer structure 706b has a top dimension 708 between about 1.0 microns and about 5.0 microns at its top. In various embodiments, the opening 516 between the first redistribution layer structure 706a and the second redistribution layer structure 706b has a bottom dimension 710 between about 0.8 microns and about 4.0 microns at its bottom. In various embodiments, the opening 516 between the first redistribution layer structure 706a and the second redistribution layer structure 706b has a minimum dimension 712 between its top and its bottom between about 0.6 microns and about 3.6 microns. In various embodiments, the difference between the top dimension 708 and the minimum dimension 712 is between about 0.4 microns and about 1.4 microns. In various embodiments, the difference between the top dimension 708 and the bottom dimension 710 is between about 0.2 microns and about 1.0 microns. In various embodiments, the difference between the bottom dimension 710 and the minimum dimension 712 is between about 0.2 microns and about 0.4 microns.

[0096] In various embodiments, the barrel height 714 in the opening 516 is defined as the distance between the top plane of the first protection layer 308 and the plane where the minimum dimension 712 is located, and the ratio of the barrel height 714 to the redistribution layer thickness 716 is between about 2% and about 20%. In various embodiments, the redistribution layer 706a / 706b has a thickness between about 2 microns and about 3 microns. In various embodiments, the opening 516 separating the first redistribution layer structure 706a from the second redistribution layer structure 706b is formed by an anisotropic etching operation to a first depth, followed by an isotropic etching operation, including lateral etching of the ends of the first redistribution layer structure 706a and the second redistribution layer structure 706b below the first depth.

[0097] At block 216, the exemplary method 200 includes forming a first dielectric layer on the redistribution layer and in the opening between the redistribution layer structures. The first dielectric layer may be formed by a suitable deposition technique. In various embodiments, the first dielectric layer includes undoped silicon glass plus a high density plasma layer 114. Fig.10 and Fig.11 As an example, in the embodiment of block 216, a first dielectric layer 1002, 1102 has been formed over the redistribution layer 312 and in the opening between the redistribution layer structures 706a and 706b.

[0098] At block 218, the exemplary method 200 includes forming a second dielectric layer on the first dielectric layer. The second dielectric layer may be formed by a suitable deposition technique. In various embodiments, the second dielectric layer includes silicon nitride. Fig.12 In an example of the present invention, in an embodiment of block 218 , a second dielectric layer 1202 is formed over the first dielectric layer 1102 .

[0099] At block 220, the exemplary method 200 includes forming a bump opening in the first dielectric layer and the second dielectric layer. The bump opening may be formed by suitable lithography, patterning, and etching techniques. Fig.13 In an example of block 220 , a bump opening 1302 is formed in the first dielectric layer 1102 and the second dielectric layer 1202 .

[0100] At block 222, the exemplary method 200 includes forming a second protection layer on the second dielectric layer and the sidewalls of the bump opening. The second protection layer may be formed by a suitable deposition technique.

[0101] At block 224, the exemplary method 200 includes forming a bump structure over the second protection layer and in the bump opening. In various embodiments, the bump structure includes an under bump metallurgy layer, a conductive pillar, and a solder layer.

[0102] Reference Fig.14As an example, in the embodiments of blocks 222 and 224, a second protective layer 1402 is formed on the second dielectric layer 1202 and the sidewalls of the bump opening, and the bump structure 1404 includes an under-bump metal layer 1406, a conductive column 1408, and a solder layer 1410 formed above the second protective layer 1402 and in the bump opening, wherein the bump structure 1404 is electrically connected to the second redistribution layer structure 706b.

[0103] In the present disclosure, embodiments provide improved resistance to stress migration related issues. By forming a convex profile on the sidewalls of the redistribution layers in the region separated into multiple redistribution layer (e.g., AlCu redistribution layer) structures, the stress migration effects can be minimized. In addition, due to the profile of the sidewalls, the embodiments of the present disclosure can minimize cracks formed within or across the metal-insulator-metal capacitors located near the sidewalls of the separated redistribution layers. The profile of the sidewalls can further improve film adhesion and provide good protection of the pads by preventing voids formed by stress migration.

[0104] The present disclosure presents embodiments of semiconductor structures and methods for forming semiconductor structures having sidewall profiles that reduce the occurrence of problems associated with stress migration. In some embodiments, stress migration is mitigated by including a convex sidewall profile for a redistribution layer structure. In some exemplary embodiments, the sidewall profile is formed using a lateral etching operation.

[0105] Embodiments of the present disclosure provide advantages over the prior art, and while it is understood that other embodiments may provide different advantages, not all advantages are necessarily discussed in the present disclosure, and all embodiments do not require a particular advantage. For example, embodiments discussed in the present disclosure include methods for forming a redistribution layer structure with a convex sidewall profile that minimizes stress migration, which helps eliminate cracks that occur in the device. Embodiments described in the present disclosure provide a more simplified thin film strategy and etching process that does not require additional masks. Embodiments described in the present disclosure are suitable for integration with the next packaging layer.

[0106] One embodiment of the present disclosure describes a device comprising a first protective layer located above a substrate and containing an embedded metal-insulator-metal capacitor; a redistribution layer is formed on the first protective layer, the redistribution layer comprising a first redistribution layer structure and a second redistribution layer structure, the first redistribution layer structure is separated from the second redistribution layer structure by a dielectric-filled opening, wherein the dielectric-filled opening is located above a portion of the metal-insulator-metal capacitor; wherein the sidewalls of each of the first redistribution layer structure and the second redistribution layer structure have a convex profile, wherein the convex profile defines the dielectric-filled opening separating the first redistribution layer structure and the second redistribution layer structure; wherein the convex profiles on these sidewalls resist stress migration from the redistribution layer to the metal-insulator-metal capacitor to resist cracks caused by stress migration from the redistribution layer to the metal-insulator-metal capacitor.

[0107] In some embodiments of the device, an angle between the bottom contour defined by the first protection layer at the end of the redistribution layer structure to the horizontal boundary of the redistribution layer and the upwardly extending edge is between about 90 degrees and about 120 degrees.

[0108] In some embodiments of this device, the dielectric-filled opening has: a top dimension at its top between about 1.0 microns and about 5.0 microns; a bottom dimension at its bottom between about 0.8 microns and about 4.0 microns; and a minimum dimension between its top and its bottom between about 0.6 microns and about 3.6 microns.

[0109] In some embodiments of this device, the difference between the top dimension and the smallest dimension is between about 0.4 microns and about 1.4 microns; the difference between the top dimension and the bottom dimension is between about 0.2 microns and about 1.0 microns; and the difference between the bottom dimension and the smallest dimension is between about 0.2 microns and about 0.4 microns.

[0110] In some embodiments of the device, a barrel height in the dielectric-filled opening is defined as a distance between a top plane of the first protection layer and a plane where a minimum dimension is located; and a ratio of the barrel height to the thickness of the redistribution layer is between about 2% and about 20%.

[0111] In some embodiments of the device, the redistribution layer has a thickness between about 2 microns and about 3 microns.

[0112] In some embodiments of the device, a dielectric-filled opening separating a first redistributed layer structure from a second redistributed layer structure is formed by an anisotropic vertical etching operation to a first depth and then by an isotropic etching operation including lateral etching of ends of the first redistributed layer structure and the second redistributed layer structure to below the first depth.

[0113] Another embodiment of the present disclosure describes a method, comprising: providing a first protective layer containing an embedded metal-insulator-metal capacitor above a substrate; forming a redistribution layer above the first protective layer; forming an opening in the redistribution layer and above a portion of the metal-insulator-metal capacitor, wherein the opening separates the redistribution layer into a first redistribution layer structure and a second redistribution layer structure, wherein the sidewalls of each of the first redistribution layer structure and the second redistribution layer structure have a convex profile on the sidewalls defining the separation of the first redistribution layer structure and the second redistribution layer structure, the convex profile defines the opening separating the first redistribution layer structure and the second redistribution layer structure, and forming the opening comprises: performing a first etching operation to remove a portion of the redistribution layer located above the metal-insulator-metal capacitor to a first depth; performing a second etching operation to remove a portion of the redistribution layer located above the metal-insulator-metal capacitor to a second depth from the top of the first protective layer, the second etching operation comprising laterally etching these sidewalls of the first redistribution layer structure and the second redistribution layer structure located below the first depth to the second depth to form the convex profile.

[0114] In some embodiments of the method, the first etching operation comprises an anisotropic vertical etching operation and the second etching operation comprises an isotropic etching operation.

[0115] In some embodiments of the method, forming the convex profile includes forming a bottom profile angle defined by the first protection layer at the end of the redistribution layer structure to the horizontal boundary of the redistribution layer and the upwardly extending edge, wherein the bottom profile angle is between about 90 degrees and about 120 degrees.

[0116] In some embodiments of this method, an opening is formed in a redistribution layer above a portion of a metal-insulator-metal capacitor having: a top dimension at its top between about 1.0 microns and about 5.0 microns; a bottom dimension at its bottom between about 0.8 microns and about 4.0 microns; and a minimum dimension between its top and its bottom between about 0.6 microns and about 3.6 microns.

[0117] In some embodiments of this method, the difference between the top dimension and the minimum dimension is between about 0.4 microns and about 1.4 microns; the difference between the top dimension and the bottom dimension is between about 0.2 microns and about 1.0 microns; and the difference between the bottom dimension and the minimum dimension is between about 0.2 microns and about 0.4 microns.

[0118] In some embodiments of the method, a barrel height in the dielectric-filled opening is defined as a distance between a top plane of the first protection layer and a plane where a minimum dimension is located; and a ratio of the barrel height to the thickness of the redistribution layer is between about 2% and about 20%.

[0119] In some embodiments of the method, a redistribution layer is formed on the first protection layer to have a thickness between about 2 microns and about 3 microns.

[0120] Another embodiment of the present disclosure describes a method, comprising: providing a substrate having an interconnect structure in a dielectric layer above the substrate, and having a first protective layer above the dielectric layer, the first protective layer having a first sublayer, a second sublayer above the first sublayer, and a metal-insulator-metal capacitor formed between the first sublayer and the second sublayer; forming a redistribution layer on the first protective layer and forming the redistribution layer in an opening of the first protective layer above a top metal structure in the interconnect structure to connect the top metal structure; and forming a metal-insulator-metal capacitor in the redistribution layer and in a portion of the metal-insulator-metal capacitor. An opening is formed above the capacitor, wherein the opening separates a redistribution layer into a first redistribution layer structure not connected to a top metal structure and a second redistribution layer structure including the redistribution layer connected to the top metal structure, wherein each of the first redistribution layer structure and the second redistribution layer structure has a convex profile on a sidewall, wherein the convex profile defines an opening in the redistribution layer separating the first redistribution layer structure and the second redistribution layer structure, wherein the convex profile on these sidewalls resists stress migration from the redistribution layer to the metal-insulator-metal capacitor to resist cracks caused by stress migration formed in the metal-insulator-metal capacitor. Forming an opening in a redistribution layer includes: forming a patterned photoresist layer, wherein the patterned photoresist layer defines an opening above a portion of a metal-insulator-metal capacitor; performing a first etching operation to remove a portion of the redistribution layer below the opening in the patterned photoresist layer to a first depth; performing a second etching operation to remove a portion of the redistribution layer located below the opening in the patterned photoresist layer to a second depth from the top of a first protective layer, the second etching operation including laterally etching the sidewalls of the first redistribution layer structure and the second redistribution layer structure located below the first depth to a second depth to form a convex profile; and removing the patterned photoresist layer.

[0121] In some embodiments of the method, the first etching operation comprises an anisotropic vertical etching operation and the second etching operation comprises an isotropic etching operation.

[0122] In some embodiments, the method further includes forming a first dielectric layer above the redistribution layer; forming a second dielectric layer above the first dielectric layer; forming a bump opening in the first dielectric layer and the second dielectric layer above the first redistribution layer structure; forming a second protective layer above the second dielectric layer and the sidewalls of the bump opening; and forming a conductive column above the second protective layer and the bump opening.

[0123] In some embodiments of the method, the conductive pillar includes an under bump metallurgy layer, a copper bump structure, and a solder layer.

[0124] In some embodiments of the method, forming the convex profile includes forming a bottom profile angle defined by the first protection layer at the end of the redistribution layer structure to the horizontal boundary of the redistribution layer and the upwardly extending edge, wherein the bottom profile angle is between about 90 degrees and about 120 degrees.

[0125] In some embodiments of this method, an opening is formed in a redistribution layer above a portion of a metal-insulator-metal capacitor having: a top dimension at its top between about 1.0 microns and about 5.0 microns; a bottom dimension at its bottom between about 0.8 microns and about 4.0 microns; and a minimum dimension between its top and its bottom between about 0.6 microns and about 3.6 microns.

[0126] In some embodiments of this method, the difference between the top dimension and the minimum dimension is between about 0.4 microns and about 1.4 microns; the difference between the top dimension and the bottom dimension is between about 0.2 microns and about 1.0 microns; and the difference between the bottom dimension and the minimum dimension is between about 0.2 microns and about 0.4 microns.

[0127] The foregoing summarizes the features of several embodiments or examples so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can be changed, substituted and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: a first protection layer located above a substrate and containing an embedded metal-insulator-metal (MIM) capacitor; as well as a redistribution layer (RDL) formed on the first protection layer, the RDL comprising a first RDL structure and a second RDL structure, the first RDL structure being separated from the second RDL structure by a dielectric-filled opening, wherein the dielectric-filled opening is located on a portion of the metal-insulator-metal capacitor; A sidewall of each of the first redistribution layer structure and the second redistribution layer structure has a convex profile, and the convex profile defines the dielectric-filled opening separating the first redistribution layer structure and the second redistribution layer structure.

2. The semiconductor device according to claim 1, wherein An angle of a bottom contour defined by the first protection layer at an end of the first redistribution layer structure or the second redistribution layer structure to a horizontal boundary of the redistribution layer and an upwardly extending edge is between 90 degrees and 120 degrees.

3. The semiconductor device according to claim 1 or 2, wherein: The dielectric-filled opening has: A top dimension at the top of the device is between 1.0 micrometer and 5.0 micrometer; A bottom dimension at the bottom thereof is between 0.8 micrometers and 4.0 micrometers; and A minimum dimension between its top and its bottom is between 0.6 microns and 3.6 microns.

4. The semiconductor device according to claim 3, wherein: The difference between the top dimension and the minimum dimension is between 0.4 microns and 1.4 microns; The difference between the top dimension and the bottom dimension is between 0.2 microns and 1.0 microns; and The difference between the bottom dimension and the minimum dimension is between 0.2 microns and 0.4 microns.

5. The semiconductor device according to claim 3, wherein: A barrel height in the dielectric-filled opening is defined as a distance between a plane of the top of the first protective layer and a plane where the minimum dimension is located; and The ratio of the barrel height to a thickness of the redistribution layer is between 2% and 20%.

6. The semiconductor device according to claim 1, wherein: The redistribution layer has a thickness between 2 microns and 3 microns.

7. A semiconductor structure, characterized in that: Include: a first protective layer disposed on a substrate, wherein the first protective layer contains an embedded metal-insulator-metal capacitor; and A redistribution layer, including a first redistribution layer structure and a second redistribution layer structure, is located above the first protection layer, wherein a sidewall of each of the first redistribution layer structure and the second redistribution layer structure has a convex profile.

8. The semiconductor structure according to claim 7, wherein: A bottom contour angle defined by a horizontal boundary from the first protection layer to the redistribution layer at an end of the first redistribution layer structure or the second redistribution layer structure and an upwardly extending edge is between 90 degrees and 120 degrees.

9. A semiconductor structure, characterized in that: Include: A substrate having an interconnect structure in a dielectric layer thereon, and having a first protection layer above the dielectric layer, the first protection layer having a first sublayer, a second sublayer above the first sublayer, and a metal-insulator-metal capacitor between the first sublayer and the second sublayer; as well as A redistribution layer is located above the first protective layer and in the first protective layer above a top metal structure in the interconnect structure, wherein the redistribution layer has a first redistribution layer structure and a second redistribution layer structure, the first redistribution layer structure is not connected to the top metal structure, the second redistribution layer structure is connected to the top metal structure, and a side wall of each of the first redistribution layer structure and the second redistribution layer structure has a convex profile.

10. The semiconductor structure according to claim 9, wherein: An angle of a bottom contour defined by the first protection layer at an end of the first redistribution layer structure or the second redistribution layer structure to a horizontal boundary of the redistribution layer and an upwardly extending edge is between 90 degrees and 120 degrees.

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