Box type equipment

Abstract

The embodiment of the utility model provides box type equipment. The box type equipment comprises a processing module, a bridge piece, a first PHY module and a second PHY module, wherein the first interface of the processing module is electrically connected with the first interface of the bridge sheet; the second interface of the bridge sheet is electrically connected with the first PHY module; the first PHY module comprises a plurality of electrical ports; a third interface of the bridge sheet is electrically connected with the second PHY module, and a second interface of the processing module is electrically connected with the second PHY module; the second PHY module includes a plurality of optical ports. The box-type equipment has the functions of electric signal transmission and optical signal transmission at the same time, the data read-write and processing capabilities of the processing module are fully utilized, and the performance and resources of the box-type equipment are fully exerted.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a box-type device. Background Art

[0002] With the development of communication technology, the data transmission and processing capabilities of devices are increasing. In order to achieve data transmission in different scenarios, sufficient resources are required for management and scheduling. However, in related technologies, although the resources and performance of devices have been greatly improved, they have not been fully utilized. In addition, the scalability of the devices is poor, which hinders the further expansion and utilization of resources. Therefore, how to improve the resource utilization of devices is a technical problem to be solved in this field. Utility Model Content

[0003] The purpose of the embodiments of the present application is to provide a box-type device to achieve the technical effect of improving the resource utilization of the device.

[0004] The embodiment of the present application provides a box-type device, including: a processing module, a bridge chip, a first PHY module and a second PHY module; wherein,

[0005] The first interface of the processing module is electrically connected to the first interface of the bridge chip;

[0006] The second interface of the bridge is electrically connected to the first PHY module; the first PHY module includes a plurality of electrical ports;

[0007] The third interface of the bridge chip is electrically connected to the second PHY module, and the second interface of the processing module is electrically connected to the second PHY module; the second PHY module includes a plurality of optical ports.

[0008] In the above implementation process, the processing module is externally connected to a bridge chip, and the bridge chip is connected to the first PHY module. The first PHY module provides multiple electrical ports, so that the box-type device can transmit electrical signals through the electrical ports. The processing module is connected to the second PHY module, and the second PHY module provides an optical port, so the box-type device can transmit optical signals through the optical port. At the same time, the processing module is externally connected to a bridge chip, and the bridge chip is also connected to the second PHY module. The processing module can expand the number of available optical ports through the bridge chip, so that more optical ports in the second PHY module can be used by the box-type device. The box-type device has the functions of both electrical signal transmission and optical signal transmission, making full use of the data reading, writing and processing capabilities of the processing module, and giving full play to the performance and resources of the box-type device.

[0009] Furthermore, the first interface of the processing module is a high-speed serial computer expansion bus PCIe3.0×8 interface, and the first interface of the bridge chip is a PCIe3.0×16 interface.

[0010] In the above implementation process, the total amount of data transmitted by the PCIe 3.0×8 interface is large, and the PCIe 3.0×8 interface has a high data read and write bandwidth, so the read and write bandwidth of the PCIe 3.0×8 interface in the processing module 110 can be fully utilized, and its read and write resources can be fully utilized.

[0011] Furthermore, the second interface of the bridge chip is a PCIe3.0 interface; the first PHY module is a PHY module for converting PCIe to media independent interface MII; and the first PHY module includes multiple Gigabit electrical ports.

[0012] In the above implementation process, thanks to the high transmission bandwidth of the PCIe3.0 interface, it is ultimately possible to expand multiple Gigabit electrical ports, so that the box-type device can perform high-speed transmission of electrical signals through multiple Gigabit electrical ports.

[0013] Further, the second interface of the bridge chip includes two PCIe3.0×2 interfaces and two PCIe3.0×1 interfaces; the first PHY module includes two four-port PCIe to MII PHY chips and two two-port PCIe to MII PHY chips;

[0014] Wherein, each of the PCIe3.0×2 interfaces is electrically connected to the four-port PCIe to MII PHY chip; each of the four-port PCIe to MII PHY chips includes 4 Gigabit electrical ports;

[0015] Each of the PCIe3.0×1 interfaces is electrically connected to the two-port PCIe-to-MII PHY chip; each of the two-port PCIe-to-MII PHY chips includes two Gigabit electrical ports.

[0016] In the above implementation process, a total of 12 Gigabit electrical ports were expanded through the 4 PCIe3.0 interfaces on the bridge chip, which greatly improved the data transmission performance of the box-type device and fully utilized the powerful data reading and writing and processing capabilities of the processing module.

[0017] Furthermore, the third interface of the bridge chip is a PCIe3.0 interface; the second interface of the processing module is a PCIe3.0 interface; the second PHY module includes a PCIe to MII PHY submodule and an MII to 1000BASE-X PHY submodule; the MII to 1000BASE-X PHY submodule includes multiple Gigabit optical ports.

[0018] In the above implementation process, thanks to the high transmission bandwidth of the PCIe3.0 interface, it is ultimately possible to expand multiple Gigabit optical ports, so that the box-type device can perform high-speed transmission of optical signals through multiple Gigabit optical ports.

[0019] Further, the third interface of the bridge chip includes two PCIe3.0×1 interfaces; the second interface of the processing module includes two PCIe3.0×1 interfaces and one PCIe3.0×8 interface;

[0020] The PCIe-to-MII PHY submodule includes four two-port PCIe-to-MII PHY chips and one four-port PCIe-to-MII PHY chip;

[0021] The MII to 1000BASE-X PHY submodule includes 12 MII to 1000BASE-X PHY chips;

[0022] Among them, each of the PCIe3.0×1 interfaces in the third interface of the bridge chip is electrically connected to the two-port PCIe to MII PHY chip; each of the PCIe3.0×1 interfaces in the second interface of the processing module is electrically connected to the two-port PCIe to MII PHY chip; the PCIe3.0×8 interface in the second interface of the processing module is electrically connected to the four-port PCIe to MII PHY chip;

[0023] Each of the two-port PCIe to MII PHY chips and the four-port PCIe to MII PHY chips are electrically connected to the MII to 1000BASE-X PHY chip respectively; each of the MII to 1000BASE-X PHY chips includes 1 Gigabit optical port.

[0024] In the above implementation process, a total of 12 Gigabit optical ports were expanded through the PCIe3.0 interface on the bridge chip and the processing module, which greatly improved the data transmission performance of the box-type device and fully utilized the powerful data reading and writing and processing capabilities of the processing module.

[0025] Furthermore, the device also includes a business daughter card slot; wherein, the third interface of the processing module is electrically connected to the business daughter card slot; the third interface is a PCIe3.0x8 interface; the business daughter card slot supports an optical port business daughter card; the optical port business daughter card includes a 10 Gigabit optical port.

[0026] In the above implementation process, the optical port service daughter card can output a 10 Gigabit optical interface, so that the box-type device has the communication capability of a 10 Gigabit optical port.

[0027] Furthermore, the device also includes an encryption module; wherein the fourth interface of the bridge chip is electrically connected to the encryption module.

[0028] In the above implementation process, since the processing module is connected to the bridge chip, the encryption chip can control the system startup.

[0029] Furthermore, the processing module is a domestic Feiteng processor; the bridge chip is a domestic Feiteng bridge chip; the first PHY module and the second PHY module include domestic PHY chips; and the encryption module is a domestic trusted platform control module TPCM chip.

[0030] In the above implementation process, the selection and design of domestic devices can ensure that the box-type equipment has the core competitiveness of security, confidentiality, and pure domestic production, has strong competitiveness in the core security field, and ensures reliable and safe operation in high-confidentiality occasions.

[0031] Furthermore, the box-type device is a network intermediate device.

[0032] In the above implementation process, the box-type device is applied in the network security scenario to improve the security of network data transmission to ensure high confidentiality. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A hardware structure diagram of a box-type device provided in an embodiment of the present application;

[0035] Figure 2 A hardware structure diagram of another box-type device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0037] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0038] In order to improve the resource utilization of computing devices, the present application provides a box device. As one feasible example, the box device can be applied to a network security scenario. Exemplarily, the box device can be a network intermediate device for data transmission. Of course, the application scenario of the box device is not limited to the network security scenario, and other scenarios that require data transmission functions can use the box device provided by this implementation. The present application is not limited here.

[0039] like Figure 1 As shown, the box-type device 100 includes a processing module 110 , a bridge chip 120 , a first PHY (Physical, port physical layer) module 130 , and a second PHY module 140 .

[0040] The processing module 110 includes but is not limited to a first interface 111 and a second interface 112. The bridge chip 120 includes but is not limited to a first interface 121, a second interface 122 and a third interface 123.

[0041] The first interface 111 of the processing module 110 is electrically connected to the first interface 121 of the bridge chip 120 .

[0042] The second interface 122 of the bridge chip 120 is electrically connected to the first PHY module 130. The first PHY module 130 includes a plurality of electrical ports (not shown in the figure).

[0043] The third interface 123 of the bridge chip 120 is electrically connected to the second PHY module 140. Meanwhile, the second interface 112 of the processing module 110 is also electrically connected to the second PHY module 140. The second PHY module 140 includes a plurality of optical ports (not shown in the figure).

[0044] The processing module 110 is the computing core and control core of the box device 100, and has the functions of data reading and writing, data processing, and program running. For example, the processing module may be a CPU (Central Processing Unit).

[0045] The bridge chip 120 is a processing chip that directly exchanges data and instructions with the processing module 110 and acts as a connection bridge, and can be used for external expansion of interface functions.

[0046] The first PHY module 130 and the second PHY module 140 have digital-to-analog conversion functions, interface conversion functions, etc. The data from the processing module 110 or the bridge chip 120 can be converted from digital to analog and then transmitted in wires or optical fibers.

[0047] The electrical connection refers to two electrically connected devices being connected via wires or conductor lines to form a pathway that can be used for transmission of data and information.

[0048] It can be seen that the present embodiment provides a box-type device, in which the processing module is externally connected to a bridge chip, and the bridge chip is connected to the first PHY module. The first PHY module is provided with multiple electrical ports, so that the box-type device can transmit electrical signals through the electrical ports. The processing module is connected to the second PHY module, and the second PHY module is provided with an optical port, so the box-type device can transmit optical signals through the optical port. At the same time, the processing module is externally connected to a bridge chip, and the bridge chip is also connected to the second PHY module. The processing module can expand the number of available optical ports through the bridge chip, so that more optical ports in the second PHY module can be used by the box-type device. The box-type device has the functions of both electrical signal transmission and optical signal transmission, fully utilizing the data reading, writing and processing capabilities of the processing module, and giving full play to the performance and resources of the box-type device.

[0049] Based on the above embodiment, illustratively, the first interface 111 of the processing module 110 is a PCIe (Peripheral Component Interconnect express) 3.0×8 interface. The first interface 121 of the bridge chip 120 is a PCIe 3.0×16 interface.

[0050] PCIe is a high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot plugging, and quality of service. PCIe has multiple specifications. This embodiment uses the interface of PCIe3.0 specification, which is the latest standard that can be used in mainstream personal computers in production.

[0051] Among them, the bandwidth of PCIe3.0×8 is smaller than that of PCIe3.0×16, and the PCIe3.0×16 interface is backward compatible with the PCIe3.0×8 interface. Therefore, the data transmission bandwidth between the PCIe3.0×8 interface and the PCIe3.0×16 interface follows the PCIe3.0×8 data transmission bandwidth.

[0052] In addition, according to the above, the processing module 110 is connected to the bridge chip 120 through the PCIe3.0×8 interface, and the bridge chip has multiple electrical ports and optical ports expanded through the first PHY module 130 and the second PHY module 140. Then, all data received through the electrical port, and part of the data received through the optical port, will be transmitted to the PCIe3.0×8 interface of the processing module 110 through the PCIe3.0×16 interface of the bridge chip 120. It can be seen that the total amount of data transmitted by the PCIe3.0×8 interface is large, and at the same time, the PCIe3.0×8 interface has a high data read and write bandwidth. Therefore, the read and write bandwidth of the PCIe3.0×8 interface in the processing module 110 can be fully utilized, and its read and write resources are fully utilized.

[0053] Based on the above embodiment, exemplarily, the second interface 122 of the bridge chip 120 is a PCIe 3.0 interface, for example, a PCIe 3.0×2 or PCIe 3.0×1 interface. The first PHY module 130 is a PCIe to MII (Media Independent Interface) PHY module. The first PHY module 130 includes multiple Gigabit electrical ports.

[0054] The PCIe3.0 interface of the bridge chip 120 is connected to the PCIe to MII PHY module, which can realize the conversion from the PCIe interface to the MII interface. Thanks to the high transmission bandwidth of the PCIe3.0 interface, multiple Gigabit electrical ports can be expanded, so that the box-type device can transmit electrical signals at high speed through multiple Gigabit electrical ports.

[0055] Further, see Figure 2 , Figure 2 The second interface 122 of the PCIE bridge shown includes four, specifically, two PCIe 3.0×2 interfaces (i.e. Figure 2 The PCIe 3.0×2 interface 1 and PCIe 3.0×2 interface 2 in the PCIE bridge shown in the figure are connected to two PCIe 3.0×1 interfaces (i.e. Figure 2 The PCIe 3.0×1 interface 3 and the PCIe 3.0×1 interface 4 in the PCIE bridge shown.

[0056] The first PHY module 130 includes four PCIe to MII PHY chips, specifically, two four-port PCIe to MII PHY chips (i.e. Figure 2 4-port Gigabit electrical port PHY chip 1 and 4-port Gigabit electrical port PHY chip 2), and 2 2-port PCIe to MII PHY chips (i.e. Figure 2 2-port Gigabit electrical port PHY chip 1 and 2-port Gigabit electrical port PHY chip 2).

[0057] Among them, each PCIe3.0×2 interface in the second interface 122 is electrically connected to the four-port PCIe to MII PHY chip. Each PCIe3.0×2 interface has a one-to-one correspondence with the four-port PCIe to MII PHY chip. Since each four-port PCIe to MII PHY chip includes 4 Gigabit electrical ports, each PCIe3.0×2 interface in the second interface 122 can be expanded to 4 Gigabit electrical ports. The 2 PCIe3.0×2 interfaces in the second interface 122 of the bridge chip 120 can be expanded to a total of 8 Gigabit electrical ports (i.e. Figure 2 Gigabit Ethernet ports 0-7 are shown).

[0058] In addition, each PCIe3.0×1 interface in the second interface 122 is electrically connected to a two-port PCIe to MII PHY chip. Each PCIe3.0×1 interface has a one-to-one correspondence with a two-port PCIe to MII PHY chip. Since each two-port PCIe to MII PHY chip includes two Gigabit electrical ports, each PCIe3.0×1 interface in the second interface 122 can be expanded to two Gigabit electrical ports. The two PCIe3.0×1 interfaces in the second interface 122 of the bridge chip 120 can be expanded to a total of four Gigabit electrical ports (i.e. Figure 2 Thus, the second interface 122 of the bridge chip 120 has a total of 12 Gigabit electrical ports.

[0059] It can be seen that a total of 12 Gigabit electrical ports are expanded through the 4 PCIe3.0 interfaces on the bridge chip, which greatly improves the data transmission performance of the box-type device and fully utilizes the powerful data reading and writing and processing capabilities of the processing module.

[0060] Based on the above embodiments, exemplarily, the third interface 123 of the bridge chip 120 is a PCIe3.0 interface, for example, it can be a PCIe3.0×1 interface. The second interface 112 of the processing module 110 is a PCIe3.0 interface, for example, it can be a PCIe3.0×1 interface or a PCIe3.0×8 interface. The second PHY module 140 includes a PHY submodule for PCIe to MII and a PHY submodule for MII to 1000BASE-X. The PHY submodule for MII to 1000BASE-X includes multiple Gigabit optical ports.

[0061] The PCIe3.0 interface of the bridge chip 120 is electrically connected to the PHY submodule of PCIe to MII, and the PCIe3.0 interface of the processing module 110 is electrically connected to the PHY submodule of PCIe to MII. The PHY submodule of PCIe to MII is electrically connected to the PHY submodule of MII to 1000BASE-X.

[0062] The PCIe to MII PHY submodule can realize the conversion from PCIe interface to MII interface. The MII to 1000BASE-X PHY submodule can realize the conversion from MII interface to 1000BASE-X interface, that is, the optical port. Thanks to the high transmission bandwidth of the PCIe3.0 interface, it is finally possible to expand multiple Gigabit optical ports, so that the box-type device can transmit optical signals at high speed through multiple Gigabit optical ports.

[0063] Further, see Figure 2 , Figure 2 The third interface 123 of the PCIE bridge shown includes two, specifically, two PCIe 3.0×1 interfaces (i.e. Figure 2 The PCIe 3.0×1 interface 1 and the PCIe 3.0×1 interface 2 in the PCIE bridge shown.

[0064] The second interface 112 of the processing module 110 includes three, specifically, two PCIe 3.0×1 interfaces (i.e. Figure 2 The central processor shown has a PCIe 3.0×1 interface 1 and a PCIe 3.0×1 interface 2) and a PCIe 3.0×8 interface (i.e. Figure 2 The PCIe 3.0×8 interface in the central processing unit is shown 2).

[0065] The PCIe-to-MII PHY submodule in the second PHY module 140 includes five PCIe-to-MII PHY chips, specifically, four two-port PCIe-to-MII PHY chips (i.e. Figure 2 2-port Gigabit electrical port PHY chip 3-6), and 1 4-port PCIe to MII PHY chip (i.e. Figure 2 4-port Gigabit electrical port PHY chip in 3).

[0066] The MII-to-1000BASE-X PHY submodule in the second PHY module 140 includes 12 MII-to-1000BASE-X PHY chips (i.e. Figure 2 MII to 1000BASE-X PHY chips 0-11).

[0067] Among them, each PCIe3.0×1 interface in the third interface 123 of the bridge chip 120 is electrically connected to the two-port PCIe to MII PHY chip. Each PCIe3.0×1 interface in the second interface 112 of the processing module 110 is electrically connected to the two-port PCIe to MII PHY chip. Each PCIe3.0×1 interface and the two-port PCIe to MII PHY chip are in a one-to-one correspondence. Each two-port PCIe to MII PHY chip can provide 2 MII interfaces. In this way, each PCIe3.0×1 interface in the third interface 123 of the bridge chip 120 can expand 2 MII interfaces, and each PCIe3.0×1 interface in the second interface 112 of the processing module 110 can expand 2 MII interfaces.

[0068] In addition, the PCIe3.0×8 interface in the second interface 112 of the processing module 110 is electrically connected to the four-port PCIe to MII PHY chip. The PCIe3.0×8 interface and the four-port PCIe to MII PHY chip are in a one-to-one correspondence. Each four-port PCIe to MII PHY chip can provide 4 MII interfaces. In this way, each PCIe3.0×8 interface in the second interface 112 of the processing module 110 can expand 4 MII interfaces.

[0069] That is, the third interface 123 of the bridge chip 120 has a total of 4 MII interfaces externally expanded, and the second interface of the processing module 110 has a total of 8 MII interfaces externally expanded.

[0070] At the same time, each two-port PCIe to MII PHY chip and each four-port PCIe to MII PHY chip are electrically connected to the MII to 1000BASE-X PHY chip. Exemplarily, in the two-port PCIe to MII PHY chip and the four-port PCIe to MII PHY chip, each MII interface is in a one-to-one correspondence with the MII to 1000BASE-X PHY chip.

[0071] Thus, since each two-port PCIe to MII PHY chip includes two MII interfaces, each two-port PCIe to MII PHY chip is electrically connected to two MII to 1000BASE-X PHY chips. Since each four-port PCIe to MII PHY chip includes four MII interfaces, each four-port PCIe to MII PHY chip is electrically connected to four MII to 1000BASE-X PHY chips.

[0072] Each MII to 1000BASE-X PHY chip includes one Gigabit optical port.

[0073] Thus, the third interface 123 of the bridge chip 120 includes two PCIe 3.0×1 interfaces, which are expanded to four MII interfaces through two two-port PCIe to MII PHY chips, and finally four Gigabit optical ports (i.e. Figure 2 Gigabit optical ports 0-3 are shown).

[0074] The second interface 112 of the processing module 110 includes two PCIe3.0×1 interfaces, which can be expanded to four MII interfaces through two two-port PCIe to MII PHY chips, and can eventually expand to four Gigabit optical ports (i.e. Figure 2 Gigabit optical ports 4-7 are shown).

[0075] The second interface 112 of the processing module 110 includes a PCIe3.0×8 interface, which can be expanded to four MII interfaces through a four-port PCIe to MII PHY chip, and can eventually expand to four Gigabit optical ports (i.e. Figure 2 Gigabit optical ports 8-11 are shown).

[0076] It can be seen that a total of 12 Gigabit optical ports are expanded through the PCIe3.0 interface on the bridge chip and the processing module, which greatly improves the data transmission performance of the box-type device and fully utilizes the powerful data reading and writing and processing capabilities of the processing module.

[0077] Based on any of the above embodiments, the box-type device further includes a service daughter card slot. The processing module further includes a third interface. The third interface is a PCIe3.0x8 interface. The third interface of the processing module is electrically connected to the service daughter card slot. The service daughter card slot supports an optical port service daughter card. The optical port service daughter card includes a 10 Gigabit optical port.

[0078] For example, the 10 Gigabit optical port may be 4 × 10G SFP+ optical interface.

[0079] For example, Figure 2 As shown, the third interface of the processing module may include two, namely Figure 2 The PCIe 3.0x8 interface 3 and the PCIe 3.0x8 interface 4 in the central processor are shown. The two PCIe 3.0x8 interfaces are electrically connected to the service daughter card slots. Figure 2 The optical port service daughter card can output 4 × The 10G SFP+ optical interface enables the box-type device to have the communication capability of a 10G optical port.

[0080] Based on any of the above embodiments, the box-type device further includes an encryption module. The bridge chip further includes a fourth interface. The fourth interface of the bridge chip is electrically connected to the encryption module.

[0081] Exemplarily, the encryption module may include a TPCM (Trusted Platform Control Module) chip, which is a type of encryption chip.

[0082] As an example, Figure 2 As shown, the fourth interface of the bridge sheet includes two, namely Figure 2 The SPI interface 1 and SPI interface 2 in the PCIE bridge are shown. The two SPI interfaces are externally connected to the encryption chip. Since the processing module is connected to the bridge through the PCIE3.0 x8 interface, the TPCM encryption chip can control the system startup.

[0083] Based on any of the above embodiments, Figure 2 As shown, the box-type device also includes the following hardware modules:

[0084] 1) System Management Interface

[0085] Figure 2 The central processor shown includes an RGMII (Reduced Gigabit Media Independent Interface) interface, an external PHY chip, and provides one serial port through the PHY chip. Exemplarily, the serial port is a console port.

[0086] The central processing unit includes a UART (Universal Asynchronous Receiver / Transmitter) interface, an external serial port driver chip, and provides a network management port through the serial port driver chip. Exemplarily, the network management port is an RJ45 network management port.

[0087] The central processing unit includes an I2C (Inter-Integrated Circuit) interface, specifically Figure 2 The I2C interface 2 in the central processing unit is shown. The I2C interface is externally connected to an I2C switch, and the I2C switch is externally connected to a system power supply and a system fan. Specifically, the system power supply is a pluggable power supply, and the number can be 2. The system fan is a pluggable PWM (Pulse Width Modulation) speed regulating fan, and the number can be 4.

[0088] 2) Storage unit interface

[0089] Figure 2The PCIE bridge shown includes a USB (Universal Serial Bus) 3.0 interface. The USB 3.0 interface includes two, namely Figure 2 The USB 3.0 interface 1 and the USB 3.0 interface 2 in the PCIE bridge chip are shown. The two USB 3.0 interfaces are used for external storage expansion.

[0090] In addition, the PCIE bridge also includes a SATA (Serial ATA) 3.0 interface. Among them, the SATA 3.0 interface includes two, namely Figure 2 The SATA 3.0 interface 1 and the SATA 3.0 interface 2 in the PCIE bridge are shown in FIG. The two SATA 3.0 interfaces are used to provide hard disk slots 1-2 for expanding the system storage space. For example, the hard disk slots may be 2.5-inch slots.

[0091] In addition, the PCIE bridge chip also includes an eMMC (Embedded Multi Media Card) interface. For example, it is an eMMC5.1 interface. The eMMC interface can be connected to an external 32G eMMC memory card as a system disk.

[0092] 3)CPU system

[0093] Figure 2 The central processing unit shown includes a DDR interface. For example, a DDR4 interface. The DDR interface can be connected to an external memory stick. For example, a UDIMM (Unbuffered Dual In-Line Memory Modules) memory stick. The number of UDIMM memory sticks can be 2, and the memory space can be 32G.

[0094] In addition, the central processing unit also includes a QSPI (Quad Serial Perripheral Interface) interface, and two external Norflash (non-volatile flash memory) chips are connected to execute the boot program.

[0095] In addition, the CPU also includes an I2C interface, specifically Figure 2 The I2C interface 1 in the central processing unit is shown. Through the I2C interface, an external temperature sensing chip and an EEPROM (Electrically Erasable Programmable ReadOnly Memory) chip can be connected to realize the device temperature management and device information management functions.

[0096] In addition, the central processing unit also includes an SPI (Serial Perripheral Interface) interface. An external logic control unit can be connected via the SPI interface. Exemplarily, the logic control unit may include a programmable logic chip to implement one or more of device status monitoring, interrupt reporting, power-on timing control, and reset control.

[0097] 4) Power supply and clock unit

[0098] like Figure 2 As shown, there are many types of secondary power supplies in the system, including 11 types in total, namely V, 3.3V, 1.8V_1, 1.8V_2, 1.2V_1, 1.2V_2, 1.1V, 0.9V, 0.88V, and 0.8V.

[0099] There are 6 types of system clocks in total, including 2 100Mhz differential clocks, 48Mhz single-ended clock, 33Mhz single-ended clock, and 2 25Mhz single-ended clocks.

[0100] based on Figure 2 The box-type device shown has the following working process: After the box-type device is powered on, the central processing unit boots the startup program through the external Norflash chip, and the encryption chip, namely the TPCM chip, verifies the startup boot. After the verification passes, the system completes the loading of the boot program. After the boot program is loaded, the startup work of running APP (Application) is started. The system loads the running APP from the external eMMC memory card into the memory stick and starts the running APP startup process. During the startup process of the APP, all PHY chips, PCIE bridge chips and programmable logic chips will be initialized, and the boot program will be loaded and verified. After the running APP starts normally, the box-type device can be managed and service configuration can be performed.

[0101] Specifically, box device management can include: temperature monitoring, device information management, fan speed regulation, power status monitoring, etc. Business configuration refers to completing the connection networking and command line configuration distribution according to actual business needs to ensure the normal implementation of business functions and performance.

[0102] In addition, in the context of the promotion of domestic information security, information security issues are becoming increasingly important. In the past, security equipment often relied on foreign hardware manufacturing technology. However, with the vigorous development of domestic chip manufacturing technology, a mature domestic alternative has gradually been formed. Modern information technology competition is no longer a competition of single products and technologies, but a competition involving industrial chains and ecosystems.

[0103] In order to comply with the purely domestic design concept advocated by the country and meet the application requirements of equipment in key core areas of the country, this embodiment also provides a box-type device based on purely domestic hardware design.

[0104] Specifically, the processing module, namely Figure 1 The processing module 110 in Figure 2 The central processor in the device can be a domestic Feiteng processor, for example, Feiteng Tengrui D2000 / 8 standard version (2.3GHz).

[0105] The bridge piece, namely Figure 1 The bridge piece in 120, or Figure 2 The PCIE bridge chip in the embodiment can be a domestic Feiteng bridge chip, for example, a Feiteng bridge chip X100.

[0106] The first PHY module and the second PHY module include domestic PHY chips. Specifically, the four-port PCIe to MII PHY chip (i.e. Figure 2 The 4-port Gigabit electrical port PHY chip 1-3 shown in the figure can use the PHY chip of Netcom WX1860A4. The 2-port PCIe to MII PHY chip (i.e. Figure 2 The 2-port Gigabit electrical port PHY chip 1-6 shown in the figure can use the PHY chip of Netcom WX1860A2. The PHY chip of MII to 1000BASE-X (i.e. Figure 2 The MII to 1000BASE-X PHY chip 0-11) shown can use the YT8521 PHY chip of Yutai Micro.

[0107] In addition, the optical port service subcard described in the above embodiment can adopt the PHY chip of MuChuang N10G-X4. The programmable logic chip can adopt the CPLD (Complex Programmable logic device) chip of Unigroup Tongchuang. The memory used by the box-type device can adopt Unigroup Guoxin memory. And the encryption chip can adopt the National Technology TPCM encryption chip. In addition, the remaining non-core components in the box-type device also adopt pure domestic solutions. The selection and design of domestic devices can ensure that the box-type equipment has the core competitiveness of security and confidentiality, pure domestic products, has strong competitiveness in the core field of security, and ensures reliable and safe operation in high confidentiality occasions.

[0108] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0109] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0110] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0111] The above description is only an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0112] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0113] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

Claims

1. A box-type device, characterized in that: include: A processing module, a bridge chip, a first PHY module and a second PHY module; wherein, The first interface of the processing module is electrically connected to the first interface of the bridge chip; The second interface of the bridge is electrically connected to the first PHY module; the first PHY module includes a plurality of electrical ports; The third interface of the bridge chip is electrically connected to the second PHY module, and the second interface of the processing module is electrically connected to the second PHY module; the second PHY module includes a plurality of optical ports.

2. The device according to claim 1, characterized in that The first interface of the processing module is a high-speed serial computer expansion bus PCIe3.0×8 interface, and the first interface of the bridge chip is a PCIe3.0×16 interface.

3. The device according to claim 1, characterized in that The second interface of the bridge chip is a PCIe3.0 interface; the first PHY module is a PHY module for converting PCIe to media independent interface MII; the first PHY module includes multiple Gigabit electrical ports.

4. The device according to claim 3, characterized in that The second interface of the bridge chip includes two PCIe3.0×2 interfaces and two PCIe3.0×1 interfaces; the first PHY module includes two four-port PCIe to MII PHY chips and two two-port PCIe to MII PHY chips; Wherein, each of the PCIe3.0×2 interfaces is electrically connected to the four-port PCIe to MII PHY chip; each of the four-port PCIe to MII PHY chips includes 4 Gigabit electrical ports; Each of the PCIe3.0×1 interfaces is electrically connected to the two-port PCIe-to-MII PHY chip; each of the two-port PCIe-to-MII PHY chips includes two Gigabit electrical ports.

5. The device according to claim 1, characterized in that The third interface of the bridge chip is a PCIe3.0 interface; the second interface of the processing module is a PCIe3.0 interface; the second PHY module includes a PCIe to MII PHY submodule and a MII to 1000BASE-X PHY submodule; the MII to 1000BASE-X PHY submodule includes multiple Gigabit optical ports.

6. The device according to claim 5, characterized in that The third interface of the bridge chip includes two PCIe3.0×1 interfaces; the second interface of the processing module includes two PCIe3.0×1 interfaces and one PCIe3.0×8 interface; The PCIe-to-MII PHY submodule includes four two-port PCIe-to-MII PHY chips and one four-port PCIe-to-MII PHY chip; The MII to 1000BASE-X PHY submodule includes 12 MII to 1000BASE-X PHY chips; Among them, each of the PCIe3.0×1 interfaces in the third interface of the bridge chip is electrically connected to the two-port PCIe to MII PHY chip; each of the PCIe3.0×1 interfaces in the second interface of the processing module is electrically connected to the two-port PCIe to MII PHY chip; the PCIe3.0×8 interface in the second interface of the processing module is electrically connected to the four-port PCIe to MII PHY chip; Each of the two-port PCIe to MII PHY chips and the four-port PCIe to MII PHY chips are electrically connected to the MII to 1000BASE-X PHY chip respectively; each of the MII to 1000BASE-X PHY chips includes 1 Gigabit optical port.

7. The device according to any one of claims 1 to 6, characterized in that: The device also includes a service daughter card slot; wherein, the third interface of the processing module is electrically connected to the service daughter card slot; the third interface is a PCIe3.0x8 interface; the service daughter card slot supports an optical port service daughter card; the optical port service daughter card includes a 10 Gigabit optical port.

8. The device according to any one of claims 1 to 6, characterized in that: The device further includes an encryption module; wherein the fourth interface of the bridge chip is electrically connected to the encryption module.

9. The device according to claim 8, characterized in that The processing module is a domestic Feiteng processor; the bridge chip is a domestic Feiteng bridge chip; the first PHY module and the second PHY module include domestic PHY chips; the encryption module is a domestic trusted platform control module TPCM chip.

10. The device according to claim 1, characterized in that The box-type device is a network intermediate device.

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