Circuit board

Abstract

A circuit board is provided. The interlayer connection conductor is provided inside a through-hole that passes through the first insulator layer and the second insulator layer in the Z-axis direction. The first conductor layer is located on the negative main surface of the insulator layer at a position closer to the negative direction of the Z axis than the second insulator layer, and is in contact with an end portion of the interlayer connection conductor in the negative direction of the Z axis. The second conductor layer is located on the front main surface of the second insulator layer and is in contact with an end portion of the interlayer connection conductor in the positive direction of the Z axis. A surface roughness of a portion of the inner peripheral surface of the through hole located in the second insulator layer is greater than a surface roughness of a portion of the inner peripheral surface of the through hole located in the first insulator layer. A conductor layer in contact with the interlayer connection conductor is not provided between the first insulator layer and the second insulator layer.

Description

Technical Field

[0001] The utility model relates to a circuit substrate having a structure in which a plurality of insulating layers are stacked. Background Art

[0002] As a conventional invention related to a circuit substrate, for example, a resin substrate described in Patent Document 1 is known. The resin substrate includes a resin substrate, an interlayer connection conductor, and two conductors, and the resin substrate has a structure in which a plurality of insulating substrate layers are stacked in the vertical direction. The two conductors are provided on the upper main surface and the lower main surface of the insulating layer. The interlayer connection conductor penetrates the insulating layer in the vertical direction. Thus, the interlayer connection conductor electrically connects the two conductors.

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2020 / 045402 Utility Model Content

[0006] Problems to be solved by utility models

[0007] However, in the resin substrate described in Patent Document 1, there is a desire to suppress the occurrence of poor connection between the interlayer connection conductors and the conductors.

[0008] Therefore, an object of the present invention is to provide a circuit board and a method for manufacturing the circuit board that can suppress the occurrence of poor connection between an interlayer connection conductor and a conductor layer.

[0009] Technical solutions to solve problems

[0010] A circuit substrate according to one aspect of the present invention comprises:

[0011] A laminate having a structure in which a plurality of insulating layers including a first insulating layer and a second insulating layer are laminated in a Z-axis direction, wherein the second insulating layer has a Young's modulus at room temperature higher than that of the first insulating layer at room temperature, wherein the plurality of insulating layers respectively have a negative principal surface located in the negative direction of the Z-axis and a positive principal surface located in the positive direction of the Z-axis, and the negative principal surface of the second insulating layer is in contact with the positive principal surface of the first insulating layer;

[0012] an interlayer connection conductor disposed inside a through hole penetrating the first insulating layer and the second insulating layer along the Z-axis direction;

[0013] a first conductor layer located on the negative main surface of the insulating layer more negative in the Z-axis direction than the second insulating layer and in contact with an end of the interlayer connecting conductor in the negative direction of the Z-axis; and

[0014] a second conductor layer located on the front main surface of the second insulator layer and in contact with an end portion of the interlayer connection conductor in the positive direction of the Z axis,

[0015] The surface roughness of a portion of the inner peripheral surface of the through hole located in the second insulator layer is greater than the surface roughness of a portion of the inner peripheral surface of the through hole located in the first insulator layer.

[0016] A conductor layer in contact with the interlayer connection conductor is not provided between the first insulator layer and the second insulator layer.

[0017] A method for manufacturing a circuit board according to one aspect of the present invention comprises:

[0018] A preparation step of preparing a first insulator layer and a second insulator layer having a negative main surface located in the negative direction of the Z axis and a positive main surface located in the positive direction of the Z axis, wherein the second insulator layer has a Young's modulus at room temperature higher than that of the first insulator layer at room temperature, and a second conductor layer is provided on the positive main surface of the second insulator layer;

[0019] a lamination step of laminating the first insulator layer and the second insulator layer after the preparation step so that the negative main surface of the second insulator layer in the Z axis contacts the positive main surface of the first insulator layer;

[0020] a through hole forming step of irradiating a laser beam from a space located in a negative direction of the first insulator layer and the second insulator layer after the lamination step to form a through hole penetrating the first insulator layer and the second insulator layer in a Z-axis direction; and

[0021] an interlayer connection conductor forming step of forming an interlayer connection conductor inside the through hole after the through hole forming step,

[0022] In the through hole forming step, the laser beam is irradiated while increasing the intensity of the laser beam with the passage of time.

[0023] Utility Model Effect

[0024] According to the circuit board and the method for manufacturing the circuit board of the present invention, it is possible to suppress the occurrence of poor connection between the interlayer connection conductor and the conductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is an exploded perspective view of the circuit board 10 .

[0026] Figure 2 It is a cross-sectional view of the right end portion of the circuit board 10 .

[0027] Figure 3 It is a rear view of the electronic device 1 including the circuit board 10 .

[0028] Figure 4 It is a cross-sectional view of the circuit board 10 during manufacturing.

[0029] Figure 5 It is a cross-sectional view of the circuit board 10 during manufacturing.

[0030] Figure 6 It is a cross-sectional view of the circuit board 10 during manufacturing.

[0031] Figure 7 It is a cross-sectional view of the circuit board 10 during manufacturing.

[0032] Figure 8 It is a cross-sectional view of the circuit board 10 during manufacturing.

[0033] Fig. 9 It is a cross-sectional view of the right end portion of the circuit board 10a.

[0034] Fig.10 It is a cross-sectional view of the right end portion of the circuit board 10b.

[0035] Fig.11 It is a cross-sectional view of the right end portion of the circuit board 10c.

[0036] Fig.12 It is a cross-sectional view of the right end portion of the circuit board 10d.

[0037] Fig.13 It is a cross-sectional view of the right end portion of the circuit board 10e.

[0038] Description of Reference Numerals

[0039] 1: Electronic equipment;

[0040] 10, 10a~10e: circuit substrate;

[0041] 12: laminate;

[0042] 16a, 16b, 16e, 17a-17e, 18a, 18b, 116a, 116b: insulator layer;

[0043] 20: signal conductor layer;

[0044] 22: first ground conductor layer;

[0045] 24: second ground conductor layer;

[0046] 26a, 26b: signal terminals;

[0047] 28a, 28b, 30a, 30b, 32a, 32b, 34a, 34b: connecting conductor layers;

[0048] 200a-200e: conductor layer;

[0049] A1: first interval;

[0050] A2: The second interval;

[0051] A3: The third interval;

[0052] H: through hole;

[0053] P: particle;

[0054] Pa, Pb, Pc: part;

[0055] v1, v2, v2a, v2b, v3, v4, v4a, v4b, v4c, v4d, v4e, v5, v6: interlayer connecting conductors. DETAILED DESCRIPTION

[0056] (Implementation Method)

[0057] [Structure of circuit board]

[0058] Hereinafter, the structure of the circuit board 10 according to the embodiment of the present invention will be described with reference to the drawings. Figure 1 It is an exploded perspective view of the circuit board 10 . Figure 2 2 is a cross-sectional view of the right end portion of the circuit substrate 10. Figure 2 , a cross section perpendicular to the front-rear direction is shown.

[0059] In this specification, directions are defined as follows. The stacking direction of the laminate 12 of the circuit substrate 10 is defined as the up-down direction. In addition, the up-down direction is consistent with the Z-axis direction. The upper direction is the positive direction of the Z-axis. The lower direction is the negative direction of the Z-axis. In addition, the direction in which the signal conductor layer 20 of the circuit substrate 10 extends is defined as the left-right direction. In addition, the line width direction of the signal conductor layer 20 when observed along the up-down direction is defined as the front-back direction. The up-down direction, the front-back direction, and the left-right direction are orthogonal to each other. It should be noted that the upper direction and the lower direction of the up-down direction can also be swapped, the left direction and the right direction of the left-right direction can also be swapped, and the front direction and the rear direction of the front-back direction can also be swapped.

[0060] Hereinafter, X is a component or member of the circuit board 10. In this specification, unless otherwise specified, the various parts of X are defined as follows. The front part of X refers to the front half of X. The rear part of X refers to the rear half of X. The left part of X refers to the left half of X. The right part of X refers to the right half of X. The upper part of X refers to the upper half of X. The lower part of X refers to the lower half of X. The front end of X refers to the front end of X. The rear end of X refers to the rear end of X. The left end of X refers to the left end of X. The right end of X refers to the right end of X. The upper end of X refers to the upper end of X. The lower end of X refers to the lower end of X. The front end of X refers to the front end of X and its vicinity. The rear end of X refers to the rear end of X and its vicinity. The left end of X refers to the left end of X and its vicinity. The right end of X refers to the right end of X and its vicinity. The upper end of X refers to the upper end of X and its vicinity. The lower end of X refers to the lower end of X and its vicinity.

[0061] First, refer to Figure 1 The structure of the circuit substrate 10 is described. The circuit substrate 10 transmits high-frequency signals. The circuit substrate 10 is used to electrically connect two circuits in electronic devices such as smartphones. Figure 1 As shown, the circuit substrate 10 includes a stacked body 12, a signal conductor layer 20, a first ground conductor layer 22, a second ground conductor layer 24, signal terminals 26a, 26b, connecting conductor layers 28a, 28b, 30a, 30b, 32a, 32b, 34a, 34b, interlayer connecting conductors v1 to v4, and a plurality of interlayer connecting conductors v5, v6.

[0062] The stack 12 has a plate shape. Therefore, the stack 12 has an upper main surface and a lower main surface. The upper main surface and the lower main surface of the stack 12 have a rectangular shape, and the rectangular shape has a long side extending in the left-right direction. Therefore, the length of the stack 12 in the left-right direction is longer than the length of the stack 12 in the front-back direction. The stack 12 has flexibility.

[0063] like Figure 1 As shown, the stack 12 has a structure in which insulating layers 16a, 16b, 17a to 17e, 18a, and 18b are stacked in the up-down direction (Z-axis direction). The insulating layers 18a, 16a, 17a, 16b, 17b to 17e, and 18b are stacked in order from top to bottom. The insulating layers 16a, 16b, 17a to 17e, 18a, and 18b have a lower main surface (a negative main surface located in the negative direction of the Z-axis) and an upper main surface (a positive main surface located in the positive direction of the Z-axis). The lower main surface (negative main surface) of the insulating layer 16a (the second insulating layer) is in contact with the upper main surface (positive main surface) of the insulating layer 17a (the first insulating layer). The lower main surface (negative main surface) of the insulating layer 16b (the second insulating layer) is in contact with the upper main surface (positive main surface) of the insulating layer 17b (the first insulating layer).

[0064] The insulating layers 16a, 16b, 17a to 17e, 18a, and 18b have the same rectangular shape as the stack 12 when viewed in the up-down direction. The insulating layers 16a, 16b, and 17a to 17e are flexible dielectric sheets. The material of the insulating layers 16a, 16b, and 17a to 17e is, for example, a thermoplastic resin. However, the insulating layers 16a and 16b (second insulating layers) have a Young's modulus at room temperature that is higher than the Young's modulus of the insulating layers 17a to 17e (first insulating layers) at room temperature. The material of the insulating layers 16a and 16b is, for example, a fluororesin. The material of the insulating layers 17a to 17e is, for example, a liquid crystal polymer. In addition, the thickness of the insulating layers 16a and 16b (second insulating layers) in the up-down direction (Z-axis direction) is smaller than the thickness of the insulating layers 17a and 17b (first insulating layers) in the up-down direction (Z-axis direction). In this specification, the thickness of the insulating layer in the vertical direction is, for example, an average value of the thickness of the entire insulating layer in the vertical direction. The insulating layers 18a and 18b will be described below.

[0065] like Figure 1 As shown, the signal conductor layer 20 is provided in the laminate 12. In the present embodiment, the signal conductor layer 20 is located on the upper main surface of the insulator layer 17c. In other words, the signal conductor layer 20 (second conductor layer) is located on the lower main surface (negative main surface) of the insulator layer 17b (first insulator layer), and the insulator layer 17b is located below (negative direction of the Z axis) the insulator layer 16b (second insulator layer). The signal conductor layer 20 has a linear shape. The signal conductor layer 20 extends in the left-right direction. High-frequency signals are transmitted in the signal conductor layer 20.

[0066] like Figure 1 As shown, the first ground conductor layer 22 is provided in the laminate 12. The first ground conductor layer 22 is provided at a position above the signal conductor layer 20 so as to overlap with the signal conductor layer 20 when viewed in the up-down direction. In the present embodiment, the first ground conductor layer 22 (second conductor layer) is located on the upper main surface (front main surface) of the insulator layer 16a (second insulator layer). In addition, the first ground conductor layer 22 covers substantially the entire upper main surface of the insulator layer 16a. The first ground conductor layer 22 is connected to the ground potential.

[0067] like Figure 1As shown, the second ground conductor layer 24 is provided in the laminate 12. The second ground conductor layer 24 is provided at a position lower than the signal conductor layer 20 so as to overlap with the signal conductor layer 20 when viewed in the up-down direction. In the present embodiment, the second ground conductor layer 24 is located on the lower main surface of the insulating layer 17e. In addition, the second ground conductor layer 24 covers substantially the entire lower main surface of the insulating layer 17e. The ground potential is connected to the second ground conductor layer 24. The signal conductor layer 20, the first ground conductor layer 22, and the second ground conductor layer 24 as described above have a stripline structure.

[0068] The signal terminal 26b is provided at the right end of the laminate 12. More specifically, the signal terminal 26b (second conductor layer) is located on the upper main surface (front main surface) of the insulator layer 16a (second insulator layer). The signal terminal 26b overlaps the right end of the signal conductor layer 20 when viewed in the up-down direction. The signal terminal 26b has a rectangular shape when viewed in the up-down direction. The signal terminal 26b is an external terminal for inputting and outputting high-frequency signals. The signal terminal 26b does not contact the first ground conductor layer 22.

[0069] The connecting conductor layer 28b is provided at the right end of the laminate 12. In more detail, the connecting conductor layer 28b (second conductor layer) is located on the upper main surface (positive main surface) of the insulator layer 16b (second insulator layer). In other words, the connecting conductor layer 28b (first conductor layer) is located on the lower main surface (negative main surface) of the insulator layer 17a (first insulator layer), and the insulator layer 17a is located below (negative direction of the Z axis) the insulator layer 16a (second insulator layer). The connecting conductor layer 28b functions as a first conductor layer relative to the interlayer connecting conductor v2a, and functions as a second conductor layer relative to the interlayer connecting conductor v2b. The connecting conductor layer 28b overlaps with the right end of the signal conductor layer 20 when viewed in the up-down direction. The connecting conductor layer 28b has a rectangular shape when viewed in the up-down direction.

[0070] The connecting conductor layer 30b is provided at the right end of the laminate 12. In more detail, the connecting conductor layer 30b (second conductor layer) is located on the upper principal surface (positive principal surface) of the insulator layer 16b (second insulator layer). The connecting conductor layer 30b is located on the right side of the connecting conductor layer 28b. In other words, the connecting conductor layer 30b (first conductor layer) is located on the lower principal surface (negative principal surface) of the insulator layer 17a (first insulator layer), and the insulator layer 17a is located below (negative direction of the Z axis) than the insulator layer 16a (second insulator layer). The connecting conductor layer 30b overlaps with the first grounding conductor layer 22 and the second grounding conductor layer 24 when viewed in the up-down direction. The connecting conductor layer 30b has a rectangular shape when viewed in the up-down direction.

[0071] The connecting conductor layer 32b is provided at the right end of the laminate 12. More specifically, the connecting conductor layer 32b (second conductor layer) is located on the upper main surface of the insulating layer 17c. In other words, the connecting conductor layer 32b (first conductor layer) is located on the lower main surface (negative main surface) of the insulating layer 17b (first insulating layer), and the insulating layer 17b is located below (negative direction of the Z axis) the insulating layer 16b (second insulating layer). The connecting conductor layer 32b overlaps the first grounding conductor layer 22 and the second grounding conductor layer 24 when viewed in the up-down direction. The connecting conductor layer 32b has a rectangular shape when viewed in the up-down direction.

[0072] The connection conductor layer 34b is provided at the right end of the laminate 12. More specifically, the connection conductor layer 34b is located on the upper main surface of the insulating layer 17d. The connection conductor layer 34b overlaps the first ground conductor layer 22 and the second ground conductor layer 24 when viewed in the up-down direction. The connection conductor layer 34b has a rectangular shape when viewed in the up-down direction.

[0073] The interlayer connection conductor v2 electrically connects the signal terminal 26b, the connection conductor layer 28b, and the right end of the signal conductor layer 20. In more detail, the interlayer connection conductor v2 includes interlayer connection conductors v2a and v2b. The interlayer connection conductor v2a is arranged inside a through hole that penetrates the insulator layer 16a (the second insulator layer) and the insulator layer 17a (the first insulator layer) in the up-down direction (Z-axis direction). Thus, the signal terminal 26b (the second conductor layer) contacts the upper end (the end in the positive direction of the Z-axis) of the interlayer connection conductor v2a. The connection conductor layer 28b (the first conductor layer) contacts the lower end (the end in the negative direction of the Z-axis) of the interlayer connection conductor v2a. However, the interlayer connection conductor v2a does not penetrate the connection conductor layer 28b (the first conductor layer) and the signal terminal 26b (the second conductor layer) in the up-down direction (Z-axis direction).

[0074] In addition, the interlayer connection conductor v2a has a truncated cone shape. When viewed in the up-down direction (Z-axis direction), the area of ​​the upper end (the end in the positive direction of the Z-axis) of the interlayer connection conductor v2a is smaller than the area of ​​the lower end (the end in the negative direction of the Z-axis) of the interlayer connection conductor v2a. Moreover, the surface roughness of the portion Pa of the inner circumferential surface of the through hole located in the insulator layer 16a (the second insulator layer) is greater than the surface roughness of the portion Pb of the inner circumferential surface of the through hole located in the insulator layer 17a (the first insulator layer).

[0075] The interlayer connection conductor v2b is arranged inside a through hole that penetrates the insulator layer 16b (second insulator layer) and the insulator layer 17b (first insulator layer) in the up-down direction (Z-axis direction). As a result, the connection conductor layer 28b (second conductor layer) contacts the upper end portion (the end portion in the positive direction of the Z-axis) of the interlayer connection conductor v2b. The right end portion of the signal conductor layer 20 (first conductor layer) contacts the lower end portion (the end portion in the negative direction of the Z-axis) of the interlayer connection conductor v2b. However, the interlayer connection conductor v2b does not penetrate the signal conductor layer 20 (first conductor layer) and the connection conductor layer 28b (second conductor layer) in the up-down direction (Z-axis direction).

[0076] In addition, the interlayer connection conductor v2b has a truncated cone shape. When viewed in the up-down direction (Z-axis direction), the area of ​​the upper end (the end in the positive direction of the Z-axis) of the interlayer connection conductor v2b is smaller than the area of ​​the lower end (the end in the negative direction of the Z-axis) of the interlayer connection conductor v2b. Moreover, the surface roughness of the portion Pa of the inner circumferential surface of the through hole located in the insulator layer 16b (the second insulator layer) is greater than the surface roughness of the portion Pb of the inner circumferential surface of the through hole located in the insulator layer 17b (the first insulator layer).

[0077] The interlayer connection conductor v4 electrically connects the first grounding conductor layer 22, the connection conductor layer 30b, the connection conductor layer 32b, the connection conductor layer 34b, and the second grounding conductor layer 24. In more detail, the interlayer connection conductor v4 includes interlayer connection conductors v4a, v4b, v4c, v4d, and v4e. The interlayer connection conductor v4a is arranged inside a through hole that penetrates the insulator layer 16a (the second insulator layer) and the insulator layer 17a (the first insulator layer) in the up-down direction (Z-axis direction). Thus, the first grounding conductor layer 22 (the second conductor layer) is in contact with the upper end portion (the end portion in the positive direction of the Z-axis) of the interlayer connection conductor v4a. The connection conductor layer 30b (the first conductor layer) is in contact with the lower end portion (the end portion in the negative direction of the Z-axis) of the interlayer connection conductor v4a. However, the interlayer connection conductor v4a does not penetrate the connection conductor layer 30b (the first conductor layer) and the first grounding conductor layer 22 (the second conductor layer) in the up-down direction (Z-axis direction).

[0078] In addition, the interlayer connection conductor v4a has a truncated cone shape. When viewed in the up-down direction (Z-axis direction), the area of ​​the upper end (the end in the positive direction of the Z-axis) of the interlayer connection conductor v4a is smaller than the area of ​​the lower end (the end in the negative direction of the Z-axis) of the interlayer connection conductor v4a. Moreover, the surface roughness of the portion Pa of the inner circumferential surface of the through hole located in the insulator layer 16a (the second insulator layer) is greater than the surface roughness of the portion Pb of the inner circumferential surface of the through hole located in the insulator layer 17a (the first insulator layer).

[0079] The interlayer connection conductor v4b is arranged inside a through hole that penetrates the insulator layer 16b (second insulator layer) and the insulator layer 17b (first insulator layer) in the up-down direction (Z-axis direction). Thus, the connection conductor layer 30b (second conductor layer) contacts the upper end portion (the end portion in the positive direction of the Z-axis) of the interlayer connection conductor v4b. The connection conductor layer 32b (first conductor layer) contacts the lower end portion (the end portion in the negative direction of the Z-axis) of the interlayer connection conductor v4b. However, the interlayer connection conductor v4b does not penetrate the connection conductor layer 32b (first conductor layer) and the connection conductor layer 30b (second conductor layer) in the up-down direction (Z-axis direction).

[0080] In addition, the interlayer connection conductor v4b has a truncated cone shape. When viewed in the up-down direction (Z-axis direction), the area of ​​the upper end (the end in the positive direction of the Z-axis) of the interlayer connection conductor v4b is smaller than the area of ​​the lower end (the end in the negative direction of the Z-axis) of the interlayer connection conductor v4b. Moreover, the surface roughness of the portion Pa of the inner circumferential surface of the through hole located in the insulator layer 16b (the second insulator layer) is greater than the surface roughness of the portion Pb of the inner circumferential surface of the through hole located in the insulator layer 17b (the first insulator layer).

[0081] The interlayer connection conductor v4c is arranged inside the through hole that penetrates the insulating layer 17c in the up-down direction. As a result, the connection conductor layer 32b contacts the upper end of the interlayer connection conductor v4c. The connection conductor layer 34b contacts the lower end of the interlayer connection conductor v4c. However, the interlayer connection conductor v4c does not penetrate the connection conductor layer 34b and the connection conductor layer 32b in the up-down direction. In addition, the interlayer connection conductor v4c has a truncated cone shape. When viewed in the up-down direction, the area of ​​the upper end of the interlayer connection conductor v4c is smaller than the area of ​​the lower end of the interlayer connection conductor v4c.

[0082] The interlayer connection conductors v4d and v4e are respectively arranged inside the through holes that penetrate the insulating layers 17d and 17e in the up-down direction. The interlayer connection conductor v4d and the interlayer connection conductor v4e are connected in an aligned manner in the up-down direction. As a result, the connection conductor layer 34b is in contact with the upper end of the interlayer connection conductor v4d. The second grounding conductor layer 24 is in contact with the lower end of the interlayer connection conductor v4e. However, the interlayer connection conductor v4d does not penetrate the connection conductor layer 34b in the up-down direction. The interlayer connection conductor v4e does not penetrate the second grounding conductor layer 24 in the up-down direction. In addition, the interlayer connection conductors v4d and v4e have a truncated cone shape. When viewed in the up-down direction, the area of ​​the upper end of the interlayer connection conductor v4d is smaller than the area of ​​the lower end of the interlayer connection conductor v4d. When viewed in the up-down direction, the area of ​​the lower end of the interlayer connection conductor v4e is smaller than the area of ​​the upper end of the interlayer connection conductor v4e. The vertical position of the lower end of the interlayer connection conductor v4d and the vertical position of the upper end of the interlayer connection conductor v4e coincide with the vertical position of the lower main surface of the insulating layer 17d and the vertical position of the upper main surface of the insulating layer 17e.

[0083] In addition, between the insulator layer 17a (first insulator layer) and the insulator layer 16a (second insulator layer), a conductor layer in contact with the interlayer connection conductors v2a and v4a is not provided. In the present embodiment, a conductor layer is not provided between the insulator layer 17a (first insulator layer) and the insulator layer 16a (second insulator layer). Similarly, between the insulator layer 17b (first insulator layer) and the insulator layer 16b (second insulator layer), a conductor layer in contact with the interlayer connection conductors v2b and v4b is not provided. In the present embodiment, a conductor layer is not provided between the insulator layer 17b (first insulator layer) and the insulator layer 16b (second insulator layer).

[0084] The plurality of interlayer connection conductors v5 are located on the front side of the signal conductor layer 20. The plurality of interlayer connection conductors v5 are arranged in a row in the left-right direction. The plurality of interlayer connection conductors v5 electrically connect the first ground conductor layer 22 and the second ground conductor layer 24. However, the structure of the plurality of interlayer connection conductors v5 is the same as that of the interlayer connection conductor v4, so the description thereof is omitted.

[0085] The plurality of interlayer connection conductors v6 are located on the rear side of the signal conductor layer 20. The plurality of interlayer connection conductors v6 are arranged in a row in the left-right direction. The plurality of interlayer connection conductors v6 electrically connect the first ground conductor layer 22 and the second ground conductor layer 24. However, the structure of the plurality of interlayer connection conductors v6 is the same as that of the interlayer connection conductor v4, so the description thereof is omitted.

[0086] The insulating layers 18 a and 18 b are protective layers having flexibility and have the same rectangular shape as the laminate 12 when viewed in the up-down direction.

[0087] The insulating layer 18a covers substantially the entire upper main surface of the insulating layer 16a. Thus, the insulating layer 18a protects the first grounding conductor layer 22. However, the insulating layer 18a is provided with openings h1 to h6. The opening h4 overlaps with the signal terminal 26b when viewed in the up-down direction. Thus, the signal terminal 26b is exposed to the outside from the circuit substrate 10 through the opening h4. The opening h5 is provided on the rear side of the opening h4. The opening h5 overlaps with the first grounding conductor layer 22 when viewed in the up-down direction. Thus, a portion of the first grounding conductor layer 22 is exposed to the outside from the circuit substrate 10 through the opening h5. A portion of the first grounding conductor layer 22 functions as a grounding terminal. The opening h6 is provided on the front side of the opening h4. The opening h6 overlaps with the first grounding conductor layer 22 when viewed in the up-down direction. Thus, a portion of the first grounding conductor layer 22 is exposed to the outside from the circuit substrate 10 through the opening h6. A portion of the first grounding conductor layer 22 functions as a grounding terminal.

[0088] The insulating layer 18 b covers substantially the entire lower main surface of the insulating layer 17 e . Thus, the insulating layer 18 b covers the second ground conductor layer 24 .

[0089] The structure of the right end of the circuit board 10 is described above. The structure of the left end of the circuit board 10 is bilaterally symmetrical to the structure of the right end of the circuit board 10. Therefore, the description of the structure of the left end of the circuit board 10 is omitted.

[0090] The first ground conductor layer 22, the second ground conductor layer 24, the signal terminals 26a, 26b, and the connection conductor layers 28a, 28b, 30a, 30b, 32a, 32b, 34a, 34b are formed by, for example, etching a metal foil provided on the upper main surface or the lower main surface of the insulating layers 16a, 16b, 17a to 17e. The metal foil is, for example, a copper foil.

[0091] It should be noted that the surface roughness of the lower main surface (negative main surface) of the first ground conductor layer 22, the second ground conductor layer 24, the signal terminals 26a, 26b, and the connecting conductor layers 28a, 28b, 30a, 30b, 32a, 32b, 34a, 34b (first conductor layer, second conductor layer) is substantially equal to the surface roughness of the upper main surface (positive main surface) of the first ground conductor layer 22, the second ground conductor layer 24, the signal terminals 26a, 26b, and the connecting conductor layers 28a, 28b, 30a, 30b, 32a, 32b, 34a, 34b (first conductor layer, second conductor layer). However, the copper foil is chemically bonded to the fluororesin. Therefore, the first ground conductor layer 22 and the signal terminals 26a, 26b are firmly fixed to the insulating layer 16a. The connecting conductor layers 28a, 28b, 30a, 30b are firmly fixed to the insulating layer 16b.

[0092] The interlayer connection conductors v1 to v6 are, for example, via-hole conductors. The via-hole conductors are produced by forming through-holes in the insulating layers 16a, 16b, and 17a to 17e, filling the through-holes with a conductive paste, and sintering the conductive paste. The conductive paste is a mixture of metal powder and resin.

[0093] [Structure of electronic equipment]

[0094] Next, the structure of the electronic device 1 including the circuit board 10 will be described with reference to the drawings. Figure 3 1 is a rear view of an electronic device 1 including a circuit board 10. The electronic device 1 is, for example, a portable wireless communication terminal. The electronic device 1 is, for example, a smartphone.

[0095] like Figure 3 As shown, the circuit board 10 is used in a state where the laminate 12 is bent. "The laminate 12 is bent" means that the laminate 12 is deformed and bent by applying an external force to the laminate 12. The deformation may be elastic deformation, plastic deformation, or both.

[0096] The stack 12 has a first section A1, a second section A2 and a third section A3. The first section A1, the second section A2 and the third section A3 are arranged in sequence from left to right. The first section A1 and the third section A3 are not curved. The second section A2 is curved relative to the first section A1 in the downward direction (Z-axis direction) of the first section A1. However, the first section A1 and the third section A3 may also be slightly curved. In this case, the radius of curvature of the first section A1 and the radius of curvature of the third section A3 are larger than the radius of curvature of the second section A2.

[0097] The electronic device 1 includes a circuit board 10, connectors 50a, 50b, 150a, 150b, and circuit boards 100a, 100b. The connector 50a is mounted on the left end of the upper main surface of the circuit board 10. The connector 150b is mounted on the right end of the upper main surface of the circuit board 10.

[0098] The connector 150a is mounted on the lower main surface of the circuit board 100a. The connector 150a is connected to the connector 50a. The connector 150b is mounted on the lower main surface of the circuit board 100b. The connector 150b is connected to the connector 50b. Thus, the circuit board 10 electrically connects the circuit board 100a and the circuit board 100b.

[0099] [Method for Manufacturing Circuit Board 10]

[0100] Next, a method for manufacturing the circuit board 10 will be described with reference to the drawings. Figures 4 to 8 It is a cross-sectional view of the circuit board 10 during manufacturing.

[0101] like Figure 4 As shown, insulator layers 17a, 17b (first insulator layer) and insulator layers 16a, 16b (second insulator layer) having a lower main surface (negative main surface located in the negative direction of the Z axis) and an upper main surface (positive main surface located in the positive direction of the Z axis) are prepared (preparation process). Insulator layers 16a, 16b (second insulator layer) have a Young's modulus at room temperature that is higher than the Young's modulus of insulator layers 17a, 17b (first insulator layer) at room temperature. In this specification, room temperature is above 5°C and below 35°C. In addition, a conductor layer 200a (second conductor layer) is provided on the upper main surface (positive main surface) of the insulator layer 16a (second insulator layer). A conductor layer 200b (second conductor layer) is provided on the upper main surface (positive main surface) of the insulator layer 16b (second insulator layer).

[0102] In addition, if Figure 5 As shown, insulator layers 17c to 17e are prepared. Conductor layer 200c is provided on the upper main surface of insulator layer 17c. Conductor layer 200d is provided on the upper main surface of insulator layer 17d. Conductor layer 200e is provided on the upper main surface of insulator layer 17e.

[0103] After the preparation process, Figure 5As shown, the insulator layer 17a (first insulator layer) and the insulator layer 16a (second insulator layer) are stacked so that the lower main surface (negative main surface) of the insulator layer 16a (second insulator layer) is in contact with the upper main surface (positive main surface) of the insulator layer 17a (first insulator layer) (stacking process). At this time, the insulator layer 17a and the insulator layer 16a are subjected to heat treatment and pressure treatment to heat-press the insulator layer 17a and the insulator layer 16a. Similarly, the insulator layer 17b (first insulator layer) and the insulator layer 16b (second insulator layer) are stacked so that the lower main surface (negative main surface) of the insulator layer 16b (second insulator layer) is in contact with the upper main surface (positive main surface) of the insulator layer 17b (first insulator layer) (stacking process). At this time, the insulating layer 17 b and the insulating layer 16 b are subjected to a heating treatment and a pressurizing treatment, so that the insulating layer 17 b and the insulating layer 16 b are thermocompressed.

[0104] After the lamination process, Figure 6 As shown, the conductor layers 200a to 200e are patterned by photolithography (patterning step), thereby forming the first ground conductor layer 22, the second ground conductor layer 24, the signal terminals 26a and 26b, and the connection conductor layers 28a and 28b, 30a and 30b, 32a and 32b, 34a and 34b.

[0105] After the patterning process, Figure 7 As shown, a laser beam is irradiated from a space located below (in the negative direction of the Z axis) the insulator layer 17a (first insulator layer) and the insulator layer 16a (second insulator layer) to form a through hole H that penetrates the insulator layer 17a (first insulator layer) and the insulator layer 16a (second insulator layer) in the vertical direction (in the Z axis direction) (through hole forming process). In the through hole forming process, the laser beam is irradiated so that the through hole H does not penetrate the conductor layer 200a (second conductor layer) in the vertical direction (in the Z axis direction). Similarly, a laser beam is irradiated from a space located below (in the negative direction of the Z axis) the insulator layer 17b (first insulator layer) and the insulator layer 16b (second insulator layer) to form a through hole H that penetrates the insulator layer 17b (first insulator layer) and the insulator layer 16b (second insulator layer) in the vertical direction (in the Z axis direction) (through hole forming process). In the through hole forming step, the laser beam is irradiated so that the through hole H does not penetrate the conductor layer 200 b (second conductor layer) in the vertical direction (Z-axis direction). In addition, the through hole H is also formed by irradiating the insulating layers 17 c to 17 e with a laser beam.

[0106] Here, in the through hole forming process, the laser beam is irradiated while the intensity of the laser beam is increased with the passage of time. The increase in the intensity of the laser beam can be continuous or step-by-step. As a result, the surface roughness of the portion Pa of the inner circumferential surface of the through hole located in the insulator layer 16a (second insulator layer) is greater than the surface roughness of the portion Pb of the inner circumferential surface of the through hole located in the insulator layer 17a (first insulator layer). Similarly, the surface roughness of the portion Pa of the inner circumferential surface of the through hole located in the insulator layer 16b (second insulator layer) is greater than the surface roughness of the portion Pb of the inner circumferential surface of the through hole located in the insulator layer 17b (first insulator layer).

[0107] After the through hole forming process, Figure 8 As shown, interlayer connection conductors v1 to v6 are formed inside the through hole H (interlayer connection conductor forming step). In the interlayer connection conductor forming step, the through hole H is filled with a conductive paste.

[0108] After the through hole forming process, Figure 2 As shown, the insulating layers 16a, 16b, 17a to 17e, 18a, and 18b including the insulating layers 17a and 17b (first insulating layers) and the insulating layers 16a and 16b (second insulating layers) are stacked (second stacking process). In the second stacking process, the insulating layers 16a, 16b, 17a to 17e, 18a, and 18b are subjected to heat treatment and pressurization treatment, and the insulating layers 16a, 16b, 17a to 17e, 18a, and 18b are thermocompressed. By the heat treatment, the insulating layers 16a, 16b, 17a to 17e, 18a, and 18b are welded, and the conductive paste in the through hole H is cured. After the above steps, the circuit board 10 is completed.

[0109] [Effect]

[0110] According to the circuit board 10, it is possible to suppress the occurrence of poor connection between the interlayer connection conductor v2a and the signal terminal 26b. In more detail, the insulator layer 16a (the second insulator layer) has a Young's modulus at room temperature that is higher than the Young's modulus at room temperature of the insulator layer 17a (the first insulator layer) (condition 1). Moreover, the surface roughness of the portion Pa located in the insulator layer 16a (the second insulator layer) of the inner circumference of the through hole is greater than the surface roughness of the portion Pb located in the insulator layer 17a (the first insulator layer) of the inner circumference of the through hole (condition 2). As a result, the interlayer connection conductor v2a is strongly attached to the hard insulator layer 16a. That is, the interlayer connection conductor v2a is retained in the insulator layer 16a by the anchoring effect. As a result, the interlayer connection conductor v2a is suppressed from falling off from the through hole when the stack 12 is deformed. As described above, the circuit board 10 can suppress the occurrence of poor connection between the interlayer connection conductor v2a and the signal terminal 26b. Note that, for the same reason as the interlayer connection conductor v2a, poor connection is also suppressed in the interlayer connection conductors v2b, v4a, and v4b.

[0111] The proof of condition 1 is as follows. First, the insulator layers 16a and 17a are taken out from the laminate 12 to prepare a test piece. Only the insulator layer 16a is scraped off from the test piece, and the Young's modulus of the test piece at room temperature is measured. When the Young's modulus of the test piece at room temperature decreases with the removal of the insulator layer 16a, the Young's modulus of the insulator layer 16a at room temperature is higher than the Young's modulus of the insulator layer 17a at room temperature.

[0112] The proof of condition 2 is as follows. The circuit substrate 10 is cut to form Figure 2 The cross section is shown. Then, the cross section is observed by SEM. At this time, an image of the inner peripheral surface of the through hole (i.e., the surface formed by the insulating layer) is observed. The surface roughness is measured by depicting an image of the inner peripheral surface of the through hole. The surface roughness in this specification is, for example, the arithmetic surface roughness. The height information of each part is converted by depicting an image of the inner peripheral surface of the through hole, and the arithmetic average roughness is calculated according to the definition of the arithmetic average roughness.

[0113] According to the circuit board 10, it is also possible to suppress the occurrence of poor connection between the interlayer connection conductor v2a and the signal terminal 26b for the following reasons. More specifically, when viewed in the up-down direction (Z-axis direction), the area of ​​the upper end (the end in the positive direction of the Z-axis) of the interlayer connection conductor v2a is smaller than the area of ​​the lower end (the end in the negative direction of the Z-axis) of the interlayer connection conductor v2a. In such an interlayer connection conductor v2a, poor connection is likely to occur between the upper end of the interlayer connection conductor v2a, which has a smaller area when viewed in the up-down direction, and the signal terminal 26b.

[0114] Thus, the lower main surface (negative main surface) of the insulator layer 16a (second insulator layer) contacts the upper main surface (positive main surface) of the insulator layer 17a (first insulator layer). That is, the insulator layer 16a is located on the upper side of the insulator layer 17a. Moreover, the insulator layer 16a (second insulator layer) has a Young's modulus at room temperature that is higher than the Young's modulus at room temperature of the insulator layer 17a (first insulator layer). Moreover, the surface roughness of the portion Pa located in the insulator layer 16a (second insulator layer) of the inner circumferential surface of the through hole is greater than the surface roughness of the portion Pb located in the insulator layer 17a (first insulator layer) of the inner circumferential surface of the through hole. As a result, the upper end portion of the interlayer connection conductor v2a, which is prone to poor connection, is strongly attached to the hard insulator layer 16a. That is, the upper end portion of the interlayer connection conductor v2a, which is prone to poor connection, is maintained on the insulator layer 16a by the anchoring effect. As a result, the positional displacement of the upper end of the interlayer connection conductor v2a is suppressed when the laminate 12 is deformed. As described above, according to the circuit board 10, it is possible to suppress the occurrence of poor connection between the interlayer connection conductor v2a and the signal terminal 26b. It should be noted that, for the same reason as the interlayer connection conductor v2a, the occurrence of poor connection is also suppressed in the interlayer connection conductors v2b, v4a, and v4b.

[0115] In the circuit substrate 10, the surface roughness of the portion Pa of the inner circumferential surface of the through hole located in the insulator layer 16a (the second insulator layer) is greater than the surface roughness of the portion Pb of the inner circumferential surface of the through hole located in the insulator layer 17a (the first insulator layer). That is, the surface roughness of a portion of the interlayer connection conductor v2a is greater. Therefore, in the interlayer connection conductor v2a, the portion where loss is easily generated in the high-frequency signal is reduced. Therefore, according to the circuit substrate 10, the loss generated in the high-frequency signal is suppressed in the interlayer connection conductor v2a. For the same reason as the interlayer connection conductor v2a, the loss generated in the high-frequency signal is suppressed in the interlayer connection conductors v2b, v4a, and v4b.

[0116] According to the circuit board 10, the loss generated in the high-frequency signal is also suppressed in the interlayer connection conductor v2a for the following reasons. In more detail, the thickness of the insulator layers 16a, 16b (second insulator layer) in the vertical direction (Z-axis direction) is smaller than the thickness of the insulator layers 17a, 17b (first insulator layer) in the vertical direction (Z-axis direction). As a result, the area of ​​the portion Pb becomes smaller, and therefore, in the interlayer connection conductor v2a, the portion where the loss is easily generated in the high-frequency signal becomes smaller. Therefore, according to the circuit board 10, the loss generated in the high-frequency signal is suppressed in the interlayer connection conductor v2a. For the same reason as the interlayer connection conductor v2a, the loss generated in the high-frequency signal is suppressed in the interlayer connection conductors v2b, v4a, and v4b.

[0117] According to the circuit board 10, the connector 50b is installed on the signal terminal 26b. Therefore, when the connector 50b is connected to the other connector, it is easy to apply force to the signal terminal 26b. Therefore, it is easy to cause poor connection between the signal terminal 26b and the interlayer connection conductor v2a. Therefore, the insulator layers 16a and 17a located near the signal terminal 26b have the following structure. The insulator layer 16a (second insulator layer) has a Young's modulus at room temperature that is higher than the Young's modulus of the insulator layer 17a (first insulator layer) at room temperature. Moreover, the surface roughness of the portion Pa located in the insulator layer 16a (second insulator layer) of the inner circumferential surface of the through hole is greater than the surface roughness of the portion Pb located in the insulator layer 17a (first insulator layer) of the inner circumferential surface of the through hole. Thus, as described above, it is possible to suppress the occurrence of poor connection between the interlayer connection conductor v2a and the signal terminal 26b.

[0118] In the circuit board 10, the material of the insulating layers 16a and 16b is different from the material of the insulating layers 17a and 17b. Thus, various materials of the insulating layers 16a and 16b can be combined with various materials of the insulating layers 17a and 17b. As a result, various electrical characteristics and various mechanical characteristics can be obtained in the circuit board 10.

[0119] In the circuit board 10, the insulator layers 16a, 16b (second insulator layers) have a Young's modulus at room temperature that is higher than the Young's modulus at room temperature of the insulator layers 17a, 17b (first insulator layers). The thickness of the insulator layers 16a, 16b (second insulator layers) in the up-down direction (Z-axis direction) is smaller than the thickness of the insulator layers 17a, 17b (first insulator layers) in the up-down direction (Z-axis direction). That is, the hard insulator layers 16a, 16b are thinner than the soft insulator layers 17a, 17b. Thus, the laminate 12 can be easily bent.

[0120] (First Modification)

[0121] Hereinafter, a circuit board 10 a according to a first modified example will be described with reference to the drawings. Fig. 9 It is a cross-sectional view of the right end portion of the circuit board 10a.

[0122] The circuit board 10a is different from the circuit board 10 in that the interlayer connection conductors v2a, v2b, and v4a to v4d are through-hole conductors and that an insulator layer 16e is provided instead of the insulator layer 17d. The through-hole conductor is formed by plating the inner peripheral surface of the through hole. In addition, the interlayer connection conductor v2a penetrates the connection conductor layer 28b in the vertical direction. The interlayer connection conductor v2b penetrates the signal conductor layer 20 in the vertical direction. The interlayer connection conductor v4a penetrates the connection conductor layer 30b in the vertical direction. The interlayer connection conductor v4b penetrates the connection conductor layer 32b in the vertical direction. The interlayer connection conductor v4c penetrates the connection conductor layer 34b in the vertical direction. The interlayer connection conductor v4d penetrates the second ground conductor layer 24 in the vertical direction. In addition, the interlayer connection conductor v4d penetrates the insulator layers 16e and 17e in the vertical direction.

[0123] In addition, insulating materials are filled inside the interlayer connection conductors v2a, v2b, and v4a to v4c. More specifically, a portion of the insulator layer 16b is filled inside the interlayer connection conductors v2a and v4a. A portion of the insulator layer 17c is filled inside the interlayer connection conductors v2b and v4b. A portion of the insulator layer 16e is filled inside the interlayer connection conductor v4c. However, insulating materials are not filled inside the interlayer connection conductor v4d. The other structures of the circuit substrate 10a are the same as those of the circuit substrate 10, so the description is omitted. The circuit substrate 10a can have the same effects as the circuit substrate 10.

[0124] (Second Modification)

[0125] Hereinafter, a circuit board 10 b according to a second modified example will be described with reference to the drawings. Fig.10 It is a cross-sectional view of the right end portion of the circuit board 10b.

[0126] The circuit substrate 10b is different from the circuit substrate 10 in that the laminate 12 includes insulator layers 116a and 116b (third insulator layers). In more detail, the insulator layers 116a and 116b (third insulator layers) have a Young's modulus at room temperature that is higher than the Young's modulus at room temperature of the insulator layers 17a and 17b (first insulator layers). Moreover, the insulator layer 116a (third insulator layer) is located below (in the negative direction of the Z axis) than the insulator layer 17a (first insulator layer) and is in contact with the insulator layer 17a (first insulator layer). The insulator layer 116b (third insulator layer) is located below (in the negative direction of the Z axis) than the insulator layer 17b (first insulator layer) and is in contact with the insulator layer 17b (first insulator layer).

[0127] The connection conductor layers 28b and 30b (first conductor layer) are located on the lower main surface of the insulator layer 116a (third insulator layer), and the insulator layer 116a is located below (in the negative direction of the Z axis) the insulator layer 16a (second insulator layer). The signal conductor layer 20 and the connection conductor layer 32b (first conductor layer) are located on the lower main surface of the insulator layer 116b (third insulator layer), and the insulator layer 116b is located below (in the negative direction of the Z axis) the insulator layer 16b (second insulator layer).

[0128] The through hole provided with the interlayer connection conductors v2a and v4a penetrates the insulator layer 116a (third insulator layer) in the up-down direction (Z-axis direction). The surface roughness of the portion Pc located in the insulator layer 116a (third insulator layer) of the inner circumference of the through hole is greater than the surface roughness of the portion Pb located in the insulator layer 17a (first insulator layer) of the inner circumference of the through hole. The through hole provided with the interlayer connection conductors v2b and v4b penetrates the insulator layer 116b (third insulator layer) in the up-down direction (Z-axis direction). The surface roughness of the portion Pc located in the insulator layer 116b (third insulator layer) of the inner circumference of the through hole is greater than the surface roughness of the portion Pb located in the insulator layer 17b (first insulator layer) of the inner circumference of the through hole. The other structures of the circuit substrate 10b are the same as those of the circuit substrate 10, so the description is omitted. The circuit substrate 10b can play the same role and effect as the circuit substrate 10.

[0129] In addition, according to the circuit board 10b, the area of ​​the portion where the interlayer connection conductor v2a is firmly held is large, thereby being able to suppress the occurrence of connection failure between the interlayer connection conductor v2a and the signal terminal 26b.

[0130] In addition, according to the circuit board 10b, it is possible to suppress the occurrence of poor connection between the interlayer connection conductor v2a and the connection conductor layer 28b. In more detail, the insulator layer 116a (third insulator layer) is located below (in the negative direction of the Z axis) the insulator layer 17a (first insulator layer) and is in contact with the insulator layer 17a (first insulator layer). Moreover, the surface roughness of the portion Pc located in the insulator layer 116a (third insulator layer) of the inner circumference of the through hole is greater than the surface roughness of the portion Pb located in the insulator layer 17a (first insulator layer) of the inner circumference of the through hole. As a result, the lower end of the interlayer connection conductor v2a is strongly in close contact with the hard insulator layer 116a. That is, the lower end of the interlayer connection conductor v2a is maintained in the insulator layer 116a by the anchoring effect. As a result, the positional displacement of the lower end of the interlayer connection conductor v2a is suppressed when the stack 12 is deformed. As described above, according to the circuit board 10b, poor connection between the interlayer connection conductor v2a and the connection conductor layer 28b can be suppressed. For the same reason as the interlayer connection conductor v2a, poor connection is also suppressed in the interlayer connection conductors v2b, v4a, and v4b.

[0131] (Third Modification)

[0132] Hereinafter, a circuit board 10c according to a third modified example will be described with reference to the drawings. Fig.11 It is a cross-sectional view of the right end portion of the circuit board 10c.

[0133] The circuit board 10c is different from the circuit board 10 in the structure of the insulating layers 16a and 16b. In more detail, the insulating layers 16a and 16b (the second insulating layer) have a structure in which a plurality of particles P are dispersed in the resin. The plurality of particles P have a shape having a long side direction and a short side direction. The number of the plurality of particles P whose long side direction forms an angle of more than 45 degrees with the Z axis is greater than the number of the plurality of particles P whose long side direction forms an angle less than 45 degrees with the Z axis. Moreover, a portion of the plurality of particles P is exposed on the inner circumference of the through hole in the insulating layers 16a and 16b (the second insulating layer). As a result, the surface roughness of the portion Pa of the inner circumference of the through hole located in the insulating layer 16a is greater than the surface roughness of the portion Pb of the inner circumference of the through hole located in the insulating layer 17a. The surface roughness of the portion Pa of the inner circumference of the through hole located in the insulating layer 16b is greater than the surface roughness of the portion Pb of the inner circumference of the through hole located in the insulating layer 17b.

[0134] Here, the resin is, for example, a fluororesin. The material of the plurality of particles P is an inorganic material. The material of the plurality of particles P is, for example, boron nitride. Therefore, the Young's modulus of the plurality of particles P at room temperature is greater than the Young's modulus of the resin at room temperature. Thus, the Young's modulus of the insulating layers 16a and 16b at room temperature is greater than the Young's modulus of the insulating layers 17a to 17e at room temperature. The dielectric constant of the plurality of particles P may also be lower than the dielectric constant of the resin. Thus, the dielectric constant of the insulating layers 16a and 16b decreases.

[0135] In the circuit board 10c, the material of the insulating layers 17a to 17e is the same fluororesin as the material of the insulating layers 16a and 16b. The other structures of the circuit board 10c are the same as those of the circuit board 10. The circuit board 10c can achieve the same functions and effects as the circuit board 10.

[0136] In addition, in the circuit board 10c, the plurality of particles P have a shape having a long side direction and a short side direction. The number of the plurality of particles P whose long side direction forms an angle of 45 degrees or more with the Z axis is greater than the number of the plurality of particles P whose long side direction forms an angle of less than 45 degrees with the Z axis (condition 3). As a result, the linear expansion coefficients of the insulator layers 16a and 16b in the front-to-back direction and the left-to-right direction are reduced.

[0137] It should be noted that the proof of condition 3 is carried out by the following steps. First, a test piece is cut out from the insulator layers 16a and 16b. By observing the test piece, the number of multiple particles P whose long side direction forms an angle of 45 degrees or more with the Z axis and the number of multiple particles P whose long side direction forms an angle of less than 45 degrees with the Z axis are counted.

[0138] (Fourth Modification)

[0139] Hereinafter, a circuit board 10d according to a fourth modified example will be described with reference to the drawings. Fig.12 It is a cross-sectional view of the right end portion of the circuit board 10d.

[0140] In the circuit board 10d, the surface roughness of the upper main surface (positive main surface) of the connecting conductor layer 28b, 30b (first conductor layer) is smaller than the surface roughness of the lower main surface (negative main surface) of the connecting conductor layer 28b, 30b (first conductor layer). Thus, the connecting conductor layer 28b, 30b is firmly fixed to the insulating layer 16b by the anchoring effect. In addition, the surface roughness of the lower main surface (negative main surface) of the first grounding conductor layer 22 and the signal terminal 26b (second conductor layer) is greater than the surface roughness of the upper main surface (positive main surface) of the first grounding conductor layer 22 and the signal terminal 26b (second conductor layer). Thus, the first grounding conductor layer 22 and the signal terminal 26b are firmly fixed to the insulating layer 16a by the anchoring effect. The other structures of the circuit board 10d are the same as those of the circuit board 10, so the description is omitted. The circuit board 10d can play the same role and effect as the circuit board 10.

[0141] It should be noted that in the circuit board 10d, the connection conductor layers 28b and 30b are firmly fixed to the insulator layer 16b by the anchor effect. In addition, the first ground conductor layer 22 and the signal terminal 26b are firmly fixed to the insulator layer 16a by the anchor effect. Therefore, the connection conductor layers 28b and 30b do not need to be chemically bonded to the insulator layer 16b. In addition, the first ground conductor layer 22 and the signal terminal 26b do not need to be chemically bonded to the insulator layer 16a. Therefore, the degree of freedom in selecting the material of the insulator layers 16a and 16b is improved.

[0142] (Fifth Modification)

[0143] Hereinafter, a circuit board 10e according to a fifth modification will be described with reference to the drawings. Fig.13 It is a cross-sectional view of the right end portion of the circuit board 10e.

[0144] The circuit board 10e is different from the circuit board 10a in that the interlayer connection conductors v2a, v2b, and v4a to v4d are filled with a conductive material. The conductive material is formed by sintering a conductive paste, which is a mixture of resin and metal powder. The other structures of the circuit board 10e are the same as those of the circuit board 10a, so the description is omitted. The circuit board 10e can play the same role and effect as the circuit board 10a.

[0145] (Other embodiments)

[0146] The transmission line of the present invention is not limited to the circuit boards 10 and 10a to 10e, and can be modified within the scope of the gist thereof. It should be noted that the structures of the circuit boards 10 and 10a to 10e can be arbitrarily combined.

[0147] It should be noted that a conductor layer may be present between the first insulating layer and the second insulating layer.

[0148] It should be noted that the interlayer connection conductor may also penetrate the first conductor layer or the second conductor layer along the Z-axis direction.

[0149] It should be noted that, when viewed in the up-down direction, the area of ​​the end of the interlayer connection conductor in the positive direction of the Z axis may be larger than the area of ​​the end of the interlayer connection conductor in the negative direction of the Z axis.

[0150] It should be noted that the plurality of particles may not have a long side direction and a short side direction. That is, the shape of the plurality of particles may be a spherical shape.

[0151] It should be noted that the number of particles whose long side direction forms an angle of 45 degrees or more with the Z axis may be less than the number of particles whose long side direction forms an angle of less than 45 degrees with the Z axis.

[0152] In addition, in the circuit board 10c, the resin of the insulating layers 16a and 16b may be different from the resin of the insulating layers 17a and 17b.

[0153] It should be noted that the thickness of the second insulating layer in the Z-axis direction may be greater than the thickness of the first insulating layer in the Z-axis direction.

[0154] It should be noted that the material of the first insulating layer and / or the material of the second insulating layer may also be a fluororesin.

Claims

1. A circuit substrate, characterized in that: The circuit substrate comprises: A laminate having a structure in which a plurality of insulating layers including a first insulating layer and a second insulating layer are laminated in a Z-axis direction, wherein the second insulating layer has a Young's modulus at room temperature higher than that of the first insulating layer at room temperature, wherein the plurality of insulating layers respectively have a negative principal surface located in the negative direction of the Z-axis and a positive principal surface located in the positive direction of the Z-axis, and the negative principal surface of the second insulating layer is in contact with the positive principal surface of the first insulating layer; an interlayer connection conductor disposed inside a through hole penetrating the first insulating layer and the second insulating layer along the Z-axis direction; a first conductor layer located on the negative main surface of the insulating layer at a position closer to the negative direction of the Z axis than the second insulating layer and in contact with an end of the interlayer connecting conductor in the negative direction of the Z axis; as well as a second conductor layer located on the front main surface of the second insulator layer and in contact with an end portion of the interlayer connection conductor in the positive direction of the Z axis, The surface roughness of a portion of the inner peripheral surface of the through hole located in the second insulator layer is greater than the surface roughness of a portion of the inner peripheral surface of the through hole located in the first insulator layer. A conductor layer in contact with the interlayer connection conductor is not provided between the first insulator layer and the second insulator layer.

2. The circuit substrate according to claim 1, characterized in that: The first conductor layer is located on the negative main surface of the first insulator layer.

3. The circuit substrate according to claim 1, characterized in that: The plurality of insulator layers include a third insulator layer, The third insulating layer has a Young's modulus at room temperature higher than that of the first insulating layer at room temperature, is located closer to the negative direction of the Z axis than the first insulating layer, and is in contact with the first insulating layer. The through hole penetrates the third insulating layer along the Z-axis direction, The insulating layer located closer to the negative direction of the Z axis than the second insulating layer is the third insulating layer.

4. The circuit substrate according to claim 3, characterized in that: A portion of the inner peripheral surface of the through hole located in the third insulator layer has a surface roughness greater than a surface roughness of a portion of the inner peripheral surface of the through hole located in the first insulator layer.

5. The circuit substrate according to any one of claims 1 to 4, characterized in that: No conductor layer is provided between the first insulator layer and the second insulator layer.

6. The circuit substrate according to any one of claims 1 to 4, characterized in that: The interlayer connection conductor does not penetrate the first conductor layer and the second conductor layer along the Z-axis direction.

7. The circuit substrate according to any one of claims 1 to 4, characterized in that: When viewed in the Z-axis direction, an area of ​​an end of the interlayer connection conductor in the positive direction of the Z-axis is smaller than an area of ​​an end of the interlayer connection conductor in the negative direction of the Z-axis.

8. The circuit substrate according to any one of claims 1 to 4, characterized in that: The second insulating layer has a structure in which a plurality of particles are dispersed in a resin.

9. The circuit substrate according to claim 8, characterized in that: The plurality of particles have a shape having a long side direction and a short side direction.

10. The circuit substrate according to claim 9, characterized in that: The number of the plurality of particles whose long side direction forms an angle of 45 degrees or more with the Z axis is greater than the number of the plurality of particles whose long side direction forms an angle of less than 45 degrees with the Z axis.

11. The circuit substrate according to claim 8, characterized in that: Part of the plurality of particles is exposed on an inner peripheral surface of the through hole in the second insulating layer.

12. The circuit substrate according to any one of claims 1 to 4, characterized in that: The surface roughness of the front main surface of the first conductor layer is smaller than the surface roughness of the negative main surface of the first conductor layer. The surface roughness of the negative main surface of the second conductor layer is greater than the surface roughness of the positive main surface of the second conductor layer.

13. The circuit substrate according to any one of claims 1 to 4, characterized in that: The surface roughness of the negative main surface of the first conductor layer is substantially equal to the surface roughness of the positive main surface of the first conductor layer. The surface roughness of the negative main surface of the second conductive layer is substantially equal to the surface roughness of the positive main surface of the second conductive layer.

14. The circuit substrate according to claim 13, characterized in that: The material of the first insulating layer and / or the material of the second insulating layer is fluororesin.

15. The circuit substrate according to any one of claims 1 to 4, characterized in that: The stacked body has a first section and a second section, The second section is curved relative to the first section in the Z-axis direction of the first section.

16. The circuit substrate according to any one of claims 1 to 4, characterized in that: The thickness of the second insulator layer in the Z-axis direction is smaller than the thickness of the first insulator layer in the Z-axis direction.

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