Stacked semiconductor device

Abstract

The stacked semiconductor device includes a first die, and a second die, a third die and a heat dissipation element bonded to the first die. The heat dissipation elements are integrally formed and are respectively adjacent to at least two edges of the second die and the third die.

Description

Technical Field

[0001] The present disclosure relates to a stacked semiconductor device. Background Art

[0002] A semiconductor wafer may be composed of multiple bare dies. In order to reduce the area occupied by multiple bare dies and improve the performance of the wafer, a technology for stacking and integrating bare dies has been developed. Various bonding techniques may be used to form a stacked structure, such as wafer-to-wafer bonding, bare die-to-wafer bonding, bare die-to-bare die bonding, fusion bonding, hybrid bonding (e.g., including simultaneous metal-to-metal bonding and dielectric-to-dielectric bonding), etc. Utility Model Content

[0003] According to some embodiments of the present disclosure, a stacked semiconductor device includes: a first die, a second die bonded to the first die, a third die bonded to the first die, and a heat dissipation element. The heat dissipation element is integrally formed and bonded to the first die. Furthermore, the heat dissipation element is adjacent to at least two edges of the second die, and the heat dissipation element is adjacent to at least two edges of the third die.

[0004] According to some embodiments of the present disclosure, a stacked semiconductor device includes: a first bare die, a second bare die bonded to the first bare die, and a heat dissipation cap element. The heat dissipation cap element is bonded to the first bare die and covers the second bare die. In addition, the heat dissipation cap element includes a covering portion, and the covering portion is disposed above the second bare die, and the covering portion has a through hole formed above the second bare die.

[0005] According to some embodiments of the present disclosure, a stacked semiconductor device includes a substrate, an interposer, a plurality of bare dies, and a heat dissipation element. The interposer is disposed above the substrate. The bare dies are bonded to the interposer, and the plurality of bare dies are electrically connected to the substrate through the interposer. The heat dissipation element is bonded to at least one of the plurality of bare dies, and the heat dissipation element includes a covering portion, and the covering portion is disposed above at least one of the plurality of bare dies. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The embodiments of the present disclosure may be better understood from the following detailed description when read in conjunction with the accompanying drawings. It is noteworthy that, in accordance with standard practice in practice, the features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A schematic top view of a stacked semiconductor device according to some embodiments is depicted;

[0008] Figure 2 A cross-sectional view of a stacked semiconductor device according to some embodiments is shown, wherein Figure 2 It is along Figure 1A cross-sectional view depicted along the AA section line;

[0009] Figure 3 depicts a cross-sectional view of a first die of a stacked semiconductor device according to some embodiments;

[0010] Figure 4 is a flow chart of steps for a method of manufacturing a stacked semiconductor device according to some embodiments;

[0011] Figures 5 to 12 depicts a cross-sectional view of a structure at an intermediate stage of a method for manufacturing a stacked semiconductor device according to some embodiments;

[0012] Fig.13 A schematic top view of a stacked semiconductor device according to some embodiments is depicted;

[0013] Fig.14 A cross-sectional view of a stacked semiconductor device according to some embodiments is shown, wherein Fig.14 It is along Fig.13 The cross-sectional view is shown along the CC section line in FIG.

[0014] Fig.15 A cross-sectional view of a stacked semiconductor device according to some embodiments is shown, wherein Fig.15 It is along Fig.13 The cross-sectional view is shown along the cross-sectional line DD in FIG.

[0015] Fig.16 A cross-sectional view of a heat dissipation element of a stacked semiconductor device according to some embodiments is shown, wherein Fig.16 It is along Fig.13 A cross-sectional view depicted along the E1-E1 section line in FIG.

[0016] Fig.17 is a flow chart of steps for a method of manufacturing a stacked semiconductor device according to some embodiments;

[0017] Figures 18 to 27 depicts a cross-sectional view of a structure at an intermediate stage of a method for manufacturing a stacked semiconductor device according to some embodiments;

[0018] Figure 28 to Figure 35 are top views and cross-sectional views of different variations of heat dissipation elements of stacked semiconductor devices according to some embodiments;

[0019] Fig.36 depicts a top view of a variation of a stacked semiconductor device according to some embodiments;

[0020] Fig.37 A cross-sectional view of a variation of a stacked semiconductor device according to some embodiments is shown, wherein Fig.37 It is along Fig.36 a cross-sectional view taken along the section line FF in FIG. ; and

[0021] Fig.38 and Fig.39 Cross-sectional views of various examples of final products of stacked semiconductor devices according to some embodiments are depicted.

[0022]

Explanation of symbols

[0023] 1: First bare crystal / bare crystal

[0024] 1A: First surface

[0025] 1B: Second surface

[0026] 2: Second bare crystal / bare crystal

[0027] 3: The third bare crystal / bare crystal

[0028] 5: Heat dissipation components

[0029] 5A, 5B: Heat dissipation components

[0030] 6: Gluing materials

[0031] 7: Intermediary layer

[0032] 8:Substrate

[0033] 9: Cooling structure

[0034] 10: Dielectric layer

[0035] 11:Substrate

[0036] 12: Dielectric structure

[0037] 13: Wiring layer

[0038] 14: Internal through hole

[0039] 15: Sealing structure

[0040] 16: Dielectric film

[0041] 17: Installation

[0042] 18: Conductive pad

[0043] 19: Interconnection components

[0044] 20: Solder bump

[0045] 21,22: Edge

[0046] 31,32,33: Edge

[0047] 41: First virtual bare crystal / virtual bare crystal

[0048] 42: Second virtual bare die / virtual bare die

[0049] 43: Third virtual bare crystal / virtual bare crystal

[0050] 61,62,63,64,65: Bare crystal

[0051] 91: Heat dissipation glue

[0052] 92: Radiator

[0053] 92A: Metal layer

[0054] 92B:Metal components

[0055] 100: First carrier wafer

[0056] 110,120: Dielectric layer

[0057] 125: Dielectric layer

[0058] 200: Second carrier wafer

[0059] 300: Detector

[0060] 511: First virtual bare die part / virtual bare die part

[0061] 512: Second virtual bare die part / virtual bare die part

[0062] 513: Third virtual bare die part / virtual bare die part

[0063] 520: Interconnection

[0064] 521: First frame part / frame part

[0065] 522: Second frame part / frame part

[0066] 523: Third frame part / frame part

[0067] 531: First covering part / covering part

[0068] 532: Second covering part / covering part

[0069] 533: Interconnection

[0070] 541: First Space

[0071] 542: Second Space

[0072] 543: First Opening

[0073] 544: Second opening

[0074] 551,552:Through hole

[0075] 561,562: Opening

[0076] AA,BB: Section line

[0077] CC,DD,E1-E1: Section Line

[0078] E2-E2,E3-E3,E4-E4,E5-E5,E6-E6,E7-E7,E8-E8,E9-E9: Section Line

[0079] FF: Section Line

[0080] d: edge spacing

[0081] h1: thickness

[0082] h2: distance

[0083] h3:Thickness / Total thickness

[0084] S01,S02,S03,S04,S05,S06,S07,S08: Steps

[0085] S11, S12, S13, S14, S15, S16, S17, S18: Steps DETAILED DESCRIPTION

[0086] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these specific examples are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly in contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0087] Additionally, for ease of description, spatially relative terms, such as "above," "below," "overlying," "upper," and the like, may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0088] Figure 1 A top view of a stacked semiconductor device according to some embodiments is depicted. The stacked semiconductor device includes a first die 1, a second die 2, a third die 3 and a heat dissipation structure. The heat dissipation structure includes a first virtual die 41, a second virtual die 42 and a third virtual die 43. The first die 1 is the bottom die (a die located in the first layer) of the stacked semiconductor device, and the second die 2 and the third die 3 are located in the second layer above the first layer. It should be noted that the exemplary embodiment is only for convenience of description, and the specific number and arrangement of the die and the virtual die in the present disclosure are not limited thereto. In the exemplary embodiment of the present embodiment, the length and width of the first die 1 are greater than the length and width of the second die 2 and the third die 3, and the second die 2 and the third die 3 are bonded to the first die 1. In order to enhance the uniformity and efficiency of heat dissipation, the first virtual die 41, the second virtual die 42 and the third virtual die 43 are bonded to the first die 1 in multiple regions, and the multiple regions are not occupied by the second die 2 or the third die 3. According to some embodiments, the virtual bare die 41, 42, 43 can be manufactured using a silicon wafer in a general lithography process (e.g., a process for forming a shallow trench isolation (STI) structure), and therefore each virtual bare die 41, 42, 43 is a piece of single crystal silicon, and the thermal conductivity is about 149W / (m·K), which is much greater than the thermal conductivity of SiO2 (about 1.1W / (m·K)). Depending on the type of silicon wafer used to manufacture the virtual bare die 41, 42, 43, in some embodiments, the virtual bare die 41, 42, 43 may include an n-type dopant (e.g., phosphorus, antimony, arsenic, etc.) or a p-type dopant (e.g., boron, indium, etc.). In other embodiments, the virtual bare die 41, 42, 43 can be manufactured using other suitable materials, such as other types of semiconductor wafers (e.g., GaAs wafers, InP wafers, SiC wafers, etc.), and the present disclosure is not limited thereto.

[0089] Figure 2 Draw along the Figure 1 An example of a cross-sectional view drawn along the AA section line of . A dielectric layer 10 (e.g., a SiO2 layer, a layer of other suitable material, or any combination thereof) is formed on top of the first bare die 1, wherein the dielectric layer 10 is embedded with at least one metal pad (e.g., made of copper, gold, other suitable metals, or any combination thereof). The second bare die 2 is bonded to the first bare die 1, for example, using a hybrid bond (e.g., including both metal-metal bonding and dielectric-dielectric bonding). Therefore, the first bare die 1 and the second bare die 2 are physically and electrically connected to each other. The third bare die 3 can also be bonded to the first bare die 1 in a similar manner, so for the sake of brevity, its details are omitted here.

[0090] See also Figure 3The first die 1 includes a substrate 11, a dielectric structure 12, one or more wiring layers 13, a plurality of internal vias 14, a sealing structure 15, a dielectric film 16, a plurality of devices 17, one or more conductive pads 18 and at least one interconnection element 19. The substrate 11 may be, for example, a silicon substrate.

[0091] The dielectric structure 12 is formed on the substrate 11. In an exemplary embodiment, the dielectric structure 12 includes a plurality of dielectric layers 125 stacked on each other. The dielectric layer 125 may include, for example, silicon oxide, silicon nitride, silicon carbide, phosphosilicate glass (PSG), undoped silicate glass (USG), tetraethoxysilane (TEOS) oxide, low-k material, ultra-low-k material, other suitable materials, or any combination thereof.

[0092] One or more wiring layers 13 are formed in the dielectric structure 12. Different wiring layers 13 may be electrically connected through internal vias 14 embedded in the dielectric structure 12 between the wiring layers 13.

[0093] The sealing structure 15 is embedded in the dielectric structure 12 and disposed around the wiring layer 13 and the internal via 14 to prevent the wiring layer 13 and the internal via 14 from being corroded by moisture.

[0094] The dielectric film 16 may include, for example, silicon oxide, other suitable materials, or any combination thereof.

[0095] The device 17 may include, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), a diode, other types of circuit elements, or any combination thereof, and the device 17 may be electrically connected to the wiring layer 13 through the internal via 14 .

[0096] The interconnection element 19 may include, for example, a through-silicon via (TSV), a through-oxide via (TOV), other suitable structures, or any combination thereof, configured to connect between dies.

[0097] According to some embodiments, the basic structures of the second die 2 and the third die 3 may be similar to the basic structure of the first die 1 , and therefore, for the sake of brevity, the details of the second die 2 and the third die 3 are omitted here.

[0098] Figure 4 is a flow chart of steps for a method of manufacturing a stacked semiconductor device according to some embodiments, and Figure 4 Cooperate Figures 5 to 12 To illustrate Figure 1 The manufacturing process of the stacked semiconductor device shown in FIG. Figures 5 to 12 depicts a cross-sectional view of a structure at an intermediate stage of a method for manufacturing a stacked semiconductor device according to some embodiments, and Figures 5 to 12 It is along Figure 1 The cross-sectional view is shown along the BB cross-sectional line in FIG.

[0099] See also Figure 1 , Figure 4 and Figure 5 , the first bare die 1 is bonded to the first carrier wafer 100 (step S01) by using, for example, fusion, other suitable techniques or any combination thereof. The first bare die 1 has a first surface 1A and a second surface 1B, and the second surface 1B is opposite to the first surface 1A, and the second surface 1B is connected to the first carrier wafer 100. Since the exemplary process is a wafer-level process, there may be multiple bare die bonded to the first carrier wafer 100, and accordingly, a dielectric layer 110 can be formed to fill the gaps between the multiple bare die. The dielectric layer 110 may include, for example, silicon oxide, silicon nitride, TEOS oxide, other suitable materials or any combination thereof. The first carrier wafer 100 is configured to enhance the overall mechanical strength of the structure to avoid mechanical damage caused by subsequent process steps.

[0100] See also Figure 1 , Figure 4 and Figure 6 , the second die 2 and the third die 3 are bonded to the first die 1 by using, for example, hybrid bonding, other suitable techniques or any combination thereof (step S02). According to some embodiments, a suction machine (not shown) may be used to pick up the second die 2 and the third die 3 and place them on corresponding predetermined areas of the first surface 1A of the first die 1. Then, an annealing process may be used to bond the second die 2 and the third die 3 to the first die 1.

[0101] See also Figure 1 , Figure 4 and Figure 7 , the virtual bare die 41, 42, 43 is bonded to the first bare die 1 by using, for example, fusion bonding, other suitable techniques or any combination thereof (step S03). According to some embodiments, the suction machine can be configured to pick up the virtual bare die 41, 42, 43 and place them on each predetermined area of ​​the first surface 1A of the first bare die 1, and the predetermined area is adjacent to the second bare die 2 and / or the third bare die 3. Then, the virtual bare die 41, 42, 43 is bonded to the first bare die 1 using an annealing process.

[0102] According to some embodiments, the bonding of the virtual dies 41, 42, 43 (step S03) may be performed before the bonding of the second and third dies 2, 3 (step S02). According to some embodiments, the second and third dies 2, 3 and the virtual dies 41, 42, 43 may all be placed on the first surface 1A of the first die 1, and then the annealing process may be performed to bond these dies 2, 3, 41, 42, 43 to the first die 1 to reduce the overall processing time. However, bonding the second and third dies 2, 3 before bonding the virtual dies 41, 42, 43 may prevent particle contamination that may be generated by picking up and placing the virtual dies 41, 42, 43 during the bonding of the second and third dies 2, 3.

[0103] See also Figure 1 , Figure 4 and Figure 8 , a dielectric layer 120 is deposited (step S04) to fill the gaps between the second and third dies 2, 3 and the dummy dies 41, 42, 43. The dielectric layer 120 may include, for example, silicon oxide, silicon nitride, TEOS oxide, other suitable materials or any combination thereof.

[0104] See also Figure 1 , Figure 4 and Fig. 9 , a planarization process is performed on the dielectric layer 120 (step S05) to expose the top surfaces of the second and third bare dies 2, 3 and the virtual bare dies 41, 42, 43. In this way, the second and third bare dies 2, 3 and the virtual bare dies 41, 42, 43 can have the same thickness. According to some embodiments, the planarization process can be, for example, a chemical-mechanical planarization (CMP) process, other suitable processes or any combination thereof. Since the top surfaces of the second and third bare dies 2, 3 and the virtual bare dies 41, 42, 43 are generally made of silicon (the thermal conductivity is greater than the thermal conductivity of the dielectric layer 120), exposing the second and third bare dies 2, 3 and the virtual bare dies 41, 42, 43 can be beneficial to heat dissipation.

[0105] See also Figure 1 , Figure 4 and Fig.10, the second carrier wafer 200 is bonded to the dielectric layer 120, the second and third bare die 2, 3 and the virtual bare die 41, 42, 43, and then the combined wafer and bare die are flipped for subsequent operations (step S06). In some embodiments, a bonding dielectric film (not shown) can be formed above the dielectric layer 120, the second and third bare die 2, 3 and the virtual bare die 41, 42, 43, and then the second carrier wafer 200 is bonded to the bonding dielectric film (not shown). The bonding dielectric film is bonded by using, for example, fusion bonding, other suitable techniques or any combination thereof. The second carrier wafer 200 is configured to enhance the overall mechanical strength of the structure to avoid mechanical damage caused by subsequent process steps.

[0106] See also Figure 1 , Figure 4 and Fig.11 , by using, for example, a CMP process, a grinding process, other suitable thinning techniques or any combination thereof, to remove the first carrier wafer 100 (see Fig.10 ) (step S07), thereby exposing the second surface 1B of the first bare die 1. The second surface 1B of the first bare die 1 may be the surface of the dielectric film 16 (see Figure 3 ).

[0107] See also Figure 1 , Figure 2 , Figure 4 and Fig.12 , forming a plurality of solder bumps 20 on the first bare die 1 (step S08), so that the solder bumps 20 are connected to the conductive pads 18 of the first bare die 1 (see Figure 3 In some embodiments, the dielectric film 16 and the dielectric structure 12 are etched to expose the conductive pads 18 , and then, the solder bumps 20 are formed on the conductive pads 18 .

[0108] Fig.13 FIG. 4 is a schematic top view of a stacked semiconductor device according to some embodiments. Fig.13 and Figure 1 The difference is that Figure 1 The virtual bare die 41, 42, 43 in the figure are replaced by the heat dissipation element 5, and the heat dissipation element 5 is made into a cap to cover the second bare die 2 and the third bare die 3. The heat dissipation element 5 is integrally formed, and the thermal conductivity of the heat dissipation element 5 is greater than that of SiO2 to achieve better heat dissipation capability. Figure 1The virtual bare die 41, 42, 43 in the heat dissipation element 5 can be made of a silicon wafer and through a general lithography process (e.g., a process for forming an STI structure), and therefore, can be a piece of single crystal silicon, but the present disclosure is not limited thereto. In other embodiments, the heat dissipation element 5 can be made of other suitable materials, such as other types of semiconductor wafers (e.g., GaAs wafers, InP wafers, SiC wafers, etc.). Fig.14 It is along Fig.13 A cross-sectional view of the stacked semiconductor device taken along the CC cross-sectional line in FIG.

[0109] Fig.15 It is along Fig.13 The heat dissipation element 5 laterally surrounds and covers the second die 2 and the third die 3, and the heat dissipation element 5 forms a first space 541 for accommodating the second die 2 and a second space 542 for accommodating the third die 3. Fig.13 As shown, the top view of the heat dissipation element 5 is virtually divided into a plurality of rectangular parts, which are respectively called the first virtual die part 511, the second virtual die part 512, the third virtual die part 513, the interconnection part 520, the first frame part 521, the second frame part 522, the third frame part 523, the first cover part 531 and the second cover part 532. In this embodiment, the heat dissipation element 5 has a flat top surface, that is, the top surfaces of the virtual die parts 511, 512, 513, the interconnection part 520, the frame parts 521, 522, 523 and the cover parts 531, 532 are coplanar.

[0110] The bottom surface of each of the virtual die portions 511, 512, 513, the interconnection portion 520, and the frame portions 521, 522, 523 may be attached to the first die 1 by, for example, fusion bonding. The first virtual die portion 511 has a first edge (or side surface) and a second edge, and the first edge of the first virtual die portion 511 extends in parallel and is adjacent to the edge 21 of the second die 2, while the second edge of the first virtual die portion 511 extends in parallel and is adjacent to the edge 31 of the third die 3. The second virtual die portion 512 has a first edge and a second edge, and the first edge of the second virtual die portion 512 extends in parallel and is adjacent to the edge 22 of the second die 2, while the second edge of the second virtual die portion 512 extends in parallel and is adjacent to the edge 32 of the third die 3. The third virtual die portion 513 has an edge, and the edge of the third virtual die portion 513 extends in parallel and is adjacent to the edge 33 of the third die 3. The lateral edge-to-edge distance d between the heat dissipation element 5 and the die 2, 3 can be determined according to the accuracy of the suction machine when placing the die and the heat dissipation element 5. For example, when the accuracy of the suction machine is ±1μm, the edge distance d can be designed to be greater than and close to about 2μm, and in some embodiments, the edge distance d can be designed to be as small as about 0.01μm. The interconnection portion 520 is arranged between the second die 2 and the third die 3, and the interconnection portion 520 interconnects the first virtual die portion 511 and the second virtual die portion 512. The virtual die portions 511, 512, the interconnection portion 520 and the frame portions 521, 522 collectively surround or enclose the second die 2. The virtual die portions 511, 512, 513, the interconnection portion 520 and the frame portion 523 collectively surround or enclose the third die 3.

[0111] The first cover portion 531 is connected and matched with the dummy die portions 511, 512, the interconnection portion 520, and the frame portions 521, 522 to form a first space 541 for accommodating the second die 2, and the first cover portion 531 is disposed above the second die 2 and covers the second die 2. The second cover portion 532 is connected and matched with the dummy die portions 511, 512, 513, the interconnection portion 520, and the frame portion 523 to form a second space 542 for accommodating the third die 3, and the second cover portion 532 is disposed above the third die 3 and covers the third die 3. In an exemplary embodiment, the cover portions 531, 532 are hanging portions that are not bonded to the first die 1, and the thickness of the cover portions 531, 532 is thinner than the dummy die portions 511, 512, 513, the interconnection portion 520, and the frame portions 521, 522. According to some embodiments, the thickness h1 of each cover 531, 532 is greater than about 100 μm, so as to have sufficient mechanical strength to prevent damage that may be caused by the process of picking up and placing the heat dissipation element 5 to the first die 1. In some embodiments, the thickness h1 can be as low as about 0.01 μm. The distance between the die (e.g., the second die 2 or the third die 3) and the corresponding cover (e.g., the first cover 531 or the second cover 532) is the distance h2, which is the distance between the top surface of the die and the bottom surface of the corresponding cover, and the distance h2 can be determined based on the manufacturing accuracy relative to the thickness of the die. According to some embodiments, the distance h2 can be designed to be greater than about 2 μm to match the allowable deviation of the thickness variation of the die. Through good process control, in some embodiments, the distance h2 can be designed to be as low as about 0.01 μm. The smaller the distance h2, the better the heat dissipation of the heat generated by the die. Therefore, in some embodiments, the distance h2 can be designed to be less than about 10 μm to achieve the desired heat dissipation capability. According to some embodiments, the total thickness h3 of the heat dissipation element 5 (i.e., the thickness in each virtual die portion 511, 512, 513, the interconnection portion 520, and the frame portion 521, 522, 523) may be equal to the sum of the thickness h1 of the corresponding cover portion of the second or third die 2 or 3 and the distance h2 between the die and the cover portion. In some embodiments, the thickness h3 is designed to be the maximum possible value, i.e., equal to the wafer thickness of about 800 μm, and the thickness h1 of the cover portion may be about 780 μm. Figure 1 Compared with the virtual bare die 41, 42, 43 in the heat dissipation element 5, the heat dissipation element 5 has a larger total top surface area for heat dissipation, thereby achieving better heat dissipation uniformity and performance. According to some embodiments, even if the bare die thicknesses are different, the spaces (e.g., the first space 541 and the second space 542) configured to accommodate the bare die (e.g., the second bare die 2 and the third bare die 3) can be made to have the same height, so these spaces can be formed simultaneously in a single lithography process, thereby reducing manufacturing costs.

[0112] An adhesive material 6 is provided between the heat dissipation element 5 and each of the second die 2 and the third die 3 to further fix the die 2, 3 and the heat dissipation element 5 relative to the first die 1 and protect the die 2, 3 from moisture. According to some embodiments, the adhesive material 6 may include an organic material, such as epoxy resin, other suitable materials, or any combination thereof. According to some embodiments, one or more additional substances with good thermal conductivity may be added to the adhesive material 6 to enhance the heat dissipation capability of the adhesive material 6. The additional substance may include, for example, a two-dimensional (2D) material, such as graphene (having a thermal conductivity between about 4400 W / (m·K) and about 5800 W / (m·K)), a metal, other suitable materials, or any combination thereof.

[0113] like Fig.13 As shown, each of the covering parts 531, 532 has through holes 551, 552 and openings 561, 562 formed in the respective top surfaces. Since the covering parts 531, 532 have similar structures, only the covering part 532 will be described in detail for the sake of brevity. Fig.16 , Fig.16 A cross-sectional view of a heat dissipation element of a stacked semiconductor device according to some embodiments is shown, wherein Fig.16 It is along Fig.13 , and both the through hole 552 and the opening 562 are spatially connected to the second space 542. In other words, the opening 562 is spatially connected to the through hole 552 through the second space 542. In this exemplary embodiment, the through hole 552 serves as a glue inlet, which is configured to inject the adhesive material 6 into the second space 542, and the opening 562 serves as a glue outlet, which is configured to overflow from the glue outlet when the adhesive material 6 is injected. According to some embodiments, the through hole 552 is a circular hole with a diameter greater than about 15 μm to facilitate the injection of the adhesive material 6. In some embodiments, the through hole 552 can be formed into other shapes, and the cross-sectional area of ​​the through hole 552 is not less than the cross-sectional area of ​​the diameter of about 15 μm when viewed from above. According to some embodiments, the through hole 552 is disposed adjacent to one edge of the third bare die 3, and the opening 562 is disposed adjacent to another opposite edge of the third bare die 3. According to some embodiments, the size of the through hole 552 is larger than the size of the opening 562 , so that when the adhesive material 6 is injected, a greater hydraulic pressure is generated, which is conducive to filling the adhesive material 6 into the second space 542 .

[0114] Fig.17 is a flow chart of steps for a method of manufacturing a stacked semiconductor device according to some embodiments, and Fig.17 Cooperate Figures 18 to 27 To illustrate Fig.13The manufacturing process of the stacked semiconductor device shown in FIG. Fig.18 , Fig.19 and Figure 24 to Figure 27 It is along Fig.13 The cross-sectional view is drawn by the DD section line, and Figure 20 to Figure 23 It is along Fig.13 The cross-sectional view is shown by the E1-E1 cross-sectional line in FIG. Figure 4 Steps S01 and S02 in the flowchart shown are similar, so for the sake of brevity, the relevant details are not repeated here.

[0115] See also Fig.13 , Fig.17 and Fig.18 , by using, for example, fusion bonding, other suitable techniques or any combination thereof, the heat dissipation element 5 is bonded to the first bare die 1 (step S13). According to some embodiments, a suction machine (not shown) can be used to pick up the heat dissipation element 5 and place it on the first surface 1A of the first bare die 1, so that the second bare die 2 is accommodated in the first space 541 (see Fig.14 ), and the third bare die 3 is accommodated in the second space 542 (see Fig.15 ). Then, an annealing process may be performed to bond the heat dissipation element 5 to the first bare die 1. In this exemplary embodiment, since the heat dissipation element 5 is integrally formed, only one pick-and-place operation needs to be performed in step S13. Figure 1 Compared with the embodiment shown, Figure 1 Compared with the situation where multiple pick and place operations must be performed for multiple virtual bare chips respectively, the use of the heat dissipation element 5 can reduce the overall process time.

[0116] According to some embodiments, bonding the heat dissipation element 5 (step S13) may be performed before bonding the bare die 2 and 3 (step S12). According to some embodiments, the bare die 2 and 3 and the heat dissipation element 5 may all be placed on the first surface 1A of the first bare die 1, and then an annealing process is performed to bond the bare die 2 and 3 and the heat dissipation element 5 to the first bare die 1 together, thereby reducing the overall process time. However, bonding the bare die 2 and 3 before bonding the heat dissipation element 5 can prevent particle contamination that may be caused by picking up and placing the heat dissipation element 5 during bonding the bare die 2 and 3.

[0117] See also Fig.13 , Fig.17 and Fig.19 , the adhesive material 6 is injected into the heat dissipation element 5 (step S14) to fill the space between the bare die 2, 3 and the heat dissipation element 5 (for example, the first space 541 and the second space 542, see Fig.14 and Fig.15During the injection process, the adhesive material 6 may flow over the top surface and the side surfaces of the heat dissipation element 5 . Figure 20 to Figure 23 The glue injection process according to some embodiments is depicted in more detail.

[0118] Fig. 20 The corresponding Fig.13 The cross-sectional view is taken along the E1-E1 section line in FIG. Fig. 20 The structure shown is obtained after step S13, Fig. 20 It is shown that the third bare die 3 is accommodated in the second space 542 , and the second space 542 is spatially connected with the through hole 552 and the opening 562 .

[0119] like Fig.21 As shown, the adhesive material 6 is injected into the second space 542 through the through hole 552. During the injection process, the adhesive material 6 overflows from the through hole 552, thereby spreading over the top surface and the side surface of the heat dissipation element 5.

[0120] like Fig. 22 As shown, the adhesive material 6 is continuously injected into the second space 542 from the through hole 552 . Therefore, when the second space 542 is filled with the adhesive material 6 , the adhesive material 6 will overflow from the opening 562 .

[0121] When the adhesive material 6 is injected into the second space 542, the detector 300 can be used to instantly detect the internal condition of the heat dissipation element 5 when the adhesive material 6 is injected. For example, the detector 300 can detect whether there is a gap inside the heat dissipation element 5 that is not filled with the adhesive material 6. When the gap is detected, the injection parameters (for example, the injection time or pressure) can be adjusted immediately to eliminate the gap. According to some embodiments, the detector 300 can be implemented using, for example, an infrared (IR) detector, other suitable types of detectors, or any combination thereof.

[0122] like Fig.23As shown, the adhesive material 6 is injected and the adhesive material 6 is disposed on the top surface and the side surface of the heat dissipation element 5. According to some embodiments, the adhesive material 6 does not need to completely cover the heat dissipation element 5 (i.e., cover the entire top surface and the side surface of the heat dissipation element 5). Then, an annealing process may be performed to solidify the adhesive material 6. In this exemplary embodiment, since the adhesive material 6 fills the through hole 552 and the opening 562, and both the through hole 552 and the opening 562 extend in a vertical direction perpendicular to the surface of the first bare crystal 1 (the surface bonded to the heat dissipation element 5), the cured adhesive material 6 has a first extension portion and a second extension portion, and the first extension portion extends from the through hole 552 through the covering portion 532, and the second extension portion extends from the opening 562 through the covering portion 532, and both the first extension portion and the second extension portion extend in a vertical direction. In some embodiments, one or more adhesive outlets (e.g. Fig.29 , Fig.30 and Fig.32 The curing adhesive material 6 may form one or more extensions (corresponding to the adhesive outlets, respectively) which extend through one or more side walls of the heat dissipation element 5 along a direction parallel to the surface of the first bare crystal 1 (the surface bonded to the heat dissipation element 5).

[0123] See also Fig.13 , Fig.17 and Fig.24 , a planarization process is performed on the cured adhesive material 6 (step S15) to expose the top surface of the heat dissipation element 5. According to some embodiments, the planarization process may be, for example, a CMP process, other suitable processes or any combination thereof. Since the thermal conductivity of the heat dissipation element 5 is generally greater than the thermal conductivity of the adhesive material 6, exposing the top surface of the heat dissipation element 5 is beneficial to heat dissipation.

[0124] See also Fig.13 , Fig.17 and Fig.25 , the second carrier wafer 200 is bonded to the heat dissipation element 5, and then the combined wafer and bare die are flipped for subsequent processing (step S16). In some embodiments, a bonding dielectric film (not shown) can be formed above the heat dissipation element 5, and then the second carrier wafer 200 can be bonded to the bonding dielectric film using, for example, fusion bonding, other suitable techniques, or any combination thereof. The second carrier wafer 200 is configured to enhance the overall mechanical strength of the structure to avoid mechanical damage caused by subsequent process steps. According to some embodiments, the thickness of the heat dissipation element 5 is thick enough (e.g., greater than 600 μm) to provide sufficient mechanical strength for subsequent process steps, and the bonding of the second carrier wafer 200 can be omitted.

[0125] See also Fig.13 , Fig.17 and Fig.26 , by using, for example, a CMP process, a grinding process, other suitable thinning techniques or any combination thereof, to remove the first carrier wafer 100 (see Fig.25 )(step S17 ) to expose the second surface 1B of the first bare die 1 .

[0126] See also Fig.13 , Fig.17 and Fig. 27 , forming a plurality of solder bumps 20 on the first bare die 1 (step S18), so that the solder bumps 20 are connected to the conductive pads 18 of the first bare die 1 (see Figure 3 ).

[0127] Figure 28 to Figure 35 1 and 2 are some variations of heat dissipation elements of a stacked semiconductor device according to some embodiments, wherein the area indicated by the dotted line blocks corresponds to the locations of the second die 2 and the third die 3 .

[0128] See also Fig.28 , Fig.28 The first variation of the heat dissipation element 5 provided according to some embodiments is shown in FIG. 1. In this exemplary variation, the heat dissipation element 5 includes a first virtual die portion 511 to be bonded to a lower die (eg, the aforementioned first die 1), a virtual die portion 512, and a third virtual die portion 513. Fig.28 Part (a) is a top view of the heat dissipation element 5, Fig.28 Part (b) is along Fig.28 A cross-sectional view of the heat dissipation element 5 drawn along the E2-E2 section line of part (a). The first virtual die portion 511 and the second virtual die portion 512 are respectively adjacent to two of the edges of the aforementioned second die 2. The first virtual die portion 511, the second virtual die portion 512 and the third virtual die portion 513 are respectively adjacent to three of the edges of the aforementioned third die 3. The other portions of the heat dissipation element 5 include covering portions 531, 532, and the other portions of the heat dissipation element 5 are hanging portions. The hanging portion is thinner than the virtual die portions 511, 512, 513 and will not be bonded to the aforementioned first die 1. The hanging portion interconnects the virtual die portions 511, 512, 513, and the top surface of the hanging portion is coplanar with the top surface of the virtual die portions 511, 512, 513. Fig.13 Compared with the configuration shown in the figure, the configuration of this embodiment can provide a larger space to accommodate the aforementioned bare die 2, 3, and also allow a larger allowable deviation when placing the heat dissipation element 5 on the aforementioned first bare die 1.

[0129] Fig.29 According to some embodiments, Fig.13A second variation of the heat dissipation element 5 is similar to the heat dissipation element 5. In an exemplary variation, Fig.29 Part (a) is a top view of the heat dissipation element 5, Fig.29 Part (b) is along Fig.29 5. A cross-sectional view of the heat dissipation element 5 drawn along the E3-E3 section line of part (a). In this variation, the openings 561 and 562 of the heat dissipation element 5 are respectively formed on the side surface of the heat dissipation element 5, and the openings 561 and 562 are configured to allow excess adhesive material 6 to flow out of the heat dissipation element 5 laterally during the glue injection process. In addition, the openings 561 and 562 are respectively formed as uncovered channels that penetrate the top surface and the bottom surface of the heat dissipation component 5, wherein the openings 561 and 562 respectively extend to the first space 541 under the corresponding covering portion 531 and the second space 542 under the covering portion 532, and are spatially connected.

[0130] Fig.30 FIG. 1 is a diagram illustrating a method for performing a Fig.29 The second variation of the heat dissipation element 5 is similar to the third variation of the heat dissipation element 5. In an exemplary variation, Fig.30 Part (a) is a top view of the heat dissipation element 5, Fig.30 Part (b) is along Fig.30 5. A cross-sectional view of the heat dissipation element 5 drawn along the E4-E4 section line of part (a). In the present variation, the openings 561, 562 of the heat dissipation element 5 are each formed on the side surface of the heat dissipation element 5, and the openings 561, 562 are configured so that the excess adhesive material 6 flows out of the heat dissipation element 5 laterally. The openings 561, 562 are each formed as a channel, and the channel is covered by the top surface of the heat dissipation component 5. The openings 561, 562 extend to the first space 541 under the corresponding covering portion 531 and the second space 542 under the covering portion 532, respectively, and are spatially connected. In an exemplary embodiment, the covering portions 531, 532 extend to cover the openings 561, 562, respectively.

[0131] Fig.31 According to some embodiments, Fig.13 The heat dissipation element 5 is similar to the fourth variation of the heat dissipation element 5. In the exemplary variation, Fig.31 Part (a) is a top view of the heat dissipation element 5, Fig.31 Part (b) is along Fig.31A cross-sectional view of the heat dissipation element 5 drawn along the E5-E5 section line of part (a). In this variation, the top surface of the heat dissipation element 5 is provided with an opening 563 extending from the first covering portion 531 to the second covering portion 532, so that the opening 563 is spatially connected to the first space 541 below the first covering portion 531 and the second space 542 below the second covering portion 532. In this way, the first space 541 is spatially connected to the second space 542 through the opening 563, so that during the glue injection process, the adhesive material 6 can flow between the first space 541 and the second space 542. Since the heat dissipation element 5 may require at least one glue inlet and at least one glue outlet to perform the glue injection process. Therefore, in this configuration, the opening 563 can be used as a glue inlet or a glue outlet, and one of the through holes 551, 552 can be used as a glue outlet (when the opening 563 is used as a glue inlet) or as a glue inlet (when the opening 563 is used as a glue outlet). According to some embodiments, one of the through holes 551, 552 may be omitted. According to some embodiments, additional openings may be formed in the top surface and / or side surface of the heat dissipation element 5 to allow the glue material 6 to be injected and / or flowed out, for example Fig.13 , Fig.28 , Fig.29 , Fig.30 shown.

[0132] Fig.32 According to some embodiments, Fig.31 The fifth variation of the heat dissipation element 5 is similar to the heat dissipation element 5. In the exemplary variation, Fig.32 Part (a) is a top view of the heat dissipation element 5, Fig.32 Part (b) is along Fig.32 5. A cross-sectional view of the heat dissipation element 5 drawn along the E6-E6 section line of part (a). In this variation, the interconnection portion 533 between the covering portions 531 and 532 of the heat dissipation element 5 is a hanging portion, which will not be bonded to the aforementioned first bare die 1, and interconnects the covering portions 531 and 532 (i.e., the covering portions 531, 532 and the interconnection portion 533 are integrally formed into a large hanging member), so that the first space 541 under the first covering portion 531 is spatially connected to the second space 542 under the second covering portion 532 through the space under the interconnection portion 533. In this exemplary embodiment, the heat dissipation element 5 is formed with openings 561, 562, as shown in FIG. Fig.32 As shown, but this variation is not limited thereto. In some embodiments, through holes 551, 552 can be used as a glue inlet-glue outlet pair, and openings 561, 562 can be omitted. In some embodiments, heat dissipation element 5 can be formed with only one of through holes 551, 552 as a glue inlet, and heat dissipation element 5 can be formed with only one of openings 561, 562 as a glue outlet.

[0133] Fig.33 According to some embodiments, Fig.13 The sixth variation of the heat dissipation element 5 is similar to the heat dissipation element 5. In the exemplary variation, Fig.33 Part (a) is a top view of the heat dissipation element 5, Fig.33 Part (b) is along Fig.33 A cross-sectional view of the heat dissipation element 5 drawn along the E7-E7 section line of part (a). In this variation, Fig.13 The covering parts 531 and 532 are omitted, so the top surface of the heat dissipation element 5 is formed with a first opening 543 and a second opening 544, and the first opening 543 is spatially connected with the first space 541, and the second opening 544 is spatially connected with the first space 542. According to some embodiments, the first opening 543 is aligned with the first space 541 and has the same length and width, and the second opening 544 is aligned with the second space 542 and has the same length and width as the second space 542. Through the openings 543 and 544, the adhesive material 6 can be directly dispensed onto the bare die 2 and 3 through the openings 543 and 544 with a larger flow rate, thereby reducing the time required for the injection process.

[0134] Fig.34 According to some embodiments, Fig.33 The heat dissipation element 5 is similar to the seventh variation of the heat dissipation element 5. In the exemplary variation, Fig.34 Part (a) is a top view of the heat dissipation element 5, Fig.34 Part (b) is along Fig.34 FIG. 5 is a cross-sectional view of the heat dissipation element 5 drawn along the E8-E8 section line of the portion (a) of FIG. 5 . In this variation, the length and width of the heat dissipation element 5 are smaller than the first die 1, and the heat dissipation element 5 is configured not to surround or not to completely surround the die 2, 3. When the heat dissipation element 5 is placed on the first die 1 at a predetermined position adjacent to the die 2, 3, the edge of the heat dissipation element 5 will be arranged within the boundary defined by the edge of the first die 1, and the edge of the heat dissipation element 5 is spaced apart from the edge of the first die 1 in the lateral direction.

[0135] Fig.35 According to some embodiments, Fig.34 The seventh variation of the heat dissipation element 5 is similar to the eighth variation of the heat dissipation element 5. In the exemplary variation, Fig.35 Part (a) is a top view of the heat dissipation element 5, Fig.35 Part (b) is along Fig.35FIG. 5 is a cross-sectional view of the heat dissipation element 5 drawn along the E9-E9 section line of the portion (a) of FIG. 5 . In this variation, the heat dissipation element 5 is extended in some lateral directions beyond the boundaries defined by the edges of the first die 1, so that when the heat dissipation element 5 is placed on the first die 1 at a predetermined position adjacent to the die 2 and 3, a portion of the edge of the heat dissipation element 5 is disposed outside the first die 1 and is spaced apart from the edge adjacent to the first die 1.

[0136] See also Fig.36 and Fig.37 According to some embodiments, the heat dissipation structure of the stacked semiconductor device includes a plurality of heat dissipation elements 5A, 5B for the bare die 2, 3, respectively, wherein Fig.36 A top view of a stacked semiconductor device is shown, and Fig.37 Draw along the Fig.36 FF section line of the stacked semiconductor device. In an exemplary embodiment, the heat dissipation elements 5A and 5B are bonded to the first die 1, and the heat dissipation elements 5A and 5B are spaced apart from each other. Each heat dissipation element 5A and 5B is formed with a space to accommodate the corresponding die 2 and 3. Specifically, the heat dissipation element 5A includes a first bonding portion and a first covering portion 531, the first bonding portion is bonded to the first die 1 and surrounds the second die 2, and the first bonding portion includes a dummy die portion 511. The first covering portion 531 is connected to the first bonding portion and is disposed above the second die 2 and covers the second die 2. The heat dissipation element 5B includes a second bonding portion and a second covering portion 532. The second bonding portion is bonded to the first die 1 and surrounds the third die 3, and the second bonding portion includes dummy die portions 512 and 513. The second covering portion 532 is connected to the second bonding portion, and the second covering portion 532 is disposed above the third die 3 and covers the third die 3. According to some embodiments, the top surfaces of the heat dissipation elements 5A and 5B are coplanar. After the glue injection process, the glue material 6 fills the space for accommodating the bare die 2 and 3 , and the glue material 6 fills the gap between the heat dissipation components 5A and 5B.

[0137] According to some embodiments, the heat dissipation element 5, 5A, 5B can be used with a die in the top layer of a stacked semiconductor device, and the number of layers of the stacked semiconductor device can vary. For example, when the stacked semiconductor device includes three layers of die stacked together, such as a first die layer, a second die layer, and a third die layer from bottom to top, the heat dissipation element 5, 5A, 5B can be used for the third die layer.

[0138] Fig.38 Various examples of cross-sectional views of final products of stacked semiconductor devices according to some embodiments are shown. Fig.38In the example shown in parts (a) to (d) of the present invention, a plurality of bare die 61 to 65 are bonded to an interposer 7 and electrically connected to a substrate 8 through the interposer 7, so that electrical signals can be transmitted between the bare die 61 to 65 through the interposer 7 and the substrate 8. Some of the bare die 61 to 65 can be made into a structure having a stacked semiconductor device according to some embodiments of the present disclosure (i.e., using heat dissipation elements 5, 5A, 5B). Although the bare die 61 to 65 can have their own heat dissipation structure, the final product can have an additional cooling structure 9 formed above each bare die 61 to 65. As shown in FIG. Fig.38 As shown in parts (a) to (d), the cooling structure 9 can be made of, for example, heat dissipation glue, and the cooling structure 9 can have different forms (for example, having different types of serrated surfaces, being formed with some gaps, etc.), other suitable structures or any combination thereof.

[0139] Fig.39 Various examples of cross-sectional views of final products of stacked semiconductor devices according to some embodiments are shown. Fig.39 In the embodiment, the cooling structure may include a heat dissipation adhesive 91 and a heat sink 92 made of metal, wherein the heat dissipation adhesive 91 is used as an adhesive between the heat sink 92 and the bare die 61 to 65. The heat sink 92 may have different structures. Fig.39 In part (a), the heat sink 92 may be a metal seat including multiple layers of different metals; Fig.39 In part (b), the heat sink 92 may include a first metal sheet portion and a second metal sheet portion, wherein the first metal sheet portion contacts the top surface of the heat dissipation adhesive 91, and the second metal sheet portion contacts the side surface of the heat dissipation adhesive 91; Fig.39 In part (c), the heat sink 92 may be a metal base made of a single metal material, and the heat sink 92 is disposed above the heat dissipation glue 91; Fig.39 In part (d), the heat sink may include a metal layer 92A and a plurality of metal components 92B, wherein the metal layer 92A covers the heat dissipation adhesive 91, and the plurality of metal components 92B are disposed on the metal layer 92A, and the metal layer 92A and the metal components 92B are made of different metal materials.

[0140] In summary, in some embodiments of the present disclosure, the heat dissipation element is integrally formed to correspond to the position of the unoccupied space on the lower bare die, thereby reducing the multiple pick-and-place actions of placing the heat dissipation element on the lower bare die, thereby shortening the overall process time. In some embodiments of the present disclosure, the heat dissipation element is formed as a cap, which includes one or more covering portions arranged above the bare die and covering the bare die, thereby obtaining a larger heat dissipation area and achieving uniform and better heat dissipation. When the heat dissipation element is thick enough, the second carrier wafer can be omitted in the process of removing the first carrier wafer and forming the solder bump, thereby simplifying the process and reducing material costs.

[0141] According to some embodiments, a stacked semiconductor device is provided, and the stacked semiconductor device includes a first die, a second die bonded to the first die, a third die bonded to the first die, and a heat dissipation element, wherein the heat dissipation element is integrally formed and bonded to the first die. The heat dissipation element is adjacent to at least two edges of the second die, and the heat dissipation element is adjacent to at least two edges of the third die.

[0142] According to some embodiments, the heat dissipation element includes a semiconductor material.

[0143] According to some embodiments, the heat dissipation element includes a covering portion, and the covering portion covers at least one of the second die or the third die.

[0144] According to some embodiments, the heat dissipation element surrounds the second die and the third die, and forms a first space for accommodating the second die and a second space for accommodating the third die. The first space and the second space are spatially connected to each other.

[0145] According to some embodiments, the heat dissipation element laterally surrounds the second die, and the heat dissipation element laterally surrounds the third die.

[0146] According to some embodiments, the stacked semiconductor device further includes a heat dissipation adhesive layer, and the heat dissipation adhesive layer is disposed between the heat dissipation element and the second die, and the heat dissipation adhesive layer is disposed between the heat dissipation element and the third die.

[0147] According to some embodiments, the heat dissipation element includes a covering portion, and the covering portion covers at least one of the second bare die or the third bare die, and the heat dissipation adhesive layer disposed between the heat dissipation element and the second bare die and the third bare die respectively has a first extension portion, and the first extension portion extends through the covering portion.

[0148] According to some embodiments, the heat dissipation adhesive layer respectively disposed between the heat dissipation element and the second bare die and the third bare die has a second extension portion, and the second extension portion is spaced apart from the first extension portion, and the second extension portion extends through the side wall of one of the covering portion and the heat dissipation element.

[0149] According to some embodiments, the material disposed between the heat dissipation element and the second die and the third die, respectively, comprises a two-dimensional material.

[0150] According to some embodiments, a stacked semiconductor device is provided, and the stacked semiconductor device includes a first bare die, a second bare die bonded to the first bare die, and a heat dissipation cap element. The heat dissipation cap element is bonded to the first bare die and covers the second bare die. The heat dissipation cap element includes a covering portion, and the covering portion is disposed above the second bare die, and the covering portion has a through hole formed above the second bare die.

[0151] According to some embodiments, the heat sink cap element includes single crystal silicon.

[0152] According to some embodiments, the stacked semiconductor device further includes a bonding material, and the bonding material is disposed between the second die and the heat dissipation cap element.

[0153] According to some embodiments, the heat dissipation cap element includes a covering portion, and the covering portion is disposed above the second die, and a through hole is formed in the covering portion above the second die.

[0154] According to some embodiments, the heat dissipation cap element has an opening formed in one of the cover portion and a side surface of the heat dissipation cap element, and the opening is spatially connected to the through hole of the cover portion through the space where the second die is located.

[0155] According to some embodiments, the stacked semiconductor device further includes a third die bonded to the first die and another heat dissipation cap element. The other heat dissipation cap element is bonded to the first die and covers the third die. The heat dissipation cap element and the other heat dissipation cap element are spaced apart from each other.

[0156] According to some embodiments, the stacked semiconductor device further includes a third die bonded to the first die. The heat dissipation cap element is integrally formed and further covers the third die.

[0157] According to some embodiments, a method for manufacturing a stacked semiconductor device is provided. In one step, a first die is provided, and a second die and a third die are bonded to the first die. In one step, a heat dissipation element is disposed at a position of the first die, so that the heat dissipation element is adjacent to at least two edges of the second die and adjacent to at least two edges of the third die. The heat dissipation element is integrally formed. In one step, the heat dissipation element is bonded to the first die.

[0158] According to some embodiments, the heat dissipation element is formed with a space, and the heat dissipation element has a covering portion corresponding to the position of the space. In the step of placing the heat dissipation element on the first die, the heat dissipation element is placed in a position such that one of the second die and the third die is accommodated in the space of the heat dissipation element, and the covering portion covers one of the second die and the third die.

[0159] According to some embodiments, the cover portion is formed with a glue inlet hole that is spatially connected to the space accommodating one of the second die and the third die. In a step of the method, a glue material is injected into the space through the glue inlet.

[0160] According to some embodiments, the heat dissipation element has a glue outlet formed on one of the cover portion and the side surface of the heat dissipation element, and the glue outlet is spatially connected to the space accommodating one of the second bare die and the third bare die. In one step of the method, when the glue material overflows from the glue outlet, the injection of the glue material is terminated.

[0161] According to some embodiments, a stacked semiconductor device includes a substrate, an interposer disposed above the substrate, a plurality of bare dies bonded to the interposer, and a heat dissipation element bonded to at least one of the bare dies. In addition, the bare dies are electrically connected to the substrate through the interposer. The heat dissipation element is bonded to at least one of the plurality of bare dies, and the heat dissipation element includes a covering portion, and the covering portion is disposed above at least one of the plurality of bare dies. According to some embodiments, the stacked semiconductor device further includes a cooling structure disposed above each of the plurality of bare dies.

[0162] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that those skilled in the art can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A stacked semiconductor device, characterized in that: include: a first bare crystal; a second die bonded to the first die; a third die bonded to the first die; as well as a heat dissipation element, which is integrally formed and bonded to the first die; The heat dissipation element is adjacent to at least two edges of the second die, and the heat dissipation element is adjacent to at least two edges of the third die.

2. The stacked semiconductor device according to claim 1, wherein: The heat dissipation element includes a covering portion, and the covering portion covers at least one of the second bare die or the third bare die.

3. The stacked semiconductor device according to claim 1, wherein: The heat dissipation element surrounds the second die and the third die, and forms a first space for accommodating the second die and a second space for accommodating the third die; and The first space and the second space are spatially connected to each other.

4. The stacked semiconductor device according to claim 1, wherein: Further including: A heat dissipation adhesive layer is disposed between the heat dissipation element and the second bare die, and between the heat dissipation element and the third bare die.

5. The stacked semiconductor device according to claim 4, wherein: The heat dissipation element includes a covering portion, and the covering portion covers at least one of the second bare crystal or the third bare crystal, and the heat dissipation adhesive layer between the heat dissipation element and the second bare crystal and the third bare crystal has a first extension portion respectively, and the first extension portion extends through the covering portion.

6. A stacked semiconductor device, characterized in that: include: a first bare crystal; a second die bonded to the first die; as well as a heat dissipation cap element, bonded to the first die and covering the second die; The heat dissipation cap element includes a covering portion, and the covering portion is arranged above the second bare die, and the covering portion forms a through hole above the second bare die.

7. The stacked semiconductor device according to claim 6, wherein: The heat dissipation cap element has an opening formed in one of the covering portion and a side surface of the heat dissipation cap element, and the opening is spatially connected with a through hole of the covering portion through a space where the second bare die is located.

8. The stacked semiconductor device according to claim 6, wherein: Further including: a third die bonded to the first die; as well as Another heat dissipation cap element is bonded to the first die and covers the third die; The heat dissipation cap element and the other heat dissipation cap element are spaced apart from each other.

9. A stacked semiconductor device, characterized in that: include: a substrate; an interposer layer disposed above the substrate; A plurality of bare dies bonded to the interposer, wherein the plurality of bare dies are electrically connected to the substrate through the interposer; as well as A heat dissipation element is bonded to at least one of the plurality of bare dies, wherein the heat dissipation element comprises a covering portion, and the covering portion is disposed above at least one of the plurality of bare dies.

10. The stacked semiconductor device according to claim 9, wherein: Further including: A cooling structure is disposed above each of the plurality of bare chips.

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