Wafer stack

Abstract

The utility model discloses a wafer stack. The wafer stack includes a first wafer element, a second wafer element, and a third wafer element. The first wafer element includes a front side and a back side. The wafer stack also includes a second wafer element having a front side and a back side such that the front side of the second wafer element is bonded to the front side of the first wafer element. Further, the wafer stack includes a third wafer element having a front side and a back side such that the front side of the third wafer element is bonded to the back side of the second wafer element. The first wafer element includes a composite metal mesh array with one or more photodiodes formed on a backside.

Description

Technical Field

[0001] The present disclosure relates to a wafer stack. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive material layers over a semiconductor substrate and patterning the various material layers using lithography techniques to form circuit elements and components on the material layers. Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer.

[0003] As semiconductor technology has further advanced, stacked semiconductor devices, such as three-dimensional integrated circuits, have emerged to further reduce the physical size of semiconductor devices. In a stacked semiconductor device, various circuits are manufactured on different semiconductor wafers. The semiconductor wafers can then be stacked on top of each other to achieve a smaller form factor for the semiconductor device. Utility Model Content

[0004] According to some embodiments, a wafer stack is provided, the wafer stack comprising a first wafer element having a front side and a back side. The wafer stack also comprises a second wafer element having a front side and a back side, such that the front side of the second wafer element is bonded to the front side of the first wafer element. Furthermore, the wafer stack comprises a third wafer element having a front side and a back side, such that the front side of the third wafer element is bonded to the back side of the second wafer element. The first wafer element is a system chip, and at least one photodiode is formed on the back side of the first wafer element.

[0005] According to some embodiments, a wafer stack is provided, the wafer stack comprising a first wafer element having a front side and a back side. The wafer stack also comprises a second wafer element having a front side and a back side, such that the front side of the second wafer element is bonded to the front side of the first wafer element. At least one metal layer element is disposed on the back side of the second wafer element. In addition, the wafer stack comprises a third wafer element having a front side and a back side, such that the front side of the third wafer element is bonded to the back side of the second wafer element. The third wafer element further comprises at least one transistor and at least one metal-insulator-metal element disposed on the metal layer element, the metal-insulator-metal element electrically contacting the transistor, wherein the transistor is a three-dimensional transistor or a planar transistor.

[0006] According to some embodiments, a wafer stack is provided, the wafer stack comprising a first wafer element having a front side and a back side. The wafer stack also comprises a second wafer element having a front side and a back side, such that the front side of the second wafer element is bonded to the front side of the first wafer element. In addition, the wafer stack comprises a third wafer element having a front side and a back side, such that the front side of the third wafer element is bonded to the back side of the second wafer element. The second wafer element comprises a substrate having a front side layer and a back side layer located between the front side and the back side of the substrate, a front side dielectric layer disposed on the substrate, and a back side dielectric layer disposed on the substrate. At least one metal layer element is disposed in the front side dielectric layer, and at least one metal layer element is disposed in the back side dielectric layer. The second wafer element comprises at least one through hole and at least one transistor, the through hole contacts at least one front side metal layer element and at least one back side metal layer element through the substrate, and the transistor is located on the back side layer of the substrate and contacts the metal layer element disposed in the back side dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a cross-sectional view of a CMOS image sensor device wafer stack according to a first embodiment;

[0009] Figures 2A to 2M is a simplified cross-sectional diagram of a process flow for manufacturing a CMOS image sensor device wafer stack according to some embodiments;

[0010] FIG. 3A to FIG. 3I A simplified cross-sectional process flow for forming a planar transistor according to an example embodiment;

[0011] Figure 4 is a cross-sectional view of a CMOS image sensor device wafer stack according to a second embodiment;

[0012] FIG. 5A to FIG. 5I To form for Figure 4 A simplified cross-sectional process flow diagram of a three-dimensional transistor in a second embodiment;

[0013] FIG. 6A to FIG. 6B For use Figure 4 A simplified cross-sectional view and a top view of a three-dimensional transistor in a second embodiment;

[0014] Figure 7 is a cross-sectional view of a CMOS image sensor device wafer stack according to a third embodiment;

[0015] FIG. 8A to FIG. 8I To form for Figure 7 A simplified cross-sectional process flow diagram of a three-dimensional transistor in a third embodiment of the present invention;

[0016] FIG. 9A to FIG. 9B For use Figure 7 A simplified cross-sectional view and a top view of a three-dimensional transistor in a third embodiment of the present invention;

[0017] Fig.10 is a cross-sectional view of a CMOS image sensor device wafer stack according to a fourth embodiment;

[0018] Fig.11 For use Fig.10 A simplified cross-sectional view of a 1T1C element in a fourth embodiment of the present invention;

[0019] Fig.12 is a cross-sectional view of a CMOS image sensor device wafer stack according to a fifth embodiment;

[0020] Fig.13 For use Fig.12 A simplified cross-sectional view of a 1T1C element in a fifth embodiment of the present invention;

[0021] Fig.14 is a cross-sectional view of a CMOS image sensor device wafer stack according to a sixth embodiment;

[0022] Fig.15 For use Fig.14 A simplified cross-sectional view of a 1T1C element in a sixth embodiment of the present invention;

[0023] Fig.16A is an illustration of pixel-level hybrid bonding (PLHB) of wafer stacking according to some embodiments;

[0024] Fig. 16B is an illustration of column-level hybrid bonding (CLHB) for wafer stacking according to some embodiments;

[0025] FIG. 17A to FIG. 17C is an illustration of a hybrid bonding type used in wafer stacking according to some embodiments;

[0026] Fig.18A For use according to some embodiments FIG. 17A to FIG. 17C A description of a PLHB engagement of one of the hybrid engagement types;

[0027] Fig.18B For use according to some embodiments FIG. 17A to FIG. 17C a description of a PLHB engagement of another of the hybrid engagement types;

[0028] Fig.19 is an illustration of various configurations of PLHB and CLHB wafer stack bonding according to some embodiments;

[0029] Fig. 20 A flowchart for illustrating a method for manufacturing a wafer stack according to one embodiment;

[0030] Fig.21 A flow chart illustrating a method for manufacturing a wafer stack according to one embodiment.

[0031]

Explanation of symbols

[0032] 100,400,700,1000,1200,1400: Wafer stacking

[0033] 102: first SOC wafer component / SOC wafer component / first wafer component

[0034] 104: first ASIC wafer component / second wafer component

[0035] 106: Second ASIC wafer component / third wafer component

[0036] 108: First SOC wafer front side

[0037] 110: First SOC wafer back side

[0038] 112: First ASIC wafer front side

[0039] 114: First ASIC wafer back side

[0040] 116: Second ASIC wafer front side

[0041] 118: Second ASIC wafer back side

[0042] 120:SOC substrate

[0043] 122: Dielectric layer

[0044] 124: Anchor layer

[0045] 126: Composite Metal Mesh

[0046] 128A, 128B, 128C, 188A, 188B, 188C, 188D, 188E, 222A, 222B, 222C, 222D, 222E, 222F, 240A, 240B, 240C, 240D: first metal layer components

[0047] 130A, 130B, 130C, 190A, 190B, 190C, 190D, 242A, 242B, 242C, 242D: Second metal layer components

[0048] 132A, 132B, 132C, 192A, 192B, 192C, 192D, 192E, 192F, 192G, 224A, 224B, 224C, 224D, 224E, 224F, 224G, 224H, 224I, 224J, 224K, 224L, 244A, 244B, 244C, 244D, 708A~708H, 728A, 728B, 728C, 728D, 728E, 728F, 728G, 728H, 738A, 738B, 738C, 738D, 738E, 738F, 738G, 738H: First through hole

[0049] 134A, 134B, 134C, 194A, 194B, 194C, 246A, 246B, 246C: Third metal layer components

[0050] 136A, 136B, 136C, 196A, 196B, 196C, 196D, 228A, 228B, 228C, 228D, 228E, 228F, 248A, 248B, 248C: Second through hole

[0051] 138A, 138B, 138C, 198A, 198B, 198C, 226A, 226B, 226C, 226D, 226E, 226F, 250A, 250B, 250C, 250D, 250E, 250F: Top metal layer components

[0052] 140A, 140B, 140C, 200A, 200B, 200C, 252A, 252B, 252C, 252D: Third through hole

[0053] 142A, 142B, 142C, 202A, 202B, 202C, 229A, 229B, 229C, 229D, 229E, 229F, 254A, 254B, 254C, 706A~706H, 726A, 726B, 726C, 726D, 726E, 726F, 726G, 726H, 736A, 736B, 736C, 736D, 736E, 736F, 736G, 736H: Metal-insulator-metal element

[0054] 144A, 144B, 144C, 204A, 204B, 204C, 256A, 256B, 256C: fourth through hole

[0055] 146A,146B,146C,206A,206B,206C,230A,230B,230C,230D,230E,230F:

[0056] Redistribution (RDL) components

[0057] 148,208,232,260: Anchor pad

[0058] 150,210,262: Contact

[0059] 152: Polycrystalline gate

[0060] 154,214,266: Mixed cloth plants

[0061] 156A,216A,268A,326B,356B,370B: Drain

[0062] 156B,216B,268B,326A,356A,370A: Source

[0063] 158:STI

[0064] 160: Boron IMP

[0065] 162: Backside deep trench isolation element

[0066] 164: Lower grid element

[0067] 166: Upper grid element

[0068] 168: Photodiode

[0069] 170: First ASIC wafer substrate

[0070] 172: front side layer

[0071] 174: Silicon on Insulator

[0072] 176: Dorsal layer

[0073] 178: front dielectric layer

[0074] 180: Back side dielectric layer

[0075] 182: Oxide layer

[0076] 184: front anchoring layer

[0077] 186: Dorsal anchoring layer

[0078] 212,264: Gate element

[0079] 218: Large Through Silicon Via (BTSV)

[0080] 220A, 220B, 220C, 220D, 220E, 220F, 701A, 701B, 702A, 702B, 702C, 702D, 702E, 702F, 702G, 702H, 704A, 704B, 704C: Planar transistors

[0081] 234: Second ASIC wafer substrate

[0082] 236: Second ASIC dielectric layer

[0083] 238: Second ASIC anchor layer

[0084] 258A, 258B, 258C, 258D, 258E, 258F: redistribution layer components

[0085] 300: Device wafer

[0086] 302: Carrier wafer

[0087] 304: Device wafer substrate

[0088] 306: Device wafer SiGe EPI layer

[0089] 308:Si EPI layer

[0090] 310: Carrier wafer substrate

[0091] 312: Carrier wafer SiGe EPI layer

[0092] 314: Carrier wafer Si EPI layer

[0093] 316,318:SiO2 layer

[0094] 320,350,376: Gate

[0095] 322,352,374:HK film

[0096] 324,354,372:IGZO channel

[0097] 328,358,378: Contact path

[0098] 402A, 402B, 402C, 402D, 402E, 402F, 720A, 720B, 722A, 722B, 722C, 722D, 722E, 722F, 722G, 722H, 724A, 724B, 724C, 730A, 730B, 732A, 732B, 732C, 732D, 732E, 732F, 732G, 732H: Three-dimensional transistor

[0099] 734A~734C: Combination transistor

[0100] 1600: Photodiode area

[0101] 1602: Surrounding Area

[0102] 1604: Mixed joint

[0103] 2000,2100:Flowchart

[0104] S100,S102,S104,S106,S108,S110,S112,S114,S116,S118,S120,S122,S124,S1 26,S128,S130,S132,S134,S136,S138,S140,S200,S202,S204,S206,S208,S210:

[0105] step DETAILED DESCRIPTION

[0106] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. The specific examples of the components and configurations described below are for simplifying the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0107] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0108] The term "about" can be used to include any numerical value that can vary without changing the basic function of the value. When used with a range, "about" also discloses a range defined by the absolute values ​​of the two endpoints, for example, "about 2 to about 4" also discloses a range of "from 2 to 4". The term "about" can refer to plus or minus 10% of the indicated number.

[0109] The present disclosure relates to structures composed of different layers. When the terms "on" or "over" are used in reference to two different layers (including a substrate), these terms simply indicate that one layer is on or above another layer. These terms do not require that the two layers are in direct contact with each other, and allow other layers to be between the two layers. For example, all layers of a structure may be considered to be "on" a substrate, even if they are not all in direct contact with the substrate. The term "directly" may be used to indicate that two layers are in direct contact with each other without any layers in between. In addition, depending on the context, when it is mentioned that a process step is performed on a substrate, this should be interpreted as also performing such a step on any layer that may be present on the substrate.

[0110] As semiconductor technology has further advanced, stacked semiconductor devices have become an effective alternative for further reducing the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic, memory, processor circuits, and the like are manufactured on different semiconductor wafers. Two or more semiconductor wafers may be mounted one on top of another to further reduce the form factor of the semiconductor device.

[0111] The two semiconductor wafers may be bonded together via a suitable bonding technique. Suitable bonding techniques may include, for example, but not limited to, direct bonding, chemical activation bonding, plasma activation bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermocompression bonding, reaction bonding, hybrid bonding, and the like. Once the two semiconductor wafers are bonded together, the interface between the two semiconductor wafers may provide a conductive path between the stacked semiconductor wafers.

[0112] One advantageous feature of stacked semiconductor devices is that much higher density can be achieved by using stacked semiconductor devices. In addition, stacked semiconductor devices can achieve smaller form factors, cost-effectiveness, enhanced performance and lower power consumption. For example, a complementary metal oxide semiconductor (CMOS) image sensor (CIS) device may include multiple pixel regions configured on or within a substrate. Each pixel region includes an image sensing component, such as a photodiode, for receiving incident light including photons. The pixel regions can be separated from each other by a deep trench isolation (DTI) structure to improve the quantum efficiency of the CIS. This CIS can utilize a system on chip (SOC) wafer stacked on an application specific integrated circuit (ASIC) wafer. As the complexity increases, the requirements for CIS devices increase, and additional features also increase. According to some embodiments disclosed herein, a CIS device is provided that utilizes three or more stacked wafer elements to provide, among other advantages, enhanced processing capabilities, data storage (i.e., memory), and the like. In such embodiments, the CIS device may utilize, for example, one SOC wafer and two ASIC wafers or two SOC wafers and one ASIC wafer in combination. In addition, each wafer may include a Metal-Insulator-Metal (MIM) as a capacitor and a control node to form a single transistor / single capacitor element, i.e., 1T1C. According to one embodiment, by using a silicon on insulator (SOI) substrate, the middle wafer may include a front-side transistor array and a back-side transistor array. In one embodiment, the backside transistor array may include a vertical 3D transistor array (three-dimensional thin film transistor of indium-gallium-zinc-oxygen InGaZnO (3D TFTIGZO) with FinFET structure) for backside bias and current driving.

[0113] Now turn Figure 1 , provides a cross-sectional view of a CIS device wafer stack 100 according to one embodiment of the present disclosure. Figure 1As shown in FIG. 1 , the CIS device wafer stack 100 includes a first SOC wafer element 102, a first ASIC wafer element 104, and a second ASIC wafer element 106. It should be understood that the CIS device wafer stack 100 is a representative but non-limiting example of one possible implementation of the systems and methods described herein. Figure 1 As illustrated in FIG. 1 , the first SOC wafer element 102 includes a first SOC wafer front side 108 and a first SOC wafer back side 110. The first ASIC wafer element 104 includes a first ASIC wafer front side 112 and a first ASIC wafer back side 114. Similarly, the second ASIC wafer element 106 includes a second ASIC wafer front side 116 and a second ASIC wafer back side 118. Figure 1 In the embodiment of the present invention, the first SOC wafer front side 108 is bonded to the first ASIC wafer front side 112, and the first ASIC wafer back side 114 is bonded to the second ASIC wafer front side 116. According to some embodiments, variations of wafer stacking are contemplated herein, namely, Figure 1 The front / back side joint described in Figure 1 The description of the order in is intended only as an example of such an order of wafer stacking. Furthermore, it should be understood that the wafer stack 100 may include a single ASIC wafer element and two SOC wafer elements, three SOC wafer elements, three ASIC wafer elements, or four or more wafer elements utilizing connectivity, layout, features, and bonding as described herein. In practice, various components may be added to and / or omitted from the wafer stack 100, and the embodiments disclosed herein are not intended to be limited to any particular embodiment. Figure 1 The limitations of the content shown in .

[0114] According to some embodiments, the first ASIC wafer component 104, described in more detail below, may include, for example, but not limited to, logic circuitry, an analog-to-digital converter (ADC), an image signal processor (ISP), and the like. The second ASIC wafer component 106, described in more detail below, may include, for example, but not limited to, logic circuitry, an image signal processor (ISP), an analog-to-digital converter (ADC), and the like.

[0115] exist Figure 1In the example embodiment depicted in , the first SOC wafer element 102 includes a SOC substrate 120, a dielectric layer 122, and an anchoring layer 124. In some embodiments, the SOC substrate 120 may be implemented as a semiconductor material. Such materials may include silicon, for example, but not limited to, silicon in the form of crystalline Si or polycrystalline Si. In alternative embodiments, the substrate may be made of other elemental semiconductors such as germanium, or may include compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, or other suitable substrate materials. In a specific embodiment, the SOC substrate 120 is silicon.

[0116] like Figure 1 As described in the drawings, the dielectric layer 122 may include an insulating material such as silicon dioxide (SiO2) or silicon nitride (SiN), silicon oxynitride (SiON), fluorine-doped silicate glass or other dielectric materials. It should be understood that the aforementioned anchor layer 124 may be implemented as a suitable dielectric material, including, for example but not limited to, SiN, oxide, SiO x F y C z N a , polymer, resin, low-K material, high-K material or any related insulating layer. In some embodiments, the dielectric layer 122 and the anchor layer 124 can be implemented as the same or different materials.

[0117] The dielectric layer 122 of the SOC wafer component 102 is Figure 11 and 12. The dielectric layer 122 is depicted as including one or more first metal layer elements 128A, 128B, 128C. One or more second metal layer elements 130A, 130B, 130C are disposed in the dielectric layer 122, and these second metal layer elements 130A, 130B, 130C are electrically connected to the respective first metal layer elements 128A, 128B, 128C through respective first vias 132A, 132B, 132C. It should be understood that such first vias 132A-132C can be made of suitable conductive materials, which include, for example but not limited to copper, copper alloys, aluminum, aluminum alloys, and the like. The SOC wafer component 102 further includes one or more third metal layer components 134A, 134B, 134C disposed in the dielectric layer 122 and electrically connected to the respective one or more second metal layer components 130A, 130B, 130C through respective second vias 136A, 136B, 136C. It should be understood that such second vias 136A-136C can be made of suitable conductive materials, which conductive materials include, for example but not limited to copper, copper alloys, aluminum, aluminum alloys, and the like. The one or more third metal layer components 134A, 134B, 134C are connected to the respective one or more top metal layer components 138A, 138B, 138C through respective third vias 140A, 140B, 140C. According to some embodiments, the third vias 140A- 140C may be made of a suitable conductive material, including, for example but not limited to, copper, copper alloy, aluminum, aluminum alloy, metal, metal alloy, or the like.

[0118] One or more top metal layer elements 138A, 138B, 138C are Figure 1 144A, 144B, and 144C are electrically connected to suitable metal-insulator-metal (MIM) elements 142A, 142B, and 142C, and the metal-insulator-metal elements 142A, 142B, and 142C are respectively coupled to the second metal layer elements 130A, 130B, and 130C. In some embodiments, as Figure 1 As shown in FIG. 1 , redistribution layer (RDL) elements 146A, 146B, 146C are electrically connected to respective top metal elements 138A, 138B, 138C, and RDL elements 146A-146C extend through SOC anchor layer 124. In some embodiments, metal layer elements 128A-128C, 130A-130C, 134A-134C, and 138A-138C may be made of copper, copper alloys, aluminum, aluminum alloys, or other conductive materials.

[0119] like Figure 1, the SOC wafer component 102 includes one or more anchor pads 148 in or on the anchor layer 124 on the front side 108. The anchor pads 148 may be implemented, for example but not limited to, copper, copper alloy, aluminum, aluminum alloy, metal, metal alloy, etc. to provide one or more connection or attachment points between the SOC wafer component 102 and / or the first ASIC wafer component 104.

[0120] The back side 110 of the first SOC wafer element 102 (i.e., the side of the SOC substrate 120 depicted as the top of the CIS device wafer stack 100) includes a composite metal grid 126 extending vertically from the SOC substrate 120. It should be appreciated that the back side 110 of the SOC wafer element 102 may include a variety of components. Figure 1 In the exemplary embodiment of , the SOC wafer component 102 includes one or more photodiodes 168. In particular, each photodiode 168, generally represented by a box on the back side 110 of the SOC wafer component 102, includes a contact 150 that electrically couples the photodiode 168 to the first metal layer components 128A-128C. Figure 1 As shown in FIG. 1 , the contact 150 is coupled to the poly gate 152, the hybrid plant 154, the drain 156A, and the source 156B. In addition, the photodiode 168 may include the STI 158, the boron IMP 160, the backside deep trench isolation (BDTI) element 162, and a portion of the composite metal grid 126. Figure 1 , the composite metal mesh 126 includes a lower mesh element 164 and an upper mesh element 166. According to some embodiments, the lower mesh element 164 may be implemented as, for example, but not limited to, a tungsten component, and the upper mesh element 166 may be implemented as, for example, but not limited to, an oxide component.

[0121] Figure 1 The first ASIC wafer element 104 depicted in FIG. 1 includes a first ASIC wafer substrate 170 including one or more layers. Figure 1 In an example embodiment of the present invention, substrate 170 includes a front side layer 172, a silicon-on-insulator (SOI) layer 174, and a back side layer 176. According to some embodiments, front side layer 172 and back side layer 176 may include, for example but not limited to, non-low-k dielectric materials such as silicon oxide, silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), or the like. Figure 1 In the description of FIG. 1 , the SOI layer 174 may include, for example but not limited to, silicon oxide or other suitable insulating materials. Figure 1As shown in FIG. 1 , the first ASIC wafer component 104 may be implemented using components (ie, functionality) formed on the front side 112 and the back side 114 of the component 104. Figure 1 As described in , the fabrication of the elements may be constructed on the front side layer 172 and the back side layer 176 of the substrate 170, wherein the elements formed on the front side layer 172 and the back side layer 176 are electrically connected between the front side 112 and the back side 114 using Big Through Silicon Via (BTSV) 218 ​​(i.e., a big silicon via extending through the entire substrate 170 (e.g., the front side layer 172, the SOI layer 174, and the back side layer 176)), thereby achieving connectivity between the elements disposed in the front side layer 172 and the elements disposed in the back side layer 176. It should be understood that such BTSV 218 may be made of a suitable conductive material, which includes, for example, but not limited to, copper, copper alloys, aluminum, aluminum alloys, and the like.

[0122] The front side 112 of the first ASIC wafer component 104 further includes a front side dielectric layer 178 formed on the front side layer 172 of the substrate 170. The back side 114 of the first ASIC wafer component 104 includes a back side dielectric layer 180 deposited on the back side layer 176 of the substrate 170. Figure 1 As described in the foregoing, an oxide layer 182 may be formed on the backside layer 176 of the substrate 170. In some embodiments, the oxide layer 182 may include, for example but not limited to, an aluminum oxide layer (e.g., Al2O3) or the like. The first ASIC wafer element 104 may further include a front-side anchoring layer 184 formed on the front-side dielectric layer 178 and a back-side anchoring layer 186 formed on the back-side dielectric layer 180. It should be understood that the aforementioned anchoring layers 184-186 may be implemented as suitable dielectric materials, including, for example but not limited to, SiN, oxide, SiO x F y C z N a , polymers, resins, low-K materials, high-K materials or any related insulating layers.

[0123] The front side dielectric layer 178 of the first ASIC wafer element 104 is Figure 1188A, 188B, 188C, 188D, and 188E. The first ASIC wafer element 104 further includes one or more second metal layer elements 190A, 190B, 190C, and 190D disposed in the front side dielectric layer 178 and electrically connected to the respective first metal layer elements 188A, 188B, 188C, 188D, 188E through first vias 192A, 192B, 192C, 192D, 192E, 192F, 192G. It should be understood that such first vias 192A-192G may be made of a suitable conductive material including, for example, but not limited to, copper, copper alloys, aluminum, aluminum alloys, and the like. The first ASIC wafer element 104 further includes one or more third metal layer elements 194A, 194B, 194C disposed in the front side dielectric layer 178 and electrically connected to the respective one or more second metal layer elements 190A, 190B, 190C, 190D through respective second vias 196A, 196B, 196C, 196D. It should be understood that such second vias 196A-196D may be made of a suitable conductive material, which conductive material includes, for example but not limited to, copper, copper alloys, aluminum, aluminum alloys, and the like. The one or more third metal layer elements 194A, 194B, 194C are electrically connected to the respective one or more top metal layer elements 198A, 198B, 198C through respective third vias 200A, 200B, 200C. It should be understood that such third through holes 200A-200C can be made of suitable conductive materials, including, for example but not limited to, copper, copper alloys, aluminum, aluminum alloys, and the like. In some embodiments, the aforementioned metal layer elements 188A-188E, 190A-190D, and 194A-194C can be made of copper, copper alloys, aluminum, aluminum alloys, or other conductive materials.

[0124] One or more top metal layer elements 198A, 198B, 198C are Figure 1 2 is illustrated as being electrically connected to appropriate metal-insulator-metal (MIM) elements 202A, 202B, 202C via respective fourth vias 204A, 204B, and 204C, and the metal-insulator-metal elements 202A, 202B, 202C are coupled to the second metal layer elements 190A, 190C, and 190D, respectively. In some embodiments, as Figure 1 As shown in FIG. 1 , redistribution layer (RDL) elements 206A, 206B, 206C are electrically connected to respective top metal elements 198A, 198B, 198C, and RDL elements 206A-206C extend through the front side anchor layer 184. Figure 1As illustrated in , the first ASIC wafer element 104 includes one or more anchor pads 208 located in or on the front side anchor layer 184 .

[0125] In addition, if Figure 1 As shown in , the front side 112 of the first ASIC wafer element 104 may include one or more transistor gates or "devices", i.e., FinFET devices, GAA devices, HKMG devices, SiGe S / D devices, SOI devices, polycrystalline devices, doped polycrystalline devices, etc., which include contacts 210 coupling the gate element 212 to the first metal layer elements 188B-188D. These "devices" may be formed on or in the front side layer 172 of the first ASIC wafer substrate 170. As shown in Figure 1 As further described in FIG. 2 , it should be understood that such a “device” may include a gate element 212 , a hybrid plant 214 , a drain 216A, and a source 216B.

[0126] As briefly discussed above, the back side 114 of the first ASIC wafer element 104 includes a back side dielectric layer 180. Figure 1 The back side 114 of the first ASIC wafer element 104 depicted in FIG. 1 includes one or more transistors 220A, 220B, 220C, 220D, 220E, 220F formed on the oxide layer 182 of the back side layer 176 of the substrate 170. According to one embodiment, the transistors 220A-220F may be implemented as an array thereof, such as planar or three-dimensional transistors, thin film transistors, etc. According to one embodiment, the transistors 220A-220F may be implemented as TFT FinFET transistors or the like. FIG. 3A to FIG. 3I , FIG. 5A to FIG. 5I and FIG. 8A to FIG. 8I Variations and further discussion of transistors 220A-220F are provided in greater detail.

[0127] exist Figure 1 1 and 2, one or more first metal layer elements 222A, 222B, 222C, 222D, 222E, and 222F are illustrated in FIG. 1 . In some embodiments, one or more first metal layer elements 222A-222F are electrically connected to respective transistors 220A-220F through respective first vias 224A, 224B, 224C, 224D, 224E, 224F, 224G, 224H, 224I, 224J, 224K, and 224L. It should be understood that such first vias 224A-224L may be made of a suitable conductive material, including, for example, but not limited to, copper, copper alloys, aluminum, aluminum alloys, and the like. In some embodiments, the aforementioned metal layer elements 222A-222F may be made of copper, copper alloys, aluminum, aluminum alloys, or other conductive materials.

[0128] The first ASIC wafer element 104 further includes one or more top metal layer elements 226A, 226B, 226C, 226D, 226E, and 226F disposed in the backside dielectric layer 180 and electrically connected to the respective first metal layer elements 222A, 222B, 222C, 222D, 222E, and 222F through second vias 228A, 228B, 228C, 228D, 228E, and 228F. It should be understood that such second vias 228A-228F may be made of a suitable conductive material, including, for example, but not limited to, copper, copper alloys, aluminum, aluminum alloys, and the like. According to some embodiments, Figure 1 One or more top metal layer elements 226A~226F described in the figure can be electrically connected to respective metal-insulator-metal (MIM) elements 229A, 229B, 229C, 229D, 229E and 229F, and metal-insulator-metal elements 229A, 229B, 229C, 229D, 229E and 229F are respectively coupled to first metal layer elements 222A, 222B, 222C, 222D, 222E and 222F.

[0129] In some embodiments, redistribution layer (RDL) elements 230A, 230B, 230C, 230D, 230E, and 230F are electrically connected to respective top metal elements 226A, 226B, 226C, 226D, 226E, and 226F. Figure 1 As shown in FIG. 1 , RDL elements 230A- 230F extend through backside anchor layer 186. Figure 1 As illustrated in , the first ASIC wafer element 104 includes one or more anchor pads 232 located in or on the backside anchor layer 186 .

[0130] As shown, Figure 1 The CIS device wafer stack 100 may further include a third wafer element, namely, a second ASIC wafer element 106, bonded to the backside anchor layer 186. According to one embodiment, Figure 1 The second ASIC wafer component 106 depicted in the figure includes a second ASIC wafer substrate 234, which includes one or more layers. The second ASIC wafer component 106 further includes a second ASIC dielectric layer 236 formed on the substrate 234. The second ASIC wafer component 106 may further include a second ASIC anchoring layer 238 formed on the second ASIC dielectric layer 236. The aforementioned anchoring layer 238 may be implemented as a suitable dielectric material, including, for example but not limited to, SiN, oxide, SiOx F y C z N a , polymers, resins, low-K materials, high-K materials or any related insulating layers or the like.

[0131] The second ASIC dielectric layer 236 of the second ASIC wafer element 106 is Figure 1 2. The second ASIC wafer component 106 further includes one or more second metal layer elements 242A, 242B, 242C, and 242D disposed in the dielectric layer 236 and electrically connected to the respective first metal layer elements 240A, 240B, 240C, and 240D through first vias 244A, 244B, 244C, and 244D. It should be understood that such first vias 244A-244D may be made of a suitable conductive material, including, for example, but not limited to, copper, copper alloys, aluminum, aluminum alloys, and the like.

[0132] The second ASIC wafer component 106 further includes one or more third metal layer elements 246A, 246B, 246C disposed in the dielectric layer 236 and electrically connected to the respective one or more second metal layer elements 242A, 242C, 242D through respective second vias 248A, 248B, and 248C. It should be understood that such second vias 248A-248C may be made of a suitable conductive material, including, for example but not limited to, copper, copper alloys, aluminum, aluminum alloys, and the like. Figure 1 As described in FIG. 1 , the second ASIC wafer component 106 may further include one or more top metal layer components 250A, 250B, 250C, 250D, 250E, and 250F. Figure 1 As shown in FIG. 1 , one or more third metal layer elements 246A, 246B, 246C are electrically connected to respective top metal layer elements 250A, 250C, 250E, and 250F through respective third vias 252A, 252B, 252C, and 252D. It should be understood that such third vias 252A-252D may be made of suitable conductive materials, including, for example, but not limited to, copper, copper alloys, aluminum, aluminum alloys, and the like. In some embodiments, the aforementioned metal layer elements 240A-240D, 242A-242D, and 246A-246C may be made of copper, copper alloys, aluminum, aluminum alloys, or other conductive materials.

[0133] One or more of the top metal layer elements 250B, 250D, 250F are Figure 1250A, 250B, 250C, 250D, 250E, and 250F. In some embodiments, the top metal elements 250A, 250B, 250C, 250D, 250E, and 250F are electrically connected to the top metal elements 250A, 250B, 250C, 250D, 250E, and 250F via respective fourth vias 256A, 256B, and 256C. The MIM elements 254A, 254B, and 254C are coupled to the second metal layer elements 242B, 242C, and 242D, respectively. In some embodiments, the redistribution layer (RDL) elements 258A, 258B, 258C, 258D, 258E, and 258F are electrically connected to the respective top metal elements 250A, 250B, 250C, 250D, 250E, and 250F. In some embodiments, as Figure 1 As shown in FIG, RDL elements 258A-258F extend through the second ASIC anchor layer 238. Figure 1 As illustrated in , the second ASIC wafer element 106 includes one or more anchor pads 260 located in or on the second ASIC anchor layer 238 .

[0134] In addition, if Figure 1 As shown in , the second ASIC wafer component 106 may include one or more transistor gates or "devices", i.e., FinFET devices, GAA devices, HKMG devices, SiGe S / D devices, SOI devices, polycrystalline devices, doped polycrystalline devices, etc., and the one or more transistor gates or "devices" include contacts 262 that couple gate elements 264 to first metal layer elements 240A-240D. These "devices" may be formed on or in the second ASIC substrate 234. As shown in Figure 1 As further described in , it should be understood that such a "device" may include a gate element 264, a hybrid plant 266, a drain 268A and a source 268B.

[0135] Now turn Figures 2A to 2M , showing the manufacturing Figure 1 FIG. 1 is a cross-sectional view of the process flow of a CIS device wafer stack 100. It should be understood that Figures 2A to 2M A simplified view of a manufacturing process according to an example embodiment is shown and is intended only to illustrate and not to limit the methods and apparatus described herein. The simplified process begins with Figure 2A , which depicts a device wafer 300 and a carrier wafer 302. Figure 2A As shown in FIG. 1 , the device wafer 300 includes a device wafer substrate 304 , on which a device wafer SiGe EPI layer 306 and a Si EPI layer 308 are formed. Figure 2AThe carrier wafer 302 shown in FIG. 1 includes a carrier wafer substrate 310 on which a carrier wafer SiGe EPI layer 312 and a carrier wafer Si EPI layer 314 are formed. It should be understood that the device wafer 300 corresponds to the front side layer 172 of the first ASIC wafer substrate 170 after fabrication, and the carrier wafer 302 corresponds to the back side layer 176 of the first ASIC wafer substrate 170 after fabrication.

[0136] exist Figure 2B , each of the device wafer 300 and the carrier wafer 302 has a respective SiO2 layer 316 and 318 deposited on its respective Si EPI layer 308 and 314. Figure 2C As shown in FIG. 1 , oxide-oxide bonding is performed between the device wafer 300 and the carrier wafer 302. That is, the device wafer 300 is inverted, and the SiO2 layer 316 is bonded to the SiO2 layer 318 of the carrier wafer 302. Figure 2C As shown in FIG. , the bonded SiO2 layers 316 and 318 correspond to Figure 1 The SOI layer 172 of the first ASIC wafer substrate 170 is depicted in FIG. Figure 2D As shown in FIG. 3 , the device wafer 300 is etched, wherein the SiGe EPI layer 306 acts as an etch stop layer.

[0137] exist Figure 2E In the embodiment of the present invention, etching is performed to remove the SiGe EPI layer 306 from the device wafer 300. That is, the Si EPI layer 308 acts as an etch stop layer during the removal (ie, etching) of the SiGe EPI layer 306. It should be understood that, as shown in FIG. Figure 1 As shown in FIG. , the resulting device wafer 300 now reflects the front side layer 172 of the SOI 170. Thereafter, Figure 2F In the embodiment, a portion of the first ASIC wafer element 104 is formed on the front side layer 172 of the SOI 170. It should be understood that Figure 2F The intermediate device depicted in FIG. 1 illustrates the first ASIC FEOL / BEOL / RDL formation thereon.

[0138] exist Figure 2G middle, Figure 2F The intermediate device is then inverted and hybrid bonded (eg, a combination of oxide-oxide and metal-metal bonding) to the SOC wafer element 102. The process then continues to Figure 2H , and then the carrier wafer substrate 310 is removed (ie, etched) using the carrier wafer SiGe EPI layer 312 as an etch stop layer. Fig.2I As shown in FIG. 3 , a SiGe etch is then performed to remove the SiGe EPI layer 312 . Figure 2JThe following steps of forming the low temperature IGZO transistor array 220A-220F on the oxide layer 182, forming various metal layer components, RDL components, MIM components, etc., and finalizing the first ASIC wafer component 104 are described. That is, both the front side 112 and the back side 114 of the first ASIC wafer component 104 are now Figure 2J The following is an explanation of FIG. 3A to FIG. 3I A discussion and description of the aforementioned IGZO transistor is provided. Figure 2K As shown in FIG. 1 , the second ASIC wafer element 106 is then bonded to the back side 114 of the first ASIC wafer element 104 and the combined wafer stack is inverted, placing the back side 110 of the ASIC wafer element 102 at the top of the page. Figure 2L As discussed in , the wafer stack is flipped over to enable further processing on the SOC wafer element 102 .

[0139] exist Figure 2L In the embodiment, the back side 110 of the SOC wafer element 102 (ie, the SOC substrate 120) is thinned as shown. It should be understood that in some embodiments, CMP or other mechanical or chemical methods are used to thin the SOC substrate 120. Thereafter, in Figure 2M In the process, metal gate formation is performed, that is, composite metal grid 126 and associated elements are formed. Although not shown, it should be understood that in Figure 2M Thereafter, individual dies or chips may then be separated from the wafer stack.

[0140] Now turn FIG. 3A to FIG. 3I , showing the formation of a Figures 1 to 2M A simplified cross-sectional process flow diagram of the planar transistors 220A-220F of FIG. The process begins at Figure 3A , then the oxide layer 182 is deposited on the back side layer 176 of the SOI substrate 170, that is, deposited on the back side layer 176 of the SOI substrate 170. Figures 2A to 2M 3. In some embodiments, the oxide layer 182 may include, for example but not limited to, an aluminum oxide layer (eg, Al2O3) or the like. Figure 3B In the embodiment, a gate 320 is formed on the oxide layer 182. That is, Figure 3B Results of depositing gate material (eg, TiN or similar), photoresist, patterning, etching, photoresist removal, etc. are illustrated.

[0141] like Figure 3C As described in , a HK film 322 is then formed on each gate 320. In some embodiments, the formation of the HK film 322 may include, for example but not limited to, depositing a HK material (such as HfO2 or the like) on the gate 320, followed by photoresist application, patterning, etching, photoresist removal, etc. Figure 3D As shown in FIG. 3 , an IGZO channel 324 is then formed on the HK film 322 and the gate 320. According to some embodiments, the formation of the IGZO channel 324 may include, for example but not limited to, depositing an IGZO material on the HK film 322, followed by photoresist application, patterning, etching, photoresist removal, etc.

[0142] exist Figure 3E In the embodiment, a source 326A and a drain 326B are formed on the IGZO channel 324, thereby completing Figures 1 to 2M According to some embodiments, the formation of source 326A and drain 326B may include, for example but not limited to, deposition of source / drain material (such as TiN or the like), photoresist, patterning, etching, photoresist removal, etc. Figure 3F In the embodiment of the present invention, a dielectric layer 180 (ie, an oxide layer or other insulating layer) is deposited on the back side 114 of the first ASIC wafer component 104 .

[0143] Then proceed to the contact point (ie, Figure 1 The etching of the first through holes 224A to 224L is performed. Figure 3G An illustration of a contact path 328 formed through the backside dielectric layer 180 is provided. It should be understood that the formation of such a contact path 328 may include, for example, but not limited to, photoresist application, patterning, etching, and photoresist removal. Thereafter, as Figure 3H As shown in , metal wiring is applied to ultimately form the back side 114 of the first ASIC wafer element 104. According to one embodiment, as Fig. 3I As shown in FIG. 1 , one or more MIM elements 229A- 229F may be located between metal wirings, that is, between metal layer elements.

[0144] Now turn Figure 4 , as discussed in more detail below, shows a CIS device wafer stack 400 according to a second embodiment, wherein Figure 1 The planar transistors 220A-220F are replaced by three-dimensional transistors. That is, Figure 4 Provides similar Figure 1 FIG. 4 is a cross-sectional view of a CIS wafer stack 400 of the wafer stack 100. Figure 4 As shown in FIG. 4 , the wafer stack 400 includes a first SOC wafer element 102, a first ASIC wafer element 104, and a second ASIC wafer element 106. Figure 4 As described in the first SOC wafer component 102 and the second ASIC wafer component 106 and Figure 1Therefore, the various components described above with respect to the first SOC wafer component 102 and the second ASIC wafer component 106 are applicable to Figure 4 .

[0145] Figure 4 The first ASIC wafer element 104 shown in FIG. 1 utilizes an array of three-dimensional transistors 402A, 402B, 402C, 402D, 402E, and 402F to replace the planar transistors 220A-220F. Figure 4 The back side 114 of the first ASIC wafer element 104 depicted in FIG. 1 includes one or more transistors 402A, 402B, 402C, 402D, 402E, and 402F formed on the oxide layer 182 of the back side layer 176 of the substrate 170. According to one embodiment, the transistors 402A-402F may be implemented as an array thereof. Figure 4 In an exemplary embodiment of the present invention, transistors 402A-402F are three-dimensional transistors, such as (for example but not limited to) as thin film transistors. According to one embodiment, transistors 402A-402F may be implemented as three-dimensional TFT FinFET transistors or the like. In this embodiment, the three-dimensional TFT FinFET transistor may be a three-dimensional TFT FinFET transistor using a gate (TiN), a source / drain (TiN), a high-K dielectric film (HfO x ) and IGZO channel (InGaZnO) 3D TFT IGZO transistor.

[0146] Below about FIG. 5A to FIG. 6B The formation of three-dimensional transistors 402A-402F is described in more detail. FIG. 5A to FIG. 5I , showing a method for forming a Figure 4 A simplified cross-sectional process flow diagram of three-dimensional transistors 402A-402F in a CIS device wafer stack 400 is shown. The process begins at Figure 5A , then the oxide layer 182 is deposited on the back side layer 176 of the SOI substrate 170, that is, deposited on the back side layer 176 of the SOI substrate 170. Figures 2A to 2M 3. In some embodiments, the oxide layer 182 may include, for example but not limited to, an aluminum oxide layer (eg, Al2O3) or the like. Figure 5B In the embodiment, a gate 350 is formed on the oxide layer 182. That is, Figure 5B Results of depositing gate material (eg, TiN or similar), photoresist, patterning, etching, photoresist removal, etc. are illustrated.

[0147] like Figure 5CAs described in , a HK film 352 is then formed on each gate 350. In some embodiments, the formation of the HK film 352 may include, for example but not limited to, depositing a HK material (such as HfO2 or the like) on the gate 350, followed by photoresist application, patterning, etching, photoresist removal, etc. Figure 5D As shown in FIG. 3 , an IGZO channel 354 is then formed on the HK film 352 and the gate 350. According to some embodiments, the formation of the IGZO channel 354 may include, for example but not limited to, depositing an IGZO material on the HK film 352, followed by photoresist application, patterning, etching, photoresist removal, etc.

[0148] exist Figure 5E In the embodiment, a source 356A and a drain 356B are formed on the IGZO channel 354, thereby completing Figure 4 According to some embodiments, the formation of the source 356A and the drain 356B may include, for example but not limited to, deposition of source / drain material (such as TiN or the like), photoresist, patterning, etching, photoresist removal, etc. Fig. 5F In the embodiment of the present invention, a dielectric layer 180 (ie, an oxide layer or other insulating layer) is deposited on the back side 114 of the first ASIC wafer component 104 .

[0149] Then proceed to the contact point (ie, Figure 4 The etching of the first through holes 224A to 224L is performed. Figure 5G An illustration of a contact path 358 formed through the backside dielectric layer 180 is provided. It should be appreciated that the formation of such a contact path 358 may include, for example, but not limited to, photoresist application, patterning, etching, and photoresist removal. Thereafter, as Figure 5H As shown in FIG. 1 , metal wiring is applied to ultimately form the back side 114 of the first ASIC wafer element 104 . Fig.5I Another embodiment is described in which one or more MIM elements 229A-229F may be located between metal wirings, ie, between metal layer elements.

[0150] Reference Fig. 6A and Figure 6B , respectively, showing the Figures 4 to 5I A schematic cross-sectional view of three-dimensional transistors 402A-402F in a CIS device wafer stack 400 ( Fig. 6A ) and top view ( Figure 6B ).exist Fig. 6A and Figure 6B , a gate 350, a HK film 352, an IGZO channel 354, a source 356A, and a drain 356B of each three-dimensional transistor 402A-402F are shown.

[0151] Now turn Figure 7 , as discussed in more detail below, shows a CIS device wafer stack 700 according to a third embodiment, wherein Figure 1 Planar transistors 220A to 220F or Figure 4 The three-dimensional transistors 402A-402F are replaced by alternative three-dimensional transistors. That is, Figure 7 Provides similar Figure 1 Wafer stacking 100 and Figure 4 FIG. 4 is a schematic cross-sectional view of a CIS wafer stack 400 and a CIS wafer stack 700. Figure 7 As shown in FIG. 7 , the wafer stack 700 includes a first SOC wafer element 102, a first ASIC wafer element 104, and a second ASIC wafer element 106. Figure 7 As described in the first SOC wafer component 102 and the second ASIC wafer component 106 and Figure 1 and Figure 4 Therefore, the various components described above with respect to the first SOC wafer component 102 and the second ASIC wafer component 106 are applicable to Figure 7 .

[0152] Figure 7 The first ASIC wafer element 104 shown in FIG. 1 is replaced by an array of three-dimensional transistors 702A, 702B, 702C, 702D, 702E and 702F. Figure 1 Planar transistors 220A to 220F and Figure 4 Therefore, if Figure 7 As depicted in FIG. 1 , the back side 114 of the first ASIC wafer element 104 includes one or more transistors 702A, 702B, 702C, 702D, 702E, and 702F formed on the oxide layer 182 of the back side layer 176 of the substrate 170. According to one embodiment, the three-dimensional transistors 702A-702F may be implemented as an array thereof. Figure 7 In an exemplary embodiment of the present invention, transistors 702A-702F are three-dimensional transistors, such as (for example but not limited to) as thin film transistors. According to one embodiment, transistors 702A-702F may be implemented as three-dimensional TFT FinFET transistors or the like. In this embodiment, the three-dimensional TFT FinFET transistors may be a three-dimensional TFT FinFET transistor using a gate (TiN), a source / drain (TiN), a high-K dielectric film (HfO x ) and IGZO channel (InGaZnO) 3D TFT IGZO transistor.

[0153] Below about FIG. 8A to FIG. 9B The formation of three-dimensional transistors 702A-702F is described in more detail. FIG. 8A to FIG. 8I , showing a method for forming a Figure 7 A simplified cross-sectional process flow diagram of three-dimensional transistors 702A-702F in a CIS device wafer stack 700. The process begins at Fig. 8A , then the oxide layer 182 is deposited on the back side layer 176 of the SOI substrate 170, that is, deposited on the back side layer 176 of the SOI substrate 170. Figures 2A to 2M 3. In some embodiments, the oxide layer 182 may include, for example but not limited to, an aluminum oxide layer (eg, Al2O3) or the like. Figure 8B In the embodiment, a source 370A and a drain 370B are formed on the oxide layer 182. That is, Figure 8B Results of depositing source / drain material (eg, TiN or similar), photoresist, patterning, etching, photoresist removal, etc. are illustrated.

[0154] like Figure 8C As shown in , an IGZO channel 372 is then formed on the source 370A and the drain 370B. According to some embodiments, the formation of the IGZO channel 372 may include, for example but not limited to, depositing IGZO material on the source / drain 370A-370B, followed by photoresist application, patterning, etching, photoresist removal, etc. Fig.8D , then a HK film 374 is formed on each source / drain 370A-370B. In some embodiments, the formation of the HK film 352 may include, for example but not limited to, depositing a HK material (such as HfO2 or the like) on the source / drain 370A-370B, followed by photoresist application, patterning, etching, photoresist removal, etc.

[0155] exist Fig. 8E In the embodiment, a gate 376 is formed on the HK film 374, thereby completing the fabrication of the three-dimensional transistors 702A-702F depicted in FIGS. 5A-5I. According to some embodiments, the formation of the gate 376 may include, for example but not limited to, deposition of source / drain material (such as TiN or the like), photoresist, patterning, etching, photoresist removal, etc. Fig.8F In the embodiment of the present invention, a dielectric layer 180 (ie, an oxide layer or other insulating layer) is deposited on the back side 114 of the first ASIC wafer component 104 .

[0156] Then proceed to the contact point (ie, Figure 7 The etching of the first through holes 224A to 224L is performed. Figure 8G An illustration of a contact path 378 formed through the backside dielectric layer 180 is provided. It should be understood that the formation of such a contact path 378 may include, for example, but not limited to, photoresist application, patterning, etching, and photoresist removal. Thereafter, as Figure 8HAs shown in , metal wiring is applied to ultimately form the back side 114 of the first ASIC wafer element 104. According to one embodiment, as Figure 8I As shown in FIG. 1 , one or more MIM elements 229A- 229F may be located between metal wirings, that is, between metal layer elements.

[0157] Reference Fig. 9A and Fig. 9B , respectively, showing the Figures 7 to 8I Schematic diagram of a cross-section of three-dimensional transistors 702A-702F in a CIS device wafer stack 700 ( Fig. 9A ) and top view ( Fig. 9B ).exist Fig. 9A and Fig. 9B , a gate 376, an HK film 374, an IGZO channel 372, a source 370A, and a drain 370B of each three-dimensional transistor 702A-702F are shown.

[0158] Now turn Fig.10 , provides a cross-sectional view of a CIS device wafer stack 1000 according to a fourth embodiment of the present disclosure, wherein Figure 1 , Figure 4 and Figure 7 In contrast to the single wafer element 104 discussed in , each wafer element 102, 104, and 106 of the CIS device wafer stack 1000 includes one or more planar transistors. Fig.10 As shown in FIG. 1 , the CIS device wafer stack 1000 includes a first SOC wafer element 102, a first ASIC wafer element 104, and a second ASIC wafer element 106. It should be understood that the CIS device wafer stack 1000 is a representative but non-limiting example of one possible implementation of the systems and methods described herein. Fig.10 As described in Figure 1 , Figure 4 and Figure 7 In the depicted embodiment, the first SOC wafer element 102 includes a first SOC wafer front side 108 and a first SOC wafer back side 110. The first ASIC wafer element 104 includes a first ASIC wafer front side 112 and a first ASIC wafer back side 114. Similarly, the second ASIC wafer element 106 includes a second ASIC wafer front side 116 and a second ASIC wafer back side 118. Fig.10 In the embodiment of the present invention, the first SOC wafer front side 108 is bonded to the first ASIC wafer front side 112, and the first ASIC wafer back side 114 is bonded to the second ASIC wafer front side 116. According to some embodiments, variations of wafer stacking are contemplated herein, namely, Fig.10 The front / back side joint described in Fig.10The description of the order in is intended only as an example of this order of wafer stacking. Furthermore, it should be understood that wafer stack 1000 may include a single ASIC wafer element and two SOC wafer elements, three SOC wafer elements, three ASIC wafer elements, or four or more wafer elements utilizing connectivity, layout, features, and bonding as described herein.

[0159] As discussed above, the first ASIC wafer component 104 may include, for example, but not limited to, logic circuitry, an analog-to-digital converter (ADC), an image signal processor (ISP), and the like. The second ASIC wafer component 106 may include, for example, but not limited to, logic circuitry, an image signal processor (ISP), an analog-to-digital converter (ADC), and the like.

[0160] exist Fig.10 In the example embodiment depicted in , the first SOC wafer element 102 includes a SOC substrate 120, a dielectric layer 122, and an anchoring layer 124. In some embodiments, the SOC substrate 120 may be implemented as a semiconductor material. Such materials may include silicon, for example, but not limited to, silicon in the form of crystalline Si or polycrystalline Si. In alternative embodiments, the substrate may be made of other elemental semiconductors such as germanium, or may include compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In a specific embodiment, the SOC substrate 120 is silicon.

[0161] like Fig.10 As described in the drawings, the dielectric layer 122 may include an insulating material such as silicon dioxide (SiO2) or silicon nitride (SiN), silicon oxynitride (SiON), fluorine-doped silicate glass or other dielectric materials. It should be understood that the aforementioned anchor layer 124 may be implemented as a suitable dielectric material, including, for example but not limited to, SiN, oxide, SiO x F y C z N a , polymer, resin, low-K material, high-K material or any related insulating layer. In some embodiments, the dielectric layer 122 and the anchor layer 124 can be implemented as the same or different materials.

[0162] The dielectric layer 122 of the SOC wafer component 102 is Figure 11 and 12. The dielectric layer 122 is depicted as including one or more first metal layer elements 128A, 128B, and 128C. One or more second metal layer elements 130A, 130B, 130C are disposed in the dielectric layer 122, and these second metal layer elements 130A, 130B, 130C are electrically connected to the respective first metal layer elements 128A, 128B, 128C through respective first vias 132A, 132B, 132C. It should be understood that such first vias 132A-132C can be made of suitable conductive materials, including, for example, but not limited to, copper, copper alloys, aluminum, aluminum alloys, and the like. The SOC wafer component 102 further includes one or more third metal layer components 134A, 134B, 134C disposed in the dielectric layer 122 and electrically connected to the respective one or more second metal layer components 130A, 130B, 130C through respective second vias 136A, 136B, 136C. It should be understood that such second vias 136A-136C can be made of suitable conductive materials, which conductive materials include, for example but not limited to copper, copper alloys, aluminum, aluminum alloys, and the like. The one or more third metal layer components 134A, 134B, 134C are connected to the respective one or more top metal layer components 138A, 138B, 138C through respective third vias 140A, 140B, 140C. According to some embodiments, the third vias 140A- 140C may be made of a suitable conductive material, including, for example but not limited to, copper, copper alloy, aluminum, aluminum alloy, metal, metal alloy, or the like.

[0163] Fig.10 The SOC wafer device 102 further illustrates one or more planar transistors 701A, 701B formed on respective first metal layer devices 128A and 128C. FIG. 3A to FIG. 3I The planar transistors 701A-701B are described in more detail. At least one of the source or drain of the planar transistors 701A-701B is electrically connected to suitable metal-insulator-metal (MIM) elements 142A and 142B, which are coupled to the top metal layer elements 138A and 138B via respective fourth vias 144A and 144B. It should be understood that the combination of the planar transistors 701A-701B and the MIM elements 142A-142B corresponds to a 1T1C element, that is, a single transistor single capacitor element.

[0164] In some embodiments, Fig.10As shown in FIG. 1 , redistribution layer (RDL) elements 146A, 146B, 146C are electrically connected to respective top metal elements 138A, 138B, 138C, and RDL elements 146A-146C extend through SOC anchor layer 124. In some embodiments, metal layer elements 128A-128C, 130A-130C, 134A-134C, and 138A-138C may be made of copper, copper alloys, aluminum, aluminum alloys, or other conductive materials.

[0165] like Fig.10 , the SOC wafer component 102 includes one or more anchor pads 148 in or on the anchor layer 124 on the front side 108. The anchor pads 148 may be implemented, for example but not limited to, copper, copper alloy, aluminum, aluminum alloy, metal, metal alloy, etc. to provide one or more connection or attachment points between the SOC wafer component 102 and / or the first ASIC wafer component 104.

[0166] The back side 110 of the first SOC wafer element 102 (i.e., the side of the SOC substrate 120 depicted as the top of the CIS device wafer stack 1000) includes a composite metal grid 126 extending vertically from the SOC substrate 120. It should be appreciated that the back side 110 of the SOC wafer element 102 may include a variety of components. Figure 1 The embodiments presented in Fig.10 The SOC wafer element 102 includes one or more photodiodes 168, as described above with respect to Figure 1 Described in more detail.

[0167] Fig.10 The first ASIC wafer element 104 depicted in FIG. 1 includes a first ASIC wafer substrate 170 including one or more layers. Fig.10 In an example embodiment of the present invention, substrate 170 includes a front side layer 172, a silicon-on-insulator (SOI) layer 174, and a back side layer 176. According to some embodiments, front side layer 172 and back side layer 176 may include, for example but not limited to, non-low-k dielectric materials such as silicon oxide, silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), or the like. Fig.10 In the description of FIG. 1 , the SOI layer 174 may include, for example but not limited to, silicon oxide or other suitable insulating materials. Fig.10 As shown in FIG. 1 , the first ASIC wafer component 104 may be implemented using components (ie, functionality) formed on the front side 112 and the back side 114 of the component 104. Fig.10As described in , the fabrication of the elements may be constructed on the front side layer 172 and the back side layer 176 of the substrate 170, wherein the elements formed on the front side layer 172 and the back side layer 176 are electrically connected between the front side 112 and the back side 114 using Big Through Silicon Via (BTSV) 218 ​​(i.e., a big silicon via extending through the entire substrate 170 (e.g., the front side layer 172, the SOI layer 174, and the back side layer 176)), thereby achieving connectivity between the elements disposed in the front side layer 172 and the elements disposed in the back side layer 176. It should be understood that such BTSV 218 may be made of a suitable conductive material, which includes, for example, but not limited to, copper, copper alloys, aluminum, aluminum alloys, and the like.

[0168] Above about Figure 1 Describes in more detail Fig.10 The front side 112 of the first ASIC wafer element 104. Figure 1 The first ASIC wafer component 104, such as Fig.10 As described in the foregoing, an oxide layer 182 may be formed on the backside layer 176 of the substrate 170. In some embodiments, the oxide layer 182 may include, for example but not limited to, an aluminum oxide layer (e.g., Al2O3) or the like. The first ASIC wafer element 104 may further include a front-side anchoring layer 184 formed on the front-side dielectric layer 178 and a back-side anchoring layer 186 formed on the back-side dielectric layer 180. It should be understood that the aforementioned anchoring layers 184-186 may be implemented as suitable dielectric materials, including, for example but not limited to, SiN, oxide, SiO x F y C z N a , polymer, resin, low-K material, high-K material or any related insulating layer. Figure 1 The front side 112 of the first ASIC wafer element 104 is shown. Fig.10 Other elements described in .

[0169] Fig.10 The embodiment presented in FIG. 1 illustrates the back side 114 of the first ASIC wafer element 104 having a back side dielectric layer 180. Fig.10 The back side 114 of the first ASIC wafer element 104 depicted in FIG. 1 includes one or more transistors 702A, 702B, 702C, 702D, 702E, 702F, 702G, and 702H formed on the oxide layer 182 of the back side layer 176 of the substrate 170. According to one embodiment, the transistors 702A-702H may be implemented as an array thereof. According to one embodiment, the transistors 702A-702H may be implemented as TFT FinFET transistors or the like. FIG. 3A to FIG. 3IThe formation of transistors 702A-702H is described in further detail.

[0170] At least one of the source or drain of the planar transistors 702A-702H is electrically connected to a suitable metal-insulator-metal (MIM) element 706A-706H, respectively, and the metal-insulator-metal element 706A-706H is coupled to the first vias 708A-708H, respectively. It should be understood that the combination of the planar transistors 702A-702H and the MIM elements 706A-706H corresponds to a 1T1C element, that is, a single transistor single capacitor element. Fig.10 The back side 114 of the first ASIC wafer element 104 shown in FIG. 1 further includes one or more top metal layer elements 226A, 226B, 226C, 226D, 226E, and 226F disposed in the back side dielectric layer 180. Fig.10 In the embodiment shown in FIG, top metal layer elements 226A-226F are electrically connected to first vias 708A-708H. It should be appreciated that such first vias 708A-708H may be made of suitable conductive materials including, for example but not limited to, copper, copper alloys, aluminum, aluminum alloys, and the like.

[0171] like Fig.10 As illustrated in FIG. 1 , redistribution layer (RDL) elements 230A, 230B, 230C, 230D, 230E, and 230F are electrically connected to respective top metal elements 226A, 226B, 226C, 226D, 226E, and 226F. Fig.10 As shown in FIG. 1 , the RDL elements 230A- 230F extend through the backside anchor layer 186. Additionally, one or more anchor pads 232 are located in or on the backside anchor layer 186.

[0172] As shown, Fig.10 The CIS device wafer stack 1000 illustrated in FIG. 1 further includes a third wafer element, namely, a second ASIC wafer element 106, bonded to the backside anchor layer 186. According to one embodiment, Fig.10 The second ASIC wafer component 106 depicted in the figure includes a second ASIC wafer substrate 234, which includes one or more layers. The second ASIC wafer component 106 further includes a second ASIC dielectric layer 236 formed on the substrate 234. The second ASIC wafer component 106 may further include a second ASIC anchoring layer 238 formed on the second ASIC dielectric layer 236. The aforementioned anchoring layer 238 may be implemented as a suitable dielectric material, including, for example but not limited to, SiN, oxide, SiO x Fy C z N a , polymers, resins, low-K materials, high-K materials or any related insulating layers or the like.

[0173] exist Fig.10 , the second ASIC dielectric layer 236 of the second ASIC wafer component 106 includes one or more first metal layer components 240A, 240B, and 240C. The second ASIC wafer component 106 further includes one or more second metal layer components 242A, 242B, and 242C disposed in the dielectric layer 236 and electrically connected to the respective first metal layer components 240A, 240B, and 240C through first vias 244A, 244B, and 244C. It should be understood that such first vias 244A-244D may be made of a suitable conductive material, including, for example, but not limited to, copper, copper alloys, aluminum, aluminum alloys, and the like.

[0174] The second ASIC wafer component 106 further includes one or more third metal layer elements 246A, 246B, and 246C disposed in the dielectric layer 236 and electrically connected to the respective one or more second metal layer elements 242A, 242B, 242C through respective second vias 248A, 248B, and 248C. It should be understood that such second vias 248A-248C may be made of a suitable conductive material including, for example, but not limited to, copper, copper alloys, aluminum, aluminum alloys, and the like.

[0175] Fig.10 The second ASIC wafer element 106 depicted in FIG. 1 further includes one or more top metal layer elements 250A, 250B, and 250C. One or more third metal layer elements 246A, 246B, and 246C are electrically connected to respective top metal layer elements 250A, 250B, and 250C through respective third vias 252A, 252B, and 252C. It should be understood that such third vias 252A-252C may be made of suitable conductive materials, including, for example, but not limited to, copper, copper alloys, aluminum, aluminum alloys, and the like. In some embodiments, the aforementioned metal layer elements 240A-240C, 242A-242C, and 246A-246C may be made of copper, copper alloys, aluminum, aluminum alloys, or other conductive materials.

[0176] Fig.10The second ASIC wafer element 106 described in the figure further includes one or more planar transistors 704A, 704B and 704C located on or adjacent to the respective first metal layer elements 240A, 240B and 240C. At least one of the source or drain of the planar transistors 704A-704C is electrically connected to a suitable metal-insulator-metal (MIM) element 254A-254C, respectively, and the metal-insulator-metal element 254A-254C is coupled to the fourth through-hole 256A-256C, respectively. FIG. 3A to FIG. 3I The formation of transistors 704A-704C is described in more detail. It should be appreciated that the combination of planar transistors 704A-704C and MIM elements 254A-254C corresponds to a 1T1C element, that is, a single transistor single capacitor element. Fig.10 As shown in FIG. 1 , 1T1C elements (i.e., combined transistors (704A-704C) with corresponding capacitors (MIM elements 254A-254C)) are located between respective first metal layer elements 240A-240C and top metal layer elements 250A-250C. Thus, as shown, fourth vias 256A-256C establish electrical connections between top metal layer elements 250A-250C and MIM elements 254A-254C.

[0177] Fig.10 Further depicted are one or more redistribution layer (RDL) elements 258A, 258B, 258C, 258D, 258E, and 258F electrically connected to the top metal elements 250A, 250B, and 250C. In some embodiments, as Fig.10 As shown in FIG. 1 , the RDL components 258A-258F extend through the second ASIC anchoring layer 238 to contact the corresponding RDL components 230A-230F of the first ASIC wafer component 104. In addition, the second ASIC wafer component 106 includes one or more anchor pads 260 located in or on the second ASIC anchoring layer 238, and the one or more anchor pads 260 are used to contact the corresponding anchor pads 232 of the first ASIC wafer component 104. Fig.10 As shown in FIG. 1 , the second ASIC wafer element 106 also includes one or more transistor gates or “devices”, i.e., FinFET devices, GAA devices, HKMG devices, SiGe S / D devices, SOI devices, polycrystalline devices, doped polycrystalline devices, etc., as described above with respect to Figure 1 As discussed, the one or more transistor gates or "devices" include contacts 262 coupling gate elements 264 to first metal layer elements 240A-240D.

[0178] Fig.11 Provided Fig.10 A simplified schematic diagram of the 1T (single transistor)-1C (MIM) combination. That is, Fig.11 Planar transistors 701A-701B, 702A-702H, or 704A-704C are depicted having source / drain electrodes contacting capacitors (MIM elements) 142A-142B, 706A-706H, or 254A-254C, respectively.

[0179] Now turn Fig.12 , as discussed in more detail below, shows a CIS device wafer stack 1200 according to a fifth embodiment, wherein Fig.10 The planar transistors 701A-701B, 702A-702F and 704A-704C are replaced by three-dimensional transistors. That is, Fig.12 Provides similar Fig.10 FIG. 1 is a schematic cross-sectional view of a CIS wafer stack 1200 of a wafer stack 1000. Fig.12 As shown in FIG. 1 , the wafer stack 1200 includes a first SOC wafer element 102, a first ASIC wafer element 104, and a second ASIC wafer element 106. Fig.12 As described in the above, the first SOC wafer element 102, the first ASIC wafer element 104 and the second ASIC wafer element 106 are similar to the above Fig.10 The first SOC wafer component, the first ASIC wafer component, and the second ASIC wafer component illustrated and described are substantially the same. Therefore, except as noted below, the various components described above with respect to the first SOC wafer component 102, the first ASIC wafer component 104, and the second ASIC wafer component 106 are applicable to Fig.12 .

[0180] exist Fig.12 In addition to the planar transistors 701A and 701B being replaced by three-dimensional transistors 720A and 720B, the first SOC wafer element 102 includes the above Fig.10 All the features described. That is, Fig.12 The first SOC wafer element 102 described in the above uses FIG. 5A to FIG. 6B The three-dimensional transistors 720A-720B of the general structure discussed. Therefore, Fig.10The planar transistors 701A-701B shown in FIG. 1 have been replaced by three-dimensional transistors 720A and 720B. At least one of the source or drain of the three-dimensional transistors 720A-720B is electrically connected to metal-insulator-metal (MIM) elements 142A and 142B, which are coupled to top metal layer elements 138A and 138B via respective fourth vias 144A and 144B. It should be understood that the combination of the three-dimensional transistors 720A-720B and the MIM elements 142A-142B corresponds to a 1T1C element, that is, a single transistor single capacitor element. Fig.12 The remaining components of the first SOC wafer element 102 correspond to those previously described above with respect to Fig.10 Those elements described.

[0181] Fig.12 The first ASIC wafer element 104 shown in FIG. 1 is similar to the first ASIC wafer element 104 shown in FIG. Fig.10 However, if Fig.12 As illustrated in FIG. 1 , the planar transistors 702A-702H located on the oxide layer 182 of the back side 114 of the first ASIC wafer element 104 have been replaced by three-dimensional transistors 722A, 722B, 722C, 722D, 722E, 722F, 722G, and 722H as shown. Thus, at least one of the source or drain of the three-dimensional transistors 722A-722F is electrically connected to appropriate metal-insulator-metal (MIM) elements 726A, 726B, 726C, 726D, 726E, 726F, 726G, and 726H, and the metal-insulator-metal (MIM) elements 726A, 726B, 726C, 726D, 726E, 726F, 726G, and 726H are respectively coupled to the top metal layer elements 226A, 226B, 226C, 226D, 226E, and 226F through respective first vias 728A, 728B, 728C, 728D, 728E, 728F, 728G, and 728H. The three-dimensional transistors 722A-722H can be formed as described above with respect to FIG. 5A to FIG. 6B It should be appreciated that the combination of the three-dimensional transistors 722A-722H and the MIM elements 726A-726H corresponds to a 1T1C element, ie, a single transistor single capacitor element. Fig.12 The remaining components of the first ASIC wafer element 104 correspond to those previously described above with respect to Fig.10 Those elements described.

[0182] Fig.12The second ASIC wafer element 106 of the CIS device wafer stack 1200 depicted in FIG. 1 is similar to the second ASIC wafer element 106 of FIG. 11 . Fig.10 The described embodiments. Fig.12 In the embodiment, the planar transistors 704A-704C located on or adjacent to the respective first metal layer elements 240A, 240B and 240C are replaced by three-dimensional transistors 724A, 724B and 724C. At least one of the source or drain of the three-dimensional transistors 724A-724C is electrically connected to a suitable metal-insulator-metal (MIM) element 254A-254C, respectively, and the metal-insulator-metal element 254A-254C is coupled to the fourth through-hole 256A-256C, respectively. FIG. 5A to FIG. 6B The formation of transistors 724A-724C is described in more detail. It should be understood that the combination of three-dimensional transistors 724A-724C and MIM elements 254A-254C corresponds to a 1T1C element, that is, a single transistor single capacitor element. Fig.12 As shown in FIG. 1 , 1T1C elements (i.e., combined transistors (724A-724C) with corresponding capacitors (MIM elements 254A-254C)) are located between respective first metal layer elements 240A-240C and top metal layer elements 250A-250C. Thus, as shown, fourth vias 256A-256C establish electrical connections between top metal layer elements 250A-250C and MiM elements 254A-254C. Fig.12 The remaining elements of the second ASIC wafer element 106 correspond to those previously described above with respect to Fig.10 Those elements described.

[0183] Fig.13 Provided Fig.12 A simplified schematic diagram of a transistor-MIM combination. That is, Fig.13 Three-dimensional transistors 720A-720B, 722A-722H, or 724A-724C are depicted, having source / drain electrodes contacting capacitors (MIM elements) 142A-142B, 726A-726H, or 254A-254C, respectively.

[0184] Reference Fig.14 , as discussed in more detail below, shows a CIS device wafer stack 1400 according to a sixth embodiment, wherein Fig.10 The planar transistors 701A-701B, 702A-702F and 704A-704C and the three-dimensional transistors 720A-720B, 722A-722F and 724A-724C are replaced by alternative three-dimensional transistors. That is, Fig.14 Provides similar Fig.10 Wafer stacking 1000 and Fig.12 FIG. 1 is a cross-sectional view of a CIS wafer stack 1400 of a wafer stack 1200. Fig.14 As shown in FIG. 1 , the wafer stack 1400 utilizes a first SOC wafer element 102, a first ASIC wafer element 104, and a second ASIC wafer element 106. Fig.14 As described in the above, the first SOC wafer element 102, the first ASIC wafer element 104 and the second ASIC wafer element 106 are similar to the above Fig.10 and Fig.12 The first SOC wafer component, the first ASIC wafer component, and the second ASIC wafer component illustrated and described are substantially the same. Therefore, except as noted below, the various components described above with respect to the first SOC wafer component 102, the first ASIC wafer component 104, and the second ASIC wafer component 106 are applicable to Fig.14 .

[0185] like Fig.14 As described in Fig.14 The first SOC wafer element 102 shown in FIG. 1 is replaced with a different three-dimensional transistor design. Fig.10 Planar transistors 701A-701B and Fig.12 Therefore, the planar transistors 701A and 701B are replaced by the three-dimensional transistors 730A and 730B, respectively. That is, Fig.14 The first SOC wafer element 102 described in the above uses FIG. 8A to FIG. 9B The three-dimensional transistors 730A-730B of the general structure discussed. At least one of the source or drain of the three-dimensional transistors 730A-730B is electrically connected to metal-insulator-metal (MIM) elements 142A and 142B, which are coupled to the top metal layer elements 138A and 138B via respective fourth vias 144A and 144B. It should be understood that the combination of the three-dimensional transistors 730A-730B and the MIM elements 142A-142B corresponds to a 1T1C element, that is, a single transistor single capacitor element. Fig.14 The remaining components of the first SOC wafer element 102 correspond to those previously described above with respect to Fig.10 Those elements described.

[0186] Fig.14 The first ASIC wafer element 104 shown in FIG. 1 is similar to the first ASIC wafer element 104 shown in FIG. Fig.10 and Fig.12 However, if Fig.14As shown in FIG. 1 , planar transistors 702A-702H ( FIG. 1 ) located on the oxide layer 182 of the back side 114 of the first ASIC wafer element 104 are Fig.10 ) and three-dimensional transistors 720A-720H ( Fig.12 ) has been replaced by three-dimensional transistors 732A, 732B, 732C, 732D, 732E, 732F, 732G and 732H as shown. Thus, at least one of the source or drain of the three-dimensional transistors 732A-732F is electrically connected to appropriate metal-insulator-metal (MIM) elements 736A, 736B, 736C, 736D, 736E, 736F, 736G, and 736H, and the metal-insulator-metal elements 736A, 736B, 736C, 736D, 736E, 736F, 736G, and 736H are coupled to the top metal layer elements 226A, 226B, 226C, 226D, 226E, and 226F through respective first vias 738A, 738B, 738C, 738D, 738E, 738F, 738G, and 738H, respectively. The three-dimensional transistors 732A-732H can be formed as described above with respect to FIG. 8A to FIG. 9B It should be appreciated that the combination of three-dimensional transistors 732A-732H and MIM elements 736A-736H corresponds to a 1T1C element, ie, a single transistor single capacitor element. Fig.14 The remaining components of the first ASIC wafer element 104 correspond to those previously described above with respect to Fig.10 and Fig.12 Those elements described.

[0187] Fig.14 The second ASIC wafer element 106 of the CIS device wafer stack 1400 depicted in FIG. 1 is similar to the second ASIC wafer element 106 of FIG. 11 . Fig.10 and Fig.12 The described embodiments. Fig.14 In the embodiment, planar transistors 704A-704C ( FIG. 1 ) located on or adjacent to respective first metal layer elements 240A, 240B, and 240C are provided. Fig.10 ) and three-dimensional transistors 724A-724C ( Fig.12 ) are replaced by three-dimensional transistors 734A, 734B and 734C. At least one of the source or drain of the three-dimensional transistors 724A-724C is electrically connected to a suitable metal-insulator-metal (MIM) element 254A-254C, respectively, and the metal-insulator-metal element 254A-254C is coupled to the fourth through-holes 256A-256C, respectively. FIG. 8A to FIG. 9BThe formation of transistors 724A-724C is described in more detail. It should be understood that the combination of three-dimensional transistors 734A-734C and MIM elements 254A-254C corresponds to a 1T1C element, that is, a single transistor single capacitor element. Fig.14 As shown in FIG. 1 , 1T1C elements (i.e., combined transistors (734A-734C) with corresponding capacitors (MIM elements 254A-254C)) are located between respective first metal layer elements 240A-240C and top metal layer elements 250A-250C. Thus, as shown, fourth vias 256A-256C establish electrical connections between top metal layer elements 250A-250C and MIM elements 254A-254C. Fig.14 The remaining elements of the second ASIC wafer element 106 correspond to those previously described above with respect to Fig.10 and Fig.12 Those elements described.

[0188] Fig.15 Provided Fig.14 A simplified schematic diagram of a transistor-MIM combination. That is, Fig.15 Three-dimensional transistors 730A-730B, 732A-732H, or 734A-734C are depicted, having source / drain electrodes contacting capacitors (MIM elements) 142A-142B, 726A-726H, or 254A-254C, respectively.

[0189] In some embodiments, the three-dimensional transistors described herein may be implemented as IGZO thicknesses may range from about 1 nm to 12 nm, and in some cases may be 2 nm to 6 nm. In such embodiments, HfO x The TiN component may have a thickness in the range of about 1 nm to 30 nm, and in some cases 5 nm to 15 nm. The length of the IGZO channel (vertically) may be in the range of about 5 nm to 100 nm, and in some cases 20 nm to 80 nm. In such embodiments, the in-plane critical dimension may be in the range of about 10 nm to 90 nm, and in some cases 25 nm to 75 nm.

[0190] According to some embodiments, different types of hybrid bonding may be utilized herein. In some embodiments, pixel-level hybrid bonding (PLHB) or column-level hybrid bonding (CLHB) may be used. In PLHB, bonding (i.e., RDL to RDL of wafer) occurs below the photodiode array. In CLHB, bonding (i.e., RDL to RDL of wafer) occurs below (layer by layer), but outside the photodiode area. Fig.16A and Fig. 16B Provides various Figure 1 , Figure 4 , Figure 7 , Fig.10 , Fig.12 and Fig.14 1 is a simplified top view of wafer stacks 100, 400, 700, 1000, 1200, and 1400. All components except the general markings of the RDL to RDL connections (i.e., hybrid bonding) and the location of the photodiode 168 array have been removed to illustrate the positioning of the various RDL elements 146A-146C / 206A-206C, 230A-230F / 258A-258F directly under the photodiode 168 (PLHB) or around the photodiode 168 (CLHB).

[0191] For example, Fig.16A An illustration of a PLHB is provided, wherein a photodiode region 1600 is shown by a box located in the center of the image. Surrounding the photodiode region 1600 is a peripheral region 1602 where no RDL to RDL bonding occurs. Hybrid bonding 1604 is represented by multiple circles within the photodiode region 1600. Thus, when viewing Figure 1 , Figure 4 , Figure 7 , Fig.10 , Fig.12 and Fig.14 , hybrid bonding 1604 corresponds to RDL-to-RDL component bonding between wafer components 102, 104, and 106. Fig.16A In the PLHB, the hybrid junction 1604 is located directly below the photodiode region 1600. Fig. 16B An illustration of a CLHB embodiment is provided in which no hybrid junction 1604 is located in the peripheral region 1602 and not beneath the photodiode region 1600 .

[0192] Reference 17A to 17C , illustrates various types of hybrid joints 1600 that can be used in one or more embodiments. Fig.17A and Fig. 17BType 1 hybrid bonding is described, which utilizes a single thin column of RDL material ( Fig.17A ) or using two thin RDL material pillars ( Fig. 17B ). Fig. 17C A description of a Type 2 hybrid bond is provided, in which a single substantially larger column of RDL material is used to form FIG. 16A to FIG. 16B 1604 as depicted in . According to some embodiments, the CLHB bond utilizes a Type 2 hybrid bond. In other embodiments, the PLHB bond may utilize a Type 1 hybrid bond and / or a Type 2 hybrid bond.

[0193] As discussed above, the wafer stacks 100, 400, 700, 1000, 1200, and / or 1400 may utilize one or more anchor pads 148, 208, 232, 260 as a bond between the wafer elements 102-106. Fig.18A As described in FIG. 1 , such anchor pads 148, 208, 232, 260 may be used in PLHB bonding. In some embodiments, such as Fig.18B As shown in , the PLHB bond can be formed using a Type 2 hybrid bond. It should be understood that in this embodiment (i.e., Fig.18B ), replacing the anchor pads 148, 208, 232, 260 with a Type 2 hybrid bond connection reduces manufacturing cost and time because the Type 2 hybrid bond is generally stronger than the Type 1 hybrid bond, the material used for this bond has already been deposited for the RDL elements 146A-146C / 206A-206C, 230A-230F / 258A-258F, and no additional metal deposition is required as an anchor pad. Fig. 17C With the use of Type 2 connections, the PLHB and CLHB implementations of wafer stacks 100, 400, 700, 1000, 1200, and 1400 may utilize any variation of the columns and / or rows of hybrid junctions 1604 in the peripheral region 1602, such as Fig.19 This is illustrated in the various configurations depicted in .

[0194] Now turn Fig. 20 , a flow chart 2000 illustrating a method for forming a CIS device wafer stack 100 according to some embodiments is shown. The method starts at S100, and then an oxide layer such as a SiO2 layer 316 is deposited on a device wafer 300. The device wafer 300 includes a device wafer substrate 304, on which a device wafer SiGe EPI layer 306 and a SiEPI layer 308 are formed. In S102, an oxide layer such as a SiO2 layer 318 is deposited on a carrier wafer 302. Figure 2AThe carrier wafer 302 shown in FIG. 1 includes a carrier wafer substrate 310, on which a carrier wafer SiGe EPI layer 312 and a carrier wafer Si EPI layer 314 are formed. In S104, the device wafer 300 is bonded to the carrier wafer 302. That is, an oxide-oxide bond is formed between the device wafer 300 and the carrier wafer 302.

[0195] In S106, the Si EPI layer 308 of the device wafer 300 is removed by etching or other suitable mechanisms. In S108, the SiGe EPI layer 306 is removed by etching or other suitable mechanisms. In S110, ASIC components, i.e., metal layer components, such as Figure 2F In some embodiments, ASIC formation corresponds to FEoL, BEoL, etc. as shown.

[0196] In S112, a dielectric layer 178 is then deposited. In S114, a front-side anchor layer 184 is formed on the dielectric layer 178. In S116, front-side redistribution layer elements 206A-206C are formed. In S118, an intermediate device (such as Figure 2F ) is then inverted and hybrid bonded (e.g., a combination of oxide-oxide and metal-metal bonding) to the SOC wafer device 102. In S120, the carrier wafer substrate 310 is removed (i.e., etched) using the carrier wafer SiGe EPI layer 312 as an etch stop layer. In S122, the SiGe EPI layer 312 is then removed by etching or other suitable mechanisms, such as Fig.2I . In S124, a low temperature IGZO transistor array 220A-220F is formed on the oxide layer 182. In S126, one or more ASIC components, such as metal layer components 222A-222F, 226A-226F, are formed on the back side 114. In S128, a dielectric layer 180 is deposited on the back side 114 of the first ASIC wafer component 104. Then, in S130, one or more BTSVs 218 are formed to electrically couple the front side 112 and the back side 114 of the first ASIC wafer component 104.

[0197] In S132, a backside anchoring layer 186 is formed on the dielectric layer 180. Then, in S134, one or more backside redistribution layer elements 230A-230F are formed through the anchoring layer 186 and the dielectric layer 180. In S136, the second ASIC wafer element 106 is then bonded to the back side 114 of the first ASIC wafer element 104. Then, in S138, the back side 110 of the SOC wafer element 102 (i.e., the SOC substrate 120) is thinned. In some embodiments, CMP or other mechanical or chemical methods are used to thin the SOC substrate 120. In S140, a composite metal grid and remaining photodiode elements are formed.

[0198] Now turn Fig.21 , a flow chart 2100 illustrating a method for forming a wafer stack according to another embodiment is shown. The method starts at S200, and then the front side 108 of the first wafer component 102 is bonded to the front side 112 of the second wafer component 104. In S202, one or more metal layer components 226A-226F, 222A-222F are formed in the dielectric layer 180 of the second wafer component 104. Then in S204, an anchoring layer 186 is formed on the dielectric layer 180. In S206, one or more redistribution layer components 230A-230F are formed on the metal layer components 226A-226F, and the one or more redistribution layer components 230A-230F extend through the dielectric layer 180 and the anchoring layer 186.

[0199] In S208, the third wafer element 106 is bonded to the second wafer element 104. In some embodiments, the third wafer element 106 includes an anchor layer 238 and redistribution layer elements 258A-258F. In addition, the bonding of the second wafer element 104 and the third wafer element 106 corresponds to the bonding of the redistribution layer elements 230A-230F and the redistribution layer elements 258A-258F. In S210, a composite metal grid 126 is formed on the back side 110 of the first wafer element 102.

[0200] In some embodiments, the use of three-dimensional 1T1C elements can enhance SOI backside power drive due to the low current usage of the backside transistor array. In other embodiments, the use of the above three-dimensional 1T1C elements can provide backside bias and current drive. Therefore, the three-dimensional 1T1C elements described herein can act as DRAM, FeRAM, RRAM, and the like.

[0201] According to a first embodiment, a method for forming a wafer stack is provided. The method includes: bonding the front side of a first wafer element to the front side of a second wafer element. The method further includes: forming one or more metal layer elements in a dielectric layer on the back side of the second wafer element; and forming an anchoring layer on the dielectric layer on the back side of the second wafer element. In addition, the method includes: forming one or more redistribution layer elements on the metal layer element so that the redistribution layer elements extend through the dielectric layer and the anchoring layer. The method further includes: bonding a third wafer element to the second wafer element. In this embodiment, the third wafer element includes an anchoring layer and one or more redistribution layer elements extending through the anchoring layer. In addition, the bonding of the third wafer element to the second wafer element corresponds to the bonding of the redistribution layer elements of the second wafer element to the redistribution layer elements of the third wafer element.

[0202] In some embodiments, the first wafer element is a system chip wafer element, and the second wafer element and the third wafer element are special application integrated circuit wafer elements. In some embodiments, the method further includes forming at least one transistor on the back side of the second wafer element, wherein the transistor contacts the metal layer element. In some embodiments, the method further includes forming at least one metal-insulator-metal element that contacts the transistor. In some embodiments, the transistor is a three-dimensional transistor or a planar transistor. In some embodiments, the method further includes a step of forming a second wafer element, including the following steps: depositing a dielectric layer on a device wafer, the device wafer including a substrate, a first EPI layer and a second EPI layer, wherein the dielectric layer is deposited on the second EPI layer. The step of forming the second wafer element also includes depositing a dielectric layer on a carrier wafer, the carrier wafer including a substrate, a first EPI layer and a second EPI layer, wherein the dielectric layer is deposited on the second EPI layer. Then, the dielectric layer of the device wafer is bonded to the dielectric layer of the carrier wafer; the substrate of the device wafer is removed; the first EPI layer of the device wafer is removed; at least one metal layer element is formed in the dielectric layer on the second EPI layer of the device wafer; an anchor layer is formed on the dielectric layer; and at least one redistribution layer element is formed, the redistribution layer element extending through the anchor layer to the metal layer element disposed in the dielectric layer. In some embodiments, the first wafer element includes a substrate having a front surface and a back surface, a dielectric layer located on the front surface, at least one metal layer element disposed in the dielectric layer, an anchor layer formed on the dielectric layer, and at least one redistribution layer element extending through the anchor layer to the metal layer element disposed in the dielectric layer, wherein the redistribution layer element of the first wafer element is bonded to the redistribution layer element of the second wafer element, thereby forming a first hybrid bond therebetween.

[0203] According to a second embodiment, a wafer stack is provided, the wafer stack comprising a first wafer element having a front side and a back side. The wafer stack also comprises a second wafer element having a front side and a back side, such that the front side of the second wafer element is bonded to the front side of the first wafer element. Furthermore, the wafer stack comprises a third wafer element having a front side and a back side, such that the front side of the third wafer element is bonded to the back side of the second wafer element.

[0204] In some embodiments, the first wafer element is a system chip, and at least one photodiode is formed on the back side of the first wafer element. In some embodiments, the second wafer element includes a substrate, a front dielectric layer, a back dielectric layer, at least one through hole and at least one transistor. The substrate has a front layer and a back layer located between the front side and the back side of the substrate, the front dielectric layer is disposed on the substrate, and at least one metal layer element is disposed in the front dielectric layer. The back dielectric layer is disposed on the substrate, and at least one metal layer element is disposed in the back dielectric layer. The through hole contacts at least one front metal layer element and at least one back metal layer element through the substrate. The transistor is located on the back layer of the substrate and contacts the metal layer element disposed in the back dielectric layer. In some embodiments, the wafer stack further includes at least one metal-insulator-metal element electrically contacting the transistor. In some embodiments, the transistor is a three-dimensional transistor or a planar transistor. In some embodiments, the first wafer element further comprises a substrate having a front surface and a back surface, a dielectric layer located on the front surface, at least one metal layer element disposed in the dielectric layer, an anchoring layer formed on the dielectric layer, and at least one redistribution layer element extending through the anchoring layer to the metal layer element disposed in the dielectric layer. In some embodiments, the first wafer element further comprises a transistor disposed on the metal layer element, and at least one metal-insulator-metal element electrically contacting the transistor, wherein the transistor is a three-dimensional transistor or a planar transistor. In some embodiments, the third wafer element further comprises a substrate having a front surface and a back surface, a dielectric layer located on the front surface, at least one metal layer element disposed in the dielectric layer, an anchoring layer formed on the dielectric layer, and at least one redistribution layer element extending through the anchoring layer to the metal layer element disposed in the dielectric layer. In some embodiments, the third wafer element further comprises at least one transistor disposed on the metal layer element, and at least one metal-insulator-metal element electrically contacting the transistor, wherein the transistor is a three-dimensional transistor or a planar transistor. In some embodiments, the second wafer component further includes a front side anchoring layer formed on the front side dielectric layer, a back side anchoring layer formed on the back side dielectric layer, at least one front side redistribution layer element extending through the front side anchoring layer to the metal layer element disposed in the front side dielectric layer, and at least one back side redistribution layer element extending through the back side anchoring layer to the metal layer element disposed in the back side dielectric layer. In some embodiments, the redistribution layer element of the first wafer component is bonded to the front side redistribution layer element of the second wafer component to form a first hybrid bond therebetween, and the redistribution layer element of the third wafer component is bonded to the back side redistribution layer element of the second wafer component to form a second hybrid bond therebetween.

[0205] According to a third embodiment, a method of forming a wafer stack is provided. The method includes: forming a first ASIC wafer element by forming one or more metal layer elements on a first ASIC wafer substrate, the first ASIC wafer substrate having a front side layer and a back side layer located between the front side and the back side of the first ASIC wafer element, so that the one or more metal layer elements are formed on the front side of the first ASIC wafer substrate. Forming the first ASIC wafer element also includes: depositing a front side dielectric layer on the substrate; forming a front side anchoring layer on the front side dielectric layer; and forming one or more redistribution layer elements, the redistribution layer elements contacting the metal layer elements and extending through the front side anchoring layer. The method of forming a wafer stack further includes: bonding the front side of a system wafer element to the front side anchoring layer of the first ASIC wafer element; and forming one or more metal layer elements on the back side layer of the first ASIC wafer substrate after bonding with the system wafer element. The method further includes: depositing a back side dielectric layer on the first ASIC wafer substrate; and forming a back side anchoring layer on the back side dielectric layer. Furthermore, the method of forming the wafer stack includes forming one or more redistribution layer elements contacting the metal layer elements and extending through the backside anchoring layer. Additionally, the method includes bonding the front side of the second ASIC wafer element to the backside anchoring layer of the first ASIC wafer element.

[0206] In some embodiments, the front side of the system chip wafer element further includes a system chip anchoring layer and at least one redistribution layer element extending through the system chip anchoring layer, the front side of the second special application integrated circuit wafer element further includes a second special application integrated circuit wafer element anchoring layer and at least one redistribution layer element extending through the second special application integrated circuit wafer element anchoring layer, the redistribution layer element of the system chip wafer element is bonded to the redistribution layer element on the front side of the first special application integrated circuit wafer element, thereby forming a first hybrid bond therebetween, and the redistribution layer element of the second special application integrated circuit wafer element is bonded to the redistribution layer element on the back side of the first special application integrated circuit wafer element, thereby forming a second hybrid bond therebetween.

[0207] According to a fourth embodiment, a wafer stack is provided, the wafer stack comprising a first wafer element having a front side and a back side. The wafer stack also comprises a second wafer element having a front side and a back side, such that the front side of the second wafer element is bonded to the front side of the first wafer element. In addition, the wafer stack comprises a third wafer element having a front side and a back side, such that the front side of the third wafer element is bonded to the back side of the second wafer element. The first wafer element is a system chip, and at least one photodiode is formed on the back side of the first wafer element.

[0208] According to a fifth embodiment, a wafer stack is provided, the wafer stack comprising a first wafer element having a front side and a back side. The wafer stack also comprises a second wafer element having a front side and a back side, such that the front side of the second wafer element is bonded to the front side of the first wafer element. In addition, the wafer stack comprises a third wafer element having a front side and a back side, such that the front side of the third wafer element is bonded to the back side of the second wafer element. The third wafer element further comprises at least one transistor and at least one metal-insulator-metal element electrically contacting the transistor, wherein the transistor is a three-dimensional transistor or a planar transistor.

[0209] According to a sixth embodiment, a wafer stack is provided, the wafer stack comprising a first wafer element having a front side and a back side. The wafer stack also comprises a second wafer element having a front side and a back side, such that the front side of the second wafer element is bonded to the front side of the first wafer element. In addition, the wafer stack comprises a third wafer element having a front side and a back side, such that the front side of the third wafer element is bonded to the back side of the second wafer element. The third wafer element further comprises a substrate having a front side surface and a back side surface, a dielectric layer located on the front side surface, at least one metal layer element disposed in the dielectric layer, an anchoring layer formed on the dielectric layer, and at least one redistribution layer element, the redistribution layer element extending through the anchoring layer to the metal layer element disposed in the dielectric layer.

[0210] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A wafer stack, characterized in that: include: A first wafer element having a front side and a back side, wherein the first wafer element is a system chip and at least one photodiode is formed on the back side of the first wafer element; a second wafer element having a front side and a back side, wherein the front side of the second wafer element is bonded to the front side of the first wafer element; and A third wafer element has a front side and a back side, wherein the front side of the third wafer element is bonded to the back side of the second wafer element.

2. The wafer stack according to claim 1, wherein: The second wafer element includes: a substrate having a front layer and a back layer located between the front side and the back side of the substrate; A front dielectric layer disposed on the substrate, wherein at least one metal layer element is disposed in the front dielectric layer; a back dielectric layer disposed on the substrate, wherein at least one metal layer element is disposed in the back dielectric layer; at least one through hole, contacting at least one front metal layer component and at least one back metal layer component through the substrate; and At least one transistor is located on the back side layer of the substrate and contacts the at least one metal layer element disposed in the back side dielectric layer.

3. The wafer stack according to claim 2, wherein: Further included is at least one metal-insulator-metal element electrically contacting the at least one transistor.

4. The wafer stack according to claim 3, wherein: The at least one transistor is a three-dimensional transistor or a planar transistor.

5. The wafer stack according to claim 4, wherein: The first wafer element further comprises: A substrate having a front surface and a back surface; a dielectric layer disposed on the front surface; At least one metal layer element is disposed in the dielectric layer; an anchor layer formed on the dielectric layer; and At least one redistribution layer element extends through the anchor layer to the at least one metal layer element disposed in the dielectric layer.

6. The wafer stack according to claim 5, characterized in that The first wafer element further comprises: at least one transistor located on the at least one metal layer element, and at least one metal-insulator-metal element electrically contacting the at least one transistor, The at least one transistor is a three-dimensional transistor or a planar transistor.

7. The wafer stack according to claim 5, wherein: The third wafer element further comprises: A substrate having a front surface and a back surface; a dielectric layer disposed on the front surface; At least one metal layer element is disposed in the dielectric layer; an anchor layer formed on the dielectric layer; and At least one redistribution layer element extends through the anchor layer to the at least one metal layer element disposed in the dielectric layer.

8. A wafer stack, characterized in that: include: A first wafer element having a front side and a back side; a second wafer element having a front side and a back side, wherein the front side of the second wafer element is bonded to the front side of the first wafer element, wherein at least one metal layer element is disposed on the back side of the second wafer element; and a third wafer element having a front side and a back side, wherein the front side of the third wafer element is bonded to the back side of the second wafer element, the third wafer element further comprising: At least one transistor is disposed on the at least one metal layer element; and At least one metal-insulator-metal element electrically contacts the at least one transistor, wherein the at least one transistor is a three-dimensional transistor or a planar transistor.

9. A wafer stack, characterized in that: include: A first wafer element having a front side and a back side; a second wafer element having a front side and a back side, wherein the front side of the second wafer element is bonded to the front side of the first wafer element, wherein the second wafer element comprises: a substrate having a front layer and a back layer located between the front side and the back side of the substrate; A front dielectric layer disposed on the substrate, wherein at least one metal layer element is disposed in the front dielectric layer; a back dielectric layer disposed on the substrate, wherein at least one metal layer element is disposed in the back dielectric layer; at least one through hole, contacting at least one front metal layer component and at least one back metal layer component through the substrate; and at least one transistor located on the backside layer of the substrate and contacting the at least one metal layer element disposed in the backside dielectric layer; and A third wafer element has a front side and a back side, wherein the front side of the third wafer element is bonded to the back side of the second wafer element.

10. The wafer stack according to claim 9, wherein: The second wafer element further comprises: a front-side anchoring layer formed on the front-side dielectric layer; a backside anchoring layer formed on the backside dielectric layer; at least one front redistribution layer element extending through the front anchor layer to the at least one metal layer element disposed in the front dielectric layer; and At least one backside redistribution layer element extends through the backside anchor layer to the at least one metal layer element disposed in the backside dielectric layer.

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