Bonded chip manufacturing method and bonded chip with improved electrical performance

Abstract

The invention belongs to the field of semiconductor device manufacturing, and particularly relates to a bonding chip manufacturing method and an electrical property improved bonding chip. Comprising the steps of S1, stacking and bonding at least a first wafer and a second wafer to form a wafer stacking structure; s2, etching to form a silicon through hole conductive pattern layer; s3, forming a barrier layer / seed crystal layer on the outer surface of the wafer stacking structure and the surface of the silicon through hole conductive pattern layer in a mode that no gap is generated on the side edge of the bonding layer of the wafer stacking structure; and S4, electrochemical deposition is carried out, and a copper plating layer is formed. According to the invention, the bonding gap of the stacked wafer and the special morphology of the side wall do not need to be considered, and the conventional Bamp of the single wafer can be applied; according to the process formula of S PVD and Cu electrochemical electroplating, the period of process development is greatly shortened, and the process difficulty is greatly reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor device manufacturing, and in particular relates to a bonding chip manufacturing method and a bonding chip with improved electrical performance. Background Art

[0002] In the existing bonded chip manufacturing method, the edge bonding morphology produced by wafer bonding will affect the subsequent electrochemical plating process. After wafer bonding and wafer thinning, the stacked thinned wafers continue to undergo a Damascus process to form related structures such as alignment marks, through-silicon vias, hybrid bonding vias / pads, etc. After the barrier layer & seed layer (B&S) process is completed, the electrochemical plating process may not be able to power on normally. The reason is that there is a gap at the edge, and the B&S process cannot fill the edge bonding gap. The electrical contact conductive probe of the electrochemical plating, due to its hardware design, contacts the lower step of the stacked wafer. Since the B&S (mainly the Cu seed layer) is not filled into the bonding gap, the conductive layer is broken, which ultimately leads to abnormal electrochemical plating process. Summary of the Invention

[0003] In view of the problems existing in the prior art, the present invention provides a method for manufacturing a bonded chip with an electrical performance improvement function, comprising: step S1, stacking and bonding at least a first wafer and a second wafer to form a wafer stacking structure; step S2, etching the wafer stacking structure to form a through-silicon via conductive pattern layer; step S3, forming a barrier layer / seed layer on the outer surface of the wafer stacking structure and the surface of the through-silicon via conductive pattern layer in a manner that no gaps are generated on the side of the bonding layer of the wafer stacking structure; step S4, performing electrochemical deposition on the barrier layer / seed layer to form a copper plating layer.

[0004] In addition, preferably, in the bonded chip manufacturing method described in the present invention, in the step S3, before forming the barrier layer / seed layer, it also includes a step S31: adjusting the tilt direction of the wafer stacking structure or the deposition direction of the physical vapor deposition target material or both, to form a relative tilt angle between the placement direction of the wafer stacking structure and the deposition direction of the physical vapor deposition target material.

[0005] Furthermore, in the bonded chip manufacturing method described in the present invention, in the step S31 , the relative inclination angle between the wafer stacking structure and the deposition direction of the physical vapor deposition target is greater than or equal to 45° and less than or equal to 90°.

[0006] In addition, preferably, in the bonded chip manufacturing method described in the present invention, in the step S31, the relative inclination angle between the wafer stacking structure and the deposition direction of the physical vapor deposition target is greater than or equal to 60° and less than or equal to 90°.

[0007] In addition, preferably, in the bonded chip manufacturing method described in the present invention, in the step S31, the relative inclination angle between the wafer stacking structure and the deposition direction of the physical vapor deposition target is equal to 90°.

[0008] In addition, preferably, the bonded chip manufacturing method of the present invention further comprises step S5, detecting the side step coverage capability of the barrier layer / seed layer covering the wafer stacking structure through a conductive test.

[0009] In addition, preferably, the bonded chip manufacturing method of the present invention further comprises step S6, if the side step coverage capability does not reach the product design threshold, repeating step S3 to continue growing the barrier layer / seed layer.

[0010] In addition, preferably, the present invention also provides a bonded chip with improved electrical performance produced by any of the above bonded chip manufacturing methods.

[0011] By utilizing the present invention, B&S can be deposited uniformly and continuously not only at the bonding gap, but also on the sidewalls of the wafer. In this way, there is no need to consider the special morphology of the bonding gap and sidewalls of the stacked wafer compared to conventional single wafers. The conventional B&S PVD and Cu electrochemical plating process formulas of single wafers can be used, which greatly reduces the process development cycle and process difficulty. The final structure produced (PVD B&S and electrochemical plating Cu thickness composition) is also consistent with the structure of the original verified single wafer production, ensuring the consistency of product performance. In summary, whether B&S PVD and Cu electrochemical plating and other subsequent processes are performed on several layers of stacked wafers, they are consistent with the single wafer process formula and the completion effect is consistent. There is no need for secondary trimming, which increases the effective area of the wafer. At the same time, the symmetry of the wafer structure is guaranteed, and the structural difference between it and a single conventional wafer is minimized as much as possible to ensure the normal progress of the subsequent process. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram illustrating a wafer stacking process flow in a bonded chip manufacturing method according to an embodiment of the present invention.

[0013] Figure 2 A schematic diagram illustrating thinning of untrimmed stacked wafer edges in a method for manufacturing bonded chips according to an embodiment of the present invention.

[0014] Figure 3 FIG. 1 is a schematic diagram illustrating trimmed wafer bonding and thinning in a bonded chip manufacturing method according to an embodiment of the present invention.

[0015] Figure 4Schematic diagram of wafer bonding showing ideal and actual conditions in a method for manufacturing a bonded chip according to an embodiment of the present invention.

[0016] Figure 5 A schematic diagram illustrating an electrochemical plating machine structure and a stacked wafer structure in a method for manufacturing a bonded chip according to an embodiment of the present invention is shown.

[0017] Figure 6 A schematic diagram illustrating reducing the trimming width in a bonded chip manufacturing method according to an embodiment of the present invention.

[0018] Figure 7 A schematic diagram illustrating a thickened Cu seed layer structure in a bonding chip manufacturing method according to an embodiment of the present invention.

[0019] Figure 8 A schematic diagram illustrating secondary edge trimming in a method for manufacturing a bonded chip according to an embodiment of the present invention.

[0020] Figure 9 A schematic diagram illustrating a process flow in a method for manufacturing a bonded chip according to an embodiment of the present invention.

[0021] Figure 10 A comparison of two special B&S PVD processes of conventional and improved types in a bonded chip manufacturing method according to an embodiment of the present invention is shown.

[0022] Figure 11 A schematic diagram of wafer sidewall deposition positions in a bonding chip manufacturing method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0023] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Other embodiments or modifications derived from the embodiments of this application by ordinary technicians in this field without making any creative work are all within the scope of protection of this application.

[0024] In the process of advanced packaging, wafer-level stacking is often involved. After wafer stacking, the wafers are usually thinned, and the electrical properties of the stacked wafers are led out through the subsequent through-silicon via process, followed by other processes such as metal interconnection. Figure 1As shown. Before bonding, one side of the wafer needs to be trimmed. Because the edge of the wafer is a tilted area, this area cannot contact each other during the bonding process, so there is no support. During the thinning process of the stacked wafers, this edge position will break, resulting in broken edges and wafer fragments. The schematic diagram is shown in Figure 2 As shown. Before bonding, one side of the wafer is trimmed. After wafer bonding, the wafers can be fully in contact with each other. As the wafers are thinned, there will be no edge fragmentation caused by lack of contact and support in the original wafer edge area. With this solution, the stacked wafers can be safely thinned to the required thickness, as shown in the schematic diagram. Figure 3 shown.

[0025] However, after wafer thinning, the following processes are required, such as:

[0026] 1. Alignment mark: An alignment mark needs to be made through the thinned silicon. Subsequent photolithography processes can be aligned with this alignment mark on the same side. The alignment mark here is usually made using the Damascene process;

[0027] 2. Fabrication of through silicon vias: Figure 1 As shown, the subsequent through-silicon via process is also similar to the copper Damascus process;

[0028] 3. Hybrid bonding vias / pads: If more layers of wafers need to be stacked later, a hybrid bonding via / pad structure needs to be produced. This type of structure also needs to be produced using the copper damascene process.

[0029] The copper damascene process is a common one, typically consisting of photolithography, etching, photoresist ashing, cleaning, barrier and seed layer deposition, electroplating, and surface copper removal by chemical mechanical polishing. However, during the damascene process on stacked wafers, the electrochemical plating layer may not power up properly, resulting in arcing defects that can render the wafer scrapped and damage the machine.

[0030] The mechanism is as follows: During the wafer bonding process, in order to ensure the bonding quality of the wafer, the cross-sectional morphology of the bonding interface after chemical mechanical polishing is usually required to be high in the middle and low at the edge, or as flat as possible. The situation where the middle is low and the edge is high is not allowed. At the same time, the upper and lower suction cups of the bond will also exert force on the wafer to deform it, so that the two wafers contact in the middle first, and then contact at the edges, and bond in order from small to large radius, so as to avoid the generation of bonding bubbles. At this time, the edge position of the wafer is not completely bonded and is in a suspended state. This is also the reason why the edge of the stacked wafer is prone to fine chipping after thinning. If the edge is completely bonded, there will be some slight deviations in the thickness of the film layer in the middle of the wafer, and bubble defects will definitely appear in the middle area. Such a process window is extremely small. In order to ensure a sufficient process window, priority is given to ensuring the middle area of the wafer, and the edge position is actually not completely bonded. At the same time, the wafer thinning process is controlled to reduce the stress on the wafer, ensure the integrity of the edge area that is not fully contacted, and prevent chipping. The schematic diagram is shown as follows Figure 4 shown.

[0031] This kind of edge bonding morphology will affect the subsequent electrochemical plating process. After the subsequent wafer bonding and wafer thinning, the stacked thinned wafers will continue to carry out the above-mentioned alignment marks, through-silicon vias, and hybrid bonding via / pad related structures Damascus processes. After the B&S process is completed, when the electrochemical plating process is carried out, it will not be possible to power on normally. The reason is that there is a gap at the edge, and the B&S process cannot fill the edge bonding gap. The electrical contact conductive probe of electrochemical plating, due to its hardware design, contacts the lower step of the stacked wafer. Since the B&S (mainly the Cu seed layer) is not filled in the bonding gap, the conductive layer is broken, which eventually leads to abnormal electrochemical plating process. The schematic diagram is as follows Figure 5 shown.

[0032] There are currently several ways to solve this problem:

[0033] Reduce the wafer trimming width: By reducing the wafer trimming width, the electrochemical plating ElectricalContact can contact the position of the upper wafer of the stacked wafers, thereby avoiding the problem of bonding gap. Figure 6 As shown. The width of the electrochemically plated electrical contact is usually around 0.5mm at the edge, which is 149.5mm at the wafer radius. Therefore, it is difficult to reduce the trimming width to less than 0.5mm. At the same time, as multiple layers of wafers are stacked, multiple trimmings will be performed, and the final width will definitely be greater than 0.5mm. Therefore, it is difficult to achieve this through this method.

[0034] Modify the electrochemical plating machine hardware: By changing the position of the electrochemical plating contact to make it farther away from the edge, it can avoid falling on the lower step position of the stacked wafer (with Figure 6 The solution is similar to the one shown in the figure, and falls on the top surface of the stacked wafer, avoiding the bonding gap, so that the electrochemical plating can proceed normally. The disadvantage of this solution is that it involves hardware modification of the machine and is not compatible with conventional mass production processes.

[0035] Increase the deposition thickness of the Cu seed layer: Fill the gap directly by increasing the thickness of the Cu seed layer. This ensures the continuity of the conductive layer and the normal progress of the electrochemical plating process, such as Figure 7 As shown. The disadvantage of this solution is that the size of the structure to be manufactured is relatively small, about 2000A. The height of this gap is about 1um and the depth is about 100um. Therefore, if you want to fill the thickness of this gap, you need to significantly increase the thickness of the Cu seed layer. This process cost will increase significantly, and the process time will also increase significantly (the original 2000A pattern only requires a 200A Cu seed layer, and now 1um is deposited, and the thickness becomes 100 times that of the original process). At the same time, the Cu seed layer at this time will directly fill the structural pattern that needs to be made above, and there will be no room for Cu electrochemical plating filling later. The Cu deposited by physical vapor deposition is relatively loose in texture, and the performance cannot meet the requirements. This process is only suitable for situations where the subsequent structure size is large and the thickness of the Cu seed layer that needs to be deposited is very thick.

[0036] Add a trimming process. This is a commonly used process. After wafer bonding and thinning, a trimming process is added to remove the bonding gap to ensure the continuity of the Cu seed layer and the normal progress of electrochemical plating. Figure 8 This solution is a practical and effective way to ensure normal electrochemical plating. However, the addition of a trimming step further reduces the wafer's usable area. Furthermore, the increased trimming width makes the overall wafer structure even more asymmetrical. Subsequent processing of wafers with structures significantly different from those of conventional single wafers can cause anomalies, requiring special handling. These two points are the drawbacks of adding a secondary trimming process.

[0037] In light of the existing solutions and their shortcomings described above, the present invention addresses the technical issue of electrochemical plating not being able to properly power up due to gaps at the edges of stacked wafers by introducing a new process into the existing process flow. This also eliminates the drawbacks of the aforementioned existing solutions.

[0038] Therefore, the present invention solves the technical problem in the prior art that the Cu seed layer is discontinuous due to the gap at the edge of the bonding wafer, thereby causing the subsequent electrochemical plating to be unable to be normally powered.

[0039] According to one embodiment of the present invention, after wafer bonding and thinning, it is necessary to use the Damascus process to produce some structures on the thinned stacked wafers. After the pattern is formed by etching, before the conventional barrier layer and seed layer process is performed, an additional process is added: the sidewall crystal edge of the stacked wafer is positioned in the deposition direction of the barrier layer and seed layer, and a barrier layer and seed layer film is deposited at the bonding gap. This compensates for the problem that the conventional barrier layer and seed layer process cannot deposit at the bonding gap, ensures the continuity of the conductive film layer, and thus ensures the normal progress of the subsequent electrochemical plating process. It also ensures the continuity of the barrier layer and seed layer film on the sidewall of the stacked wafer, thereby ensuring sufficient step coverage.

[0040] This eliminates the need to consider the two most important morphological differences between stacked and single wafers (bonding gaps and sidewalls). Therefore, regardless of the number of wafer layers stacked, the B&S process recipe for single wafers can be used, reducing process development costs and ensuring process consistency for identical structures within stacked wafers. The consistent B&S results and subsequent electrochemical plating and other related processes are also consistent with single wafers, resulting in improved consistency across all subsequent processes.

[0041] This solution eliminates the need for a secondary trimming process, ensuring more effective dies (also known as cores) on the wafer. It also maximizes the normality of the wafer morphology, ensuring that subsequent processes can proceed normally.

[0042] In addition, the present invention also makes the following analysis on the mechanism. In the prior art, the discontinuity of the Cu seed layer caused by the gap at the bonding edge causes the problem that the subsequent electrochemical plating cannot be powered normally. Conventional B&S adopts the process of physical vapor deposition (also referred to as PVD), which deposits materials on the front side of the wafer from top to bottom. Due to the obstruction of the upper wafer at the bonding gap, the material cannot penetrate into the gap to fill it. Therefore, the present invention adds a special B&S deposition step before the conventional B&S PVD process, that is, after the etching of the pattern, ashing, and wet cleaning processes are completed, to evenly deposit the B&S material at the gap to ensure the continuity of the subsequent Cu seed layer and the normal operation of the electrochemical plating process.

[0043] According to one embodiment of the present invention, after the special B&S deposition of the present invention, conventional B&SPVD process, Cu electrochemical plating process, Cu chemical mechanical polishing and other processes are sequentially performed, and the corresponding pattern is produced using the Damascus process. The process flow diagram is shown in FIG. Figure 9shown.

[0044] According to one embodiment of the present invention, the difference between the special B&S PVD process used and the conventional B&S PVD process is that the side wall area of the wafer, that is, the side of the wafer faces the direction of deposition of the target material. The conventional B&SPVD process is that the surface of the wafer faces the direction of material deposition. Other aspects are similar to the conventional B&S PVD process. To achieve the purpose of the present invention, there are the following options. The first is to keep the position of the wafer unchanged, change the position of the target material, and move the target material from the original top of the wafer to the side of the wafer; the second is to keep the position of the target material unchanged, adjust the direction of the wafer, and change the original flat wafer to vertical wafer, and place the side of the wafer opposite the target position. Both schemes can realize the deposition of the B&S layer at the bonding gap position, thereby ensuring the continuity of the B&S layer and the normal operation of electrochemical plating. The comparison diagram is shown in the figure. Figure 10 shown.

[0045] Conventional B&S PVD process after stacking wafers usually makes B&S thicker to ensure B&S deposition on the wafer sidewalls, such as Figure 11 As shown. Therefore, compared with the original single-layer verified hole B&S and electrochemical plating process formulas, there are changes, and the final hole structure is also slightly changed. The B&S will be relatively thicker, and the Cu deposited by electrochemical plating will be relatively thinner. Therefore, the final structural performance is also affected. In this way, it is necessary to completely redefine a version of the process parameters based on the stacked wafers. Moreover, these process parameters will also change with the number of stacked layers. As the number of stacked layers increases, the height of the sidewall increases significantly. In order to ensure the continuity of the B&S deposition on the sidewall, it is also necessary to increase the B&S PVD process formula, such as Figure 11 As shown. This is a huge workload. At the same time, the hole structure behind each layer of stacked wafers will change (mainly due to the composition of B&S and electrochemically plated Cu). The Cu seed layer deposited by the special B&S PVD process of the present invention does not need to be very thick, and the thinnest thickness is only 100A. Because the position of the bonding gap and the vertical surface are relative to the PVD deposition direction of the material, the step coverage ability is very high. After the special B&S PVD process, B&S will be evenly deposited not only at the bonding gap, but also on the stacked wafers and the side walls of the wafers.

[0046] As mentioned before, the two most important structural morphological differences between stacked wafers and single-piece wafers, the B&S PVD at the bonding gap and the sidewall position of the wafer, have been taken into account in the present invention, and there is no need to worry about the discontinuity of the film layer affecting the subsequent electrochemical plating process. Therefore, the subsequent B&S PVD can use the process formula of the single-layer wafer (or debug and verify the process in advance on the single-piece wafer). In this way, the process development cycle and process difficulty are greatly reduced, and the final structure produced will be consistent with the original single-layer wafer, and the performance will be consistent. The process formula and completion effect of B&S PVD are exactly the same as those of the single wafer, and the subsequent Cu electrochemical plating and other processes and completion effects will not change with the change of the number of stacked wafer layers, and are exactly the same as those of the single wafer. In summary, in the embodiment of the present invention, the process formulas and final completion effects of B&S PVD, Cu electrochemical plating, etc. will not change with the number of stacked layers, and the process consistency is better.

[0047] Furthermore, in embodiments of the present invention, a secondary trimming process is no longer required. In prior art processes, factors such as the chemical mechanical polishing (CMP) and bonding processes often result in poor edge bonding (bubble defects at the edge). After subsequent thinning, there are concerns that the stacked wafer edge strength will not withstand subsequent processes, so a secondary trimming process is performed to remove the fragile edge portions. Removing the edge portions of the stacked wafers also addresses the issue of B&S PVD discontinuity and electrochemical plating power failure caused by bonding gaps. However, with current process optimizations, edge bonding is sufficiently good that secondary trimming is no longer necessary from the perspective of edge bonding strength. However, from the perspective of B&S continuity and electrochemical plating power, secondary trimming is still required in the prior art process, wasting some wafer area. If N layers of wafers are stacked, and only one trimming process is required, a total of N-1 trimming operations are required. If secondary trimming is required for each operation, 2*(N-1) trimming operations are required. When multiple wafers are stacked, secondary trimming will waste a large amount of effective area. At the same time, as the wafer is trimmed multiple times, the difference between it and the conventional wafer becomes greater and the symmetry becomes worse. This will cause abnormalities in the later process due to changes in the wafer structure. In summary, this solution does not require secondary trimming, reduces the number of trimming times, increases the available chip area, reduces the change in wafer morphology, and ensures the normal progress of subsequent processes.

[0048] Since the stacked wafers will subsequently need to undergo Damascus etching, the Cu seed layer at the bonding gap will break if a conventional B&S process is performed after each Damascus etching process. Therefore, the special B&S PVD process of the present invention is performed after each etching and before the conventional B&S PVD process to ensure that the subsequent electrochemical plating can proceed normally. This also ensures that the process recipes for each B&S and subsequent electrochemical plating process remain unchanged, and ultimately, the completion results of all subsequent processes remain unchanged compared to a single wafer.

[0049] In summary, the bonding chip manufacturing method according to the embodiment of the present invention has the following advantages:

[0050] The present invention only needs to add a special B&S PVD process, which only needs to change the relative position of the wafer and the target deposition direction (by Figure 10 As shown, this can be achieved by adjusting the position of the target or the position of the wafer), and the rest is similar to conventional B&SPVD, with low process difficulty.

[0051] After adopting the special B&S PVD process of the present invention, B&S can be deposited uniformly and continuously not only at the bonding gap, but also on the sidewall of the wafer. In this way, there is no need to consider the special morphology of the bonding gap and sidewall of the stacked wafer compared to the conventional single wafer. The conventional B&S PVD and Cu electrochemical plating process formula of the single wafer can be used, which greatly reduces the process development cycle and process difficulty. The final structure produced (PVD B&S and electrochemical plating Cu thickness composition) is also consistent with the structure of the original verified single wafer production, ensuring the consistency of product performance. In summary, whether B&S PVD and Cu electrochemical plating and other subsequent processes are performed on several layers of stacked wafers, they are consistent with the single wafer process formula and the completion effect is consistent. There is no need for secondary trimming, which increases the effective area of the wafer. At the same time, the symmetry of the wafer structure is guaranteed, and the structural difference between it and the single conventional wafer is minimized as much as possible to ensure the normal progress of the subsequent process.

[0052] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0053] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0054] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

[0055] The above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention and are not intended to limit the embodiments of the present invention. Those skilled in the art will appreciate that other variations or modifications may be made based on the above description. It is not necessary and impossible to enumerate all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the claims of the present invention.

Claims

1. A method for manufacturing a bonded chip with improved electrical performance, characterized in that: include: Step S1, stacking and bonding at least a first wafer and a second wafer to form a wafer stack structure; Step S2, etching the wafer stack structure to form a through silicon via conductive pattern layer; Step S3, forming a barrier layer / seed layer on the outer surface of the wafer stack structure and the surface of the through silicon via conductive pattern layer in a manner that no gap is generated on the side of the bonding layer of the wafer stack structure; Step S4: performing electrochemical deposition on the barrier layer / seed layer to form a copper plating layer.

2. The method for manufacturing a bonded chip according to claim 1, wherein: In the step S3, before forming the barrier layer / seed layer, it also includes a step S31: adjusting the tilt direction of the wafer stacking structure or the deposition direction of the physical vapor deposition target or both, to form a relative tilt angle between the placement direction of the wafer stacking structure and the deposition direction of the physical vapor deposition target.

3. The method for manufacturing a bonded chip according to claim 1, wherein: In the step S31 , a relative inclination angle between the wafer stacking structure and the deposition direction of the physical vapor deposition target is greater than or equal to 45° and less than or equal to 90°.

4. The method for manufacturing a bonded chip according to claim 3, wherein: In the step S31 , the relative inclination angle between the wafer stacking structure and the deposition direction of the physical vapor deposition target is greater than or equal to 60° and less than or equal to 90°.

5. The method for manufacturing a bonded chip according to claim 4, wherein: In step S31 , the relative inclination angle between the wafer stacking structure and the deposition direction of the physical vapor deposition target is equal to 90°.

6. The method for manufacturing a bonded chip according to claim 1, wherein: The method further comprises step S5 of detecting the side step coverage capability of the barrier layer / seed layer covering the wafer stack structure through a conductive test.

7. The method for manufacturing a bonded chip according to claim 6, wherein: The method further comprises step S6 , wherein if the side step coverage capability does not reach the product design threshold, step S3 is repeated to continue growing the barrier layer / seed layer. 8 . A bonded chip with improved electrical performance produced by the bonded chip manufacturing method according to claim 1 .

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