Semiconductor device

Abstract

A semiconductor device includes at least one pixel sensor and an optical blocking region. The optical blocking region is adjacent to the at least one pixel sensor and includes a substrate, a dielectric layer, and a metal layer. The dielectric layer is over the substrate. A metal layer is over the dielectric layer, includes a nanoscale grid and is configured to reflect light away from the at least one pixel sensor. The optical blocking region formed with the patterned metal reduces reflection of light toward a plurality of pixel sensors in the pixel sensor array. The optical blocking region may be formed from a metal nano-scale grid to reflect more light away from the pixel sensors. The optical barrier region may include a dielectric layer that supports patterned metal, with high absorption structures or shallow deep trench isolation structures, in order to increase absorption, and thus reduce reflection of light toward the pixel sensors.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having an optical blocking region of a pixel sensor. Background Art

[0002] Complementary metal oxide semiconductor (CMOS) image sensor (CIS) devices use light-sensitive CMOS circuits to convert light energy into electrical energy. The light-sensitive CMOS circuits may include photodiodes formed in a silicon substrate. When the photodiode is exposed to light, a charge (called photocurrent) is induced in the photodiode. The photodiode may be coupled to a switching transistor that is used to sample the charge of the photodiode. Color may be determined by placing a filter over the light-sensitive CMOS circuit.

[0003] The light received by the pixel sensors of a CMOS image sensor device is often based on the three primary colors: red, green, and blue (R, G, B). The pixel sensors that sense light for each color can be defined by the use of color filters that allow wavelengths of light of a specific color to enter the photodiode. Some pixel sensors may include a near infrared (NIR) bandpass filter that blocks visible light and passes near infrared light to the photodiode. Utility Model Content

[0004] Some embodiments of the present disclosure provide a semiconductor device, comprising: at least one pixel sensor and an optical blocking region. The optical blocking region is adjacent to the at least one pixel sensor and comprises: a substrate, a dielectric layer, and a metal layer. The dielectric layer is above the substrate. The metal layer is above the dielectric layer, comprises a nanoscale grid and is configured to reflect light away from the at least one pixel sensor.

[0005] Other embodiments of the present disclosure provide a semiconductor device comprising: at least one pixel sensor and an optical blocking region. The optical blocking region is adjacent to the at least one pixel sensor and comprises: a substrate, a dielectric layer, and a metal layer. The dielectric layer is above the substrate and includes a recessed pattern. The metal layer is above the dielectric layer, has a shape consistent with the recessed pattern and is configured to reflect light away from the at least one pixel sensor. The metal layer additionally forms a metal grid, the metal grid is above an isolation structure, and the isolation structure at least partially surrounds at least one photodiode in the at least one pixel sensor.

[0006] Still other embodiments of the present disclosure provide a semiconductor device comprising: at least one pixel sensor and an optical blocking region. The optical blocking region is adjacent to the at least one pixel sensor and comprises: a substrate, a dielectric layer, and a metal layer. The dielectric layer is above the substrate and includes a recessed pattern. The substrate includes the recessed pattern below the dielectric layer. The metal layer is above the dielectric layer, has a shape consistent with the recessed pattern and is configured to reflect light away from the at least one pixel sensor. The metal layer additionally forms a metal grid, the metal grid is above an isolation structure, and the isolation structure at least partially surrounds at least one photodiode in the at least one pixel sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure can be described in detail below and in conjunction with the accompanying Figure 1 Please read together for the best understanding. It is noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a schematic diagram of an example environment in which the systems and / or methods described herein are implemented;

[0009] Figure 2 is a schematic diagram of an image sensor device according to an embodiment described herein;

[0010] FIG. 3A to FIG. 3D is a schematic diagram of a semiconductor device according to an embodiment described herein;

[0011] FIG. 4A to FIG. 4N is a schematic diagram of an implementation of the example embodiments described herein;

[0012] FIG. 5A to FIG. 5K is a schematic diagram of an implementation of the example embodiments described herein;

[0013] FIG. 6A to FIG. 6N is a schematic diagram of an implementation of the example embodiments described herein;

[0014] FIG. 7A to FIG. 7N is a schematic diagram of an implementation of the example embodiments described herein;

[0015] FIG. 8A to FIG. 8N is a schematic diagram of an implementation of the example embodiments described herein;

[0016] Fig. 9 This article describes Figure 1 schematic diagrams of components of multiple embodiments of one or more devices;

[0017] Fig.10is a flow chart of an example process associated with forming the semiconductor devices described herein.

[0018]

Explanation of symbols

[0019] 100: Environment

[0020] 102:Deposition tools (semiconductor process tools)

[0021] 104: Exposure tools (semiconductor process tools)

[0022] 106: Developer tool (semiconductor process tool)

[0023] 108: Etching tools (semiconductor process tools)

[0024] 110: Planarization tools (semiconductor process tools)

[0025] 112: Plating tools (semiconductor process tools)

[0026] 114: Photoresist removal tool (semiconductor process tool)

[0027] 116: Annealing tools (semiconductor process tools)

[0028] 118: Wafer / die transfer tool

[0029] 200: Image sensor device

[0030] 202: Pixel sensor array

[0031] 204: Pixel sensor

[0032] 206: Optical blocking area

[0033] 208: Electrical pad area

[0034] 300: Embodiment Image Sensor Device

[0035] 302: Intermetallic dielectric layer

[0036] 304: Interlayer dielectric layer

[0037] 306:Substrate

[0038] 308: Photodiode

[0039] 310: Isolation Structure

[0040] 312: Anti-reflective coating

[0041] 314: Dielectric layer

[0042] 316: Adhesive layer

[0043] 318:Metal layer

[0044] 320:Metal Grid

[0045] 322: Color filter area

[0046] 324: Dielectric layer

[0047] 326: Microlens layer

[0048] 328: Metallization layer

[0049] 330: Shallow trench isolation area

[0050] 332: concave part

[0051] 334: Dielectric layer

[0052] 336: Electrical pad

[0053] 338: Sensing area

[0054] 340:Nanoscale Metal Grid

[0055] 342: Ground node

[0056] 344:Metal Structure

[0057] 350: Embodiment Image Sensor Device

[0058] 352: Concave pattern

[0059] 360: Embodiment Image Sensor Device

[0060] 362: Concave pattern

[0061] 364: Highly absorbent structure

[0062] 370: Embodiment Image Sensor Device

[0063] 372: Concave pattern

[0064] 374: Shallow Isolation Structure

[0065] 400: Example implementation method

[0066] 402: concave part

[0067] 404: concave part

[0068] 406: concave part

[0069] 408: Opening

[0070] 410: Opening

[0071] 500: Example implementation method

[0072] 502: concave part

[0073] 504: concave part

[0074] 506: concave part

[0075] 508: Opening

[0076] 600: Example implementation method

[0077] 602: concave part

[0078] 604: concave part

[0079] 606: concave part

[0080] 608: Opening

[0081] 610: Opening

[0082] 700: Example implementation

[0083] 702: concave part

[0084] 704: concave part

[0085] 706: concave part

[0086] 708: Opening

[0087] 710: Opening

[0088] 800: Example implementation method

[0089] 802: concave part

[0090] 804: concave part

[0091] 806: concave part

[0092] 808: Opening

[0093] 810: Opening

[0094] 900: Device

[0095] 910: Bus

[0096] 920: Processor

[0097] 930: Memory

[0098] 940: Input Component

[0099] 950: Output component

[0100] 960: Communication components

[0101] 1000: Craftsmanship

[0102] 1010: Block

[0103] 1020: Block

[0104] 1030: Block

[0105] 1040: Block

[0106] AA:Line

[0107] B: Blue

[0108] d: Depth

[0109] G: Green

[0110] R: Red

[0111] s:interval

[0112] w: width

[0113] θ: angle DETAILED DESCRIPTION

[0114] The disclosure that follows provides many different implementations or embodiments for implementing different features of the provided subject matter. Specific embodiments of components and arrangements are described below to simplify the disclosure. Of course, these are merely embodiments and are not restrictive. For example, in the subsequent description, a first feature is formed above or on a second feature, and an implementation in which the first feature and the second feature are formed in direct contact may be included, and an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numerals and / or letters in various embodiments. Such repetition is for the purpose of simplification and clarity, and the repetition itself does not mean the relationship between the various embodiments and / or configurations discussed.

[0115] Additionally, to facilitate description of the relationship of one element or feature to another element or feature as depicted in the figures, spatially relative terms may be used herein, such as "below," "below," "lower," "above," "upper," and the like. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly accordingly.

[0116] An image sensor device (e.g., a complementary metal oxide semiconductor (CMOS) image sensor (CIS) device) may include a black level correction (BLC) region adjacent to and / or surrounding a pixel sensor array of the image sensor device. The black level correction region includes one or more layers of light blocking material that prevent light from entering the sensing region below the one or more layers. The sensing region is "dark" because the one or more layers prevent incident light from entering the sensing region, which enables the sensing region to generate a dark current measurement for black level correction (or black level calibration) of the pixel sensor array. Dark current is a current generated in the image sensor device due to energy sources other than incident light. Dark current can be caused by, for example, heat generated by the image sensor device and / or by one or more other devices in the vicinity of the image sensor device. Dark current can cause noise and other defects in images and / or videos captured by the image sensor device. For example, dark current may artificially increase the photocurrent generated by pixel sensors in a pixel sensor array, which may cause black levels to increase and / or may cause some pixels in an image or video to register as white pixels or hot pixels.

[0117] The light blocking material used in the black level correction area may be metallic and reflective. While the high reflectivity may result in improved light blocking performance, the reflectivity of the light blocking material also causes light to be reflected toward the plurality of pixel sensors in the pixel sensor array. The light reflected toward the plurality of pixel sensors in the pixel sensor array may cause flares or hot spots (e.g., areas of increased brightness) in images and / or videos generated by the image sensor device and / or may degrade the image quality of the images and / or videos generated by the image sensor device.

[0118] Some embodiments described herein provide techniques and apparatus for optical blocking regions with patterned metal to reduce light reflection toward a plurality of pixel sensors in a pixel sensor array. In some embodiments, the optical blocking region may be formed by a metal nanoscale grid to reflect more light away from the pixel sensors. In some embodiments, the optical blocking region may include a dielectric layer supporting the metal with a plurality of high absorption (HA) structures or a plurality of shallow deep trench isolation (DTI) structures to increase absorption and thereby reduce light reflection toward the plurality of pixel sensors. The optical blocking region may reduce the likelihood of occurrence of flashes or hot spots in images and / or videos generated by an image sensor device, which may increase the image quality of the images and / or videos generated by the image sensor device.

[0119] Figure 1 1 is a schematic diagram of an embodiment environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown in , environment 100 may include multiple semiconductor process tools 102 to 116 and a wafer / die transfer tool 118. Multiple semiconductor process tools 102 to 116 may include a deposition tool 102, an exposure tool 104, a developer tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, a photoresist removal tool 114, an annealing tool 116, and / or another semiconductor process tool. The multiple tools included in the embodiment environment 100 may be included in a semiconductor clean room, a semiconductor manufacturing plant, a semiconductor process and / or manufacturing facility, or another location.

[0120] The deposition tool 102 is a semiconductor process tool that includes a semiconductor process chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate (e.g., a wafer). In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, an epitaxial tool, or another type of chemical vapor deposition tool. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, embodiment environment 100 includes multiple types of deposition tools 102 .

[0121] The exposure tool 104 is a semiconductor process tool capable of exposing the photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep ultraviolet light source, an extreme ultraviolet light (EUV) source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a mask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include patterns for forming one or more structures of a semiconductor device, may include patterns for etching various portions of a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0122] The developer tool 106 is a semiconductor process tool capable of developing the photoresist layer that has been exposed to the radiation source to develop the pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developer tool 106 develops the pattern by removing multiple unexposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing multiple exposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by dissolving multiple exposed portions or multiple unexposed portions of the photoresist layer through the use of a chemical developer.

[0123] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and / or the like. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may etch one or more portions of the substrate using plasma etching or plasma-assisted etching, which may involve using ionized gas to etch one or more portions isotropically or directionally.

[0124] The planarization tool 110 is a semiconductor process tool capable of grinding or flattening individual layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool, and / or another type of planarization tool that grinds or flattens a layer or surface of a deposited or plated material. The planarization tool 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and abrasive-free grinding) to grind or flatten the surface of a semiconductor device. The planarization tool 110 may utilize grinding and corrosive chemical slurries, in combination with a grinding pad and a fixed ring (e.g., typically having a larger diameter than the semiconductor device). The grinding pad and the semiconductor device may be pressed together via a dynamic grinding head and maintained in a fixed position via a fixed ring. The dynamic grinding head may be rotated with different rotation axes to remove material and flatten any irregular topography of the semiconductor device, so that the semiconductor device becomes flat or flat.

[0125] The plating tool 112 is a semiconductor process tool capable of plating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion of a substrate with one or more metals. For example, the plating tool 112 may include a copper plating device, an aluminum plating device, a nickel plating device, a tin plating device, a compound material or alloy (e.g., tin-silver, tin-lead, and / or the like) plating device, and / or a plating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0126] The photoresist removal tool 114 is a semiconductor processing tool capable of removing remaining portions of a photoresist layer from a substrate after portions of the substrate are removed by the etching tool 108. For example, the photoresist removal tool 114 may use a chemical stripper and / or another technique to remove the photoresist layer from the substrate.

[0127] The annealing tool 116 is a semiconductor process tool including a semiconductor process chamber and one or more devices capable of heating a semiconductor substrate or a semiconductor device. For example, the annealing tool 116 may include a rapid thermal annealing (RTA) tool or another type of annealing tool capable of heating a semiconductor substrate to cause a reaction between two or more materials or gases to cause material decomposition. As another embodiment, the annealing tool 116 may be configured to heat (e.g., increase or raise the temperature) a structure or layer (or a portion thereof) to reflow the structure or layer, or to crystallize the structure or layer to remove defects such as voids or seams. As another embodiment, the annealing tool 116 may be configured to heat (e.g., increase or raise the temperature) a layer (or a portion thereof) to enable bonding of two or more semiconductor devices.

[0128] In other embodiments, the wafer / die transfer tool 118 may be included in a cluster tool or in another type of tool including multiple process chambers, and may be configured to transfer substrates and / or semiconductor devices between multiple process chambers, to transfer substrates and / or semiconductor devices between a process chamber and a buffer area, to transfer substrates and / or semiconductor devices between a process chamber and an interface tool (e.g., an equipment front end module (EFEM)), and / or to transfer substrates and / or semiconductor devices between a process chamber and a transfer carrier (e.g., a frontopening unified pod (FOUP)). In some embodiments, the wafer / die transfer tool 118 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-clean process chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from a substrate and / or semiconductor device), and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations).

[0129] In some embodiments, one or more of the plurality of semiconductor process tools 102 to 116 and / or the wafer / die transfer tool 118 can perform one or more semiconductor process operations described herein. For example, in other embodiments, one or more of the plurality of semiconductor process tools 102 to 116 and / or the wafer / die transfer tool 118 can form an isolation structure in the substrate, the isolation structure surrounding at least one photodiode; pattern a portion of the substrate corresponding to the optical blocking area to form a recessed pattern; form a dielectric layer over the isolation structure and over the portion of the substrate corresponding to the optical blocking area, such that the dielectric layer has a shape consistent with the recessed pattern; and / or form a metal layer over the dielectric layer, such that the metal layer conforms to the recessed pattern in the optical blocking area.

[0130] Provided in Figure 1 The number and arrangement of tools shown in FIG. are provided as one or more embodiments. Figure 1 There may be additional multiple tools, fewer tools, different tools, or differently arranged tools compared to the multiple tools shown in . Figure 1 Two or more of the tools shown in may be implemented in a single tool, or in Figure 1 The single tool shown in the embodiment may be implemented as multiple distributed tools. Additionally or alternatively, a set of multiple tools (e.g., one or more tools) of environment 100 may perform one or more functions that are described as being performed via another set of multiple tools of environment 100.

[0131] Figure 2 2 is a schematic diagram of a top view of an image sensor device 200 of an embodiment described herein. Image sensor device 200 may include a CMOS image sensor, a back side illuminated (BSI) CMOS image sensor, and / or another type of image sensor. Image sensor device 200 may be configured to be deployed in various embodiments, such as digital cameras, video recorders, night vision cameras, automotive sensors and cameras, and / or other types of light sensing embodiments.

[0132] Image sensor device 200 may include pixel sensor array 202. Figure 2 As shown in , pixel sensor array 202 may include a plurality of pixel sensors 204. Figure 2 As further shown in FIG. 1 , the pixel sensors 204 can be arranged in a grid. In some embodiments, the pixel sensors 204 are square (e.g., Figure 2 In some embodiments, the pixel sensor 204 includes other shapes, such as a circle, an octagon, a diamond, and / or other shapes.

[0133] Pixel sensor 204 may be configured to sense and / or accumulate incident light (e.g., light directed toward pixel sensor array 202). For example, pixel sensor 204 may absorb and accumulate multiple photons of the incident light in a photodiode. The accumulation of photons in the photodiode may generate a charge representing the intensity or brightness of the incident light (e.g., a larger amount of charge may correspond to a greater intensity or brightness, while a lower amount of charge may correspond to a lower intensity or brightness).

[0134] Pixel sensor array 202 may be electrically connected to a back-end-of-line (BEOL) metallization stack (not shown) of an image sensor. The BEOL metallization stack may electrically connect pixel sensor array 202 to control circuitry that may be used to measure the accumulation of incident light in pixel sensor 204 and convert the measurement results into electrical signals.

[0135] As in Figure 2As further shown in , image sensor device 200 may include optical blocking region 206 adjacent to and / or surrounding pixel sensor array 202. Optical blocking region 206 includes one or more layers of light blocking material that prevents light from entering the sensing region below the one or more layers. The sensing region is "dark" because the one or more layers prevent incident light from entering the sensing region. This enables the sensing region to generate dark current measurements for black level correction (or black level calibration) of pixel sensor array 202. Optical blocking region 206 may be located from about 25 microns to about 200 microns from the edge of image sensor device 200. However, other values ​​for this range are also within the scope of the present disclosure.

[0136] As in Figure 2 As further shown in FIG. 2 , image sensor device 200 may include an electrical pad region 208 (also referred to as an e-pad region) adjacent to optical blocking region 206. Electrical pad region 208 may include one or more metallization layers (e.g., conductive bonding pads, e-pads, metallization layers, vias) through which electrical connections may be established between image sensor device 200 and external devices and / or external packages.

[0137] In some embodiments, image sensor device 200 includes one or more other regions, such as scribe line regions, which separate one semiconductor die or a portion of a semiconductor die (including image sensor device 200) from an adjacent semiconductor die or a portion of a semiconductor die (including other image sensor devices and / or other integrated circuits).

[0138] As mentioned above, providing Figure 2 As an example, other embodiments may differ from the Figure 2 The content described.

[0139] FIG. 3A to FIG. 3D is a schematic diagram of an embodiment semiconductor device described herein. The embodiment semiconductor device may be an embodiment image sensor device, which may be configured as Figure 2 The image sensor device 200 of the present invention or is included in the image sensor device 200. Each semiconductor device includes an optical blocking region formed by patterned metal to increase light reflected away from the pixel sensor array and reduce light reflected toward the pixel sensor array.

[0140] Figure 3A is a schematic diagram of a cross-sectional view of an image sensor device 300 according to an embodiment described herein. The cross section is taken along Figure 2 The line AA in FIG. 1 is shown. Therefore, Figure 3AMultiple cross-sectional structures and / or multiple layers of a subset of image sensor device 200 are depicted, including pixel sensor array 202 , optical blocking region 206 , and electrical pad region 208 .

[0141] As in Figure 3A As shown in , the embodiment image sensor device 300 may include various layers and / or structures. In some embodiments, during one or more semiconductor process operations, the embodiment image sensor device 300 is mounted and / or manufactured on a carrier substrate (not shown) to form the embodiment image sensor device 300. The embodiment image sensor device 300 may include an intermetal dielectric (IMD) layer 302, an interlayer dielectric (ILD) layer 304 above and / or on the intermetal dielectric layer 302, and a substrate 306 above and / or on the interlayer dielectric layer 304. The intermetal dielectric layer 302 and the interlayer dielectric layer 304 may each include one or more layers of dielectric material (e.g., silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide, and / or another dielectric material). The substrate 306 may be formed of silicon (Si), a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), a silicon on insulator (SOI), or another type of semiconductor material capable of generating charges from photons of incident light.

[0142] Various metallization layers may be formed in multiple layers of the intermetallic dielectric layer 302 and / or between multiple layers. The metallization layers may include bonding pads, wires, and / or other types of conductive structures that electrically connect various regions of the image sensor device 200 and / or electrically connect various regions of the embodiment image sensor device 300 to one or more external devices and / or external packages. The metallization layers may also be referred to as back-end process metallization stacks, and in other embodiments, may include conductive materials such as gold (Au), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), ruthenium (Ru), metal alloys, and / or combinations thereof. The back-end process metallization stack may electrically connect the pixel sensor array 202, the optical blocking region 206, and / or the electrical pad region 208 to a device die on which the integrated processing circuitry is included in various embodiments, where the embodiment image sensor device 300 includes multiple stacked and bonded semiconductor dies.

[0143] A photodiode 308 for a pixel sensor 204 in the pixel sensor array 202 may be included in a substrate 306. The photodiode 308 may include a region of the substrate 306 doped with multiple types of ions to form a pn junction or a PIN junction (e.g., a junction between a p-type portion, an intrinsic (or undoped) type portion, and an n-type portion). For example, the substrate 306 may be doped with an n-type dopant to form a first portion (e.g., an n-type portion) of the photodiode 308, and doped with a p-type dopant to form a second portion (e.g., a p-type portion) of the photodiode 308. The photodiode 308 may be configured to absorb multiple photons of incident light. The absorption of the multiple photons causes the photodiode 308 to accumulate charge (referred to as a photocurrent) due to the photoelectric effect. Here, the multiple photons bombard the photodiode 308, which causes the emission of multiple electrons of the photodiode 308. The emission of the multiple electrons causes the formation of electron-hole pairs, wherein the electrons migrate toward the cathode of the photodiode 308 and the holes migrate toward the anode, which generates the photocurrent.

[0144] Isolation structure 310 may be included in substrate 306. Isolation structure 310 may include a plurality of trenches extending from a top surface of substrate 306 and into substrate 306 around a plurality of photodiodes 308 of a plurality of pixel sensors 204. In this manner, photodiodes 308 are surrounded by the plurality of trenches of isolation structure 310. In some embodiments, isolation structure 310 may be a deep trench isolation (DTI) structure, such as a backside deep trench isolation (BDTI) structure, formed as part of a backside process of an embodiment image sensor device 300.

[0145] The plurality of trenches of the isolation structure 310 may provide optical isolation between the plurality of pixel sensors 204 in the pixel sensor array 202, which may reduce the amount of optical crosstalk between the plurality of adjacent pixel sensors 204. Specifically, the plurality of trenches of the isolation structure 310 may absorb, refract, and / or reflect incident light, which may reduce the amount of incident light that travels through a pixel sensor 204 into an adjacent pixel sensor 204 and is absorbed by the adjacent pixel sensor 204.

[0146] The surface of the isolation structure 310 may be coated with an antireflective coating (ARC) 312 to reduce reflection of incident light away from the photodiode 308 and increase transmission of the incident light into the substrate 306 and into the photodiode 308. The antireflective coating 312 may include a suitable material for reducing reflection of incident light projected toward the photodiode 308, such as a nitrogen-containing material or other embodiments.

[0147] Isolation structure 310 may include dielectric layer 314 above substrate 306 and above and / or on anti-reflective coating 312. In addition, dielectric layer 314 may fill multiple trenches of isolation structure 310. Dielectric layer 314 may be combined with adhesion layer 316 between substrate 306 and multiple upper layers of pixel sensor array 202. Adhesion layer 316 may extend above isolation structure 310 to promote adhesion between silicon of substrate 306 and metal layer 318 above substrate 306. In some embodiments, dielectric layer 314 and adhesion layer 316 may be a material including, for example, silicon oxide (SiO x ) of an oxide material. In some embodiments, silicon nitride (SiN x ), Silicon Carbide (SiC x ), or a mixture thereof, such as silicon carbon nitride (SiCN), silicon oxynitride (SiON), or another dielectric material is used instead of dielectric layer 314 as adhesion layer 316.

[0148] The metal layer 318 may be located above and / or on the adhesion layer 316. The metal layer 318 may extend laterally across the pixel sensor array 202. A metal grid 320 may be formed in the metal layer 318 in the pixel sensor array 202 to provide optical isolation between the plurality of pixel sensors 204 in the pixel sensor array 202. The metal grid 320 may include pillars or posts surrounding the pixel sensors 204. The pillars or posts of the metal grid 320 may be located above the plurality of trenches of the isolation structure 310. In other embodiments, the metal layer 318 may be formed of a metal material, such as gold (Au), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), ruthenium (Ru), a metal alloy (e.g., aluminum copper (AlCu)), and / or combinations thereof.

[0149] A plurality of color filter regions 322 of the pixel sensor 204 may be included between the metal grids 320. In other words, a plurality of color filter regions 322 may be included in place of a plurality of removed portions of the metal layer 318 above the photodiode 308. Each color filter region 322 may be configured to filter incident light to allow incident light of a particular wavelength to pass through the photodiode 308 of the associated pixel sensor 204. For example, the color filter region 322 included in the pixel sensor 204 may filter red light (and thus, the pixel sensor 204 may be a red pixel sensor). As another embodiment, the color filter region 322 included in the pixel sensor 204 may filter green light (and thus, the pixel sensor 204 may be a green pixel sensor). As another embodiment, the color filter region 322 included in the pixel sensor 204 may filter blue light (and thus, the pixel sensor 204 may be a blue pixel sensor).

[0150] The blue filter region may allow components of incident light having a wavelength of about 450 nanometers to pass through the color filter region 322 and block other wavelengths from passing through. The green filter region may allow components of incident light having a wavelength of about 550 nanometers to pass through the color filter region 322 and block other wavelengths from passing through. The red filter region may allow components of incident light having a wavelength of about 650 nanometers to pass through the color filter region 322 and block other wavelengths from passing through. The yellow filter region may allow components of incident light having a wavelength of about 580 nanometers to pass through the color filter region 322 and block other wavelengths from passing through.

[0151] In some embodiments, the color filter region 322 may be non-discriminating or non-filtering, which may define a white pixel sensor. The non-discriminating or non-filtering color filter region 322 may include a material that allows all wavelengths of light to enter the associated photodiode 308 (e.g., to determine overall brightness to increase light sensitivity for an image sensor). In some embodiments, the color filter region 322 may be a near infrared (NIR) bandpass color filter region, which may define a near infrared pixel sensor. The near infrared bandpass color filter region 322 may include a material that allows the portion of incident light in the near infrared wavelength range to pass through the associated photodiode 308 while blocking visible light from passing through.

[0152] One or more passivation layers may be formed above and / or on metal layer 318. For example, dielectric layer 324 may be disposed above and / or on portions of metal layer 318. In some embodiments, dielectric layer 324 may also be included above optical blocking region 206 and / or at least a portion of electrical pad region 208, such as in Figure 3A The dielectric layer 324 may include, for example, silicon oxide (SiO x ) oxide material. Additionally and / or alternatively, silicon nitride (SiN x ), Silicon Carbide (SiC x ), or a mixture thereof, such as silicon carbon nitride (SiCN), silicon oxynitride (SiON), or another dielectric material to replace the dielectric layer 324.

[0153] A microlens layer 326 may be included above and / or on the color filter region 322 and above and / or on the metal grid 320. The microlens layer 326 may include a respective microlens for each of the plurality of pixel sensors 204. The microlenses may be formed to focus incident light toward the photodiode 308 of the pixel sensor 204.

[0154] As shown in the electrical pad region 208 of the embodiment image sensor device 300, a plurality of electrical connections may be formed to connect to the metallization layer 328 in the intermetal dielectric layer 302. A shallow trench isolation (STI) region 330 may be located above the metallization layer 328 and / or over the metallization layer 328. The shallow trench isolation region 330 may provide electrical isolation in the electrical pad region 208. The shallow trench isolation region 330 may be located below and / or below a recess 332 in the electrical pad region 208. Above the shallow trench isolation region 330, a dielectric layer 334 (e.g., a buffer oxide layer) may be included in the recess 332, on the sidewalls of the recess 332, and on the bottom surface. The electrical pad 336 may be located in the electrical pad region 208, above the shallow trench isolation region 330, and / or above and / or on the dielectric layer 334. The electrical pad 336 may extend through the dielectric layer 334, through the shallow trench isolation region 330, and through the interlayer dielectric layer 304 to the intermetallic dielectric layer 302, and may contact the metallization layer 328 in the intermetallic dielectric layer 302. In other embodiments, the electrical pad 336 may include a conductive material, such as gold (Au), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), ruthenium (Ru), a metal alloy (e.g., aluminum copper (AlCu)), and / or a combination thereof.

[0155] As shown in the optical blocking region 206, a sensing region 338 may be included in the substrate 306. The sensing region 338 may include a portion of the substrate 306 below the metal layer 318. The optical blocking region 206 also includes a nanoscale metal grid 340 that functions as a light blocking region to prevent light from entering the sensing region 338. This enables the sensing region 338 to generate dark current measurements for black level correction (or black level calibration) of the pixel sensor array 202.

[0156] In some embodiments, the optical blocking region 206 may include a ground node 342 that connects (electrically and physically) the nanoscale metal grid 340 to the substrate 306. The ground node 342 maintains the nanoscale metal grid 340 in electrical neutrality even if photons collide with the nanoscale metal grid 340. As a result, current does not leak from the nanoscale metal grid 340 to the pixel sensor array 202, which improves the performance of the embodiment image sensor device 300.

[0157] As further indicated by reference numeral 344 (Metal Structure), the nanoscale metal grid 340 includes a plurality of metal structures 344, each metal structure 344 having a width ranging from about 100 nanometers (nm) to about 200 nm. Selecting a width of at least 100 nanometers preserves the reflective properties of the metal structures, making it less likely that light will pass through the metal structures and enter the pixel sensor array 202. Selecting a width of no more than 200 nanometers increases the density of the metal structures, making it more likely that light will be reflected rather than pass through the nanoscale metal grid 340 and enter the pixel sensor array 202. Thus, the metal grid is "nanoscale" because each metal structure of the metal grid has a dimension (e.g., width and / or height) less than about 250 nanometers.

[0158] Nanoscale metal grid 340 reduces the likelihood of light being reflected off the metal in optical blocking region 206 and directed toward pixel sensor array 202. In this manner, nanoscale metal grid 340 reduces the likelihood of the occurrence of flares or hot spots in images and / or videos produced by embodiment image sensor device 300, which improves image quality.

[0159] Figure 3B is a schematic diagram of a cross-sectional view of an image sensor device 350 according to an embodiment described herein. The cross section is taken along Figure 2 The diagram is shown by line AA in FIG. Figure 3B Similar to Figure 3A , except that the optical blocking region 206 includes a pattern 352 of depressions in the metal (e.g., a portion of the metal layer 318 in the optical blocking region 206) that functions as a light blocking region to prevent light from entering the sensing region 338. This enables the sensing region 338 to generate dark current measurements for black level correction (or black level calibration) of the pixel sensor array 202.

[0160] As in Figure 3B As further shown in FIG. 2 , a portion of the adhesive layer 316 in the optical blocking region 206 has a shape that is consistent with the recessed pattern 352. As a result, as shown in FIG. Figure 6H As described, during deposition, a portion of the metal layer 318 in the optical blocking region 206 will follow the recessed pattern 352. The metal layer 318 may include a plurality of metal structures that protrude above the top surface of the metal layer 318. Each metal structure may be larger than the "nanoscale" structures described above (e.g., having a width and / or height greater than 250 nanometers). Because the larger metal structures are formed via the recessed pattern 352 in the adhesion layer 316, fewer lithography processes are used than to form smaller metal structures.

[0161] In some embodiments, such as in combination Fig. 6FAs described above, in order to simplify the patterning of the adhesive layer 316, a portion of the adhesive layer 316 in the pixel sensor array 202 may also have a shape consistent with the recessed pattern 352. As a result, as in Figure 3B As shown in , a portion of metal layer 318 in pixel sensor array 202 will also follow pattern of recesses 352 during deposition.

[0162] Figure 3C is a schematic diagram of a cross-sectional view of an image sensor device 360 ​​according to an embodiment described herein. The cross section is taken along Figure 2 The diagram is shown by line AA in FIG. Figure 3C Similar to Figure 3A , except that the optical blocking region 206 includes a pattern 362 of depressions in the metal (e.g., a portion of the metal layer 318 in the optical blocking region 206) that functions as a light blocking region to prevent light from entering the sensing region 338. This enables the sensing region 338 to generate dark current measurements for black level correction (or black level calibration) of the pixel sensor array 202.

[0163] As in Figure 3C As further shown in FIG. 2 , a portion of the adhesive layer 316 in the optical blocking region 206 has a shape that is consistent with the recessed pattern 362. As a result, as shown in FIG. Figure 7G As described above, during deposition, a portion of the metal layer 318 in the optical blocking region 206 will follow the recessed pattern 362. In addition, a portion of the substrate 306 (and the anti-reflective coating 312 above the substrate) in the optical blocking region 206 has a shape that conforms to the recessed pattern 362. As a result, as shown in FIG. Fig. 7E As depicted, a portion of the adhesion layer 316 in the optical blocking region 206 will follow the pattern of recesses 362 during deposition.

[0164] As further indicated by reference numeral 364 (high absorbency structure), the recessed pattern 362 is caused by a plurality of high absorbency structures 364 formed in the substrate 306, and each high absorbency structure 364 is associated with an angle (e.g., an angle with the horizontal axis, in Figure 3C 306 ), this angle is in the range of about 54 degrees to about 55 degrees (in one particular embodiment, 54.7 degrees). Selecting an angle within this range preserves the crystal structure of the silicon of substrate 306, which prevents dangling bonds that could electrically interfere with pixel sensor array 202. However, other angles are within the scope of the present disclosure (e.g., when different crystal structures and / or materials are used for substrate 306). In addition, each high-absorption structure can have a spacing relative to an adjacent high-absorption structure (e.g., at the top surface of the high-absorption structure and at Figure 3C 318. The spacing may be in the range of about 0.1 nanometers to about 1.0 nanometers. Selecting a spacing of at least 0.1 nanometers prevents multiple highly absorbing structures from merging; the merged highly absorbing structures would reduce the roughness of the metal layer 318, making it more likely that light will enter the pixel sensor array 202. Selecting a spacing of no greater than 1.0 nanometers increases the density of the multiple highly absorbing structures, making the metal layer 318 present an increased roughness and, therefore, more likely to reflect light rather than allow it to enter the pixel sensor array 202. However, other spacings are also within the scope of the present disclosure.

[0165] Figure 3D is a schematic diagram of a cross-sectional view of an image sensor device 370 according to an embodiment described herein. The cross section is taken along Figure 2 The diagram is shown by line AA in FIG. Figure 3D Similar to Figure 3A , except that the optical blocking region 206 includes a pattern 372 of depressions in the metal (e.g., a portion of the metal layer 318 in the optical blocking region 206) that functions as a light blocking region to prevent light from entering the sensing region 338. This enables the sensing region 338 to generate dark current measurements for black level correction (or black level calibration) of the pixel sensor array 202.

[0166] As in Figure 3D As further shown in FIG. 2 , a portion of the adhesive layer 316 in the optical blocking region 206 has a shape that is consistent with the recessed pattern 372. As a result, as shown in FIG. Figure 8G As described above, during deposition, a portion of the metal layer 318 in the optical blocking region 206 will follow the recessed pattern 372. In addition, a portion of the substrate 306 (and the anti-reflective coating 312 above the substrate) in the optical blocking region 206 has a shape that conforms to the recessed pattern 372. As a result, as shown in FIG. Fig. 8E As depicted, a portion of the adhesion layer 316 in the optical blocking region 206 will follow the pattern of recesses 372 during deposition.

[0167] As in Figure 3D As further shown in FIG. 3 , the recessed pattern 372 is caused by a plurality of shallow isolation structures 374 (eg, shallow deep trench isolation structures (DTI)) formed in the substrate 306. Each shallow isolation structure may have a depth relative to the top surface of the substrate 306 (eg, at Figure 3DThe depth d is less than a depth of the isolation structure 310 relative to the top surface of the substrate 306. As a result, the shallow isolation structure 374 maintains the sensing area 338, which improves the accuracy of the dark current measurement used for black level correction (or black level calibration) of the pixel sensor array 202. In addition, each shallow isolation structure can have a width in the range from about 100 nanometers to about 400 nanometers (e.g., in Figure 3D Selecting a width of at least 100 nanometers results in an increased depth of the shallow isolation structures (due to the etching process), causing the metal layer 318 to exhibit increased roughness and, therefore, be more likely to reflect light rather than allow it to enter the pixel sensor array 202. Selecting a width of no more than 400 nanometers increases the density of the shallow isolation structures, causing the metal layer 318 to exhibit increased roughness and, therefore, be more likely to reflect light rather than allow it to enter the pixel sensor array 202. However, other widths are also within the scope of the present disclosure.

[0168] As mentioned above, it provides FIG. 3A to FIG. 3D As multiple embodiments. Other multiple embodiments may be related to FIG. 3A to FIG. 3D The content described is different.

[0169] FIG. 4A to FIG. 4N is a schematic diagram of an example implementation 400 described herein. Example implementation 400 may be an example process for forming example image sensor device 300 described herein. Among other examples, example image sensor device 300 may include pixel sensor array 202 (including a plurality of pixel sensors 204), optical blocking region 206 (including nanoscale metal grid 340), and electrical pad region 208. In example implementation 400, electrical pad region 208 is formed after nanoscale metal grid 340.

[0170] As in Figure 4A As shown in , among other embodiments, the embodiment image sensor device 300 may include multiple layers, including an intermetallic dielectric layer 302, an interlayer dielectric layer 304, and a substrate 306. In some embodiments, the substrate 306 may be provided as a semiconductor wafer or another type of semiconductor workpiece. In some embodiments, the deposition tool 102 may be in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combined Figure 1 The intermetal dielectric layer 302 and / or the interlayer dielectric layer 304 are deposited in another type of deposition operation as described, and / or in another suitable deposition operation. In some embodiments, after the deposition tool 102 deposits the intermetal dielectric layer 302 and / or the interlayer dielectric layer 304, the planarization tool 110 planarizes the intermetal dielectric layer 302 and / or the interlayer dielectric layer 304.

[0171] As in Figure 4A As further shown in FIG. 1 , a metallization layer 328 may be formed in the intermetallic dielectric layer 302. The intermetallic dielectric layer 302 may be formed in the electrical pad region 208 of the embodiment image sensor device 300. In some embodiments, the etching tool 108 may form a recess in the intermetallic dielectric layer 302, and the metallization layer 328 may be formed in the recess. The deposition tool 102 and / or the plating tool 112 may be operated in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, or a combination thereof. Figure 1 The metallization layer 328 is deposited in another deposition operation as described, and / or another suitable deposition operation. In some embodiments, the seed layer is deposited first, and the metallization layer 328 is deposited on the seed layer. In some embodiments, after the deposition tool 102 and / or the plating tool 112 deposits the metallization layer 328, the planarization tool 110 planarizes the metallization layer 328.

[0172] As in Figure 4A As further shown in FIG. 1 , shallow trench isolation regions 330 may be formed in substrate 306 (e.g., prior to formation of intermetallic dielectric layer 302 and / or interlayer dielectric layer 304). Shallow trench isolation regions 330 may be formed in electrical pad regions 208 of embodiment image sensor device 300. In some embodiments, deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination of Figure 1 The shallow trench isolation region 330 is deposited in another type of deposition operation as described, and / or in another suitable deposition operation. In some embodiments, after the deposition tool 102 deposits the shallow trench isolation region 330, the planarization tool 110 planarizes the shallow trench isolation region 330. In some embodiments, the etching tool 108 can form a recess in the substrate 306, and the shallow trench isolation region 330 can be formed in the recess.

[0173] As in Figure 4B , a plurality of photodiodes 308 may be formed in substrate 306. For example, an ion implantation tool may dope portions of substrate 306 using ion implantation techniques to form corresponding photodiodes 308 for a plurality of pixel sensors 204. Substrate 306 may be doped with multiple types of ions to form a pn junction for each photodiode 308. For example, substrate 306 may be doped with n-type dopants to form a first portion (e.g., n-type portion) of photodiode 308, and doped with p-type dopants to form a second portion (e.g., p-type portion) of photodiode 308. In some embodiments, another technique is used to form photodiode 308, such as diffusion.

[0174] As in Figure 4B As further shown in FIG. 1 , a sensing region 338 can be included in the substrate 306 in the optical blocking region 206 adjacent to the pixel sensor 204 of the pixel sensor array 202. In some embodiments, the sensing region 338 includes an undoped portion of the substrate 306 in the optical blocking region 206. In some embodiments, an ion implantation tool can use ion implantation techniques to dope portions of the substrate 306 to form the sensing region 338.

[0175] As in Figure 4C , recesses 402 may be formed in substrate 306 around photodiodes 308 in pixel sensor array 202. Multiple recesses 402 may be formed as part of forming isolation structures 310 in substrate 306 around multiple photodiodes 308 of multiple pixel sensors 204 in pixel sensor array 202. In some embodiments, deposition tool 102 may form a photoresist layer on substrate 306, exposure tool 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, developer tool 106 may develop and remove multiple portions of the photoresist layer to expose the pattern, and etching tool 108 may etch multiple portions of substrate 306 to form multiple recesses 402 for isolation structures 310 in substrate 306. In some embodiments, after etching tool 108 etches substrate 306, photoresist removal tool 114 removes multiple remaining portions of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0176] As in Figure 4D As shown in , an anti-reflective coating 312 may be formed above and / or on the substrate 306 and in the plurality of recesses 402. The anti-reflective coating 312 may be conformally deposited such that the anti-reflective coating 312 includes a thin film that conforms to the shape and / or contour of the recess 402. In other embodiments, the anti-reflective coating 312 may be included on the surface of the substrate 306 in the pixel sensor array 202, in the optical blocking region 206, and / or in the electrical pad region 208. The deposition tool 102 may deposit the anti-reflective coating 312 using a CVD technique, a PVD technique, an ALD technique, or another type of deposition technique.

[0177] As in Figure 4EAs shown in FIG. 4 , recess 402 may be filled with dielectric layer 314. In other embodiments, additional dielectric material may be deposited such that adhesion layer 316 extends along the surface of substrate 306 in pixel sensor array 202, in optical blocking region 206, and in electrical pad region 208. In other embodiments, deposition tool 102 may deposit dielectric layer 314 using various CVD techniques and / or ALD techniques, such as PECVD, HDP-CVD, SACVD, and / or PEALD.

[0178] As in Figure 4F As shown in , a recess 404 can be formed in the adhesive layer 316 at a portion of the optical blocking region 206 at (or near) a boundary of the pixel sensor array 202. The recess 404 can be formed as a portion of forming the ground node 342. Accordingly, the recess 404 can expose the top surface of the substrate 306. In some embodiments, the deposition tool 102 can form a photoresist layer on the adhesive layer 316, the exposure tool 104 can expose the photoresist layer to a radiation source to pattern the photoresist layer, the developer tool 106 can develop and remove multiple portions of the photoresist layer to expose the pattern, and the etching tool 108 can etch the portion of the adhesive layer 316 to form the recess 404 for the ground node 342 in the adhesive layer 316. In some embodiments, after the etching tool 108 etches the adhesive layer 316, the photoresist removal tool 114 removes multiple remaining portions of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0179] In some embodiments, as in Figure 4F As further shown in FIG. 1 , recess 406 can be formed in adhesive layer 316 at electrical pad region 208. Recess 406 can be formed as part of forming electrical pad 336. Accordingly, recess 406 can expose the top surface of substrate 306. In some embodiments, the pattern exposed via developer tool 106 can be used to form both recess 404 and recess 406. Alternatively, adhesive layer 316 can be exposed during a later etch cycle (e.g., as in combination with Figure 4J The electrical pad region 208 is etched during the etching cycle described above.

[0180] As in Figure 4GAs shown in , metal layer 318 can be formed above and / or on bonding layer 316. In other embodiments, metal layer 318 can be formed in pixel sensor array 202, in optical blocking region 206, and in electrical pad region 208. The portion of metal layer 318 in optical blocking region 206 can correspond to the light blocking layer for sensing region 338. In addition, metal layer 318 can fill recess 402 to form ground node 342. Deposition tool 102 and / or plating tool 112 can be operated in CVD, PVD, ALD, electroplating, or a combination of the above. Figure 1 The metal layer 318 is deposited in another deposition operation as described, and / or another suitable deposition operation. In some embodiments, the seed layer is deposited first, and the metal layer 318 is deposited on the seed layer. In some embodiments, after the deposition tool 102 and / or the plating tool 112 deposits the metal layer 318, the planarization tool 110 planarizes the metal layer 318.

[0181] As in Figure 4H As shown in , a plurality of openings 410408 may be formed through the metal layer 318 in the pixel sensor array 202. A plurality of openings 408 may be formed in the pixel sensor array 202 over the plurality of photodiodes 308 of the plurality of pixel sensors 204. The plurality of openings 408 may be formed by removing a plurality of first portions of the metal layer 318 to form a metal grid 320 above the isolation structure 310. The plurality of openings 408 and the metal grid 320 may be formed while masking the optical blocking region 206 and the electrical pad region 208 (e.g., via a photoresist layer or a hard mask). In some embodiments, the deposition tool 102 may form a photoresist layer on the metal layer 318 in the pixel sensor array 202, the exposure tool 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, the developer tool 106 may develop and remove a plurality of portions of the photoresist layer to expose the pattern, and the etching tool 108 may etch through a plurality of portions of the metal layer 318 to form the plurality of openings 408. In some embodiments, the etching tool 108 etches into a portion of the underlying adhesion layer 316 to ensure that the metal layer 318 is completely etched through. The removed portions of the underlying adhesion layer 316 may be referred to as over-etched regions. In some embodiments, after the etching tool 108 etches the metal layer 318, the photoresist removal tool 114 removes the remaining portions of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0182] As in Figure 4H As further shown in FIG. 1 , the metal layer 318 can be patterned into a nanoscale metal grid 340 in the optical blocking region 206. Figure 3AAs depicted, nanoscale metal grid 340 includes a plurality of metal structures, and each metal structure has a width ranging from about 100 nanometers to about 200 nanometers.

[0183] In some embodiments, forming the nanoscale metal grid 340 may use double patterning lithography to etch a plurality of nanoscale openings between the plurality of metal structures. The nanoscale metal grid 340 may be formed while masking the pixel sensor array 202 and the electrical pad region 208 (e.g., via a photoresist layer or a hard mask). Alternatively, the same process (e.g., double patterning) may be used to form the metal grid 320 and the nanoscale metal grid 340. The nanoscale metal grid 340 reduces the likelihood of light being reflected from the optical blocking region 206 and toward the pixel sensor array 202. In this manner, the nanoscale metal grid 340 reduces the likelihood of the occurrence of flashes or hot spots in images and / or videos produced by the embodiment image sensor device 300, which improves image quality. The nanoscale metal grid 340 is maintained electrically neutral via the ground node 342, even if photons collide with the nanoscale metal grid 340. As a result, current does not leak from nanoscale metal grid 340 to pixel sensor array 202 , which improves the performance of embodiment image sensor device 300 .

[0184] In some embodiments, as in Figure 4H As further shown in FIG. 4 , the recess 406 in the metal layer 318 at the electrical pad region 208 may be reopened. The recess 406 may be formed as part of forming the metal grid 320 and the nanoscale metal grid 340 (e.g., using double patterning). Alternatively, the metal layer 318 may be further opened during a later etching cycle (e.g., as in combination with FIG. Figure 4J The electrical pad region 208 is etched during the etching cycle described above.

[0185] As in Fig. 4I As shown in , a corresponding color filter region 322 may be formed in a plurality of openings 408 for each of a plurality of pixel sensors 204 in the pixel sensor array 202. Each color filter region 322 may be formed between metal grids 320 to reduce color mixing between a plurality of adjacent pixel sensors 204. Additionally or alternatively, a plurality of regions between the metal grids 320 may be filled with a passivation layer, and a color filter layer including the color filter region 322 may be formed on the passivation layer above the metal grids 320. For example, as shown in Fig. 4I As shown in FIG. 1 , a passivation layer may be further formed in the optical blocking region 206 and / or the electrical pad region 208. In some embodiments, the deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination of Figure 1Color filter regions 322 are deposited in another type of deposition operation as described, and / or in another suitable deposition operation. In some embodiments, planarization tool 110 planarizes color filter regions 322 after deposition tool 102 deposits color filter regions 322 .

[0186] As in Figure 4J As shown in FIG. 1 , a recess 332 may be formed in the electrical pad region 208. Specifically, the recess 332 may be formed through the passivation layer, through the metal layer 318, through the adhesion layer 316, through the anti-reflective coating 312, and into the substrate 306 to reach the shallow trench isolation region 330. The shallow trench isolation region 330 may be exposed through the recess 332. The recess 332 may be formed by coating the passivation layer with a photoresist (e.g., using a deposition tool 102), forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using an exposure tool 104), removing a plurality of exposed portions or a plurality of unexposed portions of the photoresist (e.g., using a developer tool 106), and etching the recess 332 based on the pattern in the photoresist (e.g., using an etching tool 108).

[0187] As in Figure 4K As shown in , dielectric layer 324 can be formed over the passivation layer in pixel sensor array 202 and / or optical blocking region 206, and over shallow trench isolation region 330 in electrical pad region 208. Dielectric layer 324 can also be formed on the exposed sidewalls of recess 332. Deposition tool 102 can conformally deposit dielectric layer 324 using CVD techniques, PVD techniques, ALD techniques, or another type of deposition technique. Other embodiments can omit dielectric layer 324 from electrical pad region 208 (e.g., as in combination with Figure 5K described).

[0188] As in Figure 4L As shown in FIG. 1 , an opening 410 may be formed in the recess 332 of the electrical pad region 208. Specifically, the opening 410 may be formed through the dielectric layer 324 (if present), through the shallow trench isolation region 330, through the interlayer dielectric layer 304, and to the metallization layer 328 in the intermetal dielectric layer 302. The opening 410 may be formed by coating the dielectric layer 324 with a photoresist (e.g., using a deposition tool 102), forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using an exposure tool 104), removing a plurality of exposed portions or a plurality of unexposed portions of the photoresist (e.g., using a developer tool 106), and etching the opening 410 based on the pattern in the photoresist (e.g., using an etching tool 108).

[0189] As in Figure 4MAs shown in FIG. 4 , an electrical pad 336 may be formed in the opening 410. For example, a semiconductor process tool (e.g., deposition tool 102 or plating tool 112) may form a metal layer (e.g., an aluminum layer, a copper layer, a tungsten layer, a gold layer, a silver layer, a metal alloy layer, or another type of metal layer) on the dielectric layer 334 (if present) and on the sidewalls of the opening 410, such that portions of the electrical pad 336 are subsequently on the metallization layer 328.

[0190] As in Figure 4N As shown in FIG. 3 , a microlens layer 326 including a plurality of microlenses is formed above and / or on color filter region 322. Microlens layer 326 may include a corresponding microlens for each of a plurality of pixel sensors 204 included in pixel sensor array 202.

[0191] As mentioned above, it provides FIG. 4A to FIG. 4N As an example, other embodiments may differ from the FIG. 4A to FIG. 4N For example, dielectric layer 324 may be omitted from part or all of embodiment image sensor device 300. Additionally or alternatively, color filter region 322 may be omitted and replaced only by the passivation layer described above.

[0192] FIG. 5A to FIG. 5K is a schematic diagram of an example implementation 500 described herein. Example implementation 500 may be an example process for forming example image sensor device 300 described herein. Among other examples, example image sensor device 300 may include pixel sensor array 202 (including a plurality of pixel sensors 204), optical blocking region 206 (including nanoscale metal grid 340), and electrical pad region 208. In example implementation 500, electrical pad region 208 is formed simultaneously with nanoscale metal grid 340.

[0193] As in FIG. 5A to FIG. 5C As shown in FIG. , example implementation 500 may include combining FIG. 4A to FIG. 4C The process described. Figure 5C As further shown in FIG. 1 , recess 504 may be formed in electrical pad region 208. Recess 504 may be formed as part of forming electrical pad 336. Accordingly, recess 504 may expose shallow trench isolation region 330 and a portion of metallization layer 328 in intermetallic dielectric layer 302. In some embodiments, the pattern exposed by developer tool 106 may be used to form recess 502 and recess 504. Alternatively, recess 504 may be exposed during a later etch cycle (e.g., as in combination with Fig. 5F The electrical pad region 208 is etched during the etching cycle described above.

[0194] As in Figure 5DAs shown in , the anti-reflective coating 312 can be formed above and / or on the substrate 306 and in the recess 502. The anti-reflective coating 312 can be conformally deposited so that the anti-reflective coating 312 includes a thin film that conforms to the shape and / or contour of the recess 502. The anti-reflective coating 312 can be included on the surface of the substrate 306 in the pixel sensor array 202 and / or in the optical blocking area 206. The anti-reflective coating 312 can be excluded from the recess 504 (and / or excluded from the entire electrical pad area 208). The deposition tool 102 can deposit the anti-reflective coating 312 using a CVD technique, a PVD technique, an ALD technique, or another type of deposition technique.

[0195] As in Figure 5E , recess 502 may be filled with dielectric layer 314. Additional dielectric material may be deposited such that adhesion layer 316 extends along the surface of substrate 306 in pixel sensor array 202 and / or in optical blocking region 206. Adhesion layer 316 may be excluded from recess 504 (and / or from the entire electrical pad region 208). Deposition tool 102 may deposit dielectric layer 314 using various CVD techniques and / or ALD techniques, such as PECVD, HDP-CVD, SACVD, and / or PEALD, among other embodiments.

[0196] As in Fig. 5F As shown in , recess 506 can be formed in adhesive layer 316 at a portion of optical blocking region 206 at (or near) a boundary of pixel sensor array 202. Recess 506 can be formed as part of forming ground node 342. Accordingly, recess 506 can expose the top surface of substrate 306. In some embodiments, deposition tool 102 can form a photoresist layer on adhesive layer 316, exposure tool 104 can expose the photoresist layer to a radiation source to pattern the photoresist layer, developer tool 106 can develop and remove portions of the photoresist layer to expose the pattern, and etching tool 108 can etch portions of adhesive layer 316 to form recess 506 for ground node 342 in adhesive layer 316. In some embodiments, after etching tool 108 etches adhesive layer 316, photoresist removal tool 114 removes remaining portions of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0197] As in Figure 5GAs shown in , metal layer 318 can be formed above and / or on bonding layer 316. Metal layer 318 can be formed in pixel sensor array 202 and / or in optical blocking region 206. The portion of metal layer 318 in optical blocking region 206 can correspond to a light blocking layer for sensing region 338. In addition, metal layer 318 can fill recess 506 to form ground node 342. Deposition tool 102 and / or plating tool 112 can be operated in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, a combination of the above. Figure 1 The metal layer 318 is deposited in another deposition operation as described, and / or another suitable deposition operation. In some embodiments, the seed layer is deposited first, and the metal layer 318 is deposited on the seed layer. In some embodiments, after the deposition tool 102 and / or the plating tool 112 deposits the metal layer 318, the planarization tool 110 planarizes the metal layer 318.

[0198] During the same deposition cycle, such as Figure 5G As further shown in FIG. 5 , an electrical pad 336 may be formed in the recess 504. For example, the electrical pad 336 may be formed using the same metal as the metal layer 318. The metal may be formed on the sidewalls of the recess 504 so that portions of the electrical pad 336 are attached to the metallization layer 328.

[0199] As in Figure 5H As shown in , a plurality of openings 508 may be formed through the metal layer 318 in the pixel sensor array 202. The plurality of openings 508 may be formed in the pixel sensor array 202 over the plurality of photodiodes 308 of the plurality of pixel sensors 204. The plurality of openings 508 may be formed by removing a plurality of first portions of the metal layer 318 to form the metal grid 320 above the isolation structure 310. The openings 508 and the metal grid 320 may be formed while masking the optical blocking region 206 and the electrical pad region 208 (e.g., via a photoresist layer or a hard mask). In some embodiments, the deposition tool 102 may form a photoresist layer on the metal layer 318 in the pixel sensor array 202, the exposure tool 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, the developer tool 106 may develop and remove a plurality of portions of the photoresist layer to expose the pattern, and the etching tool 108 may etch through a plurality of portions of the metal layer 318 to form the openings 508. In some embodiments, the etching tool 108 etches into a portion of the underlying adhesion layer 316 to ensure that the metal layer 318 is completely etched through. The removed portions of the underlying adhesion layer 316 can be referred to as over-etched regions. In some embodiments, after the etching tool 108 etches the metal layer 318, the photoresist removal tool 114 removes the remaining portions of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0200] As in Figure 5H As further shown in FIG. 1 , the metal layer 318 can be patterned into a nanoscale metal grid 340 in the optical blocking region 206. Figure 3A As depicted, nanoscale metal grid 340 includes a plurality of metal structures, and each metal structure has a width ranging from about 100 nanometers to about 200 nanometers.

[0201] In some embodiments, forming the nanoscale metal grid 340 may use double patterning lithography to etch a plurality of nanoscale openings between the plurality of metal structures. The nanoscale metal grid 340 may be formed while masking the pixel sensor array 202 and the electrical pad region 208 (e.g., via a photoresist layer or a hard mask). Alternatively, the same process (e.g., double patterning) may be used to form the metal grid 320 and the nanoscale metal grid 340. The nanoscale metal grid 340 reduces the likelihood of light being reflected from the optical blocking region 206 and toward the pixel sensor array 202. In this manner, the nanoscale metal grid 340 reduces the likelihood of the occurrence of flashes or hot spots in images and / or videos produced by the embodiment image sensor device 300, which improves image quality. The nanoscale metal grid 340 is kept electrically neutral via the ground node 342, even if photons collide with the nanoscale metal grid 340. As a result, current does not leak from nanoscale metal grid 340 to pixel sensor array 202 , which improves the performance of embodiment image sensor device 300 .

[0202] As in Fig.5I As shown in , a corresponding color filter region 322 may be formed in a plurality of openings 508 for each of a plurality of pixel sensors 204 in the pixel sensor array 202. Each color filter region 322 may be formed between metal grids 320 to reduce color mixing between a plurality of adjacent pixel sensors 204. Additionally or alternatively, a plurality of regions between the metal grids 320 may be filled with a passivation layer, and a color filter layer including the color filter region 322 may be formed on the passivation layer above the metal grids 320. For example, as shown in Fig.5I As shown in FIG. 2 , the passivation layer may be further formed in the optical blocking region 206 (and not in the electrical pad region 208). In some embodiments, the deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination of Figure 1 Color filter regions 322 are deposited in another type of deposition operation as described, and / or in another suitable deposition operation. In some embodiments, planarization tool 110 planarizes color filter regions 322 after deposition tool 102 deposits color filter regions 322 .

[0203] As in Figure 5J , dielectric layer 324 may be formed over the passivation layer in pixel sensor array 202 and / or optical blocking region 206; however, dielectric layer 324 is not present in electrical pad region 208. Deposition tool 102 may conformally deposit dielectric layer 324 using a CVD technique, a PVD technique, an ALD technique, or another type of deposition technique.

[0204] As in Figure 5K As shown in FIG. 3 , a microlens layer 326 including a plurality of microlenses is formed above and / or on color filter region 322. Microlens layer 326 may include a corresponding microlens for each of a plurality of pixel sensors 204 included in pixel sensor array 202.

[0205] As mentioned above, providing FIG. 5A to FIG. 5K As an example, other embodiments may differ from the FIG. 5A to FIG. 5K For example, dielectric layer 324 may be omitted from part or all of embodiment image sensor device 300. Additionally or alternatively, color filter region 322 may be omitted and replaced only by the passivation layer described above.

[0206] FIG. 6A to FIG. 6N 6 is a schematic diagram of an example implementation 600 described herein. Example implementation 600 may be an example process for forming an example image sensor device 350 described herein. Among other examples, example image sensor device 350 may include pixel sensor array 202 (including a plurality of pixel sensors 204), optical blocking region 206 (including nanoscale metal grid 340), and electrical pad region 208. In example implementation 600, nanoscale metal grid 340 is formed using a pattern of recesses in a supporting dielectric layer, rather than using double lithography.

[0207] As in FIG. 6A to FIG. 6E As shown in FIG. 6 , example implementation 600 may include combining FIG. 4A to FIG. 4E The process described. Fig. 6FAs further shown in FIG. 1 , a recess 604 can be formed in the bonding layer 316 at a portion of the optical blocking region 206 at (or near) a boundary of the pixel sensor array 202. The recess 604 can be formed as part of forming the ground node 342. Accordingly, the recess 604 can expose the top surface of the substrate 306. In some embodiments, the deposition tool 102 can form a photoresist layer on the bonding layer 316, the exposure tool 104 can expose the photoresist layer to a radiation source to pattern the photoresist layer, the developer tool 106 can develop and remove multiple portions of the photoresist layer to expose the pattern, and the etching tool 108 can etch the portion of the bonding layer 316 to form the recess 604 for the ground node 342 in the bonding layer 316. In some embodiments, after the etching tool 108 etches the bonding layer 316, the photoresist removal tool 114 removes multiple remaining portions of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0208] In some embodiments, as in Fig. 6F As further shown in FIG. 1 , recess 606 can be formed in adhesive layer 316 in electrical pad region 208. Recess 606 can be formed as part of forming electrical pad 336. Accordingly, recess 606 can expose the top surface of substrate 306. In some embodiments, the pattern exposed by developer tool 106 can be used to form recess 604 and recess 606. Alternatively, adhesive layer 316 can be exposed during a later etch cycle (e.g., as in combination with Figure 6J The electrical pad region 208 is etched during the etching cycle described above.

[0209] As in Fig. 6F As further shown, the adhesive layer 316 can be patterned into a recessed pattern 352 in the optical blocking region 206. Figure 3B As described, the adhesion layer 316 can be patterned so that the metal layer 318 in the optical blocking area 206 will follow the recessed pattern 352 during deposition. In some embodiments, the recessed pattern 352 can be formed using double patterning lithography to etch a plurality of holes in the adhesion layer 316. The recessed pattern 352 can be formed while masking the pixel sensor array 202 and the electrical pad area 208 (e.g., via a photoresist layer or a hard mask). Alternatively, the same process (e.g., double patterning lithography) can be used to form the recessed pattern 352 plus the recess 604 and / or the recess 606. As a result, the adhesion layer 316 in the pixel sensor array 202 also has a shape that conforms to the recessed pattern 352.

[0210] As in Figure 6GAs shown in , metal layer 318 can be formed above and / or on adhesion layer 316. In other embodiments, metal layer 318 can be formed in pixel sensor array 202, in optical blocking region 206, and in electrical pad region 208. The portion of metal layer 318 in optical blocking region 206 can correspond to the light blocking layer for sensing region 338. In addition, metal layer 318 can fill recess 604 to form ground node 342. Deposition tool 102 and / or plating tool 112 can be operated in CVD, PVD, ALD, electroplating, or a combination of the above. Figure 1 The metal layer 318 is deposited in another deposition operation as described, and / or another suitable deposition operation. In some embodiments, the seed layer is deposited first, and the metal layer 318 is deposited on the seed layer. In some embodiments, after the deposition tool 102 and / or the plating tool 112 deposits the metal layer 318, the planarization tool 110 planarizes the metal layer 318.

[0211] As in Figure 6G As further shown in FIG. 1 , the deposition rate of metal layer 318 can be relatively constant such that metal layer 318 follows a pattern of recesses 352 (although the roughness is reduced due to metal flow, unlike dielectric materials). Metal layer 318 follows a pattern of recesses 352 in optical blocking region 206. In embodiments where adhesion layer 316 in pixel sensor array 202 follows a pattern of recesses 352, metal layer 318 can also follow a pattern of recesses 352 in pixel sensor array 202.

[0212] As in Figure 6HAs shown in , a plurality of openings 608 may be formed through the metal layer 318 in the pixel sensor array 202. The plurality of openings 608 may be formed in the pixel sensor array 202 over the plurality of photodiodes 308 of the plurality of pixel sensors 204. The plurality of openings 608 may be formed by removing a plurality of first portions of the metal layer 318 to form the metal grid 320 above the isolation structure 310. The plurality of openings 608 and the metal grid 320 may be formed while masking the optical blocking region 206 and the electrical pad region 208 (e.g., via a photoresist layer or a hard mask). In some embodiments, the deposition tool 102 may form a photoresist layer on the metal layer 318 in the pixel sensor array 202, the exposure tool 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, the developer tool 106 may develop and remove a plurality of portions of the photoresist layer to expose the pattern, and the etching tool 108 may etch through a plurality of portions of the metal layer 318 to form the openings 608. In some embodiments, the etching tool 108 etches into a portion of the underlying adhesion layer 316 to ensure that the metal layer 318 is completely etched through. The removed portions of the underlying adhesion layer 316 can be referred to as over-etched regions. In some embodiments, after the etching tool 108 etches the metal layer 318, the photoresist removal tool 114 removes the remaining portions of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0213] In some embodiments, as in Figure 6H As further shown in FIG. 1 , the recess 606 in the metal layer 318 in the electrical pad region 208 may be reopened. The recess 606 may be formed as part of forming the metal grid 320 and the nanoscale metal grid 340 (e.g., using double patterning). Alternatively, the metal layer 318 may be further opened during a later etching cycle (e.g., in conjunction with Figure 6J The electrical pad region 208 is etched during the etching cycle described above.

[0214] As in Fig.6I As shown in , a corresponding color filter region 322 may be formed in a plurality of openings 608 for each of a plurality of pixel sensors 204 in the pixel sensor array 202. Each color filter region 322 may be formed between metal grids 320 to reduce color mixing between a plurality of adjacent pixel sensors 204. Additionally or alternatively, a plurality of regions between the metal grids 320 may be filled with a passivation layer, and a color filter layer including the color filter region 322 may be formed on the passivation layer above the metal grids 320. For example, as shown in Fig.6I As shown in FIG. 1 , the passivation layer may also be formed in the optical blocking region 206 and / or the electrical pad region 208. In some embodiments, the deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination of Figure 1 Color filter regions 322 are deposited in another type of deposition operation as described, and / or in another suitable deposition operation. In some embodiments, planarization tool 110 planarizes color filter regions 322 after deposition tool 102 deposits color filter regions 322 .

[0215] As in Figure 6J As shown in FIG. 1 , a recess 332 may be formed in the electrical pad region 208. Specifically, the recess 332 may be formed through the passivation layer, through the metal layer 318, through the adhesion layer 316, through the anti-reflective coating 312, and into the substrate 306 to reach the shallow trench isolation region 330. The shallow trench isolation region 330 may be exposed through the recess 332. The recess 332 may be formed by coating the passivation layer with a photoresist (e.g., using a deposition tool 102), forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using an exposure tool 104), removing a plurality of exposed portions or a plurality of unexposed portions of the photoresist (e.g., using a developer tool 106), and etching the recess 332 based on the pattern in the photoresist (e.g., using an etching tool 108).

[0216] As in Figure 6K As shown in , dielectric layer 324 can be formed over the passivation layer in pixel sensor array 202 and / or optical blocking region 206, and over shallow trench isolation region 330 in electrical pad region 208. Dielectric layer 324 can also be formed on the exposed sidewalls of recess 332. Deposition tool 102 can conformally deposit dielectric layer 324 using CVD techniques, PVD techniques, ALD techniques, or another type of deposition technique. Other embodiments can omit dielectric layer 324 from electrical pad region 208 (e.g., as in combination with Figure 5K described).

[0217] As in Figure 6L As shown in FIG. 1 , an opening 610 may be formed in the recess 332 of the electrical pad region 208. Specifically, the opening 610 may be formed through the dielectric layer 324 (if present), through the shallow trench isolation region 330, and through the interlayer dielectric layer 304 to the metallization layer 328 in the intermetal dielectric layer 302. The opening 610 may be formed by coating the dielectric layer 324 with a photoresist (e.g., using a deposition tool 102), forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using an exposure tool 104), removing a plurality of exposed portions or a plurality of unexposed portions of the photoresist (e.g., using a developer tool 106), and etching the opening 610 based on the pattern in the photoresist (e.g., using an etching tool 108).

[0218] As in Figure 6MAs shown in FIG. 6 , an electrical pad 336 may be formed in the opening 610. For example, a semiconductor process tool (e.g., deposition tool 102 or plating tool 112) may form a metal layer (e.g., an aluminum layer, a copper layer, a tungsten layer, a gold layer, a silver layer, a metal alloy layer, or another type of metal layer) on the dielectric layer 334 (if present) and on the sidewalls of the opening 610, such that portions of the electrical pad 336 are subsequently on the metallization layer 328.

[0219] As in Figure 6N As shown in FIG. 3 , a microlens layer 326 including a plurality of microlenses is formed above and / or over color filter region 322. Microlens layer 326 may include a corresponding microlens for each of a plurality of pixel sensors 204 included in pixel sensor array 202.

[0220] As mentioned above, providing FIG. 6A to FIG. 6N As an example, other embodiments may differ from the FIG. 6A to FIG. 6N For example, dielectric layer 324 may be omitted from part or all of embodiment image sensor device 350. Additionally or alternatively, color filter region 322 may be omitted and replaced only by the passivation layer described above. Additionally or alternatively, electrical pad 336 may be formed earlier (e.g., during the formation of metal layer 318, such as in conjunction with Figure 5G described).

[0221] FIG. 7A to FIG. 7N is a schematic diagram of an example implementation 700 described herein. Example implementation 700 may be an example process for forming an example image sensor device 360 ​​described herein. Among other examples, example image sensor device 360 ​​may include pixel sensor array 202 (which includes a plurality of pixel sensors 204), optical blocking region 206 (which includes nanoscale metal grid 340), and electrical pad region 208. In example implementation 700, nanoscale metal grid 340 is formed using a highly absorbing structure in a supporting dielectric layer instead of using double lithography.

[0222] As in 7A to 7C As shown in FIG. , example implementation 700 may include combining FIG. 4A to FIG. 4C The process described. Figure 7C As further shown in FIG. 1 , the substrate 306 may be patterned into a recessed pattern 362 in the optical blocking region 206. Figure 3CAs described, substrate 306 may be patterned so that adhesion layer 316 and metal layer 318 in optical blocking region 206 will follow recessed pattern 362 during deposition. In some embodiments, recessed pattern 362 may include a plurality of approximately pyramid-shaped holes. Recessed pattern 362 may be formed while masking pixel sensor array 202 and electrical pad region 208 (e.g., via a photoresist layer or hard mask). Alternatively, a same process may be used to form recessed pattern 362 plus a plurality of recesses 702.

[0223] As in Fig.7D As shown in , an anti-reflective coating 312 may be formed above and / or on the substrate 306, and in the recesses 702 and the recessed pattern 362. The anti-reflective coating 312 may be conformally deposited such that the anti-reflective coating 312 includes a thin film that conforms to the shape and / or contour of the recesses 702 and the recessed pattern 362. In other embodiments, the anti-reflective coating 312 may be included on the surface of the substrate 306 in the pixel sensor array 202, in the optical blocking region 206, and / or in the electrical pad region 208. The deposition tool 102 may deposit the anti-reflective coating 312 using a CVD technique, a PVD technique, an ALD technique, or another type of deposition technique.

[0224] As in Fig. 7E As shown in FIG. 3 , the recess 702 may be filled with a dielectric layer 314 to form an isolation structure 310. In addition, the recessed pattern 362 may be filled with a dielectric layer 314 to form a plurality of high absorption structures. The dielectric material used in the recess 702 may be the same material as that used in the recessed pattern 362 or a different material.

[0225] In other embodiments, additional dielectric material may be deposited such that the adhesion layer 316 extends along the surface of the substrate 306 in the pixel sensor array 202, in the optical blocking region 206, and in the electrical pad region 208. In other embodiments, the deposition tool 102 may deposit the dielectric layer 314 using various CVD techniques and / or ALD techniques, such as PECVD, HDP-CVD, SACVD, and / or PEALD. Fig. 7E As further shown in FIG. 3 , the dielectric material used in the recessed pattern 362 may be conformally deposited such that the adhesion layer 316 follows the recessed pattern 362 (albeit with reduced roughness) in the optical blocking region 206 .

[0226] As in Figure 7FAs shown in , a recess 704 can be formed in the adhesive layer 316 at a portion of the optical blocking region 206 at (or near) a boundary of the pixel sensor array 202. The recess 704 can be formed as a portion of forming the ground node 342. Accordingly, the recess 704 can expose the top surface of the substrate 306. In some embodiments, the deposition tool 102 can form a photoresist layer on the adhesive layer 316, the exposure tool 104 can expose the photoresist layer to a radiation source to pattern the photoresist layer, the developer tool 106 can develop and remove multiple portions of the photoresist layer to expose the pattern, and the etching tool 108 can etch the portion of the adhesive layer 316 to form the recess 704 for the ground node 342 in the adhesive layer 316. In some embodiments, after the etching tool 108 etches the adhesive layer 316, the photoresist removal tool 114 removes multiple remaining portions of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0227] In some embodiments, as in Figure 7F As further shown in FIG. 1 , recess 706 can be formed in adhesive layer 316 at electrical pad region 208. Recess 706 can be formed as part of forming electrical pad 336. Accordingly, recess 706 can expose the top surface of substrate 306. In some embodiments, the pattern exposed by developer tool 106 can be used to form recess 704 and recess 706. Alternatively, adhesive layer 316 can be exposed during a later etching cycle (e.g., as in combination with Figure 7J The electrical pad region 208 is etched during the etching cycle described above.

[0228] As in Figure 7G As shown in , metal layer 318 can be formed above and / or on bonding layer 316. In other embodiments, metal layer 318 can be formed in pixel sensor array 202, in optical blocking region 206, and in electrical pad region 208. The portion of metal layer 318 in optical blocking region 206 can correspond to the light blocking layer for sensing region 338. In addition, metal layer 318 can fill recess 704 to form ground node 342. Deposition tool 102 and / or plating tool 112 can be operated in CVD, PVD, ALD, electroplating, or a combination of the above. Figure 1 The metal layer 318 is deposited in another deposition operation as described, and / or another suitable deposition operation. In some embodiments, the seed layer is deposited first, and the metal layer 318 is deposited on the seed layer. In some embodiments, after the deposition tool 102 and / or the plating tool 112 deposits the metal layer 318, the planarization tool 110 planarizes the metal layer 318.

[0229] As in Figure 7GAs further shown in FIG. 1 , the deposition rate of metal layer 318 can be relatively constant so that metal layer 318 follows recessed pattern 362 (albeit with reduced roughness due to metal flow). Metal layer 318 has a consistent shape with recessed pattern 362 in optical blocking region 206 .

[0230] As in Figure 7H As shown in , a plurality of openings 708 may be formed through the metal layer 318 in the pixel sensor array 202. The plurality of openings 708 may be formed over the plurality of photodiodes 308 of the plurality of pixel sensors 204 in the pixel sensor array 202. The plurality of openings 708 may be formed by removing a plurality of first portions of the metal layer 318 to form the metal grid 320 above the isolation structure 310. The plurality of openings 708 and the metal grid 320 may be formed while masking the optical blocking region 206 and the electrical pad region 208 (e.g., via a photoresist layer or a hard mask). In some embodiments, the deposition tool 102 may form a photoresist layer on the metal layer 318 in the pixel sensor array 202, the exposure tool 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, the developer tool 106 may develop and remove a plurality of portions of the photoresist layer to expose the pattern, and the etching tool 108 may etch through a plurality of portions of the metal layer 318 to form the openings 708. In some embodiments, the etching tool 108 etches into a portion of the underlying adhesion layer 316 to ensure that the metal layer 318 is completely etched through. The removed portions of the underlying adhesion layer 316 can be referred to as over-etched regions. In some embodiments, after the etching tool 108 etches the metal layer 318, the photoresist removal tool 114 removes the remaining portions of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0231] In some embodiments, as in Figure 7H As further shown in FIG. 1 , the recess 706 in the metal layer 318 in the electrical pad region 208 may be reopened. The recess 706 may be formed as part of forming the metal grid 320 and the nanoscale metal grid 340 (e.g., using double patterning). Alternatively, the metal layer 318 may be opened during a later etching cycle (e.g., as in combination with FIG. 1 ). Figure 7J The electrical pad region 208 is etched during the etching cycle described above.

[0232] As in Figure 7GAs shown in , a corresponding color filter region 322 may be formed in a plurality of openings 708 of each of a plurality of pixel sensors 204 in the pixel sensor array 202. Each color filter region 322 may be formed between metal grids 320 to reduce color mixing between a plurality of adjacent pixel sensors 204. Additionally or alternatively, a plurality of regions between the metal grids 320 may be filled with a passivation layer, and a color filter layer including the color filter region 322 may be formed on the passivation layer higher than the metal grids 320. For example, as shown in Fig.7I As shown in FIG. 1 , a passivation layer may be further formed in the optical blocking region 206 and / or the electrical pad region 208. In some embodiments, the deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination of Figure 1 Color filter regions 322 are deposited in another type of deposition operation as described, and / or in another suitable deposition operation. In some embodiments, planarization tool 110 planarizes color filter regions 322 after deposition tool 102 deposits color filter regions 322 .

[0233] As in Figure 7J As shown in FIG. 1 , a recess 332 may be formed in the electrical pad region 208. Specifically, the recess 332 may be formed through the passivation layer, through the metal layer 318, through the adhesion layer 316, through the anti-reflective coating 312, and into the substrate 306 to reach the shallow trench isolation region 330. The shallow trench isolation region 330 may be exposed through the recess 332. The recess 332 may be formed by coating the passivation layer with a photoresist (e.g., using a deposition tool 102), forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using an exposure tool 104), removing a plurality of exposed portions or a plurality of unexposed portions of the photoresist (e.g., using a developer tool 106), and etching the recess 332 based on the pattern in the photoresist (e.g., using an etching tool 108).

[0234] As in Figure 7K As shown in , dielectric layer 324 can be formed over the passivation layer in pixel sensor array 202 and / or optical blocking region 206, and over shallow trench isolation region 330 in electrical pad region 208. Dielectric layer 324 can also be formed on the exposed sidewalls of recess 332. Deposition tool 102 can conformally deposit dielectric layer 324 using CVD techniques, PVD techniques, ALD techniques, or another type of deposition technique. Other embodiments can omit dielectric layer 324 from electrical pad region 208 (e.g., as in combination with Figure 5K described).

[0235] As in Figure 7LAs shown in FIG. 1 , an opening 710 may be formed in the recess 332 of the electrical pad region 208. Specifically, the opening 710 may be formed through the dielectric layer 324 (if present), through the shallow trench isolation region 330, through the interlayer dielectric layer 304, and to the metallization layer 328 in the intermetal dielectric layer 302. The opening 710 may be formed by coating the dielectric layer 324 with a photoresist (e.g., using a deposition tool 102), forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using an exposure tool 104), removing a plurality of exposed portions or a plurality of unexposed portions of the photoresist (e.g., using a developer tool 106), and etching the opening 710 based on the pattern in the photoresist (e.g., using an etching tool 108).

[0236] As in Figure 7M As shown in FIG. 1 , an electrical pad 336 may be formed in the opening 710. For example, a semiconductor process tool (e.g., deposition tool 102 or plating tool 112) may form a metal layer (e.g., an aluminum layer, a copper layer, a tungsten layer, a gold layer, a silver layer, a metal alloy layer, or another type of metal layer) on the dielectric layer 334 (if present) and on the sidewalls of the opening 710, such that portions of the electrical pad 336 are subsequently on the metallization layer 328.

[0237] As in Figure 7N As shown in FIG. 3 , a microlens layer 326 including a plurality of microlenses is formed above and / or on color filter region 322. Microlens layer 326 may include a corresponding microlens for each of a plurality of pixel sensors 204 included in pixel sensor array 202.

[0238] As mentioned above, providing FIG. 7A to FIG. 7N As an example, other embodiments may differ from the FIG. 7A to FIG. 7N For example, dielectric layer 324 may be omitted from part or all of embodiment image sensor device 360. Additionally or alternatively, color filter region 322 may be omitted and replaced only by the passivation layer described above. Additionally or alternatively, electrical pad 336 may be formed earlier (e.g., during the formation of metal layer 318, such as in conjunction with Figure 5G described).

[0239] FIG. 8A to FIG. 8N8 is a schematic diagram of an example implementation 800 described herein. Example implementation 800 may be an example process for forming an example image sensor device 370 described herein. Among other examples, example image sensor device 370 may include pixel sensor array 202 (including a plurality of pixel sensors 204), optical blocking region 206 (including nanoscale metal grid 340), and electrical pad region 208. In example implementation 800, nanoscale metal grid 340 is formed using shallow isolation structures in a supporting dielectric layer rather than using double lithography.

[0240] As in FIG. 8A to FIG. 8C As shown in FIG. 8 , example implementation 800 may include combining FIG. 4A to FIG. 4C The process described. Figure 8C As further shown in FIG. 3 , the substrate 306 may be patterned into a recessed pattern 372 in the optical blocking region 206. Figure 3D As described, substrate 306 may be patterned so that adhesion layer 316 and metal layer 318 in optical blocking region 206 will follow recessed pattern 372 during deposition. In some embodiments, recessed pattern 372 may include a plurality of shallow trenches (e.g., for shallow deep trench isolation structures). Recessed pattern 372 may be formed while masking pixel sensor array 202 and electrical pad region 208 (e.g., via a photoresist layer or hard mask). Alternatively, the same process may be used to form recessed pattern 372 plus a plurality of recesses 802.

[0241] As in Fig.8D As shown in , the anti-reflective coating 312 can be formed above and / or on the substrate 306, and in the plurality of recesses 802 and the recessed pattern 372. The anti-reflective coating 312 can be conformally deposited so that the anti-reflective coating 312 includes a thin film that conforms to the shape and / or contour of the recesses 802 and the recessed pattern 372. In other embodiments, the anti-reflective coating 312 can be included on the surface of the substrate 306 in the pixel sensor array 202, in the optical blocking region 206, and / or in the electrical pad region 208. The deposition tool 102 can deposit the anti-reflective coating 312 using a CVD technique, a PVD technique, an ALD technique, or another type of deposition technique.

[0242] As in Fig. 8E As shown in FIG. 3 , the plurality of recesses 802 may be filled with a dielectric layer 314 to form an isolation structure 310. In addition, the recessed pattern 372 may be filled with a dielectric layer 314 to form a plurality of shallow isolation structures. The dielectric material used in the plurality of recesses 802 may be the same material as that used in the recessed pattern 372 or a different material.

[0243] In other embodiments, additional dielectric material may be deposited such that the adhesion layer 316 extends along the surface of the substrate 306 in the pixel sensor array 202, in the optical blocking region 206, and in the electrical pad region 208. In other embodiments, the deposition tool 102 may deposit the dielectric layer 314 using various CVD techniques and / or ALD techniques, such as PECVD, HDP-CVD, SACVD, and / or PEALD. Fig. 8E As further shown in FIG. 3 , the dielectric material used in the recessed pattern 372 may be conformally deposited such that the adhesion layer 316 follows the recessed pattern 372 (albeit with reduced roughness) in the optical blocking region 206 .

[0244] As in Figure 8F As shown in , a recess 804 can be formed in the adhesive layer 316 at a portion of the optical blocking region 206 at (or near) a boundary of the pixel sensor array 202. The recess 804 can be formed as a portion of forming the ground node 342. Accordingly, the recess 804 can expose the top surface of the substrate 306. In some embodiments, the deposition tool 102 can form a photoresist layer on the adhesive layer 316, the exposure tool 104 can expose the photoresist layer to a radiation source to pattern the photoresist layer, the developer tool 106 can develop and remove multiple portions of the photoresist layer to expose the pattern, and the etching tool 108 can etch multiple portions of the adhesive layer 316 to form the recess 804 for the ground node 342 in the adhesive layer 316. In some embodiments, after the etching tool 108 etches the adhesive layer 316, the photoresist removal tool 114 removes multiple remaining portions of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0245] In some embodiments, as in Figure 8F As further shown in FIG. 1 , recess 806 can be formed in adhesive layer 316 at electrical pad region 208. Recess 806 can be formed as part of forming electrical pad 336. Accordingly, recess 806 can expose the top surface of substrate 306. In some embodiments, the pattern exposed by developer tool 106 can be used to form recess 804 and recess 806. Alternatively, adhesive layer 316 can be exposed during a later etching cycle (e.g., as in combination with Figure 8J The electrical pad region 208 is etched during the etching cycle described above.

[0246] As in Figure 8GAs shown in , metal layer 318 can be formed above and / or on bonding layer 316. In other embodiments, metal layer 318 can be formed in pixel sensor array 202, in optical blocking region 206, and in electrical pad region 208. Portions of metal layer 318 in optical blocking region 206 can correspond to light blocking layers for sensing region 338. In addition, metal layer 318 can fill recess 804 to form ground node 342. Deposition tool 102 and / or plating tool 112 can be operated in CVD, PVD, ALD, electroplating, or a combination of the above. Figure 1 The metal layer 318 is deposited in another deposition operation as described, and / or another suitable deposition operation. In some embodiments, the seed layer is deposited first, and the metal layer 318 is deposited on the seed layer. In some embodiments, after the deposition tool 102 and / or the plating tool 112 deposits the metal layer 318, the planarization tool 110 planarizes the metal layer 318.

[0247] As in Figure 8G As further shown in FIG. 1 , the deposition rate of the metal layer 318 can be relatively constant, so that the metal layer 318 follows the recessed pattern 372 (albeit with reduced roughness due to metal flow). The metal layer 318 has a consistent shape with the recessed pattern 372 in the optical blocking region 206 .

[0248] As in Figure 8H As shown in , a plurality of openings 808 may be formed through the metal layer 318 in the pixel sensor array 202. The plurality of openings 808 may be formed over the plurality of photodiodes 308 of the plurality of pixel sensors 204 in the pixel sensor array 202. The plurality of openings 808 may be formed by removing a plurality of first portions of the metal layer 318 to form the metal grid 320 above the isolation structure 310. The plurality of openings 808 and the metal grid 320 may be formed while masking the optical blocking region 206 and the electrical pad region 208 (e.g., via a photoresist layer or a hard mask). In some embodiments, the deposition tool 102 may form a photoresist layer on the metal layer 318 in the pixel sensor array 202, the exposure tool 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, the developer tool 106 may develop and remove a plurality of portions of the photoresist layer to expose the pattern, and the etching tool 108 may etch through a plurality of portions of the metal layer 318 to form the plurality of openings 808. In some embodiments, the etching tool 108 etches into a portion of the underlying adhesion layer 316 to ensure that the metal layer 318 is completely etched through. The removed portions of the underlying adhesion layer 316 can be referred to as over-etched regions. In some embodiments, after the etching tool 108 etches the metal layer 318, the photoresist removal tool 114 removes the remaining portions of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0249] In some embodiments, as in Figure 8H As further shown in FIG. 1 , the recess 806 in the metal layer 318 at the electrical pad region 208 may be reopened. The recess 806 may be formed as part of forming the metal grid 320 and the nanoscale metal grid 340 (e.g., using double patterning). Alternatively, the metal layer 318 may be further opened during a later etching cycle (e.g., as in combination with FIG. 1 ). Figure 8J The electrical pad region 208 is etched during the etching cycle described above.

[0250] As in Fig.8I As shown in , a corresponding color filter region 322 may be formed in a plurality of openings 808 of each of a plurality of pixel sensors 204 in the pixel sensor array 202. Each color filter region 322 may be formed between metal grids 320 to reduce color mixing between a plurality of adjacent pixel sensors 204. Additionally or alternatively, a plurality of regions between the metal grids 320 may be filled with a passivation layer, and a color filter layer including the color filter region 322 may be formed on the passivation layer higher than the metal grids 320. For example, as shown in Fig.8I As shown in FIG. 1 , the passivation layer may also be formed in the optical blocking region 206 and / or the electrical pad region 208. In some embodiments, the deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination of Figure 1 Color filter regions 322 are deposited in another type of deposition operation as described, and / or in another suitable deposition operation. In some embodiments, planarization tool 110 planarizes color filter regions 322 after deposition tool 102 deposits color filter regions 322 .

[0251] As in Figure 8J As shown in FIG. 1 , a recess 332 may be formed in the electrical pad region 208. Specifically, the recess 332 may be formed through the passivation layer, through the metal layer 318, through the adhesion layer 316, through the anti-reflective coating 312, and into the substrate 306 to reach the shallow trench isolation region 330. The shallow trench isolation region 330 may be exposed through the recess 332. The recess 332 may be formed by coating the passivation layer with a photoresist (e.g., using a deposition tool 102), forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using an exposure tool 104), removing a plurality of exposed portions or a plurality of unexposed portions of the photoresist (e.g., using a developer tool 106), and etching the recess 332 based on the pattern in the photoresist (e.g., using an etching tool 108).

[0252] As in Figure 8KAs shown in , dielectric layer 324 can be formed over the passivation layer in pixel sensor array 202 and / or optical blocking region 206, and over shallow trench isolation region 330 in electrical pad region 208. Dielectric layer 324 can also be formed on the exposed sidewalls of recess 332. Deposition tool 102 can conformally deposit dielectric layer 324 using CVD techniques, PVD techniques, ALD techniques, or another type of deposition technique. Other embodiments can omit dielectric layer 324 from electrical pad region 208 (e.g., as in combination with Figure 5K described).

[0253] As in Figure 8L As shown in FIG. 1 , an opening 810 may be formed in the recess 332 of the electrical pad region 208. Specifically, the opening 810 may be formed through the dielectric layer 324 (if present), through the shallow trench isolation region 330, through the interlayer dielectric layer 304, and to the metallization layer 328 in the intermetal dielectric layer 302. The opening 810 may be formed by coating the dielectric layer 324 with a photoresist (e.g., using a deposition tool 102), forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using an exposure tool 104), removing a plurality of exposed portions or a plurality of unexposed portions of the photoresist (e.g., using a developer tool 106), and etching the opening 810 based on the pattern in the photoresist (e.g., using an etching tool 108).

[0254] As in Figure 8M As shown in FIG. 8 , an electrical pad 336 may be formed in the opening 810. For example, a semiconductor process tool (e.g., deposition tool 102 or plating tool 112) may form a metal layer (e.g., an aluminum layer, a copper layer, a tungsten layer, a gold layer, a silver layer, a metal alloy layer, or another type of metal layer) on the dielectric layer 334 (if present) and on the sidewalls of the opening 810, such that portions of the electrical pad 336 are subsequently on the metallization layer 328.

[0255] As in Figure 8N As shown in FIG. 3 , a microlens layer 326 including a plurality of microlenses is formed above and / or on color filter region 322. Microlens layer 326 may include a corresponding microlens for each of a plurality of pixel sensors 204 included in pixel sensor array 202.

[0256] As mentioned above, providing FIG. 8A to FIG. 8N As an example, other embodiments may differ from the FIG. 8A to FIG. 8NFor example, dielectric layer 324 may be omitted from part or all of embodiment image sensor device 370. Additionally or alternatively, color filter region 322 may be omitted and replaced only by the passivation layer described above. Additionally or alternatively, electrical pad 336 may be formed earlier (e.g., during the formation of metal layer 318, such as in conjunction with Figure 5G described).

[0257] Fig. 9 900 described herein. In some embodiments, one or more of the plurality of semiconductor process tools 102 to 116 and / or the wafer / die transfer tool 118 may include one or more of the apparatus 900 and / or one or more components of the apparatus 900. Fig. 9 As shown in , device 900 may include a bus 910 , a processor 920 , a memory 930 , an input component 940 , an output component 950 , and / or a communication component 960 .

[0258] The bus 910 may include one or more components that enable wired and / or wireless communication between the various components of the device 900. The bus 910 may include one or more components that enable wired and / or wireless communication between the various components of the device 900. Fig. 9 Two or more components of a processor 910 are coupled together, for example, via operational coupling, communication coupling, electronic coupling, and / or electrical coupling. For example, bus 910 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless buses. Processor 920 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and / or another type of processing component. Processor 920 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 920 may include one or more processors that are programmable to perform one or more operations or processes described elsewhere herein.

[0259] The memory 930 may include volatile and / or non-volatile memory. For example, the memory 930 may include random access memory (RAM), read only memory (ROM), a hard drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 930 may include internal memory (e.g., random access memory, read only memory, or hard drive), and / or removable memory (e.g., removable via a universal serial bus connection). The memory 930 may be a non-transitory computer-readable medium. The memory 930 may store information related to the operation of the device 900, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, the memory 930 may include one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 920), for example via a bus 910. The communicative coupling between processor 920 and memory 930 may enable processor 920 to read and / or process information stored in memory 930 and / or store information in memory 930 .

[0260] Input assembly 940 may enable device 900 to receive input, such as user input and / or sensed input. For example, input assembly 940 may include a touch screen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS sensor, accelerometer, gyroscope, and / or actuator. Output assembly 950 may enable device 900 to provide output, such as via a display, speaker, and / or light emitting diode. Communication assembly 960 may enable device 900 to communicate with other devices via wired connection and / or wireless connection. For example, communication assembly 960 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0261] The device 900 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 930) may store a group of multiple instructions (e.g., one or more instructions or program codes) for implementation via a processor 920. The processor 920 may implement multiple instructions of the group to perform one or more operations or processes described herein. In some embodiments, the implementation of multiple instructions of the group via one or more processors 920 causes one or more processors 920 and / or the device 900 to perform one or more operations or processes described herein. In some embodiments, a hard-wired circuit may be used to replace multiple instructions or to be combined with multiple instructions to perform one or more operations or processes described herein. Additionally or alternatively, the processor 920 may be configured to perform one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuits and software.

[0262] Provided in Fig. 9 The number and arrangement of components shown in FIG. are provided as an example. Fig. 9 , device 900 may include additional components, fewer components, different components, or components in a different arrangement. Additionally or alternatively, a group of multiple components (e.g., one or more components) of device 900 may perform one or more functions (described as being performed via another group of multiple components of device 900).

[0263] Fig.10 is a flow chart of an example process 1000 associated with forming a semiconductor device as described herein. In some implementations, Fig.10 The one or more process blocks of are performed by one or more semiconductor process tools (e.g., one or more of the plurality of semiconductor process tools 102 to 116). Additionally or alternatively, performing Fig.10 One or more process blocks may be implemented via one or more components of the apparatus 900 , such as a processor 920 , a memory 930 , an input component 940 , an output component 950 , and / or a communication component 960 .

[0264] As in Fig.10 As shown in FIG. 1 , process 1000 may include forming an isolation structure in a substrate, the isolation structure surrounding at least one photodiode (block 1010). For example, one or more of the plurality of semiconductor process tools 102-116 may form an isolation structure 310 in substrate 306, the isolation structure 310 surrounding at least one photodiode 308, as described herein.

[0265] As in Fig.10As further shown in FIG. 1 , process 1000 may include patterning a portion of the substrate corresponding to the optical blocking area to form a recessed pattern (block 1020). For example, one or more of the plurality of semiconductor process tools 102 to 116 may pattern a portion of substrate 306 corresponding to optical blocking area 206 to form recessed pattern 362 or 372, as described herein.

[0266] As in Fig.10 As further shown in FIG. 1 , process 1000 may include forming a dielectric layer over the isolation structure and over the portion of the substrate corresponding to the optical blocking region, wherein the dielectric layer has a shape that conforms to the recessed pattern (block 1030). For example, one or more of the plurality of semiconductor process tools 102 to 116 may form an adhesive layer 316 over the isolation structure 310 and over the portion of the substrate 306 corresponding to the optical blocking region 206, such that the adhesive layer 316 has a shape that conforms to the recessed pattern 362 or 372, as described herein.

[0267] As in Fig.10 As further shown in FIG. 1 , process 1000 may include forming a metal layer over the dielectric layer, wherein the metal layer has a shape that conforms to the pattern of recesses in the optical blocking region (block 1040). For example, one or more of the plurality of semiconductor process tools 102 to 116 may form metal layer 318 over adhesion layer 316, such that metal layer 318 has a shape that conforms to the pattern of recesses 362 or 372 in optical blocking region 206, as described herein.

[0268] Process 1000 may include additional embodiments, such as any single embodiment or any combination of embodiments described below, and / or be combined with one or more other processes described elsewhere herein.

[0269] In a first embodiment, patterning a portion of substrate 306 includes forming a plurality of high absorption regions in substrate 306, the high absorption regions being approximately pyramidal in shape.

[0270] In a second embodiment, either alone or in combination with the first embodiment, each of the plurality of high absorbency regions is associated with an angle ranging from about 54° to about 55°.

[0271] In the third embodiment, alone or in combination with one or more of the first and second embodiments, patterning a portion of the substrate 306 includes forming a plurality of shallow isolation structures 374 in the substrate 306 .

[0272] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, each of the plurality of shallow isolation structures has a width ranging from about 100 nanometers to about 400 nanometers.

[0273] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, forming the metal layer 318 includes forming the metal layer 318 over the adhesion layer 316 in the optical blocking region 206 and over the isolation structure 310 to form a metal grid 320 .

[0274] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, forming the metal layer 318 further includes forming a conductive pad 336 over the conductive pad region 208 .

[0275] In the seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, forming the metal layer 318 further includes forming a ground node 342 adjacent to at least one photodiode 308 and connected to the substrate 306 .

[0276] although Fig.10 An example block diagram of process 1000 is shown, but in some embodiments, process 1000 includes Fig.10 More blocks, fewer blocks, different blocks, or a different arrangement of blocks than those shown in . Additionally or alternatively, two or more blocks of process 1000 may be performed in parallel.

[0277] In this manner, an optical blocking region formed with patterned metal reduces light reflection toward a plurality of pixel sensors in a pixel sensor array. The optical blocking region may be formed of a metal nanoscale grid to reflect more light away from the pixel sensors. The optical blocking region may include a dielectric layer supporting the patterned metal with a highly absorbing structure or a shallow deep trench isolation (DTI) structure to increase absorption and thereby reduce light reflection toward the pixel sensors.

[0278] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes at least one pixel sensor. The semiconductor device includes an optical blocking region adjacent to the at least one pixel sensor. The optical blocking region includes a substrate, a dielectric layer above the substrate, and a metal layer above the dielectric layer, the metal layer including a nanoscale grid and configured to reflect light away from the at least one pixel sensor.

[0279] In some embodiments, in a semiconductor device, the nanoscale grid includes a plurality of metal structures, and each of the metal structures has a width ranging from about 100 nanometers to about 200 nanometers.

[0280] In some embodiments, the semiconductor device further includes: a portion of the metal layer, between the nanoscale grid and the at least one pixel sensor, connected to the substrate and used for grounding.

[0281] In some embodiments, the semiconductor device further comprises: an isolation structure and a metal grid. The isolation structure surrounds at least one photodiode of the at least one pixel sensor. The metal grid is above the isolation structure.

[0282] As described in more detail above, some embodiments described herein provide a method. The method includes forming an isolation structure in a substrate around at least one photodiode. The method includes patterning a portion of the substrate corresponding to the optical blocking area to form a recessed pattern. The method includes forming a dielectric layer above the isolation structure and above the portion of the substrate corresponding to the optical blocking area, wherein the dielectric layer has a shape consistent with the recessed pattern. The method includes forming a metal layer above the dielectric layer, wherein the metal layer has a shape consistent with the recessed pattern in the optical blocking area.

[0283] In some embodiments, in a method of manufacturing a semiconductor device, patterning a portion of a substrate includes forming a plurality of highly absorbing (HA) regions approximately in a pyramid shape in the substrate.

[0284] In some embodiments, in a method of fabricating a semiconductor device, each of the plurality of high absorption regions is associated with an angle ranging from about 54 degrees to about 55 degrees.

[0285] In some embodiments, in a method of manufacturing a semiconductor device, patterning a portion of a substrate includes forming a plurality of shallow isolation structures in the substrate.

[0286] In some embodiments, in a method of fabricating a semiconductor device, each of the shallow isolation structures has a width ranging from about 100 nanometers to about 400 nanometers.

[0287] In some embodiments, in a method of manufacturing a semiconductor device, forming a metal layer includes: forming a metal layer over a dielectric layer and over an isolation structure in an optical blocking region to form a metal grid.

[0288] In some embodiments, in the method for manufacturing a semiconductor device, forming a metal layer further includes: forming an electrical pad over the electrical pad region.

[0289] In some embodiments, in the method of manufacturing a semiconductor device, forming the metal layer further includes: forming a ground node adjacent to the at least one photodiode connected to the substrate.

[0290] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes at least one pixel sensor. The semiconductor device includes an optical blocking region adjacent to the at least one pixel sensor. The optical blocking region includes a substrate, a dielectric layer above the substrate and including a recessed pattern, and a metal layer above the dielectric layer, the metal layer having a shape consistent with the recessed pattern and configured to reflect light away from the at least one pixel sensor.

[0291] Some embodiments of the present disclosure provide a semiconductor device comprising: at least one pixel sensor and an optical blocking region. The optical blocking region is adjacent to the at least one pixel sensor and comprises: a substrate, a dielectric layer, and a metal layer. The dielectric layer is above the substrate and includes a recessed pattern. The metal layer is above the dielectric layer, has a shape consistent with the recessed pattern and is configured to reflect light away from the at least one pixel sensor. The metal layer additionally forms a metal grid, the metal grid is above an isolation structure, and the isolation structure at least partially surrounds at least one photodiode in the at least one pixel sensor.

[0292] In some embodiments, in a semiconductor device, the metal grid follows a pattern of recesses.

[0293] In some embodiments, in a semiconductor device, a substrate includes a pattern of recesses below a dielectric layer.

[0294] In some embodiments, in a semiconductor device, a pattern of depressions in a substrate includes a plurality of high absorption (HA) regions, the plurality of high absorption (HA) regions approximately having a pyramid shape.

[0295] In some embodiments, in a semiconductor device, each of the high absorption regions is associated with an angle ranging from about 54 degrees to about 55 degrees.

[0296] In some embodiments, in a semiconductor device, a pattern recessed in a substrate includes a plurality of shallow isolation structures.

[0297] In some embodiments, in the semiconductor device, each of the shallow isolation structures has a depth ranging from about 0.5 micrometers (μm) to about 6.0 μm.

[0298] In some embodiments, the semiconductor device further includes: a portion of the metal layer, adjacent to the at least one pixel sensor, connected to the substrate for grounding.

[0299] Some embodiments of the present disclosure provide a semiconductor device comprising: at least one pixel sensor and an optical blocking region. The optical blocking region is adjacent to the at least one pixel sensor and comprises: a substrate, a dielectric layer, and a metal layer. The dielectric layer is above the substrate and comprises a recessed pattern. The substrate comprises the recessed pattern below the dielectric layer. The metal layer is above the dielectric layer, has a shape consistent with the recessed pattern and is configured to reflect light away from the at least one pixel sensor. The metal layer additionally forms a metal grid, the metal grid is above an isolation structure, and the isolation structure at least partially surrounds at least one photodiode in the at least one pixel sensor.

[0300] In some embodiments, the pattern of depressions in the substrate includes a plurality of high absorption (HA) regions that approximate a pyramid shape.

[0301] In some embodiments, the pattern recessed in the substrate includes a plurality of shallow isolation structures.

[0302] As used herein, depending on the context, "satisfying a threshold" may mean that a value is greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, or the like.

[0303] The above summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may easily use the present disclosure as a basis for the design or modification of other processes and structures to achieve the same purpose as the embodiments introduced herein, and / or to achieve the same advantages. Those skilled in the art will also appreciate that such equal constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: at least one pixel sensor; and an optical blocking region, adjacent to the at least one pixel sensor, comprising: a substrate; a dielectric layer over the substrate; and A metal layer, over the dielectric layer, includes a nanoscale grid and is configured to reflect light away from the at least one pixel sensor.

2. The semiconductor device according to claim 1, wherein The nanoscale grid includes a plurality of metal structures, and each metal structure has a width ranging from 100 nanometers to 200 nanometers.

3. The semiconductor device according to claim 1, wherein: Also includes: A portion of the metal layer, between the nanoscale grid and the at least one pixel sensor, is connected to the substrate and is used for grounding.

4. The semiconductor device according to claim 1, wherein: Also includes: an isolation structure surrounding at least one photodiode of the at least one pixel sensor; and A metal grid is above the isolation structure.

5. A semiconductor device, characterized in that: Include: at least one pixel sensor; and an optical blocking region, adjacent to the at least one pixel sensor, comprising: a substrate; a dielectric layer over the substrate and including a recessed pattern; and a metal layer, over the dielectric layer, having a shape conforming to the pattern of recesses and configured to reflect light away from the at least one pixel sensor, The metal layer additionally forms a metal grid, the metal grid being above an isolation structure, the isolation structure at least partially surrounding at least one photodiode in the at least one pixel sensor.

6. The semiconductor device according to claim 5, wherein: The metal grid follows the pattern of the recesses.

7. The semiconductor device according to claim 5, wherein: Also includes: A portion of the metal layer, adjacent to the at least one pixel sensor, is connected to the substrate for grounding.

8. A semiconductor device, characterized in that: Include: at least one pixel sensor; and an optical blocking region, adjacent to the at least one pixel sensor, comprising: a substrate; a dielectric layer over the substrate and including a recessed pattern, wherein the substrate includes the recessed pattern below the dielectric layer; and a metal layer, over the dielectric layer, having a shape conforming to the pattern of recesses and configured to reflect light away from the at least one pixel sensor, The metal layer additionally forms a metal grid, the metal grid being above an isolation structure, the isolation structure at least partially surrounding at least one photodiode in the at least one pixel sensor.

9. The semiconductor device according to claim 8, wherein: in, The pattern of depressions in the substrate includes a plurality of high absorption regions that are approximately pyramid-shaped.

10. The semiconductor device according to claim 8, wherein The recessed pattern in the substrate includes a plurality of shallow isolation structures.

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