Circuit structure for serial port bypass

Abstract

The utility model relates to a circuit structure used for serial port bypass. The circuit structure comprises a first signal relay used for being connected with a first serial port module and a second signal relay used for being connected with a second serial port module. When the first serial port module is not powered on, a pin 3 of the first signal relay is connected with a pin 2 of the first signal relay, and a pin 6 of the second signal relay is connected with a pin 7 of the second signal relay, so that a signal of the first serial port module is sent to the second serial port module; a pin 3 of the second signal relay is connected with a pin 2 of the second signal relay, and a pin 6 of the first signal relay is connected with a pin 7 of the first signal relay, so that a signal of the second serial port module is sent to the first serial port module; when the circuit is not powered on, the communication between the first serial port module and the second serial port module can be realized, the whole circuit is simple, the complexity of the system is reduced, and the cost is low.

Description

Technical Field

[0001] The utility model relates to the technical field of circuit structures used for serial port bypass, in particular to a circuit structure used for serial port bypass. Background Art

[0002] The BYPASS function is a basic function requirement in network security devices. Currently, most network security devices have the BYPASS function for electrical or optical ports.

[0003] In actual applications, network interfaces are not used between various serial devices, especially low-speed devices. Some vehicle-mounted devices use low-speed serial port signals, especially TTL serial ports are used directly between modules in a device. Such vehicle-mounted devices need to add a firewall module between the external module and the internal module to simultaneously realize industrial virus detection, industrial intrusion protection, access control and other functions.

[0004] This firewall module also needs to implement the serial port BYPASS function, which can directly physically connect the internal and external ports to protect basic business communications when the device is powered off or crashes.

[0005] Since the existing BYPASS device is an independent device, the external control method is mostly implemented through serial port or USB, which increases the complexity of the system in terms of communication. In addition, an independent subsystem is required, which not only increases the complexity of the overall system, but also has a relatively high cost.

[0006] Therefore, in the utility model patent application, the applicant carefully studied a circuit structure for serial port bypass to solve the above problems. Utility Model Content

[0007] The utility model aims to overcome the deficiencies in the above-mentioned prior art, and its main purpose is to provide a circuit structure for serial port bypass, which can realize communication between a first serial port module and a second serial port module when there is no power on, has a simple overall circuit, reduces system complexity, and has low cost.

[0008] In order to achieve the above-mentioned purpose, the utility model adopts the following technical solutions:

[0009] A circuit structure for serial port bypass includes a first signal relay for connecting to a first serial port module and a second signal relay for connecting to a second serial port module;

[0010] Pin 3 and pin 6 of the first signal relay are both used to connect to the first serial port module, and pin 4 and pin 5 of the first signal relay are both used to connect to the CPU;

[0011] Pin 3 and pin 6 of the second signal relay are both used to connect to the second serial port module, and pin 4 and pin 5 of the second signal relay are both used to connect to the CPU;

[0012] Pin 2 of the first signal relay is connected to pin 7 of the second signal relay, and pin 2 of the second signal relay is connected to pin 7 of the first signal relay;

[0013] After power-on, pin 3 of the first signal relay is connected to pin 4, and pin 6 of the first signal relay is connected to pin 5 to communicate with the first serial port module and the CPU; at the same time, pin 3 of the second signal relay is connected to pin 4, and pin 6 of the second signal relay is connected to pin 5 to communicate with the second serial port module and the CPU;

[0014] When there is no power, the pin 3 of the first signal relay is connected to its pin 2, and the pin 6 of the second signal relay is connected to its pin 7, so as to send the signal of the first serial port module to the second serial port module;

[0015] Pin 3 of the second signal relay is connected to pin 2 thereof, and pin 6 of the first signal relay is connected to pin 7 thereof, so as to send the signal of the second serial port module to the first serial port module.

[0016] As a preferred solution, a power isolation circuit is also included, and pins 1 of both the first signal relay and the second signal relay are connected to the power isolation circuit.

[0017] As a preferred solution, a signal isolation circuit is also included, and pins 4 and 5 of both the first signal relay and the second signal relay are connected to the signal isolation circuit.

[0018] As a preferred solution, a high-speed optocoupler circuit is further included, the input end of the high-speed optocoupler circuit is connected to the CPU, and the pins 8 of both the first signal relay and the second signal relay are connected to the output end of the high-speed optocoupler circuit.

[0019] Compared with the prior art, the utility model has obvious advantages and beneficial effects. Specifically, it mainly realizes communication between the first serial port module and the second serial port module when there is no power on through the cooperation of the first signal relay and the second signal relay. The overall circuit is simple, the complexity of the system is reduced, and the cost is low.

[0020] Secondly, through the cooperation of power isolation circuit, signal isolation circuit and high-speed optocoupler circuit, signal isolation and protection can be achieved when the CPU communicates with external devices.

[0021] In order to more clearly illustrate the structural features and effects of the present invention, it is described in detail below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a general control principle block diagram of an embodiment of the utility model;

[0023] Figure 2 This is a schematic diagram of the first signal relay of the embodiment of the utility model;

[0024] Figure 3 It is a schematic diagram of the second signal relay of the embodiment of the utility model;

[0025] Figure 4 It is a partial schematic diagram of an embodiment of the utility model (mainly showing a power isolation circuit, a signal isolation circuit and a high-speed optocoupler circuit).

[0026] Description of Figure Numbers:

[0027] 11. First serial port module

[0028] 12. First signal relay

[0029] 13. CPU

[0030] 14. Second signal relay

[0031] 15. Second serial port module

[0032] 16. Power isolation circuit

[0033] 17. Signal isolation circuit

[0034] 18. High-speed optocoupler circuit. DETAILED DESCRIPTION

[0035] The utility model is further described below in conjunction with the accompanying drawings and specific implementation methods.

[0036] like Figures 1 to 4 As shown, a circuit structure for serial port bypass includes a first signal relay 12 for connecting to a first serial port module 11 and a second signal relay 14 for connecting to a second serial port module 15;

[0037] Pin 3 and pin 6 of the first signal relay 12 are both used to connect to the first serial port module 11, and pin 4 and pin 5 of the first signal relay 12 are both used to connect to the CPU 13;

[0038] Pin 3 and pin 6 of the second signal relay 14 are both used to connect to the second serial port module 15, and pin 4 and pin 5 of the second signal relay 14 are both used to connect to the CPU 13;

[0039] Pin 2 of the first signal relay 12 is connected to pin 7 of the second signal relay 14, and pin 2 of the second signal relay 14 is connected to pin 7 of the first signal relay 12;

[0040] After power-on, the pin 3 of the first signal relay 12 is connected to its pin 4, and the pin 6 of the first signal relay 12 is connected to its pin 5 so as to communicate with the first serial port module 11 and the CPU 13; at the same time, the pin 3 of the second signal relay 14 is connected to its pin 4, and the pin 6 of the second signal relay 14 is connected to its pin 5 so as to communicate with the second serial port module 15 and the CPU 13;

[0041] When not powered on, the pin 3 of the first signal relay 12 is connected to its pin 2, and the pin 6 of the second signal relay 14 is connected to its pin 7, so as to send the signal of the first serial port module 11 to the second serial port module 15;

[0042] Pin 3 of the second signal relay 14 is connected to pin 2 thereof, and pin 6 of the first signal relay 12 is connected to pin 7 thereof, so as to send the signal of the second serial port module 15 to the first serial port module 11 .

[0043] It also includes a power isolation circuit 16, a signal isolation circuit 17 and a high-speed optocoupler circuit 18. Pins 1 of both the first signal relay 12 and the second signal relay 14 are connected to the power isolation circuit 16. As shown in the figure, the power isolation circuit 16 is composed of a chip U51 of model F0505S-1WR3 and its peripheral circuits.

[0044] Pins 4 and 5 of the first signal relay 12 and the second signal relay 14 are connected to the signal isolation circuit 17. As shown in the figure, the signal isolation circuit 17 is composed of a chip U52 of model SCCK11412BW2E1 and its peripheral circuits. The rate of the chip U52 meets the commonly used baud rates of the serial port, such as 9600 and 115200 bps.

[0045] The input end of the high-speed optocoupler circuit 18 is connected to the CPU 13 , and the pins 8 of both the first signal relay 12 and the second signal relay 14 are connected to the output end of the high-speed optocoupler circuit 18 .

[0046] In this embodiment, the high-speed optocoupler circuit 18 includes a resistor R1525, a resistor R619, a resistor R1524, a transistor Q9, a resistor R1523, a resistor R1514, a chip U56, a capacitor C1618, a resistor R1513, a resistor R1515, a resistor R1516 and a MOS tube Q11.

[0047] The specific circuit structure and connection relationship of the high-speed optocoupler circuit 18 are as follows: Figure 4As shown. The state of the GPIO4_13 pin of the CPU 13 is high when it is just powered on. The addition of the transistor Q9 and the MOS tube Q11 can make the high and low control of the signal not affected by the optocoupler isolation circuit of the chip U56. When the GPIO4_13 pin of the CPU 13 is high, the transistor Q9 is turned on, the pin 3 of the chip U56, namely the GPIO_BP, is low, the chip U56 is turned on, the series node BLAN12_W of the resistor R1515 and the resistor R1516 is low, the MOS tube Q11 is not turned on, the drain of the MOS tube Q11, namely the LAN12GND, is high, that is, the pin 8 of the first signal relay 12 and the second signal relay 14 is high, the first signal relay 12 and the second relay are not turned on, and the bypass function is turned on. Similarly, after entering the system, the CPU 13 can control its GPIO4_13 pin state to be low, the transistor Q9 and the chip U56 are not conducting, the MOS tube Q11 is conducting, the drain of the MOS tube Q11, namely LAN12GND, is low, the first signal relay 12 and the second relay are both opened, and the bypass function is closed.

[0048] The key points of the design of the utility model are that it can realize communication between the first serial port module and the second serial port module when there is no power on, mainly through the cooperation of the first signal relay and the second signal relay, the overall circuit is simple, the complexity of the system is reduced, and the cost is low;

[0049] Secondly, through the cooperation of power isolation circuit, signal isolation circuit and high-speed optocoupler circuit, signal isolation and protection can be achieved when the CPU communicates with external devices.

[0050] The above description is only a preferred embodiment of the present invention and does not limit the technical scope of the present invention. Therefore, any minor modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A circuit structure for serial port bypass, characterized in that: It includes a first signal relay for connecting to the first serial port module and a second signal relay for connecting to the second serial port module; Pin 3 and pin 6 of the first signal relay are both used to connect to the first serial port module, and pin 4 and pin 5 of the first signal relay are both used to connect to the CPU; Pin 3 and pin 6 of the second signal relay are both used to connect to the second serial port module, and pin 4 and pin 5 of the second signal relay are both used to connect to the CPU; Pin 2 of the first signal relay is connected to pin 7 of the second signal relay, and pin 2 of the second signal relay is connected to pin 7 of the first signal relay; After power-on, pin 3 of the first signal relay is connected to pin 4, and pin 6 of the first signal relay is connected to pin 5 to communicate with the first serial port module and the CPU; at the same time, pin 3 of the second signal relay is connected to pin 4, and pin 6 of the second signal relay is connected to pin 5 to communicate with the second serial port module and the CPU; When there is no power, the pin 3 of the first signal relay is connected to its pin 2, and the pin 6 of the second signal relay is connected to its pin 7, so as to send the signal of the first serial port module to the second serial port module; Pin 3 of the second signal relay is connected to pin 2 thereof, and pin 6 of the first signal relay is connected to pin 7 thereof, so as to send the signal of the second serial port module to the first serial port module.

2. The circuit structure for serial port bypass according to claim 1, characterized in that: A power isolation circuit is also included, and pins 1 of both the first signal relay and the second signal relay are connected to the power isolation circuit.

3. The circuit structure for serial port bypass according to claim 1, characterized in that: A signal isolation circuit is also included, and pins 4 and 5 of both the first signal relay and the second signal relay are connected to the signal isolation circuit.

4. The circuit structure for serial port bypass according to claim 1, characterized in that: A high-speed optocoupler circuit is also included, the input end of the high-speed optocoupler circuit is connected to the CPU, and the pins 8 of both the first signal relay and the second signal relay are connected to the output end of the high-speed optocoupler circuit.

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