Semiconductor device

Abstract

The utility model provides a semiconductor device. A semiconductor device includes a substrate and a plurality of gate structures disposed on the substrate. And the multi-layer interconnection is arranged above the substrate and the gate structure. And a substrate via extending vertically through the substrate and the multilayer interconnect. In one embodiment, the through substrate via has a first sidewall in a cross-sectional view, where the first sidewall includes an upper portion that interfaces with a first dielectric material of the multilayer interconnect; a middle interface with a second dielectric material, the second dielectric material being different from the first dielectric material; and a lower portion bordering the substrate.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to semiconductor technology, and more particularly to a semiconductor device with a through hole and a method for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in integrated circuit materials and design have led to several generations of integrated circuits, each with smaller and more complex circuits than the previous one. During the evolution of integrated circuits, functional density (that is, the number of interconnected devices per unit chip area) generally increases while geometry size (that is, the smallest component (or line) that can be produced using a process) decreases. This process of miniaturization generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] Recently, more and more attempts have focused on vias, such as through-silicon vias (TSVs) or through-substrate vias (TSVs). TSVs have found application in three-dimensional integrated circuits, where they are used to route electrical signals from one side of the silicon substrate of the integrated circuit to the other side. Generally, TSVs are formed by etching a vertical via opening through the substrate and filling the via opening with a conductive material. Although existing TSV structures and methods of making them are generally adequate for their intended purposes, they are not yet completely satisfactory in all aspects. Utility Model Content

[0004] The purpose of the present invention is to provide a semiconductor device to solve at least one of the above problems.

[0005] The present disclosure provides a semiconductor device. The device includes a substrate and a plurality of gate structures disposed on the substrate. A multilayer interconnect is disposed above the substrate and the gate structure. A through substrate via vertically extends through the substrate and the multilayer interconnect. In one embodiment, the through substrate via has a first sidewall in a cross-sectional view, wherein the first sidewall includes an upper portion that interfaces with a first dielectric material of the multilayer interconnect; a middle portion that interfaces with a second dielectric material, the second dielectric material being different from the first dielectric material; and a lower portion that interfaces with the substrate.

[0006] According to one embodiment of the present invention, the invention further includes: a shallow trench isolation structure, which is disposed on the substrate and borders the second dielectric material.

[0007] According to one embodiment of the present invention, it further includes: an interlayer dielectric layer, which is disposed on the shallow trench isolation structure and is coplanar with the plurality of gate structures.

[0008] According to one embodiment of the present invention, the multi-layer interconnection further includes a plurality of metallization layers extending laterally in the cross-sectional view.

[0009] According to one embodiment of the present invention, the substrate through hole includes: a barrier layer disposed on the first side wall; and a metal filling layer surrounded by the barrier layer in a top view.

[0010] According to one embodiment of the present invention, it further includes: a cut gate isolation structure, which intersects with the end of the gate structure in the top view.

[0011] According to one embodiment of the present invention, the second dielectric material surrounds the middle portion of the substrate through hole in a top view.

[0012] According to one embodiment of the present invention, at least a portion of the middle portion of the first sidewall is coplanar with the plurality of gate structures.

[0013] According to one embodiment of the present invention, it further includes: a first conductive layer and a first insulating layer, which are arranged on the substrate through hole.

[0014] According to one embodiment of the present invention, the invention further includes: a second conductive layer and a second insulating layer, which are disposed on the back side of the substrate adjacent to the substrate through hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The following will be in conjunction with the attached drawings to describe various aspects of the present disclosure. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale and are only used for illustration. In fact, the size of the elements can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present disclosure.

[0016] Figure 1 Embodiments of methods for forming a device structure and a via structure passing through the device structure are shown according to various aspects of the present disclosure.

[0017] Figure 2A , Figure 3 , Figure 4 , Figure 5A , Figure 6 , Fig. 7A , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig. 12A , Fig.13 ,as well as Fig.14 According to various methods of the present disclosure, the work object experience Figure 1 Schematic diagram of a partial cross section of the method operation.

[0018] Figure 2B , Figure 5B , Figure 7B ,as well as Fig. 12B According to various methods of the present disclosure, the work object experience Figure 1 Schematic top view of the operation of the method in .

[0019] The reference numerals are as follows:

[0020] 100: Method

[0021] 102 / 104 / 106 / 108 / 110 / 112 / 114 / 116 / 118 / 120 / 122 / 124 / 126: Block 106A / 106B / 106C: Sub-step 200: Device

[0022] 202: Base

[0023] 204: Isolation Structure

[0024] 206: Spacer

[0025] 208: (Metal) Gate Structure

[0026] 210: Installation area

[0027] 212:Through hole area

[0028] 214: Front-end-of-line (FEOL) equipment

[0029] 302 / 800A / 802A: Interlayer dielectric layer

[0030] 404: First layer / hard mask layer

[0031] 406: Second layer / hard mask layer

[0032] 502 / 902 / 902': Open

[0033] 504: Gate cutting area / cutting gate opening / opening

[0034] 602: Dielectric material

[0035] 800: Middle of the Line (MEOL) layer

[0036] 800B: (gate) contact plug

[0037] 802: Back-end of line (MEOL) layer / multi-layer interconnect (MLI) structure

[0038] 802B: Metallization layer

[0039] 802C:Through hole

[0040] 1102: Conductive material / metal filling layer

[0041] 1104: Conductive material / barrier layer

[0042] 1200:Through Silicon Via (TSV)

[0043] 1300 / 1400: Interconnection layer

[0044] 1300A / 1400A: Insulation layer

[0045] 1300B / 1400B: Conductive layer

[0046] D / W1 / W2: Dimensions

[0047] M1 / M2 / Mn: Metallization layer

[0048] W3: Width DETAILED DESCRIPTION

[0049] Various embodiments of the present disclosure relate to an integrated circuit device, and more particularly, to an interconnect structure for an integrated circuit device.

[0050] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, if the description mentions that a first element is formed on a second element, an embodiment in which the first and second elements are in direct contact may be included, and an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact may also be included. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0051] Furthermore, spatially relative terms such as "under", "below", "lower", "above", "upper" and the like may be used to facilitate description of the relationship between one component or parts and another component or parts in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the turned orientation.

[0052] In addition, when "approximately," "approximately," etc. are used to describe a number or a range of numbers, such terms are intended to cover numbers within a reasonable range, which is based on the variations inherent in the manufacturing process understood by those skilled in the art. For example, based on the known manufacturing tolerances for manufacturing components with the number associated with the component, the number or range of numbers covers a reasonable range including the number, such as within + / -10% of the number. For example, it is known to those skilled in the art that the manufacturing tolerance associated with the deposited material layer is + / -15%, and a material layer with a thickness of "about 5 nanometers" can cover a size range of 4.25 nanometers to 5.75 nanometers. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of conciseness and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0053] The interconnect structure electrically couples various components (e.g., electrodes, resistors, capacitors, and / or inductors) fabricated on a substrate so that the various components can operate in a manner specified by the design requirements. The interconnect structure includes a combination of a dielectric layer and a conductive layer configured to provide electrical signal routing, the conductive layer including vias and contact components that provide vertical connections and conductive lines that provide horizontal connections. In some embodiments, the interconnect structure may have multiple metal layers (or metallization layers) vertically interconnected by vias or contact components, and may be referred to as a multi-layer interconnect (MLI) structure. During operation of the integrated circuit device, the interconnect structure routes signals between components of the integrated circuit device and / or distributes signals (e.g., clock signals, voltage signals, and / or ground signals) to the components. The interconnect structure is formed in the back-end-of-the-line (BEOL) process, generally after the front-end-of-the-line (FEOL) process to form active devices (e.g., transistors on a substrate), and in the middle-end-of-the-line (MEOL) process to form contacts to the active devices, such as source / drain regions and conductive plugs for gate structures.

[0054] In some embodiments, it is desirable to provide a vertical interconnect extending through an interconnect structure and / or a substrate to facilitate various device structures, such as complementary metal-oxide-semiconductor (CMOS) image sensors (CISs), three-dimensional integrated circuits (3DIC), micro-electro-mechanical-system (MEMS) devices, radio frequency (RF) devices, wafer on wafer (WoW) devices, etc. Such a vertical interconnect may be referred to as a through-silicon via (TSV) or through-substrate via (TSV) because it extends through all or part of a semiconductor substrate. The term through-via or TSV in the present disclosure broadly encompasses a through-hole structure that provides direct signal routing from the front side of a substrate to the back side of a substrate, or vice versa. The TSV may extend vertically not only through the substrate, but may also extend vertically through the BEOL, MEOL, and / or FEOL regions of a device.

[0055] The vias and the areas in which the vias are formed generally span a relatively large area of ​​the substrate. In some embodiments, the vias are larger than the active devices of the device (e.g., transistors formed in a FEOL process), and therefore, the via region may have a pattern density that is significantly different from the active device region. Leaving a large vacant area to receive the vias when forming a semiconductor device (e.g., forming a FEOL, MEOL, or BEOL structure) can result in a significant process challenge, such as inconsistent processes in the via region due to pattern density differences. In one embodiment, dishing can occur in the via region during a process such as chemical mechanical polishing or planarization (CMP), but this dishing in turn can result in other process issues, such as gate profile development (e.g., polysilicon dummy gate structures).

[0056] The vias may be formed during or after the BEOL process, separate from the FEOL and MEOL processes. The present disclosure provides a method for processing a via region during the formation of FEOL components and a semiconductor structure, for example: by forming components in the via region also during the FEOL process, pattern uniformity is improved, and therefore, process challenges, such as reducing recesses, may be alleviated. In some embodiments, the FEOL process includes forming a sacrificial gate in the via region while forming an active transistor gate. In other words, in some embodiments, the metal gate is formed not only in the active region by a replacement gate process, but also in the via region by a replacement gate process. These gates in the via region are referred to as sacrificial gates because they are subsequently removed from the via region.

[0057] Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 is a flowchart showing a method 100 of forming a device structure according to various aspects of the present disclosure, wherein the device structure is a device 200 (FIG. 2 to FIG. 3 ) including a via structure. Fig.13 The method 100 is merely illustrative and is not intended to limit the present disclosure to what is explicitly described in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. Figure 2A (include Figure 2A as well as Figure 2B )to Fig.13 Describing method 100, Figures 2A to 13 1 is a partial cross-sectional schematic diagram and a top schematic diagram of a device 200 at different manufacturing stages according to various embodiments of the method 100. In the present disclosure, like reference numerals refer to like components unless otherwise explicitly stated.

[0058] The device 200 shown in the drawings of the present disclosure is simplified and not all components in the device 200 are shown or described in detail. The device 200 shown in the drawings can be an integrated circuit (IC) chip, a system on chip (SoC) or a portion thereof, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused metal-oxide semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components or combinations of the foregoing. In some embodiments, the device 200 and the formed vias are interconnected with another device (such as another device 200), for example: in a stacked form.

[0059] refer to Figure 1 , Figure 2A and Figure 2B, method 100 includes block 102, where a substrate 202 is provided. Substrate 202 is a portion of device 200, which will include further structures as method 100 proceeds. In one embodiment, substrate 202 includes silicon (Si). Alternatively or additionally, substrate 202 may include another elemental semiconductor, such as germanium (Ge); a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); or a combination of the foregoing. Alternatively, the substrate 202 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. The semiconductor-on-insulator substrate may be manufactured using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. Depending on the design requirements of the device 200, the substrate 202 may include various doped regions (not shown). In some embodiments, the substrate 202 includes a p-type doped region (e.g., a p-type well) doped with a p-type dopant, such as boron (e.g., boron fluoride (BF2)), indium, other p-type dopants, or a combination of the foregoing. In some embodiments, the substrate 202 includes an n-type doped region (e.g., an n-type well) doped with an n-type dopant, such as phosphorus (P), arsenic (As), other n-type dopants, or a combination of the foregoing. In some embodiments, the substrate 202 includes doped regions formed by a combination of p-type dopants and n-type dopants. Various doped regions can be formed directly on and / or in the substrate 202, for example, to provide a p-well structure, an n-well structure, a double-well structure, a raised structure, or a combination thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes can be performed to form the various doped regions.

[0060] Method 100 includes block 104, in which an active region is formed on substrate 202 in a FEOL process. In some embodiments, the active region is formed in a fin-shaped region, such as provided when forming a fin field-effect transistor (FinFET). In some embodiments, the active region is designed to form other multi-gate devices, such as a gate-all-around (GAA) transistor. A GAA transistor has a gate structure that can extend partially or completely around a channel region to provide access to the channel region on two or more sides. The channel region may include nanowires, nanosheets, or other shaped nanostructures. In some embodiments, the active region is planar, such as formed in a planar transistor. Between the active regions, there may be an isolation region extending between the active regions (e.g., fins or planar regions), such as a shallow trench isolation (STI) component, see isolation structure 204.

[0061] In some embodiments, the fins may be formed by directly patterning the top of the substrate 202 so that the fins protrude from the substrate 202, or by epitaxially growing an epitaxial stack of a first semiconductor layer (e.g., silicon) and a second semiconductor layer (e.g., silicon germanium), the epitaxial stacks being alternately disposed on the substrate 202 ( Figure 3 The fins are patterned by any suitable method, for example: the fins can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography processes with self-alignment processes to create, for example, patterns with a smaller pitch than that obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used as masks to pattern the fins.

[0062] In some embodiments, the formation of the active region includes forming a stack of multiple channel layers interlaced by multiple sacrificial layers. The film layers in the stack can be deposited on the substrate 202 using an epitaxial process. Exemplary epitaxial processes may include vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE) processes and / or other suitable processes. The channel layer and the sacrificial layer may have different semiconductor compositions. In some embodiments, the channel layer is formed of silicon (Si) and the sacrificial layer is formed of silicon germanium (SiGe), and the additional germanium (Ge) content in the sacrificial layer allows selective removal or depression of the sacrificial layer without significantly damaging the channel layer. The sacrificial layer and the channel layer are alternately arranged so that the sacrificial layer is interlaced with the channel layer. The number of film layers depends on the number of channel regions required for the device 200. In some embodiments, the number of channel layers is between 1 and 6.

[0063] In some embodiments, certain areas of the substrate 202 are designed to be used to form device regions, including FEOL active devices such as transistors, BEOL structures such as MLI, capacitors, memory structures, passive devices and / or other suitable structures. These areas are referred to as device regions. Figure 2A and Figure 2B The device region 210 is shown in FIG. 2 as an active region and a surrounding insulating region (eg, an isolation structure such as STI) disposed between the active regions. Other regions of the substrate 202 are designed to be regions for forming through-holes (also referred to as TSVs). Figure 2A and Figure 2B 2 is shown as a via region 212. In some embodiments, the via region 212 has a dimension D. In some embodiments, the dimension D is, for example, 5 microns or greater. In one embodiment, the via region 212 has a dimension D of approximately 6 microns. In one embodiment, the via region 212 has a dimension D between approximately 5 microns and 10 microns. It should be noted that each substrate 202 has a plurality of via regions 212 and a device region 210, and the dimension D can be measured in any and / or all directions of the via region 212, and the dimension D may be significantly larger (e.g., 5 times) than the size of the device component (e.g., gate structure).

[0064] In some embodiments, the via region 212 is approximately circular in a top view schematic. In some embodiments, the via region 212 is elliptical in a top view schematic, wherein at least one dimension is D as described above. In some embodiments, the via region 212 is rectangular (including square) from a top view schematic, wherein at least one dimension is D as described above. These shapes are merely illustrative, and other shapes are also possible, including, for example, octagons. In some embodiments, the via region 212 is defined as having the same shape as a subsequently formed via or TSV. In other embodiments, the via region 212 may have a different shape than a subsequently formed TSV. In each case, the via region 212 encases the TSV to be formed, in other words, the via region 212 is at least as large as the TSV. It should be noted that the via region 212 also encases the dielectric material formed around the TSV (see, for example, dielectric material 602), as described below.

[0065] Although shown on the substrate 202, the via region 212 and the device region 210 may also be defined in design data associated with the device 200. In one embodiment, the via region 212 and the device region 210 are defined in layout data associated with the device 200. The layout data may define the via region in a manner that does not allow placement of active devices of the device 200 in the region in accordance with design rule checker (DRC) software or data. The layout defining the device region 210 and the via region 212 may be defined in a layout database, such as a graphic data system (GDS), a second generation graphic data system (GDSII), an open artwork system interchange standard (OASIS), and / or other suitable layout formats.

[0066] The method 100 includes block 106, where FEOL devices are formed on the substrate active region of the device region. In some embodiments, the FEOL devices include transistor elements such as source / drain regions and / or gate structures. These FEOL devices are also referred to as active FEOL devices because they constitute the functionality of the device 200. While the active FEOL devices are being formed, sacrificial FEOL devices that are structurally equivalent to the active FEOL devices can be formed in the via region of the substrate. These sacrificial FEOL devices can be subsequently removed as discussed in the steps of the method 100 below.

[0067] Active and sacrificial FEOL devices may be formed by various steps, including those shown in sub-step 106A, sub-step 106B, and sub-step 106C in one example. These steps are exemplary only and are not intended to be limiting, and other methods may be used to form FEOL devices. The formed FEOL devices, active FEOL devices, and / or sacrificial FEOL devices may be components of GAA devices, FinFET devices, complementary field effect transistors (CFET) devices, planar transistors, and / or other device structures.

[0068] In one embodiment, block 106 begins with sub-step 106A, where dummy gate structures are formed in the device region and the via region. The dummy gate structures are formed in the device region 210 and the via region 212. In some embodiments, the gate structures are formed in the device region 210 and the via region 212 with substantially the same pattern density. In one embodiment, the pitch of the gate structures in the device region 210 is the same as the pitch of the gate structures in the via region 212. Generally, multiple (two or more) gate structures are formed across the via region 212.

[0069] The dummy gate structure may be polysilicon and is therefore referred to as a polysilicon gate (PG). The dummy gate structure is formed by appropriate patterning and etching to form a dummy gate structure having sidewalls. The dummy gate structure may be substantially as Figure 3 2 and the illustrated configuration of the gate structure 208. On the sidewalls of the gate structure 208, spacer elements, also referred to as spacers, are formed as shown as spacers 206. In some embodiments, the spacers 206 are made of silicon dioxide (SiO2), silicon oxynitride (Si x O y N z ), composite materials (SiO2 / Si3N4), silicon nitride (Si3N4) and / or other suitable dielectric compositions. In some embodiments, the spacer 206 can be formed by blanket deposition of one or more dielectric materials and isotropic etching back of these materials. In some embodiments, the spacer 206 can have a thickness ranging between 1 nanometer and 5 nanometers.

[0070] Block 106 continues to sub-step 106B, where source / drain features are formed adjacent to the dummy gate structure and the spacer element. The source / drain features are formed adjacent to the dummy gate structure in the device region. In some embodiments, the source / drain features are also formed adjacent to the dummy gate structure in the TSV region. In one embodiment, the source / drain features are epitaxially grown from the active region and / or a recess (e.g., fin) within the active region adjacent to the dummy gate structure.

[0071] In some embodiments, the active region and / or the dummy gate structure in the via region 212 is covered by a mask layer (e.g., a photoresist mask) to prevent epitaxial growth in the via region 212. In other embodiments, the source / drain components may also be grown in the via region 212, for example, simultaneously with the source / drain components (e.g., P-type and / or N-type) of the device region 210.

[0072] The source / drain component may be deposited using VPE, UHV-CVD, MBE, and / or other suitable processes. When the source / drain component is n-type, it may include silicon (Si) doped with n-type dopants, such as phosphorus (P) or arsenic (As). When the source / drain component is p-type, it may include silicon germanium (SiGe) doped with p-type dopants, such as boron (B) or boron difluoride (BF2). In some embodiments, the source / drain component may include multiple film layers, such as film layers with different dopant concentrations.

[0073] Block 106 continues to sub-step 106C, where a replacement gate (RPG) process is performed. The RPG process replaces the dummy gate structure (e.g., PG) discussed with reference to sub-step 106A with a functional gate structure such as a metal gate. It should be noted that other methods of forming the gate structure may be provided in block 106, including other processes such as gate-first processes, and sub-steps 106A, 106B, and 106C are merely exemplary embodiments. The RPG process or other process for forming a functional gate is performed on the dummy gate structure in the device region 210 and the via region 212.

[0074] In some embodiments, after forming the dummy polysilicon gate and the spacers, the RPG process includes an interlayer dielectric (ILD) layer that may be formed adjacent to the dummy gate structure. Figure 3As shown, an ILD layer 302 is formed on the substrate 202. The ILD layer 302 can be deposited using plasma-enhanced chemical vapor deposition (PECVD), flowable chemical vapor deposition (FCVD), spin coating, or a suitable deposition technique. In some embodiments, after forming the ILD layer 302, the device 200 can be annealed to improve the integrity of the ILD layer 302. Although not shown in the schematic diagram, a contact etch stop layer (CESL) can be deposited before depositing the ILD layer 302 so that the CESL is disposed between the ILD layer 302 and the source / drain features. The CESL can include silicon nitride or silicon oxynitride and can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or a suitable method.

[0075] After depositing the ILD layer 302, a planarization process is performed to expose the top surface of the dummy gate in the RPG process, and the planarization process may include CMP. In some embodiments, due to the presence of the dummy gate structure in the via region 212, dishing of the ILD layer 302 in the via region 212 can be avoided during the CMP process, and thus, a substantially flat surface of the ILD layer 302 from the device region 210 through the via region 212 to the device region 210 can be provided. After planarization, the dummy gate (e.g., polysilicon) is then removed to form a trench in the replacement gate formed as described above. Figure 3 A replacement gate is shown in the gate structure 208, which is essentially configured as a dummy gate structure. The gate structure 208 is disposed in the device region 210 and the via region 212. In one embodiment, the gate structure 208 includes a metal electrode and is therefore referred to as a metal gate.

[0076] The gate structure 208 may include an interface layer connected to the active areas, a gate dielectric layer above the interface layer, and a gate electrode layer above the gate dielectric layer. The gate structure 208 extends from the active areas to above the isolation structure 204 disposed between the active areas. Above the isolation structure 204, the interface layer (if present) or the gate dielectric layer (if the interface layer does not exist) interfaces with the isolation structure 204. The interface layer of the gate structure 208 may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods. The gate dielectric layer may include a high dielectric constant (k) dielectric material such as hafnium oxide. Alternatively, the gate dielectric layer of the gate structure 208 may include other high-k dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), strontium titanate (SrTiO3, STO), barium titanate (BaTiO3, BTO), barium zirconate (BaZrO), lanthanum hafnium oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), barium strontium titanate ((Ba,Sr)TiO3, BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations of the foregoing or other suitable materials. The gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation and / or other suitable methods. The gate electrode layer of the gate structure 208 may include a single layer or alternatively a multi-layer structure, such as various combinations of metal layers with selected work functions to enhance device performance (work function metal layers), liners, wetting layers, adhesion layers, metal alloys or metal silicides. For example, the gate electrode layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations of the foregoing. At this stage, the gate structure 208 is also referred to as a metal gate structure 208. In some embodiments, the gate structure 208 is the same structure in the entire device region 210 and the via region 212 . That is, in some embodiments, the gate structure 208 in the device region 210 and the via region 212 is a metal gate.

[0077] The gate structure 208 and source / drain regions (not shown) are FEOL structures 214. The FEOL structures 214 may also include diffusion regions in the substrate (as discussed above) and STI features (such as isolation structures 204).

[0078] The method 100 includes block 108, wherein a hard mask layer is formed over the FEOL structure, the FEOL structure including the gate structure and the ILD layer in the device region and the via region. In one embodiment, the hard mask layer includes a first layer and a second layer. In one embodiment, the first layer is titanium nitride (TiN). In one embodiment, the second layer is silicon nitride (SiN). Figure 4 , showing a first layer 404 and a second layer 406. In some embodiments, the first layer 404 is TiN and the second layer 406 is SiN. The hard mask layer serves as an etch mask in subsequent patterning steps.

[0079] The method 100 includes block 110, where an opening is formed by an etching process, the opening being disposed in the via region. The opening may be formed by patterning a hard mask layer of block 108 and using the patterned hard mask as an etching mask when etching the opening. The opening may extend through the mask layer of block 108 in the via region 212 and the FEOL structure of block 106. Figure 5A As an example, an opening 502 is formed.

[0080] The opening 502 may be patterned by a suitable photolithography process, for example, by forming a mask element over the hard mask layer 406 and performing an etching process through the opening in the mask element, the etching process may be a multi-step etching process. In some embodiments, the etching process may first pattern the hard mask layer 406, and using the patterned hard mask 406 in a subsequent etching, the FEOL structure may be etched. The etching process may include dry etching, wet etching, reactive ion etching (RIE) and / or other suitable processes. For example, the dry etching process may be implemented with oxygen-containing gas, fluorine-containing gas (such as carbon tetrafluoride, sulfur hexafluoride, difluoromethane, fluoroform and / or hexafluoroethane), chlorine-containing gas (such as chlorine, chloroform, carbon tetrachloride and / or boron trichloride), bromine-containing gas (such as hydrogen bromide and / or bromoform), iodine-containing gas, other suitable gases and / or plasma and / or combinations thereof. For example, the wet etching process may include etching in dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3) and / or acetic acid (CH3COOH); or other suitable wet etchants. In one embodiment, a wet etch is performed followed by a dry etch. In some embodiments, multiple etching processes are performed. Each etch may include an etchant selected based on the target material (e.g., dielectric, metal).

[0081] An exemplary embodiment of an etch flow provides a multi-stage (eg, three-stage) etch process.

[0082] In the first etching process, the hard mask layers 404 and 406 are removed. In one embodiment, the first etching process includes wet etching targeting the hard mask layer, for example, by performing phosphoric acid, nitric acid, hydrofluoric acid and / or other suitable etchant solutions.

[0083] In the second etching process, the ILD and other FEOL devices, such as the metal gate 208 or the source / drain regions, are removed. For example, the dry etching process may be performed using an oxygen-containing gas, a fluorine-containing gas (such as carbon tetrafluoride, sulfur hexafluoride, difluoromethane, fluoroform and / or hexafluoroethane), a chlorine-containing gas (such as chlorine, chloroform, carbon tetrachloride and / or boron trichloride), a bromine-containing gas (such as hydrogen bromide and / or bromoform), an iodine-containing gas, other suitable gases and / or plasma and / or combinations thereof.

[0084] In the third etching process, the opening 502 is further etched to form the isolation structure 204. In one embodiment, the third etching process is a continuation of the second etching process. For example, in one embodiment, the isolation structure 204 is etched by a dry etching process using a fluorine-containing gas (e.g., carbon tetrafluoride, sulfur hexafluoride, difluoromethane, fluoroform, and / or hexafluoroethane).

[0085] like Figure 5B As shown in the example of FIG. 5 , the opening 502 extends through the hard mask layers 406, 404, the ILD layer 302, and the isolation structure 204. In some embodiments, the opening 502 exposes the surface of the substrate 202, and the opening 502 may have a dimension D as described above. In some embodiments, as shown in the figure, the opening 502 includes a dimension W1 and a dimension W2, such as Figure 5B In some embodiments, W1 is substantially equal to W2 (eg, circular or square). In other embodiments, W1 is greater than or less than W2, and W1 and / or W2 may be greater than 5 micrometers.

[0086] In some embodiments, the opening 502 is approximately circular in the top view schematic. In some embodiments, the opening 502 is elliptical. In some embodiments, the opening 502 is rectangular (including square) in the top view schematic. These shapes are merely illustrative, and other shapes are also possible, including, for example, octagons. In some embodiments, the shape and / or size of the opening 502 is substantially the same as the via region 212. In some embodiments, the opening 502 has a shape substantially similar to the via formed subsequently, as described below. However, in other embodiments, the opening 502 may have a shape different from the TSV formed subsequently. In each case, the opening 502 encloses the TSV to be formed, in other words, the opening 502 is no larger than the TSV.

[0087] Figure 5B The top view schematic diagram of FIG. 2 shows an active region (gate oxide and diffusion, OD) and an isolation structure 204 formed in the device region 210. The via region 212 is configured so that the device region 210 surrounds the via region 212, but other embodiments are possible, for example: in some embodiments, the via region 212 can be an edge region of the device 200. The opening 502 is disposed above the isolation structure 204 on the substrate 202 and extends through the isolation structure 204, that is, the opening 502 is disposed in the via region 212 between the active regions (OD), that is, the opening 502 is located in the isolation structure 204. In another embodiment, the via region 212 and therefore the opening 502 can extend above and / or within the active region (OD) of the substrate 202. The gate structure 208 extends in a first direction, and the active region extends in a second direction perpendicular to the first direction.

[0088] In some embodiments, patterning and etching of the opening 502 are performed simultaneously with the gate cut region 504. The gate cut region 504 can be formed by a gate cut process, in which a continuous gate structure 208 is "cut" into two segments. The gate cut region (e.g., an opening or gap between a first gate structure segment and a second gate structure segment) is an opening extending between a first gate segment and a second gate segment of a gate line, which is subsequently filled with a dielectric material, as described below, which provides electrical isolation between the first gate segment and the second gate segment, that is, the cut region 504 defines an area of ​​the gate structure 208, a portion of which is removed to provide two discontinuous and disconnected gate structures, which can be disposed on different active areas. It should be noted that the opening 502 and the gate cut region 504 are formed after the metal gate structure 208. In other embodiments of the method 100, the opening 502 and / or the gate cut region 504 are performed at the dummy polysilicon gate structure of sub-step 106A.

[0089] The cut gate opening 504 and the opening 502 can be formed simultaneously. In one embodiment, a mask is used for a photolithography process to define the cut gate opening 504 and the opening 502. In some embodiments, the hard masks 404, 406 are patterned as an etching mask for etching both the cut gate opening 504 and the opening 502. In some embodiments, the etching process discussed above is used to form the opening 502 while also forming the cut gate opening 504.

[0090] The method 100 proceeds to block 112 where the opening of block 110 is filled with a dielectric material. Figure 6 , the opening 502 is filled with a dielectric material 602. In one embodiment, the opening 502 and the cut gate opening 504 are similarly filled with a dielectric material 602. The dielectric material filling the opening 504 can form a cut gate isolation structure to provide isolation between two adjacent gate segments.

[0091] The dielectric material 602 may be different in material composition from the ILD layer 302 and / or the isolation structure 204. In one embodiment, the dielectric material 602 is silicon nitride. In another embodiment, the ILD layer 302 is an oxide, such as silicon oxide. In another embodiment, the isolation structure 204 includes an oxide, such as silicon oxide. In some embodiments, the dielectric material 602 interfaces with the substrate 202, the isolation region 204, and the ILD layer 302, such as Figure 6 In one embodiment, the dielectric material 602 and the end of the gate structure 208 are connected (see Figure 7BIn embodiments where the opening 502 extends above the active area, the dielectric material 602 may interface with the active area of ​​the substrate 202 .

[0092] The method 100 includes block 114, where a planarization process is performed after the dielectric material deposition of block 112 is performed. The planarization process may include CMP or other suitable etch-back processes. Fig. 7A As shown in FIG. 6 , the dielectric material 602 is planarized. Fig. 7A As shown, the dielectric material 602 forms a substantially planar upper surface with the adjacent ILD layer 302 and / or gate structure 208 (including the spacers 206 ). Figure 7B The top view schematic diagram of FIG. 5 shows the opening 502 and the opening 504 filled with dielectric material 602. As described above, in some embodiments, the opening 502 and the cut gate opening 504 are filled with the same material in the same deposition process.

[0093] The method 100 includes block 116, where a MEOL structure is formed over the substrate. The MEOL structure may include local interconnect structures and / or plugs providing active devices connected to active regions of the substrate, such as source / drain contact plugs connected to source / drain regions of a transistor or gate contact plugs connected to a gate structure of a transistor. Figure 8 In the example of the embodiment of the present invention, the MEOL layer 800 is formed on the substrate 202. The MEOL layer 800 includes an ILD layer 800A and a contact plug 800B. In one embodiment, the MEOL layer 800 includes a gate contact plug 800B and a source / drain contact plug (not shown) extending through the ILD layer 800A. Each gate contact plug 800B extends through the ILD layer 800A to be physically and electrically coupled to one of the gate structures 208. In some embodiments, the ILD layer 800A may include silicon oxide, tetraethylorthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG) and / or other suitable dielectric materials. In one embodiment, the dielectric material of the ILD layer 800A is different from the composition of the dielectric material 602 .

[0094] As an example, the contact plug 800B may include ruthenium (Ru), cobalt (Co), nickel (Ni), tungsten (W), copper (Cu) or other metals. In some embodiments, the contact plug 800B may include a barrier layer intersecting with the ILD layer 800A, and this barrier layer may include a metal nitride, such as titanium nitride, tantalum nitride, tungsten nitride, cobalt nitride or nickel nitride. In addition, in order to reduce the contact resistance, a silicide component may be provided between the contact plug 800B and the transistor component (such as the gate 208). The silicide component may include titanium silicide. The contact plug 800B may be deposited using CVD, PVD or a suitable method. The formation of the MEOL layer 800 may end with a planarization process.

[0095] The method 100 includes block 118, where a BEOL structure is formed in a BEOL process. The BEOL structure includes an MLI, which provides interconnects using metal lines or vias extending through dielectric layers. Figure 8 As an example of the embodiment of the present invention, the BEOL process forms a BEOL layer 802, also referred to as an MLI structure 802. The MLI structure 802 may include a plurality of metallization layers 802B, such as 8 to 13 metallization layers, denoted as metallization layers M1 to Mn. These metallization layers 802B generally provide horizontal wiring, and vias 802C provide vertical wiring connecting the metallization layers 802B. Generally speaking, the metallization layers M1 to Mn include a conductive wiring layer, which includes conductive lines (e.g., metallization layers 802B extending laterally) and vias (e.g., vias 802C extending vertically between metal lines) to electrically couple to the MEOL structure 800, such as plugs 800B. The conductive wiring layer is formed in a film layer of a dielectric material, such as an inter-metal dielectric (IMD) layer 802A. The IMD layer 802A may include a low dielectric constant or an extreme low dielectric constant (ELK) material, such as oxide, silicon oxide, BPSG, TEOS, spin-on glass (SOG), USG, FSG, high-density plasma (HDP) oxide, or plasma-enhanced tetraethylorthosilicate (PETEOS). A planarization process such as a CMP process may be performed to planarize each of the IMD layers 802A.

[0096] The metallization layer including the metallization layer 802B and the through hole 802C can be formed, for example, using an electroplating and etching process or by a damascene or dual damascene process, wherein an opening is etched into a corresponding dielectric layer (IMD layer) and the opening is filled with a conductive material. The metallization layer 802B can be formed of any suitable conductive material, such as a highly conductive metal, a low resistance metal, an elemental metal, a transition metal, etc. In one embodiment, the metallization layer 802B can be formed of copper, but other materials such as tungsten, aluminum, gold, etc. can alternatively be used. In an embodiment where the metallization layer 802B is formed of copper, the metallization layer 802B can be deposited by electroplating techniques.

[0097] The metallization layer 802B and / or the through hole 802C may include a liner and / or a barrier layer. For example, a liner (not shown) may be formed over the dielectric layer in the opening, the liner covering the sidewalls and bottom of the opening. The liner may be TEOS or silicon nitride, although any suitable dielectric may be used instead. The liner may be formed using a PECVD process, but other suitable processes such as physical vapor deposition or thermal processes may be used instead. The barrier layer may be formed over the liner (if present) and cover the sidewalls and bottom of the opening. The barrier layer may be formed using processes such as CVD, PVD, PECVD, plasma enhanced physical vapor deposition (PEPVD), ALD, combinations of the foregoing, and the like. The barrier layer may include tantalum nitride, but other materials such as tantalum, titanium, titanium nitride, combinations of these materials, and the like may be used instead.

[0098] The method 100 includes block 120, where a via opening is formed. The via opening may be an opening or a trench formed in the substrate and the cover layer, which when filled forms a via or TSV. Fig. 9, an opening 902 is formed through the BEOL structure 802, the MEOL structure 800, and the dielectric material 602. The opening 902 can be formed by a suitable patterning and etching process, for example, a mask layer can be formed on the BEOL structure 802, and the mask layer can include photoresist, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, or titanium nitride, and then the deposited mask layer is subjected to a pre-exposure bake process, exposure to radiation reflected or transmitted from the photomask, a post-exposure bake process, and a development process to form a patterned mask layer having an opening aligned with the opening 902 to be formed. The etching process can be a dry etching process (e.g., RIE process). In some cases, the exemplary dry etching process can be implemented with an oxygen-containing gas (e.g., oxygen), a fluorine-containing gas (e.g., sulfur hexafluoride or nitrogen trifluoride), a chlorine-containing gas (e.g., chlorine and / or boron trichloride), a bromine-containing gas (e.g., hydrogen bromide), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. In one embodiment, the etching of the opening 902 may include a first step that performs an etch that terminates at the top surface of the substrate 202, such as Fig. 9 As shown, the termination of the etching can be controlled by time or by varying the etching rate. In one embodiment, the etching provides an opening 902 having substantially vertical sidewalls. In one embodiment, the etching of the opening 902 may include a second step that performs an etch extending through a portion of the substrate 202, such as Fig.10 As shown, an extended opening 902' is formed. The etching to form the extended opening 902' can be terminated by controlling the time. In one embodiment, the etching provides an opening 902' having substantially vertical sidewalls.

[0099] In some embodiments, the width W3 of the opening 902' is less than the W1 dimension of the opening 502. In one embodiment, the width W3 of the opening 902 is a diameter that is less than the W1 dimension (e.g., width or diameter) of the opening 502. In other words, the opening 902' is located within the dielectric material 602 that fills the opening 502, so that the remaining portion of the dielectric material 602 surrounds the opening 902'. The dielectric material 602 defines a middle region of the wall on the side of the opening 902'. The upper region of the sidewall of the opening 902' can be defined by the IMD 802A of the BEOL layer 802 and the ILD layer 800A of the MEOL layer 800. The bottom region of the sidewall of the opening 902' can be defined by the substrate 202. It should be noted that in some embodiments, a dielectric region is formed within the substrate 202 to isolate the via formed in the opening 902'.

[0100] The method 100 includes block 122, where filling the opening of block 120 with a conductive material to form a conductive via is performed. Fig.11 , conductive materials 1102 and 1104 are deposited to fill opening 902'. Fig. 12A as well as Fig. 12B , a conductive via 1200 is formed in the opening 902' by the conductive material. In some embodiments, the via 1200 may include a barrier layer 1104 and a metal filling layer 1102. In some embodiments, the barrier layer 1104 may include tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), aluminum nitride (AlN), or a combination thereof. The metal filling layer 1102 may include copper (Cu), aluminum (Al), cobalt (Co), a copper alloy, tantalum (Ta), titanium (Ti), or tungsten (W). In one embodiment, the barrier layer 1104 includes titanium nitride (TiN), and the metal filling layer 1102 includes copper (Cu). In order to form the conductive via 1200, the barrier layer 1104 is first deposited using PVD, CVD, metal-organic chemical vapor deposition (MOCVD), ALD, or a combination thereof, as exemplified in Fig.11 As shown, the metal fill layer 1102 is then deposited using electroplating, PVD, CVD, chemical plating, or a suitable method. In one embodiment, the metal fill layer 1102 is formed using electroplating. In this embodiment, after the barrier layer 1104 is formed, a seed layer may be deposited using PVD or a suitable process, including on the surface of the barrier layer 1104, and then the metal fill layer 1102 may be deposited on the seed layer using electroplating. In an embodiment using electroplating, the seed layer may include copper (Cu), titanium (Ti), or a combination of the foregoing, and the metal fill may include copper (Cu). The seed layer may be considered to be part of the metal fill layer 1102. After both the barrier layer 1104 and the metal fill layer 1102 are deposited into the opening 902', a planarization process such as CMP may be performed to remove any excess material on the top surface of the BEOL layer 802, such as Fig. 12A shown.

[0101] like Fig. 12A as well as Fig. 12B As shown, in some embodiments, the conductive via 1200 is surrounded (at the bottom) by dielectric material 602. (It should be noted that Fig. 12B ) That is, the via 1200 is disposed in the via region 212 and the dielectric material 602 .

[0102] Still refer to Fig. 12B , the gate structure 208 passing through the via region 212 may be a non-functional gate (eg, a dummy gate), including extending over the active (OD) region. Fig. 12BThe gate structures 208 above and below the vias 1200 in the device region 210 may be non-functional or dummy gate structures. Fig. 12B The sections of the gate structure 208 above and below the via 1200 covering the active region may provide a functional gate. Fig. 12B The functional gate 208 (above the via region 212 in the lower device region 210) can be isolated from the collinear functional gate segment in the lower device region 210 by the dielectric material 602.

[0103] After forming the vias, the method 100 may continue to form additional conductive and / or insulating features on the substrate. Fig.13 In the example of the embodiment of the present invention, the interconnection layer 1300 is formed on the via 1200. The interconnection layer 1300 includes a conductive layer 1300B and an insulating layer 1300A. In some embodiments, the insulating layer 1300A can be substantially similar to the ILD layer 302, the ILD 800A and / or the IMD layer 802A in terms of composition and formation process. In the described embodiment, the insulating layer 1300A can include silicon oxide, TEOS oxide, USG or doped silicon oxide, such as BPSG, FSG, PSG, BSG, low-k dielectric materials, other suitable dielectric materials or combinations of the foregoing. In one embodiment, the conductive component or interconnection layer 1300B is formed on the via 1200 and connected to the via 1200. Exemplary metal materials of the interconnection layer 1300B can include copper (Cu), cobalt (Co), nickel (Ni), aluminum (Al) or metal alloys, such as aluminum-copper alloys. After depositing the metal material and / or insulating material of the interconnect layer 1300, the device 200 is planarized using, for example, a CMP process to remove excess material and provide a planar upper surface. The interconnect layer 1300 may also include additional layers such as passivation layers, bonding pads, external interconnects (such as solder balls), and the like.

[0104] The method 100 includes block 124, where further processing is performed including grinding and polishing the substrate to expose the bottom surface of the via formed in block 122. Fig.13 In the example of , as the substrate 202 is thinned, portions of the substrate 202 are removed. The removal continues so that the bottom surface of the via 1200 is exposed. Once the bottom surface of the via 1200 is exposed, the via 1200 extends through the substrate 202. The via 1200 is also referred to as a through silicon via or through substrate via (TSV) 1200.

[0105] The method 100 includes block 124, where further processing is performed. In one embodiment, after thinning the substrate, the method 100 may continue to form additional conductive and / or insulating features on the back side of the thinned substrate. Fig.14 In the exemplary embodiment of the present invention, the interconnection layer 1400 is formed on the back side of the substrate 202 adjacent to the TSV 1200. The interconnection layer 1400 includes a conductive layer 1400B and an insulating layer 1400A. In some embodiments, the insulating layer 1400A can be substantially similar to the ILD layer 302, the ILD 800A, the IMD layer 802A and / or the insulating layer 1300A in terms of composition and formation process. In the described embodiment, the insulating layer 1400A can include silicon oxide, TEOS oxide, USG or doped silicon oxide, such as BPSG, FSG, PSG, BSG, low-k dielectric materials, other suitable dielectric materials or combinations of the foregoing. In one embodiment, the conductive component or interconnection layer 1400B is connected to the TSV 1200. Exemplary metal materials of the interconnection layer 1400B can include copper (Cu), cobalt (Co), nickel (Ni), aluminum (Al) or metal alloys, such as aluminum-copper alloys. The interconnect layer 1400 may also include additional layers, such as a passivation layer, bonding pads, external interconnects (such as solder balls), and the like.

[0106] Thus, the method 100 and the exemplary device 200 illustrate embodiments provided that sacrificial FEOL features, rather than extending through the substrate 202 in areas designed to be free of FEOL features, are formed simultaneously with active FEOL devices (e.g., metal gates) and then removed to form TSVs 1200. Although not intended to be limiting, one or more embodiments of the present disclosure provide numerous benefits to semiconductor devices and methods of fabricating the same. In some depicted embodiments, the process avoids or mitigates recessing that may occur in areas free of or with lower feature density that may be of concern to subsequent processing steps. By forming sacrificial FEOL devices in the via region 212, these process effects may be mitigated.

[0107] In an exemplary embodiment, the present disclosure provides a method for manufacturing a semiconductor device, the method comprising forming a plurality of first gate structures above a first region of a substrate, and forming a plurality of second gate structures above a second region of the substrate. A first opening is formed by removing at least one of the second gate structures in the second region of the substrate. The first opening is filled with a first dielectric material. An interconnect layer is formed above the first gate structure and the first dielectric material. A second opening is etched through the interconnect layer, the first dielectric material, and at least a portion of the second region of the substrate. The method further comprises forming a through-hole structure within the second opening, the through-hole structure extending through the interconnect layer, the first dielectric material, and the second region of the substrate.

[0108] In yet another embodiment, forming the first gate structure and the second gate structure in the method includes forming a plurality of polysilicon gate structures, removing the polysilicon gate structures to form trenches, and forming metal gate electrodes in the trenches. In one embodiment, the first dielectric material is silicon nitride. In yet another embodiment, forming the interconnect layer includes forming an intermetallic dielectric layer and a metal interconnect layer. And the intermetallic dielectric layer includes a second dielectric material, the second dielectric material being different from the first dielectric material.

[0109] In one embodiment, while forming the first opening, a third opening is formed to provide a cut gate region in the first gate of the first gate structure in the first region of the substrate. In another embodiment, while filling the first opening, the third opening is filled with the first dielectric material.

[0110] In one embodiment, the method further comprises forming an interlayer dielectric layer adjacent to and intercalating the first gate structure and adjacent to and intercalating the second gate structure. In one embodiment, the interlayer dielectric layer is silicon oxide, and the first dielectric material is silicon nitride. In one embodiment of the method, after forming the via structure, the first dielectric material is still abutting on a plurality of sidewalls of the via structure.

[0111] In another exemplary embodiment, the present disclosure provides a method for manufacturing a semiconductor device, the method comprising forming a first plurality of metal gates on a substrate and providing an interlayer dielectric adjacent to the first plurality of metal gates. Etching a first opening and a second opening, wherein the first opening extends into the interlayer dielectric and passes through the first metal gate and the second metal gate of the first plurality of metal gates, and the second opening extends through the third metal gate of the first plurality of metal gates to form a gate cutting region. The method also includes filling the first opening and the second opening with a dielectric material, and after filling the first opening and the second opening, depositing an interconnect layer over the substrate. Etching the interconnect layer to form a via opening, wherein the via opening extends through the dielectric material, wherein the conductive material is deposited in the via opening to form a via structure.

[0112] In yet another embodiment, the method includes thinning the back side of the substrate to expose the through-hole structure. In some embodiments, multiple sidewalls of the through-hole structure interface with the dielectric material. In one embodiment, the method also includes depositing a hard mask layer over the interlayer dielectric and the first metal gate, and defining a pattern of the first opening and the second opening in the hard mask layer. And in one embodiment, the first opening is formed over a shallow trench isolation structure, and the shallow trench isolation structure is disposed on the substrate. The method may also include forming the first plurality of metal gates including forming the first plurality of metal gates over a plurality of fin-type active areas, the fin-type active areas extending from the substrate.

[0113] In yet another exemplary embodiment, the present disclosure provides a semiconductor device. The device includes a substrate and a plurality of gate structures disposed on the substrate. A multilayer interconnect is disposed above the substrate and the gate structures. A through substrate via vertically extends through the substrate and the multilayer interconnect. In one embodiment, the through substrate via has a first sidewall in a cross-sectional view, wherein the first sidewall includes an upper portion that interfaces with a first dielectric material of the multilayer interconnect; a middle portion that interfaces with a second dielectric material, the second dielectric material being different from the first dielectric material; and a lower portion that interfaces with the substrate.

[0114] In one embodiment, the second dielectric material surrounds the middle portion of the substrate through hole in a top view. In one embodiment, the first dielectric material is an oxide, and the second dielectric material is silicon nitride. And in some embodiments, at least a portion of the middle portion of the first sidewall is coplanar with the gate structure.

[0115] The above summarizes the components of several embodiments so that those skilled in the art to which the present disclosure belongs can more easily understand the concepts of the embodiments of the present disclosure. Those skilled in the art to which the present disclosure belongs should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present disclosure belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a base; A plurality of gate structures are disposed on the substrate; a multi-layer interconnection disposed above the substrate and the plurality of gate structures; A through substrate via vertically extending through the substrate and the multi-layer interconnect, wherein the through substrate via has a first sidewall in a cross-sectional view, wherein the first sidewall comprises: an upper portion interfacing with a first dielectric material of the multi-layer interconnect; a middle portion bordering a second dielectric material, the second dielectric material being different from the first dielectric material; and A lower portion bordering the base.

2. The semiconductor device according to claim 1, wherein Also includes: A shallow trench isolation structure is disposed on the substrate and borders the second dielectric material.

3. The semiconductor device according to claim 2, wherein: Also includes: An interlayer dielectric layer is disposed on the shallow trench isolation structure and is coplanar with the plurality of gate structures.

4. The semiconductor device according to claim 1 or 2, wherein: The multi-layer interconnect further includes a plurality of metallization layers extending laterally in the cross-sectional view.

5. The semiconductor device according to claim 1, wherein The substrate through hole comprises: a barrier layer disposed on the first sidewall; and A metal filling layer is surrounded by the barrier layer in a top view.

6. The semiconductor device according to claim 1, wherein: Also includes: A cut gate isolation structure intersects with an end portion of the gate structure in a top view.

7. The semiconductor device according to claim 1, wherein The second dielectric material surrounds the middle portion of the through substrate via in a top view.

8. The semiconductor device according to claim 1, wherein At least a portion of the middle portion of the first sidewall is coplanar with the plurality of gate structures.

9. The semiconductor device according to claim 1, wherein: Also includes: A first conductive layer and a first insulating layer are disposed on the substrate through hole.

10. The semiconductor device according to claim 9, wherein: Also includes: A second conductive layer and a second insulating layer are disposed on the back side of the substrate adjacent to the substrate through hole.

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