Memory element

Abstract

A memory element is disclosed. The memory element includes a memory cell including a transistor and a plurality of pairs of resistors coupled in series to the transistor. Each pair of resistors includes a first resistor and a second resistor. The transistor extends along a major surface of the substrate. At least a first pair of resistors is formed in a first one of the plurality of metal layers. A first of the plurality of resistor layers is disposed over the transistor. At least a second pair of resistors is formed in a second one of the plurality of metal layers. A second one of the plurality of metal layers is disposed over a first one of the plurality of resistor layers.

Description

Technical Field

[0001] The present disclosure relates to a memory device. Background Art

[0002] The development of electronic components, such as computers, portable devices, smartphones, Internet of Things (IoT) devices, etc., has led to an increase in the demand for memory components. Generally speaking, memory components can be volatile memory components and non-volatile memory components. Volatile memory components can store data when power is supplied, but may lose the stored data once the power is turned off. Unlike volatile memory components, non-volatile memory components can retain data even after the power is turned off, but the speed may be slower than volatile memory components. Utility Model Content

[0003] In one aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory cell, the memory cell including: a transistor; and one or more pairs of resistors coupled in series to the transistor. Each of the one or more pairs of resistors includes a first resistor and a second resistor. The transistor is formed along a main surface of a substrate, and the one or more pairs of resistors are respectively formed in one or more of a plurality of metal layers disposed above the transistor.

[0004] In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory cell, the memory cell including: a transistor; and a plurality of pairs of resistors coupled in series to the transistor, each pair of resistors including a first resistor and a second resistor. The transistor is formed along a major surface of a substrate. A first pair of the resistors is formed in a first of a plurality of metal layers disposed above the transistor. At least a second pair of the resistors is formed in a second of the plurality of metal layers, the second metal layer being disposed above the first metal layer.

[0005] In another aspect of the present disclosure, a memory element is disclosed, comprising a transistor, a first metal layer, a first dielectric material, a first through-hole structure, a second metal layer, a second dielectric material, and a second through-hole structure. The first metal layer is above the transistor, and the first metal layer comprises a plurality of first conductor lines. The first dielectric material laterally separates the first conductor lines. The first through-hole structure comprises a first lower portion. The first lower portion is laterally inserted between an adjacent pair of first conductor lines. The second metal layer is above the first metal layer, and the second metal layer comprises a plurality of second conductor lines. The second dielectric material separates the second conductor lines. The second through-hole structure comprises a second lower portion, and the second lower portion is laterally inserted between an adjacent pair of second conductor lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with Figure 1When read together, the various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity, the size of various features can be increased or reduced at will.

[0007] Figure 1 A circuit diagram of a memory cell according to some embodiments is shown;

[0008] Figure 2 According to some embodiments, Figure 1 A perspective view of a semiconductor device of a portion of a memory cell;

[0009] Figure 3 According to some embodiments Figure 1 Exemplary operations of a memory cell;

[0010] Figure 4 According to some embodiments Figure 1 Another exemplary operation of the memory unit;

[0011] Figure 5 According to some embodiments, Figure 1 A schematic diagram of the probability of different voltages being output by (or read from) a memory cell;

[0012] Figure 6 A circuit diagram of another memory cell according to some embodiments is shown;

[0013] Figure 7 FIG. 1 is an illustration of an embodiment of the present invention that may be operatively implemented as Figure 6 A perspective view of a semiconductor device of a memory cell;

[0014] Figure 8 According to some embodiments Figure 7 An exemplary layout of semiconductor components;

[0015] Fig. 9 A representative diagram according to some embodiments is shown Figure 6 A block diagram of a memory unit;

[0016] Fig.10 FIG. 1 is a diagram illustrating a method for performing a Figure 6 The truth table associated with the memory unit;

[0017] Fig.11 According to some embodiments Figure 6 The operation sequence of the memory unit;

[0018] Fig.12 According to some embodiments, a plurality of Figure 6A circuit diagram of a memory array of a memory cell;

[0019] Fig.13 According to some embodiments Fig.12 An example layout diagram of a memory array;

[0020] Fig.14 An exemplary flow chart of a method for forming a semiconductor device according to some embodiments is shown.

[0021]

Explanation of symbols

[0022] A: Access line

[0023] B: Access line

[0024] D: Access line

[0025] E: Access line

[0026] F: Access line

[0027] Q, Q1, Q2, Q3: Memory location

[0028] S: Access line

[0029] S r :spacing

[0030] Y: Node

[0031] W v :width

[0032] d ov :depth

[0033] H: High resistance state

[0034] L: Low resistance state

[0035] A n ,B n ,D m ,S n, A n+1 ,B n+1 ,D m+1 ,S n+1 :Access Line

[0036] 100: memory unit

[0037] 110: Transistor

[0038] 120,130: Resistors

[0039] 200:Semiconductor components

[0040] 202: Base material

[0041] 204: Fin structure

[0042] 206: Gate structure

[0043] 208: Source / drain structure

[0044] 210: Transistor

[0045] 220: Resistor

[0046] 230: Resistor

[0047] 232: first conductor line

[0048] 234: Second conductor line

[0049] 236:Through hole structure

[0050] 238: Dielectric Materials

[0051] 240: Dielectric material

[0052] 242: Conductor wire

[0053] 510: Graphics

[0054] 530: Graphics

[0055] 600: Memory unit

[0056] 610: Transistor

[0057] 620,630,640,650,660,670: Resistors

[0058] 700:Semiconductor components

[0059] 702: Base material

[0060] 704: Fin structure

[0061] 706: Gate structure

[0062] 708: Source / drain structure

[0063] 710: Transistor

[0064] 720,730: Resistors

[0065] 732: Conductor wire

[0066] 734: Conductor wire

[0067] 736:Through hole structure

[0068] 738: Conductor wire

[0069] 740,750: Resistors

[0070] 752: Conductor wire

[0071] 754: Conductor wire

[0072] 756:Through hole structure

[0073] 758: Conductor wire

[0074] 760,770: Resistors

[0075] 772: Conductor wire

[0076] 774: Conductor wire

[0077] 776:Through hole structure

[0078] 778: Conductor wire

[0079] 800:Layout

[0080] 804,806: Pattern

[0081] 832,834,836,838,852,854,856,858,872,874,876,878: Pattern

[0082] 1101,1103,1105,1107,1109: Stage

[0083] 1200:Memory array

[0084] 1202,1204,1206,1208: memory unit

[0085] 1300: Layout

[0086] 1400: Method

[0087] 1402,1404,1406,1408,1410: Operation DETAILED DESCRIPTION

[0088] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. In order to simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are just examples and are not meant to be restrictive. For example, in the following description, a first feature formed on a second feature may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference digits and / or letters in each embodiment. This repetition is for simplicity and clarity, and does not itself determine the relationship between the various embodiments and / or configurations discussed.

[0089] Additionally, spatially relative terms, such as "below," "beneath," "below," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0090] In recent years, non-traditional non-volatile memory devices have emerged, such as ferroelectric random access memory (FRAM) devices, magnetoresistive random access memory (MRAM) devices, phase-change random access memory (PRAM) devices, and resistive random access memory (RRAM) devices. In particular, RRAM devices, which exhibit switching behavior between a high resistance state and a low resistance state, have various advantages over traditional non-volatile memory devices. These advantages include, for example, manufacturing steps compatible with current complementary metal-oxide-semiconductor (CMOS) technology, low-cost manufacturing, dense structure, flexible scalability, fast switching, high integration density, etc.

[0091] As integrated circuits are increasingly used in electronic components that provide different types of information for a variety of applications, more and more sensitive and / or critical information that may be stored in electronic components needs to be adequately protected to restrict access to such information to only other devices that have permission to access the critical information. Some application examples include authentication of devices, protection of confidential information within a device, and securing communications between two or more devices. A one-time-programmable (OTP) memory device (e.g., efuse, antifuse) is a type of non-volatile memory device used in integrated circuits to store such sensitive and / or critical information.

[0092] The present disclosure provides various embodiments of a memory device, the memory device includes a plurality of anti-fuse-like memory cells, each of which can be reversibly or irreversibly switched between a first resistance state and a second resistance state. In some embodiments, the disclosed anti-fuse memory cell can be a one-time programmable (OTP) memory cell, allowing one or a limited number of programming operations. For example, the anti-fuse memory cell can be in a first resistance state when manufactured, and can be permanently (irreversibly) programmed to a second resistance state. In another example, such a programming operation can be reversible. Each disclosed anti-fuse memory cell is implemented as a one-transistor-many-resistor (1TmR) structure. In some embodiments, the disclosed anti-fuse memory cell can include a transistor and at least one pair of resistors, wherein the transistor is formed in a front-end-of-line (FEOL) network / processing, and the at least one pair of resistors is formed in a back-end-of-line (BEOL) network / processing. The pair of resistors each have a terminal commonly connected to the source / drain terminal of the transistor. The transistor may provide a conduction path for the anti-fuse memory cell, while a pair of resistors may serve as a storage site for the anti-fuse memory cell, the storage site being configured to be programmed once or a limited number of times.

[0093] For example, the resistor pair includes (i) a first resistor formed by a first dielectric material laterally inserted between a via structure and a first conductor line; and (ii) a second resistor formed by a second dielectric material laterally inserted between the same via structure and a second conductor line. The first and second conductor lines are formed in the same layer of one of several metal layers of the BEOL network. When programmed, one of the first dielectric material or the second dielectric material is configured to switch to a high resistance state (sometimes referred to as H), while the other of the first dielectric material or the second dielectric material is configured to remain in a low resistance state (sometimes referred to as L). Therefore, when read, the output node of the anti-fuse memory cell (the node connected between the first resistor and the second resistor) can be locked to one of the programmed first resistor or the second resistor, which can advantageously and significantly expand the read window of the anti-fuse memory cell.

[0094] In other embodiments, the disclosed anti-fuse memory cell may include a transistor and multiple pairs of resistors, wherein at least two pairs of resistors are formed in different metal layers. The storage locations are evenly arranged on multiple different metal layers. Such a configuration can make the data stored in the anti-fuse memory cell significantly difficult to crack. For example, a first portion of the data can be stored in a first metal layer, and a second portion of the data can be stored in a second, higher metal layer. When attempting to reverse engineer the data by breaking down the metal layers, some portions of the data may have been removed and therefore cannot be accessed.

[0095] Figure 1 FIG. 1 is a circuit diagram of an example anti-fuse memory cell 100 according to some embodiments. Figure 1 In the example of FIG. 1 , the anti-fuse memory cell 100 is configured as a single transistor-two resistor (1T2R) structure.

[0096] For example, the anti-fuse memory cell 100 includes a transistor 110, a first resistor 120, and a second resistor 130. The transistor 110 has a gate terminal connected to an access line S, a first source / drain terminal connected to an access line D, and a second source / drain terminal commonly connected to the first resistor 120 and the second resistor 130. Specifically, each of the first resistor 120 and the second resistor 130 has a first terminal connected to the second source / drain terminal of the transistor 110 at a node Y, and a second terminal connected to a respective access line, for example, the second terminal of the first resistor 120 is connected to the access line A, and the second terminal of the second resistor 130 is connected to the access line B. However, it should be understood that the anti-fuse memory cell 100 can be configured in various other structures (e.g., a one-transistor-four-resistor (1T4R) structure, a one-transistor-six-resistor (1T6R) structure) while remaining within the scope of the present disclosure.

[0097] As will be discussed in further detail below, the first resistor 120 and the second resistor 130 each include a dielectric material laterally inserted between a common via structure and a respective conductor line. Stated another way, the first terminal (node ​​Y) and the second terminal (access line A) of the first resistor 120 may correspond to the common via structure and the first conductor line, respectively, wherein the first dielectric material inserted between the common via structure and the first conductor line may serve as a resistance portion of the first resistor 120. Similarly, the first terminal (node ​​Y) and the second terminal (access line B) of the second resistor 130 may correspond to the common via structure and the second conductor line, respectively, wherein the second dielectric material inserted between the common via structure and the second conductor line may serve as a resistance portion of the second resistor 130. The first dielectric material and the second dielectric material each include a transition metal oxide, such that the first resistor 120 and the second resistor 130 may be programmed between a first (e.g., high) resistance state and a second (e.g., low) resistance state.

[0098] In various embodiments of the present disclosure, the anti-fuse memory cell 100 can be formed on a substrate across both the FEOL network and the BEOL network, such as Figure 2 As shown in the example semiconductor component 200 of FIG. As shown, the semiconductor component 200 includes a transistor 210 formed in the FEOL network and two resistors 220, 230 formed in the BEOL network. The transistor 210 may correspond to Figure 1 The transistor 110, and the resistors 220, 230 may correspond to Figure 1 Resistors 120, 130.

[0099] exist Figure 2 In the illustrated example of FIG. 2 , transistor 210 is formed as a FinFET structure. However, transistor 210 may be formed as any of a variety of other transistor structures (e.g., a gate-around (GAA) FET structure) while remaining within the scope of the present disclosure. Figure 2 In the embodiment, on a substrate 202, a transistor 210 includes a fin structure 204 protruding from the substrate 202, a gate structure 206 crossing the fin structure 204, and a pair of source / drain structures 208 disposed on opposite sides of the gate structure 206 and connected to two ends of the fin structure 204 respectively.

[0100] Such features formed along the major surface of the substrate 202 are generally referred to as part of the FEOL network. On the FEOL network, several metal layers can be formed, each metal layer including several conductor lines, and several via structures, each via structure connecting the conductor lines of adjacent metal layers. The metal layers and via structures are generally referred to as part of the BEOL network. These metal layers are sometimes referred to as "M1 layer", "M2 layer", "M3 layer", "M4 layer", etc., and are called in order from the bottom layer to the top layer. Similarly, the via structure connecting the M1 layer and the M2 layer, the via structure connecting the M2 layer and the M3 layer, the via structure connecting the M3 layer and the M4 layer, and the via structure connecting the M4 layer and the M5 layer are sometimes referred to as "via 1 structure", "via 2 structure", "via 3 structure" and "via 4 structure", respectively.

[0101] In some embodiments, the resistors 220 and 230 are formed in the BEOL network. For example, the resistor 220 is formed by the first conductor line 232, the via structure 236, and the first dielectric material 238; and the resistor 230 is formed by the second conductor line 234, the via structure 236, and the second dielectric material 240. The first conductor line 232 and the via structure 236 can serve as the first terminal and the second terminal of the resistor 220, and the first dielectric material 238 serves as the resistance (or storage) part of the resistor 220; the second conductor line 234 and the via structure 236 can serve as the first terminal and the second terminal of the resistor 230, and the second dielectric material 240 serves as the resistance (or storage) part of the resistor 230.

[0102] In addition, the via structure 236 has a lower portion, which extends downward between the first conductor line 232 and the second conductor line 234. Therefore, the first dielectric material 238 is laterally inserted between the first conductor line 232 and the via structure 236; similarly, the second dielectric material 240 is laterally inserted between the second conductor line 234 and the via structure 236. The first conductor line 232 and the second conductor line 234 are arranged in the same metal layer (for example, the M1 layer), and therefore, the via structure 236 can be a via 1, and the via 1 can be connected to the conductor line 242 of the upper metal layer (for example, the M2 layer). The conductor line 242 can be coupled to one of the source / drain structures 208 of the transistor 210. Corresponding to Figure 1 , the first conductor line 232 and the second conductor line 234 may correspond to the access line A and the access line B, respectively, and the through-hole structure 236 may correspond to the internal node Y.

[0103] In some embodiments, the first dielectric material 238 and the second dielectric material 240 each include a transition metal oxide (TMO) having a variable resistance value. As a non-limiting example, such a transition metal oxide may include silicon dioxide (SiO2) and tantalum oxynitride (TaON). ​​As another non-limiting example, the transition metal oxide may be selected from the group consisting of: TiO x ,NiO x ,HfO x ,NbO x ,CoO x ,FeO x ,CuO x ,VO x ,TaO x ,WO x ,CrO x , and combinations thereof. The conductor lines (such as 232, 234, 242) and the via structures (such as 236) connecting the conductor lines in different metal layers can be formed of copper (Cu), respectively, while any of various other metals or conductive materials can be considered, for example, Ti, Ni, Hf, Nb, Co, Fe, Cu, V, Ta, W, Cr or combinations thereof.

[0104] In some embodiments, the dimensions of some components of the resistors 220 and 230 can be described as follows. For example, the lower portion of the via structure 236 extending to the space between the first conductor line 232 and the second conductor line 234 has a depth d ov , about 2 to 5 nanometers (nm). In addition, the first dielectric material 238 inserted laterally between the via structure 236 and the first conductor line 232 and the second dielectric material 240 inserted laterally between the via structure 236 and the second conductor line 234 each have a spacing S r , spacing S r At about 1 / 3W v To about 1 / 5W v Among them, W v represents the (eg, maximum) width of the via structure 236 .

[0105] Figure 3 and Figure 4 The memory unit 100 ( Figure 1 ) is an example (e.g., read) operation. Generally speaking, the first resistor 120 and the second resistor 130 forming the memory location Q of the memory cell 100 are programmed complementarily. That is, one of the first resistor 120 or the second resistor 130 is programmed to a first (e.g., high) resistance state, and the other of the first resistor 120 or the second resistor 130 is programmed to a second (e.g., low) resistance state. For example, in Figure 3 In the embodiment, the first resistor 120 is programmed to a high resistance state H, and the second resistor 130 is programmed to a low resistance state L. Figure 2 For example, the second dielectric material 240 (resistor 130) may have been decomposed (ie, become more conductive), while the first dielectric material 238 (resistor 120) may still be a dielectric. Figure 4 In the embodiment, the first resistor 120 is programmed to a low resistance state L, and the second resistor 130 is programmed to a high resistance state H. Figure 2 Taking the semiconductor device 200 of FIG. 1 as an example, the first dielectric material 238 (resistor 120 ) may have been decomposed (ie, become more conductive), while the second dielectric material 240 (resistor 130 ) may still be a dielectric.

[0106] In order to read Figure 3 In the example of memory cell 100 being programmed, access lines A and B are applied with VDD and ground, respectively, for example. Access line S is applied with a logic high voltage to enable transistor 110, and access line D may be floating. Since transistor 110 is enabled, the voltage present at node Y and the voltage on access line D may be substantially equal to each other. Since resistor 120 is in a high resistance state, node Y is equivalent to being disconnected from access line A, and therefore, the voltage on node Y may be close to the ground voltage. Similarly, in order to read the Figure 4 In the example of a programmed memory cell 100, access lines A and B are applied with VDD and ground, respectively, for example. Access line S is applied with a logic high voltage, enabling transistor 110, and access line D may be floating. Since transistor 110 is enabled, the voltage present at node Y and the voltage on access line D may be substantially equal to each other. Since resistor 120 is in a low resistance state, node Y is equivalent to being connected to access line A, and therefore, the voltage on node Y may be close to VDD.

[0107] Figure 5 Schematic diagram showing the probability of different voltages output by (or read from) the memory cell 100 according to various embodiments of the present disclosure. The output voltage may be the voltage present on the node Y or the access line D (when the transistor 110 is enabled). Figure 5 As shown, Figure 5 The graphs 510 and 530 are included. The peaks of the graphs 510 and 530 occur at the ground voltage and VDD, respectively. The graphs 510 and 530 may correspond to Figure 3 and Figure 4By utilizing the complementary resistance states between the first resistor 120 and the second resistor 130 (one of which is programmed to a high resistance state and the other is programmed to a low resistance state), the output voltage can be stably located at VDD or ground. Figure 5 As shown, the two graphs 510 , 530 may be separated from each other by a large voltage window (ie, no overlap). Such a voltage window is sometimes referred to as a read window of the memory cell 100 .

[0108] Figure 6 FIG. 6 is a circuit diagram of an example anti-fuse memory cell 600 according to some embodiments. Figure 6 In the example of FIG. 6 , the anti-fuse memory cell 600 is configured based on a one-transistor-two-resistor (1T2R) structure, for example, a one-transistor-six-resistor (1T6R) structure.

[0109] For example, the anti-fuse memory cell 600 includes a transistor 610, a first pair of resistors 620 and 630, a second pair of resistors 640 and 650, and a third pair of resistors 660 and 670. The transistor 610 has a gate terminal connected to the access line S, a first source / drain terminal connected to the access line D, and a second source / drain terminal commonly connected to the second pair of resistors 640 and 650. Specifically, each of the resistors 640 and 650 has a first terminal connected to the second source / drain terminal of the transistor 610 at the node Y, and a second terminal connected to the first pair of resistors or the third pair of resistors, respectively. The second terminal of the resistor 640 is commonly connected to the first terminal of the first pair of resistors 620 and 630; and the second terminal of the resistor 650 is commonly connected to the first terminal of the third pair of resistors 660 and 670. The second terminals of the first pair of resistors 620 and 630 are connected to access line B and access line A, respectively; and the second terminals of the third pair of resistors 660 and 670 are connected to access line F and access line E, respectively. In some embodiments, the first pair of resistors 620 and 630 may form a first memory location Q1 of the memory cell 600; the second pair of resistors 640 and 650 may form a second memory location Q2 of the memory cell 600; and the third pair of resistors 660 and 670 may form a third memory location Q3 of the memory cell 600.

[0110] Similar to the memory cell 100, the memory cell 600 may be formed in both the FEOL network and the BEOL network on the substrate. For example, the transistor 610 is formed in the FEOL network, and the plurality of resistor pairs 620 to 670 are formed in the BEOL network, such as Figure 7 An example semiconductor component 700 is shown.

[0111] like Figure 7 As shown, semiconductor element 700 includes a transistor 710 formed in a FEOL network, and a first pair of resistors 720 and 730, a second pair of resistors 740 and 750, and a third pair of resistors 760 and 770 formed in a BEOL network. Transistor 710 may correspond to Figure 6 The transistor 610; the first pair of resistors 720 and 730 may correspond to Figure 6 The first pair of resistors 620 and 630; the second pair of resistors 740 and 750 may correspond to Figure 6 The second pair of resistors 640 and 650 of; and the third pair of resistors 760 and 770 may correspond to Figure 6 A third pair of resistors 660 and 670.

[0112] exist Figure 7 In the illustrated example, transistor 710 is formed as a FinFET structure. However, transistor 710 may be formed as any of a variety of other transistor structures (e.g., a gate-around (GAA) FET structure) while remaining within the scope of the present disclosure. Figure 7 In the embodiment, on a substrate 702, a transistor 710 includes a fin structure 704 protruding from the substrate 702, a gate structure 706 spanning the fin structure 704, and a pair of source / drain structures 708 disposed on opposite sides of the gate structure 706 and respectively connected to two ends of the fin structure 704. A BEOL network including several metal layers, such as an M1 layer, an M2 layer, an M3 layer, an M4 layer, an M5 layer, an M6 layer, etc., is formed on the FEOL network forming the transistor 710.

[0113] According to various embodiments, different resistor pairs 720 and 730, 740 and 750, and 760 and 770 are formed on at least two different metal layers in the BEOL network. As shown, resistors 720 and 730 are formed in the M1 layer; resistors 760 and 770 are formed in the M1 layer; and resistors 740 and 750 are formed in the M5 layer. Therefore, different memory parts (e.g., Q1, Q2, and Q3) of the memory cell 600, corresponding to the semiconductor device 700, can be set in respective metal layers, which can further improve the security of the data stored in the memory cell 600.

[0114] Specifically, in Figure 7In the illustrated example, resistor 720 may be formed of a first dielectric material laterally inserted between via 1 structure 736 and conductor line 732 (in the M1 layer); resistor 730 may be formed of a second dielectric material laterally inserted between via 1 structure 736 and conductor line 734 (in the M1 layer); resistor 760 may be formed of a third dielectric material laterally inserted between via 1 structure 776 and conductor line 772 (in the M1 layer); resistor 770 may be formed of a fourth dielectric material laterally inserted between via 1 structure 776 and conductor line 774 (in the M1 layer); resistor 740 may be formed of a fifth dielectric material laterally inserted between via 5 structure 756 and conductor line 752 (in the M5 layer); and resistor 750 may be formed of a sixth dielectric material laterally inserted between via 1 structure 756 and conductor line 754 (in the M5 layer). To further illustrate, via 1 structure 736 may be connected to conductor line 738 (in the M2 layer); via 1 structure 776 may be connected to conductor line 778 (in the M2 layer); and via 5 structure 756 may be connected to conductor line 758 (in the M6 ​​layer).

[0115] According to various embodiments of the present disclosure, each of the first dielectric material to the sixth dielectric material is connected to the dielectric material 238 / 240 ( Figure 2 ) is similar. For clarity, the first dielectric material to the sixth dielectric material are not shown in FIG. Figure 7 For example, each of the first dielectric material to the sixth dielectric material includes a transition metal oxide (TMO), and the transition metal oxide has a variable resistance value. As a non-limiting example, such a transition metal oxide may include silicon dioxide (SiO2) and tantalum oxynitride (TaON). ​​As another non-limiting example, the transition metal oxide may be selected from the group consisting of: TiO x ,NiO x ,HfO x ,NbO x ,CoO x ,FeO x ,CuO x ,VO x ,TaO x ,WO x ,CrO x, and combinations thereof. The conductor lines (e.g., 732-734, 738, 772-774, 778, 752-754, 758) and the via structures (e.g., 736, 776, 756) connecting the conductor lines in different metal layers may each be formed of copper (Cu), but any of various other metals or conductive materials may be considered, such as Ti, Ni, Hf, Nb, Co, Fe, Cu, V, Ta, W, Cr, or combinations thereof.

[0116] Figure 8 Various embodiments of the present disclosure are shown for manufacturing a semiconductor device 700 (eg, Figure 6 700). As will be discussed in further detail below, the layout 800 includes some patterns of elements that may be used to define the semiconductor device 700. The layout 800 has been simplified to illustrate the patterns of certain elements that form the semiconductor device 700. Therefore, it should be understood that the layout 800 may include any of a variety of other patterns while remaining within the scope of the present disclosure.

[0117] like Figure 8 As shown, layout 800 includes pattern 804 and pattern 806 configured to form various elements in the FEOL network. For example, pattern 804 is configured to form an active region (which may be referred to herein as "oxide diffusion (OD) 804"); and pattern 806 is configured to form a gate structure (which may be referred to herein as "POLY 806"). In some embodiments, OD 804 and POLY 806 may thus define a transistor 710 of semiconductor element 700, wherein OD 804 forms a channel 704 and a source / drain structure 708, and POLY 806 forms a gate structure 706.

[0118] Layout 800 further includes patterns 832, 834, 836, 838, 872, 874, 876, 878, 852, 854, 856, and 858 configured to form various elements in the BEOL network. For example, patterns 832, 834, 872 and 874 are configured to form conductor lines in the M1 layer (referred to herein as "M1832", "M1834", "M1872" and "M1874", respectively); patterns 836 and 876 are configured to form via 1 structures (referred to herein as "via 1836" and "via 1876", respectively); patterns 838 and 878 are configured to form conductor lines in the M2 layer (referred to herein as "M2838" and "M2878", respectively); patterns 852 and 854 are configured to form conductor lines in the M5 layer (referred to herein as "M5852" and "M5854", respectively); pattern 856 is configured to form via 5 structures (referred to herein as "via 5856"); and pattern 858 is configured to form conductor lines in the M6 ​​layer (referred to herein as "M6858").

[0119] In some embodiments, the above-described BEOL components may thus form the first to third pairs of resistors 720-730, 760-770, and 740-750 of the semiconductor component 700. For example, M1 832 and M1 834 may correspond to conductor line 732 and conductor line 732, respectively; via 1 836 and via 1 876 may correspond to via 1 structure 736 and via 1 structure 776, respectively; via 2 838 and via 2 878 may correspond to conductor line 738 and conductor line 778, respectively; via 5 852 and via 5 854 may correspond to conductor line 752 and conductor line 754, respectively; via 5 856 may correspond to via 5 structure 756; and M6 858 may correspond to conductor line 758. Therefore, the memory part Q1 (resistors 720 and 730) can be formed by at least M1 832-834, through hole 1 836, dielectric material between through hole 1 836 and M1 832, and dielectric material between through hole 1 836 and M1 834; the memory part Q3 (resistors 760 and 770) can be formed by at least M1s 872-874, through hole 1 876, dielectric material between through hole 1 876 and M1 872, and dielectric material between through hole 1 876 and M1 874; and the memory part Q2 (resistors 740 and 750) can be formed by at least M5 852-854, through hole 5 856, dielectric material inserted between through hole 5 856 and M5852, and dielectric material inserted between through hole 5 856 and M5 854.

[0120] Please refer again Figure 6, the memory cell 600 includes a logic part (e.g., transistor 610) and a plurality of memory parts (e.g., Q1, Q2, and Q3). In some embodiments, the memory cell 600 can be defined as a standard cell in a cell library or an electronic component having an input D and an input S and an output Y, such as Fig. 9 The memory unit 600 can store various logic states according to the logic states respectively programmed into the memory locations Q1, Q2 and Q3, such as Fig.10 As shown in the truth table 1000 of . For example, when both inputs S and D are at logic 0, output Y can be represented as Q1Q2+Q2'Q3; when inputs S and D are at logic 0 and logic 1, respectively, output Y can be represented as Q1Q2+Q2'Q3; when inputs S and D are at logic 1 and logic 0, respectively, output Y can be tied to logic 0 (through transistor 610 being turned on); and when inputs S and D are both at logic 1, output Y can be tied to logic 1 (through transistor 610 being turned on). In some embodiments, one of the memory locations Q1, Q2, and Q3 can present a logic 1 when the first of its two resistors is programmed to a high resistance state H and the second of its two resistors is programmed to a low resistance state L, and present a logic 0 when the first resistor is programmed to L and the second resistor is programmed to H.

[0121] Please refer to the following Fig.11 , Fig.11 Exemplary operation stages 1101, 1103, 1105, 1107, and 1109 of memory cell 600 are shown. In some embodiments, operation stages 1101 to 1109 are performed according to Fig.11 The order shown forms an operation sequence. For example, the memory cell 600 can be operated from stage 1101, through stage 1103 to stage 1107, and to stage 1109. In stage 1101, the memory location Q1 of the memory cell 600 is cleared (or reset); in stage 1103, the memory locations Q2 and Q3 of the memory cell 600 are cleared (or reset); in stage 1105, the memory location Q1 of the memory cell 600 is programmed; in stage 1107, the memory location Q3 of the memory cell 600 is programmed; and in stage 1109, the memory location Q2 of the memory cell 600 is programmed.

[0122] In stage 1101 (resetting memory location Q1), two voltage combinations are shown applied to access lines D, S, B, and A, respectively. When the logic states previously programmed into memory location Q1 and memory location Q2 (e.g., resistors 620, 630, and 640 are programmed into H, L, and H, respectively) are the same, the voltages applied to access lines D, S, B, and A correspond to or are equal to logic 0, logic 1, 2VDD, and logic 0, respectively, causing resistors 620 and 640 to transition to L. When the logic states previously programmed into memory location Q1 and memory location Q2 (e.g., resistors 620, 630, and 640 are programmed into L, H, and H, respectively) are different, the voltages applied to access lines D, S, B, and A correspond to or are equal to logic 0, logic 1, logic 0, and 2VDD, respectively, causing resistors 630 and 640 to transition to L. Regardless of the logic state previously programmed into resistors 620 - 640 , each resistor 620 - 640 is reset to a low resistance state (L), ie, decomposing the corresponding dielectric material.

[0123] In stage 1103 (resetting memory locations Q2 and Q3), two voltage combinations are shown applied to access lines D, S, F, and E, respectively. When the logic states previously programmed into memory locations Q2 and Q3 (e.g., resistors 650, 660, and 670 are programmed into H, L, and H, respectively) are the same, the voltages applied to access lines D, S, F, and E correspond to or are equal to logic 0, logic 1, logic 0, and 2VDD, respectively, causing resistors 650 and 670 to transition to L. When the logic states previously programmed into memory locations Q2 and Q3 (e.g., resistors 650, 660, and 670 are programmed into H, H, and L, respectively) are different, the voltages applied to access lines D, S, F, and E correspond to or are equal to logic 0, logic 1, 2VDD, and logic 0, respectively, causing resistors 650 and 660 to transition to L. Regardless of the logic state previously programmed into resistors 650 - 670 , each resistor 650 - 670 is reset to a low resistance state (L), ie, decomposing the corresponding dielectric material.

[0124] In stage 1105 (Programming / Writing Memory Location Q1), two voltage combinations are shown applied to access lines D, S, B, and A, respectively. To program memory location Q1 to logic 0, the voltages applied to access lines D, S, B, and A correspond to or are equal to logic 0, logic 1, VDD, and 2VDD, respectively, causing resistors 630 and 640 to transition from L to H, respectively. To program memory location Q1 to logic 1, the voltages applied to access lines D, S, B, and A correspond to or are equal to logic 0, logic 1, 2VDD, and VDD, respectively, causing resistors 620 and 640 to transition from L to H, respectively.

[0125] In stage 1107 (Programming / Writing Memory Location Q3), two voltage combinations are shown applied to access lines D, S, F, and E, respectively. To program memory location Q3 to logic 0, the voltages applied to access lines D, S, F, and E correspond to or are equal to logic 0, logic 1, VDD, and 2VDD, respectively, causing resistors 650 and 670 to transition from L to H, respectively. To program memory location Q3 to logic 1, the voltages applied to access lines D, S, F, and E correspond to or are equal to logic 0, logic 1, 2VDD, and VDD, respectively, causing resistors 650 and 660 to transition from L to H, respectively.

[0126] In stage 1109 (Programming / Writing Memory Location Q2), two voltage combinations are shown applied to access lines D, S, B, A, F, and E, respectively. To program memory location Q2 to logic 0, the voltages applied to access lines D, S, F, and E correspond to or are equal to logic 0, logic 1, 2VDD, and 2VDD, respectively, causing resistor 650 to transition from H to L. To program memory location Q2 to logic 1, the voltages applied to access lines D, S, B, and A correspond to or are equal to logic 0, logic 1, 2VDD, and 2VDD, respectively, causing resistor 640 to transition from H to L.

[0127] Fig.12 FIG. 1 shows an example circuit diagram of a memory array 1200 including a plurality of memory cells 1202, 1204, 1206, and 1208 according to some embodiments. The memory cells 1202 to 1208 may each be implemented as Figure 6 For example, each memory cell 1202 to 1208 includes a transistor and three pairs of resistors, forming memory locations Q1 to Q3, and connected to a corresponding set of access lines, D, S, A, B, E and / or F. In 12, memory cell 1202 is connected to access line A n , B n , D m and S n connected, with an output node Y 1202 ; Memory unit 1204 and access line A n +1, B n +1, D m and S n+1 connected, with an output node Y 1204 ; Memory unit 1206 and access line E n 、F n , D m+1 and S n connected, with an output node Y 1206 ; and memory unit 1208 and access line E n+1 、F n+1 , D m+1 and Sn+1 connected, with an output node Y 1208 .

[0128] Fig.13 Various embodiments according to the present disclosure are shown, which can be used to manufacture Fig.12 1300 of the memory array 1200. Similar to the layout 800, the layout 1300 has been simplified, and therefore, it should be understood that the layout 1300 may include any of a variety of other patterns while remaining within the scope of the present disclosure. In addition, the layout 1300 generally includes four layouts 800 arranged as an array. For example, the array formed by the layout 1300 includes four memory cells, each memory cell having a transistor coupled to three pairs of resistors (e.g., each memory cell can be represented as Figure 6 Each of the four memory cells may be formed by the layout 800, and thus, the description of the layout 1300 will not be repeated.

[0129] Fig.14 1400. A flowchart of an exemplary method for manufacturing a semiconductor device including at least one disclosed memory cell according to various embodiments of the present disclosure is shown. For example, at least some of the operations (or steps) of method 1400 may be performed to manufacture, fabricate, or otherwise form semiconductor device 700 ( Figure 7 ). Therefore, the following discussion of method 1400 may refer to Figures 6 to 8 Some of the reference numerals used in the present disclosure are provided as non-limiting examples. Furthermore, method 1400 is only an example and is not intended to limit the present disclosure. Therefore, it should be understood that Fig.14 Additional operations may be provided before, during, and after method 1400, and some other operations may be only briefly described herein.

[0130] Method 1400 begins at operation 1402, where a transistor is formed along a major surface of a substrate. Figure 7 Taking the semiconductor device 700 as an example, a transistor (eg, 710) implemented as a FinFET is formed along a major surface of a substrate (eg, 702). However, the transistor 710 can be formed as any of a variety of other transistor structures while remaining within the scope of the present disclosure.

[0131] Method 1400 proceeds to operation 1404, where at least two first conductor lines separated from each other are formed in the first metal layer. Continuing with the above example, first conductor lines (e.g., 732 and 734, 772 and 774) are formed in a first metal layer (e.g., M1 layer). The M1 layer is formed on transistor 710. First conductor lines 732 and 734 (or 772 and 774) are formed to be laterally separated from each other. In addition, first conductor lines 732 and 734 are physically and electrically isolated from each other by a first dielectric material; and first conductor lines 772 and 774 are physically and electrically isolated from each other by a second dielectric material. In some embodiments, the first dielectric material and the second dielectric material each include a transition metal oxide that can be programmed between a first (e.g., high) resistance state and a second (e.g., low) resistance state.

[0132] Method 1400 proceeds to operation 1406, where a first via structure is formed, the first via structure having a lower portion laterally inserted between at least two first conductor lines. Continuing with the above example, the first via structure (e.g., 736 or 776) is formed to have a lower portion laterally inserted between a corresponding pair of first conductor lines. Figure 7 As shown, the first via structure 736 has a lower portion laterally inserted between the first conductor lines 732 and 734; and the first via structure 776 has a lower portion laterally inserted between the first conductor lines 772 and 774. In addition, the first via structure 736 is physically and electrically isolated from the first conductor line 732 at a portion of the first transition metal oxide, and is physically and electrically isolated from the first conductor line 734 at another portion of the first transition metal oxide; and the first via structure 776 is physically and electrically isolated from the first conductor line 772 at a portion of the second transition metal oxide, and is physically and electrically isolated from the first conductor line 774 at another portion of the second transition metal oxide.

[0133] Method 1400 proceeds to operation 1408, where at least two mutually separated second conductor lines are formed in the second metal layer. Continuing with the above example, the second conductor lines (e.g., 752 and 754) are formed in the second metal layer (e.g., M5 layer). The M5 layer is formed above the M1 layer, and the M1 layer is further formed above the transistor 710. However, it should be understood that the second conductor line can be formed in any metal layer (e.g., M3 layer, M4 layer) above the M1 layer. The second conductor lines 752 and 754 are formed to be laterally separated from each other. In addition, the second conductor lines 752 and 754 are physically isolated from each other and electrically isolated from the third dielectric material. In some embodiments, the third dielectric material includes a transition metal oxide that can be programmed between a first (e.g., high) resistance state and a second (e.g., low) resistance state.

[0134] Method 1400 proceeds to operation 1410, where a second via structure is formed having a lower portion laterally inserted between at least two second conductor lines. Continuing with the above example, a second via structure (e.g., 756) is formed to have a lower portion laterally inserted between a corresponding pair of second conductor lines. Figure 7 As shown, the second via structure 756 has a lower portion that is laterally inserted between the second conductor lines 752 and 754. In addition, the second via structure 756 is physically and electrically isolated from the second conductor line 752 by a portion of the third transition metal oxide, and is physically and electrically isolated from the second conductor line 754 by another portion of the third transition metal oxide.

[0135] In one aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory cell, the memory cell including: a transistor; and one or more pairs of resistors coupled in series to the transistor. Each of the one or more pairs of resistors includes a first resistor and a second resistor. The transistor is formed along a main surface of a substrate, and the one or more pairs of resistors are respectively formed in one or more of a plurality of metal layers disposed above the transistor.

[0136] In some embodiments, the memory cell is configured as a one-time programmable memory cell. One of the first resistor or the second resistor is configured to permanently switch from a first resistance state to a second resistance state.

[0137] In some implementations, a first of the one or more pairs of resistors is formed in a first of the metal layers and a second of the one or more pairs of resistors is formed in a second of the metal layers. The first of the metal layers is vertically spaced from the second of the metal layers.

[0138] In some embodiments, the first resistor is formed of a first dielectric material laterally located between the via structure and the first conductor line. The second resistor is formed of a second dielectric material laterally located between the via structure and the second conductor line.

[0139] In some embodiments, the first conductor line and the second conductor line are formed in the same metal layer.

[0140] In some embodiments, the via structure has a lower portion that is laterally inserted between the first conductor line and the second conductor line.

[0141] In some embodiments, the first dielectric material and the second dielectric material each include a transition metal oxide.

[0142] In some embodiments, the via structure, the first conductor line, and the second conductor line each include copper.

[0143] In some implementations, the transistor is part of a front-end-of-line (FEOL) network and the one or more pairs of resistors are part of a back-end-of-line (BEOL) network.

[0144] In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory cell, the memory cell including: a transistor; and a plurality of pairs of resistors coupled in series to the transistor, each pair of resistors including a first resistor and a second resistor. The transistor is formed along a major surface of a substrate. A first pair of the resistors is formed in a first of a plurality of metal layers disposed above the transistor. At least a second pair of the resistors is formed in a second of the plurality of metal layers, the second metal layer being disposed above the first metal layer.

[0145] In some embodiments, the memory cell is configured as a one-time programmable memory cell. One of the first resistor or the second resistor is configured to permanently switch from a first resistance state to a second resistance state.

[0146] In some embodiments, the first resistor of each pair of resistors is formed of a first dielectric material laterally located between the via structure and the first conductor line, and the second resistor of the corresponding pair of resistors is formed of a second dielectric material laterally located between the via structure and the second conductor line.

[0147] In some embodiments, the first conductor line and the second conductor line are formed in the same metal layer.

[0148] In some embodiments, the via structure has a lower portion laterally inserted between the first conductor line and the second conductor line.

[0149] In some embodiments, the first dielectric material and the second dielectric material each include a transition metal oxide.

[0150] In some embodiments, the via structure, the first conductor line, and the second conductor line each include copper.

[0151] In some embodiments, the via structure has an upper portion that extends vertically away from the first conductor line and the second conductor line.

[0152] In another aspect of the present disclosure, a method for manufacturing a memory device is disclosed, comprising forming a transistor along a major surface of a substrate. The method comprises forming a first metal layer above the transistor, wherein the first metal layer comprises a plurality of first conductor lines, the first conductor lines being laterally separated from each other by a first dielectric material. The method comprises forming a first via structure, wherein a lower portion of the first via structure is laterally inserted between a pair of adjacent first conductor lines.

[0153] In some embodiments, the method further includes forming a second metal layer above the first metal layer, wherein the second metal layer includes a plurality of second conductor lines, the second conductor lines being laterally separated by a second dielectric material. The method includes forming a second via structure having a lower portion laterally inserted between adjacent pairs of the second conductor lines.

[0154] In some embodiments, the first dielectric material and the second dielectric material each include a transition metal oxide, and the first conductor line, the second conductor line, the first via structure, and the second via structure each include copper.

[0155] In another aspect of the present disclosure, a memory element is disclosed, comprising a transistor, a first metal layer, a first dielectric material, a first through-hole structure, a second metal layer, a second dielectric material, and a second through-hole structure. The first metal layer is above the transistor, and the first metal layer comprises a plurality of first conductor lines. The first dielectric material laterally separates the first conductor lines. The first through-hole structure comprises a first lower portion. The first lower portion is laterally inserted between an adjacent pair of first conductor lines. The second metal layer is above the first metal layer, and the second metal layer comprises a plurality of second conductor lines. The second dielectric material separates the second conductor lines. The second through-hole structure comprises a second lower portion, and the second lower portion is laterally inserted between an adjacent pair of second conductor lines.

[0156] As used herein, the terms "about" and "approximately" generally refer to plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0157] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, characterized in that: Include: A memory unit comprising: a transistor; and One or more pairs of resistors are coupled in series to the transistor, each pair of the one or more pairs of resistors comprising a first resistor and a second resistor; The transistor is formed along a main surface of a substrate, and the one or more pairs of resistors are respectively formed in one or more layers of a plurality of metal layers disposed above the transistor.

2. The memory device according to claim 1, wherein: The memory cell is configured as a one-time programmable memory cell, wherein one of the first resistor or the second resistor is configured to be permanently switched from a first resistance state to a second resistance state.

3. The memory device according to claim 1, wherein: A first one of the one or more pairs of resistors is formed in a first one of the multiple metal layers, and a second one of the one or more pairs of resistors is formed in a second one of the multiple metal layers, and wherein the first one of the multiple metal layers is vertically spaced from the second one of the multiple metal layers.

4. The memory device according to claim 1, wherein: The first resistor is formed of a first dielectric material laterally located between a via structure and a first conductor line, and the second resistor is formed of a second dielectric material laterally located between the via structure and a second conductor line.

5. A memory device, characterized in that: Include: A memory unit comprising: a transistor; and A plurality of pairs of resistors coupled in series to the transistor, each pair of the plurality of pairs of resistors comprising a first resistor and a second resistor; wherein the transistor is formed along a major surface of a substrate; wherein at least a first pair of the plurality of pairs of resistors is formed in a first one of a plurality of metal layers disposed above the transistor; and At least a second pair of the plurality of pairs of resistors is formed in a second one of the plurality of metal layers, and the second one of the plurality of metal layers is disposed above the first one of the plurality of metal layers.

6. The memory device according to claim 5, wherein: The first resistor of each pair of the multiple pairs of resistors is formed by a first dielectric material laterally located between a through-hole structure and a first conductor line, and the second resistor of the corresponding multiple pairs of resistors is formed by a second dielectric material laterally located between the through-hole structure and a second conductor line.

7. The memory device according to claim 6, wherein: The first conductor line and the second conductor line are formed in the same one of the plurality of metal layers.

8. The memory device according to claim 6, wherein: The through hole structure has a lower portion which is laterally inserted between the first conductor line and the second conductor line.

9. The memory device according to claim 6, wherein: The through hole structure has an upper portion, and the upper portion extends vertically away from the first conductor line and the second conductor line.

10. A memory device, characterized in that: Include: A transistor; a first metal layer above the transistor, the first metal layer comprising a plurality of first conductor lines; a first dielectric material laterally separating the plurality of first conductor lines; a first through-hole structure comprising a first lower portion, wherein the first lower portion is laterally inserted between an adjacent pair of the plurality of first conductor lines; a second metal layer, above the first metal layer, the second metal layer comprising a plurality of second conductor lines; a second dielectric material separating the plurality of second conductor lines; as well as A second through-hole structure includes a second lower portion, which is laterally inserted between an adjacent pair of the plurality of second conductor lines.

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