HEMT device

Abstract

The utility model relates to an HEMT (High Electron Mobility Transistor) device, which comprises a semiconductor body with a semiconductor heterostructure; a gate region on the semiconductor body, the gate region having a plurality of sides; a plurality of sealing regions of a first non-conductive material extending on and in contact with the plurality of sides of the gate region; and a passivation layer of a second non-conductive material, the passivation layer having a surface portion extending on the semiconductor body laterally and at a distance from the plurality of sides of the gate region, the plurality of sealing regions having different geometric parameters from the passivation layer; and a plurality of spacer regions extending laterally and in contact with the plurality of sealing regions, the passivation layer having raised portions extending laterally and at a distance from the plurality of sealing regions on the plurality of spacer regions.

Description

Technical Field

[0001] The present disclosure relates to a high electron mobility transistor (HEMT) with reduced on-resistance and a process for manufacturing the same. Background Art

[0002] As is known, HEMT devices, also known as heterostructure field effect transistors (HFETs), have gained widespread popularity due to the possibility of operating at high voltages, their high breakdown voltage, and high density and mobility.

[0003] In HEMT devices, semiconductor heterostructures (usually based on AlGaN / GaN layers) allow the spontaneous generation of a so-called two-dimensional electron gas (2DEG) in the device, which forms a channel path for charges. The spontaneous channel can be modulated by applying a suitable voltage at the gate region above the channel path.

[0004] AlGaN / GaN HEMTs are usually depletion mode. However, for practical applications, enhancement mode (normally off) devices are preferred for safe operation and drive circuit simplification.

[0005] Several methods have been proposed to realize normally-off HEMTs based on AlGaN / GaN layers, including forming a recessed gate transistor, performing specific manufacturing steps such as incorporating a fluorine plasma under the gate, or forming the gate region of p-GaN. The last solution is used, for example, in products available on the market and is considered below.

[0006] For example, Figure 1 A HEMT device 1 formed on a semiconductor body 2 is shown, where the semiconductor body 2 comprises a substrate layer 3, a first layer 4 and a second layer 6 (hereinafter also referred to as a channel layer 4 and a barrier layer 6).

[0007] The substrate layer 3 may include Figure 1 The silicon substrate and gallium nitride (GaN) buffer layer are not shown separately.

[0008] The channel layer 4 is made of a first semiconductor material such as, for example, a first semiconductor alloy of elements of Group III and Group V of the periodic table; for example, the channel layer 4 may be made of gallium nitride (GaN).

[0009] The barrier layer 6 covers the channel layer 4 and is in direct contact with the channel layer 4, and is made of a second semiconductor material, such as, for example, a second semiconductor alloy of Group III-Group V elements of the periodic table, which is different from the first semiconductor alloy. For example, the barrier layer 6 can be made of aluminum gallium nitride (AlGaN).

[0010] The channel layer 4 and the barrier layer 6 are, for example, of N-type.

[0011] A gate region 7 of conductive material extends on the barrier layer 6. The gate region 7 is formed, for example, of a third semiconductor material such as, for example, a third semiconductor alloy of elements of Group III and Group V of the periodic table; in particular, here the gate region 7 is formed of P-conductivity type gallium nitride (pGaN).

[0012] A first insulating region 9 of, for example, silicon oxide, extends on the barrier layer 6 , on the side surfaces and on the upper surface of the gate region 7 .

[0013] An opening 11 extends through the first insulating region 9 on top of the gate region 7 , and a gate metal region 10 , for example TiN / AlCu / TiN, is in direct electrical contact with the gate region 7 and extends in the opening 11 and partially over the first insulating region 9 .

[0014] A second insulating region 12 , for example silicon oxide, extends over the first insulating region 9 and the gate metal region 10 .

[0015] A field plate 13 of conductive material may extend on the first insulating region 9, laterally to the gate metal region 10, and below the second insulating region 12. The field plate 13 may be formed of the same metal layer as the gate metal region 10.

[0016] The source metal region 15, for example Ti / AlCu / TiN, extends on and laterally of the second insulating region 12 and is in direct electrical contact with the barrier layer 6. In the HEMT device 1, the source metal region 15 has a portion extending over the gate metal region 10 and over the field plate region 13 and has a shielding function.

[0017] A drain metal region 16 of, for example, Ti / AlCu / TiN, is on and extends laterally from the second insulating region 12 (on the opposite side of the gate region 7 relative to the source metal region 15 ), on the barrier layer 6 and in direct electrical contact therewith.

[0018] In this type of HEMT transistor, etching of the layers above the semiconductor body 2 is critical and may affect the barrier layer 6. Indeed, such etching may damage the barrier layer 6 and cause an increase in its sheet resistance, thus causing an increase in the on-resistance (Ron) of the HEMT device 1.

[0019] To avoid this severity, it has been suggested to vary the parameters of the barrier layer 6 (thickness, percentage of Al); however, this solution has the disadvantage of also reducing the pinch off voltage Vpo, thus reducing the threshold voltage of the device; in addition, it also reduces the gate current Igon. The choice of parameters therefore implies a compromise between Ron, Vpo / Vth and Igo.

[0020] Another known solution to the above problem is to arrange a protective layer of ammonium hydroxide resistant material (such as Al2O3 or AlN) on the sides and (partially) on the upper side of the gate region 7, in order to prevent leakage therefrom in particular.

[0021] But this solution is also disadvantageous because the dielectric parameters (eg, thickness and material) of the added protection layer affect the gate leakage and the sheet resistance in opposite ways; therefore, an optimal value of the sheet resistance may mean a deterioration of the gate leakage.

[0022] Other known transistors provide additional dielectric layers adjacent to the gate region stack, but require more complex manufacturing processes, thereby increasing the cost of the final device. Utility Model Content

[0023] One object of the present disclosure is to overcome the disadvantages and limitations of the prior art.

[0024] According to the present disclosure, there is provided a HEMT device and a process for manufacturing the same, as defined in the accompanying claims.

[0025] According to one aspect of the present disclosure, a HEMT device is provided, comprising: a semiconductor body having a semiconductor heterostructure; a gate region on the semiconductor body, the gate region having a plurality of side surfaces; a plurality of sealing regions of a first non-conductive material extending on and in contact with the plurality of side surfaces of the gate region; and a passivation layer of a second non-conductive material, the passivation layer having a surface portion extending on the semiconductor body, laterally and at a distance from the plurality of side surfaces of the gate region, the plurality of sealing regions having different geometric parameters from the passivation layer; and a plurality of spacer regions extending laterally and in contact with the plurality of sealing regions, the passivation layer having a protruding portion extending on the plurality of spacer regions, laterally and at a distance from the plurality of sealing regions.

[0026] In some embodiments, the HEMT device further includes: an insulating structure extending above the semiconductor body, laterally and on top of the gate region; the first non-conductive material and the second non-conductive material are different materials; a first current conducting terminal, laterally to a first side of the plurality of side surfaces of the gate region, extending on the semiconductor body and contacting the semiconductor body, at least partially through the insulating structure; a second current conducting terminal, laterally to a second side of the plurality of side surfaces of the gate region, extending on the semiconductor body and contacting the semiconductor body, at least partially through the insulating structure; and a control terminal extending on and contacting the gate region, at least partially through the insulating structure.

[0027] In some embodiments, the sealing area is made of an insulating material.

[0028] In some embodiments, the plurality of sealing regions have a thickness between 2 nm and 10 nm.

[0029] In some embodiments, the passivation layer is made of an insulating material.

[0030] In some embodiments, the passivation layer has a thickness between 2 nm and 10 nm.

[0031] In some embodiments, the passivation layer has a greater thickness than the plurality of sealing regions.

[0032] In some embodiments, the plurality of spacer regions are made of oxide.

[0033] According to one aspect of the present disclosure, a HEMT device is provided, comprising: a semiconductor body having a semiconductor heterostructure; a gate region on the semiconductor body, the gate region having a plurality of side surfaces; a plurality of sealing regions of a first non-conductive material extending on and in contact with the plurality of side surfaces of the gate region; and a passivation layer of a second non-conductive material, the passivation layer having a surface portion extending on the semiconductor body, laterally and at a distance from the plurality of side surfaces of the gate region, the plurality of sealing regions and the passivation layer being made of a different material; and a plurality of spacer regions extending laterally and in contact with the plurality of sealing regions, the passivation layer having a protruding portion extending on the plurality of spacer regions, laterally and at a distance from the plurality of sealing regions.

[0034] In some embodiments, the HEMT device includes: an insulating structure extending laterally above the semiconductor body and on top of the gate region; a first current conducting terminal extending laterally to a first side of the plurality of side surfaces of the gate region on the semiconductor body and in contact with the semiconductor body, at least partially through the insulating structure; a second current conducting terminal extending laterally to a second side of the plurality of side surfaces of the gate region on the semiconductor body and in contact with the semiconductor body, at least partially through the insulating structure; and a control terminal extending on and in contact with the gate region, at least partially through the insulating structure.

[0035] In some embodiments, the plurality of sealing regions and the passivation layer have different geometric parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to understand the present disclosure, embodiments thereof will now be described, purely as non-limiting examples, with reference to the accompanying drawings, in which:

[0037] Figure 1 is the cross section of a known HEMT device;

[0038] Figure 2 is a cross section of a HEMT device according to an embodiment;

[0039] Figure 3A-3H yes Figure 2 A cross section of a semiconductor wafer in a subsequent manufacturing step of a HEMT device;

[0040] Figure 4A-4C is a cross section of a semiconductor wafer in a subsequent manufacturing step of some embodiments of the present HEMT device;

[0041] Figure 5 is a cross-section of a HEMT device according to some embodiments; and

[0042] Fig. 6A and Figure 6B yes Figure 5 Cross section of a semiconductor wafer during the subsequent fabrication steps of a HEMT device. DETAILED DESCRIPTION

[0043] The following description refers to the arrangements shown in the accompanying drawings; therefore, expressions such as "above", "below", "upper", "lower", "top", "bottom", "right", "left", etc. are relative to the drawings and should not be interpreted in a limiting manner.

[0044] Figure 2 A HEMT device 50 is shown, which comprises a semiconductor body 52 , here formed by a substrate layer 53 , a channel layer 54 and a barrier layer 56 .

[0045] The substrate layer 53 may include Figure 2 The silicon substrate and gallium nitride (GaN) buffer layer are not shown separately.

[0046] The channel layer 54 is made of a first semiconductor material, such as a first semiconductor alloy of Group III and Group V elements of the periodic table; for example, the channel layer 54 may be made of gallium nitride (GaN).

[0047] The barrier layer 56 covers and directly contacts the channel layer 54 and is made of a second semiconductor material, such as a second semiconductor alloy of Group III-V elements of the periodic table, which is different from the first semiconductor alloy. For example, the barrier layer 56 can be made of aluminum gallium nitride (AlGaN).

[0048] The channel layer 54 and the barrier layer 56 are, for example, of N-type.

[0049] A gate region 57 of conductive material extends on and is in contact with the barrier layer 56. In a manner not shown, the gate region 57 is strip-shaped and extends along a first horizontal axis Y of the Cartesian reference system XYZ.

[0050] exist Figure 2 In the embodiment, the gate region 57 includes a channel modulation region 58 (here made of pGaN (P-conductivity type gallium nitride)) and an interlayer region 59.

[0051] The channel modulation region 58 serves to modulate the thickness of a channel formed at an interface between the channel layer 54 and the barrier layer 56 based on a voltage applied thereto.

[0052] The interlayer region 59 is used to facilitate the turn-on of the channel modulation region 58 and to form a barrier to the diffusion of contaminants from the upper layer, as described later. The interlayer region 59 may be made of a material such as TiN.

[0053] exist Figure 2 In an embodiment of the present invention, along the second horizontal axis X of the Cartesian reference system XYZ, the interlayer region 59 has a smaller width than the channel modulation region 58. The interlayer region 59 is optional.

[0054] The sealing region 61 covers the side surfaces and (part of) the upper side of the channel modulation region 58 and the side surfaces of the interlayer region 59 and extends along the first horizontal axis Y. The sealing region 61 is formed by a layer of a non-conductive material, for example an oxide such as Al2O3. As an alternative, HfO2 and AlON may be used.

[0055] The thickness of the sealing region 61 may be comprised between 2 nm and 10 nm, for example 2.5 nm.

[0056] The spacer region 62 extends laterally and continuously to the sealing region 61 on both sides of the channel modulation region 58 and the interlayer region 59. The spacer region 62 is made of a dielectric material such as silicon oxide.

[0057] The passivation layer 65 extends on the side of the spacer region 62 and on the substrate 52. In detail, the passivation layer 65 has two surface portions 65A (on the opposite side of the gate region 57, each surface portion 65A extends on and contacts the barrier layer 56) and two convex portions 65B, each convex portion 65B extends on the corresponding spacer region 62 and partially extends on the corresponding side of the interlayer region 59.

[0058] A surface portion 65A of the passivation layer 65 extending over the barrier layer 56 forms an access region of the HEMT device 50 .

[0059] The passivation layer 65 is opened on the interlayer region 59 to expose a large part of the upper surface of the latter. The passivation layer 65 is an insulating material, for example, AlN, and in this embodiment, has a greater thickness than the layer forming the sealing region 61. In particular, the thickness of the passivation layer 65 may be comprised between 2 nm and 10 nm, for example 5 nm.

[0060] The first insulating layer 66 , such as silicon oxide, extends on the passivation layer 65 and opens on the interlayer region 59 , thereby forming a gate opening 67 together with the passivation layer 65 .

[0061] A multi-layer gate metal 68 , such as TiN / AlCu / TiN, extends in the gate opening 67 , is in direct electrical contact with the interlayer region 59 , and is partially on the first insulating layer 66 .

[0062] A second insulating layer 69 , such as silicon oxide, extends over the first insulating layer 66 and the gate metal 68 .

[0063] The first insulating layer 66 and the second insulating layer 69 form an insulating structure 66 , 69 . The insulating structure 66 , 69 has a source opening 82 and a drain opening 83 which extend through the entire thickness of the insulating structure 66 , 69 as far as the barrier layer 56 on different sides of the gate region 57 .

[0064] Source metal region 72 of, for example, Ti / AlCu / TiN, extends in source opening 82 and is in direct electrical contact therewith with barrier layer 56. In HEMT device 50, source metal region 72 has a portion that also extends over gate metal 68 and over field plate 70 and has a shielding function.

[0065] The field plate 70 may extend on the first insulating layer 66, below the second insulating layer 69, on one side of the gate region 57 but at a certain distance. The field plate 70 may be formed of the same metal layer as the gate metal 68 and electrically connected to the source metal region 72.

[0066] Drain metal region 73 , for example Ti / AlCu / TiN, extends in drain opening 83 and is in direct electrical contact with barrier layer 56 . Drain metal region 73 is on the opposite side of gate region 57 from source metal region 72 .

[0067] By having a sealing region 61 on the side of the gate region 57 having different properties than the surface portion 65A at the access region, Figure 2 The HEMT device 50 forms different 2DEGs at the gate region and at the access region, i.e., a first 2DEG (hereinafter also referred to as gate 2DEG) at the interface between the channel layer 54 and the barrier layer 56 below the gate region 57 and a second 2DEG (hereinafter also referred to as access 2DEG) at the interface between the channel layer 54 and the barrier layer 56 below the surface portion 65A of the passivation layer 65.

[0068] By tailoring and optimizing the parameters / features of the sealing layer 61 and the passivation layer 65 , the density of the gate 2DEG and the access 2DEG can thus be tailored and optimized according to the desired characteristics.

[0069] In particular, using Figure 2 The structure can have a high sheet resistance Rsh below and around the gate region 57, resulting in a high threshold voltage and low electric field at the corner between the channel modulation region 58 and the blocking layer 56 (at the gate 2DEG) and a low sheet resistance Rsh below the passivation layer 65, resulting in a low on-resistance Ron (at the access 2DEG).

[0070] The HEMT device 50 thus allows a good compromise to be obtained between gate current, threshold voltage and on-resistance.

[0071] The HEMT device 50 may be Figure 3A-3H As shown in the manufacture, Figure 3A-3H The wafer is shown before dicing and is cut using Figure 2 The same reference numerals are used for areas with the same name.

[0072] Figure 3A A wafer 80 is shown comprising a stack of layers including a substrate layer 53, a channel layer 54 and a barrier layer 56. On the barrier layer 56 a gate region 57 has been formed.

[0073] For example, the channel modulation region 58 and the interlayer region 59 can be formed by sputtering a TiN layer on a pGaN layer (not shown, epitaxially grown on the barrier layer 56) and photolithographically defining the TiN layer and the pGaN layer by side etching using a single mask (also not shown) to obtain a smaller width of the interlayer region 59; however, any other manufacturing steps are possible, such as by using two different masks.

[0074] exist Figure 3B In the embodiment, a sealing layer 61 is formed on the gate region 57 and the exposed portion of the barrier layer 56, and then an oxide layer 81 is formed.

[0075] For example, the sealing layer 61 is thermally or plasma deposited by ALD (Atomic Layer Deposition) technique in a H 2 O or O 3 based environment at 300° C. with a thickness of, for example, 2.5 nm.

[0076] The oxide layer 81 may be deposited, for example, by PECVD (Plasma Enhanced Chemical Vapor Deposition) in a SiO 2 SiH 4 based environment with a thickness of, for example, 200 nm.

[0077] exist Figure 3C In the embodiment, the oxide layer 81 is anisotropically (dry) etched without a mask to remove it from the surface of the barrier layer 56 and the top of the interlayer region 59 and to remain on the side surface of the gate region 57, thereby forming the spacer region 62.

[0078] exist Figure 3D In the embodiment, the sealing layer 61 is etched on the top of the interlayer region 59 and above the barrier layer 56 which is not covered by the spacer region 62. For example, the etching is a wet etching, using an etchant which is selective to the material of the barrier layer 56 of AlGaN, in particular using an etchant made by DuPont TM Production of EKC265 TM Thus, selective removal from the barrier layer 56 can be achieved without damaging the barrier layer 56 itself, and thus without affecting access to the 2DEG in operation. Therefore, the sheet resistance Rsh is not negatively affected by such etching.

[0079] A surface portion of the sealing layer 61 also remains under the spacer 62 .

[0080] exist Figure 3E In the embodiment, the passivation layer 65 is formed of, for example, AlN and is formed at about 370° C. using an ALD technique, and has a thickness of, for example, 5 nm.

[0081] exist Figure 3F In the process, a first insulating layer 66 of, for example, silicon oxide is deposited, for example by PECVD in a SiO 2 SiH 4 based environment, with a thickness of, for example, 50 nm.

[0082] exist Figure 3G In the embodiment, the first insulating layer 66 and the passivation layer 65 are etched using a mask (not shown) to form a gate opening 67, thereby exposing the top surface of the gate region 57. The etching of the first insulating layer 66 and the passivation layer 65 can be a wet etch or a dry etch, depending on the selectivity of the materials used, as known to those skilled in the art.

[0083] exist Figure 3H In the embodiment of the present invention, a gate metal layer is deposited and defined to form a gate metal 68 (in the gate opening 67) and a field plate 70 (to the side thereof). The gate metal layer may be a multilayer of TiN / AlCu / TiN.

[0084] Then, in a manner not shown, a second insulating layer 69 is deposited and then defined (using a mask not shown) together with the first insulating layer 66 to form source openings 82 and drain openings 83. Thereafter, a source / drain metal layer is deposited and defined to form source metal regions 72 and drain metal regions 73.

[0085] The final manufacturing steps then take place, including deposition of the outer passivation layers, opening of the contacts and dicing of the wafer 80 to obtain Figure 2 HEMT device 50.

[0086] Figure 4A-4C Various embodiments are described that include a double-layer field plate.

[0087] In particular, Figure 4A Shows Figure 3F The wafer 80 after the step of . Here, before opening the first insulating layer 66 and the passivation layer 65, a step forming region 85 is formed. For example, a SiN layer is deposited and defined. Here, the step forming region 85 extends laterally on the side of the gate region 57 facing the drain metal region 73.

[0088] exist Figure 4B In the embodiment, the first insulating layer 66 and the passivation layer 65 are etched to form a gate opening 67 and expose the top surface of the gate region 57, similar to the above reference Figure 3G as described.

[0089] exist Figure 4C In the embodiment, a gate metal layer is deposited and defined to form gate metal 68 (in gate opening 67) and field plate 70'. Here, field plate 70' partially extends over first insulating layer 66 and partially extends on step formation region 85, and thus is not planar.

[0090] Then, the second insulating layer 69 is deposited and etched; the source metal region 72 and the drain metal region 73 are formed as described above, followed by the final manufacturing steps.

[0091] Figure 5 A HEMT device 100 is shown in which the source metal region and the drain metal region are formed before the gate metal region.

[0092] In detail, Figure 5 Among them, Figure 2 The same regions of the HEMT device 50 have been indicated using the same reference numerals, the source metal region and the drain metal region (indicated herein by 72′, 73′) are formed only by the first insulating layer 66, and the gate metal region (indicated herein by 68′) is formed by both insulating layers 66, 69 after forming the second insulating layer 69.

[0093] In detail, Fig. 6A As shown in FIG. , when forming the first insulating layer 66 ( Figure 3F ), a first insulating layer 66 is defined to form a source opening indicated here by 82' and a drain opening indicated here by 83'. At the source opening 82' and the drain opening 83', the passivation layer 65 is also removed from the body 52.

[0094] Then, the source metal region 72 ′, the drain metal region 73 ′ and the field plate 70 are formed by depositing and defining the same metal layer or stack, for example Ti / AlCu / TiN.

[0095] After that, Figure 6B , a second insulating layer 69 is deposited and etched (together with the first insulating layer 66 and the passivation layer 65) to form a gate opening, indicated here by 67'. Figure 6B and Figure 5 In FIG. 6 , the gate opening 67 ′ extends through the first insulating layer 66 and the second insulating layer 69 .

[0096] Then, a gate metal is formed, here indicated by 68 ′, by depositing and defining a metal layer or stack, such as Ti / AlCu / TiN; in this step, the shielding region 86 may be formed of the same metal layer as the gate metal 68 ′.

[0097] By Figure 5 By forming one or more vias through the first insulating layer 66 and the second insulating layer 69 at locations not shown in the figure, the shielding region 86 can be electrically coupled to other regions in the substrate 52.

[0098] The final manufacturing steps are then performed as described above.

[0099] Finally, it is clear that numerous changes and modifications may be made to the HEMT devices and processes described and illustrated herein, all of which fall within the scope of the present disclosure as defined in the appended claims.

[0100] Generally speaking, the passivation layer 65 may have the same thickness as or greater than the sealing layer 61 .

[0101] In summary, example embodiments of the present disclosure are as follows.

[0102] Example 1. A HEMT device (50; 100), comprising:

[0103] A semiconductor body (52) having a semiconductor heterostructure (54, 56);

[0104] A gate region (57) comprising a semiconductor material and arranged on the semiconductor body (52), the gate region having a side surface;

[0105] a sealing region (61) of non-conductive material extending over and contacting the sides of the gate region (57); and

[0106] a passivation layer (65) of a non-conductive material having a surface portion (65A) extending laterally on the semiconductor body (52) and at a distance from the side of the gate region,

[0107] The sealing region (61) and the passivation layer (65) have different geometrical parameters and / or are made of different materials.

[0108] Example 1-2. The HEMT device according to Example 1, wherein the gate region (57) is arranged in direct contact with the semiconductor body (52).

[0109] Example 1-3. The HEMT device of Example 1 or Example 1-2, wherein the surface portion (65A) of the passivation layer (65) is disposed on and in direct contact with the semiconductor body (52).

[0110] Example 2. The HEMT device according to Example 1, Example 1-2, or Example 1-3, further comprising:

[0111] an insulating structure (66, 69) extending above the semiconductor body (52), laterally and on top of the gate region;

[0112] a first current conducting terminal (72; 72') of electrically conductive material extending on and in contact with the semiconductor body (52) laterally to one of the sides of the gate region (57) and at least partially through the insulating structure (66, 69);

[0113] a second current conducting terminal (73; 73') of electrically conductive material, extending on and in contact with the semiconductor body (52) at the other of the sides laterally to the gate region (57), at least partially through the insulating structure (66, 69); and

[0114] A control terminal (68; 68') of conductive material extends over and contacts the gate region (57) and at least partially passes through the insulating structure (66, 69).

[0115] Example 3. A HEMT device according to any of the preceding examples, wherein the sealing region (61) is made of an insulating material, for example an oxide such as Al2O3, HfO2 and AlON.

[0116] Example 4. A HEMT device according to any of the preceding examples, wherein the sealing region (61) has a thickness comprised between 2 nm and 10 nm, for example 2.5 nm.

[0117] Example 5. The HEMT device according to any of the preceding examples, wherein the passivation layer (65) is made of an insulating material, such as AlN.

[0118] Example 6. A HEMT device according to any of the preceding examples, wherein the passivation region (65) has a thickness comprised between 2 nm and 10 nm, for example 5 nm.

[0119] Example 7. The HEMT device of any of the preceding examples, wherein the passivation region (65) has a greater thickness than the sealing region (61).

[0120] Example 8. The HEMT device according to any of the preceding examples further comprises a spacer region (62) of dielectric material extending laterally and in contact with the sealing region (62), and the passivation layer (65) has a raised portion (65B) extending on the spacer region (62), laterally and at a distance from the sealing region.

[0121] Example 9. A process for manufacturing a HEMT device (50; 100), the process comprising:

[0122] On a semiconductor body (52) having a semiconductor heterostructure (54, 56), a gate region (57) is formed, the gate region comprising a semiconductor material and arranged on the semiconductor body (52), the gate region having a side surface;

[0123] forming a sealing region (61) of non-conductive material on the sides of and in contact with the gate region (57); and

[0124] forming a passivation layer (65) of non-conductive material having a surface portion (65A) extending laterally on the semiconductor body (52) and at a distance from the side of the gate region,

[0125] The sealing region (61) and the passivation layer (65) have different geometrical parameters and / or are made of different materials.

[0126] Example 10. The process of the preceding example, wherein forming the sealing area (61) comprises:

[0127] forming a sealing layer (61) on the gate region (57) and the semiconductor body (52);

[0128] forming a spacer region (62) on the sealing layer and adjacent to the gate region; and

[0129] The exposed sealing layer (61) on the semiconductor body (52) is selectively removed.

[0130] Example 10-2. The process of the preceding example, wherein selectively removing the sealing layer (61) includes removing the sealing layer (61) on top of the gate region (57).

[0131] Example 11. The process of example 10 or example 10-2, wherein selectively removing the sealing layer (61) comprises using an etchant that is selective with respect to the semiconductor body (52).

[0132] Example 12. The process of example 10 or example 11, wherein forming the passivation layer (65) comprises:

[0133] depositing a passivation layer (65) on the semiconductor body (52), on the spacer region (62) and on the top surface of the gate region (57); and

[0134] The passivation layer (65) is selectively removed from the top surface of the gate region.

[0135] Example 13. The process of the preceding example, wherein selectively removing the passivation layer (65) comprises:

[0136] forming a first insulating layer (66) on the passivation layer (65);

[0137] forming a control opening (67) in the first insulating layer (66) above the gate region (57); and

[0138] removing the passivation layer (65) in the control opening (67);

[0139] The process also includes:

[0140] forming a control terminal (68) of conductive material on the gate region, the control terminal extending in the control opening (67);

[0141] forming a second insulating layer (69) on the first insulating layer (66) and the control terminal (68);

[0142] forming a first conductive opening (82) and a second conductive opening (83) through the first insulating layer and the second insulating layer (66, 69) laterally to the sealing region (61); and

[0143] First and second current conducting terminals (72, 73) of electrically conductive material are formed on and in contact with the semiconductor body (52) in first and second conducting openings (82, 83), respectively.

[0144] Example 14. The process of Example 12, further comprising:

[0145] forming a first insulating layer (66) on the passivation layer (65);

[0146] A first conductive opening (82') and a second conductive opening (83') are formed through the first insulating layer (66) laterally to the sealing region (62);

[0147] forming first and second current conducting terminals (72', 73') of electrically conductive material on and in contact with the semiconductor body (52) in the first and second conducting openings (82', 83'), respectively;

[0148] forming a second insulating layer (69) on the first insulating layer (66) and the first current conducting terminal and the second current conducting terminal (72', 73');

[0149] forming a control opening (67') through the first and second insulating layers (66, 69) over the gate region (57), wherein forming the control opening (67') comprises selectively removing the passivation layer (65); and

[0150] A control terminal (68') of electrically conductive material is formed on the gate region (57) and extends in the control opening (67').

[0151] Example 15. A process according to any one of Examples 9-14, wherein the sealing region (61) is made of a first insulating material, such as an oxide such as Al2O3, HfO2 and AlON, and the passivation region (65) is made of a second insulating material, such as AlN.

[0152] Embodiment 16. The process of any one of Examples 9-14, wherein the sealing region (61) and the passivation layer (65) have different thicknesses.

[0153] The HEMT device (50; 100) can be summarized as comprising: a semiconductor body (52) having a semiconductor heterostructure (54, 56); a gate region (57) comprising a semiconductor material and arranged on the semiconductor body (52), the gate region having a side surface; a sealing region (61) of a non-conductive material extending on and in contact with the side surface of the gate region (57); and a passivation layer (65) of a non-conductive material, the passivation layer having a surface portion (65A) extending on the semiconductor body (52), laterally and at a distance from the side surface of the gate region, the sealing region (61) and the passivation layer (65) having different geometric parameters and / or being made of different materials.

[0154] The HEMT device may also include: an insulating structure (66, 69) extending above the semiconductor body (52), laterally and on top of the gate region; a first current conducting terminal (72; 72') of conductive material extending on and in contact with the semiconductor body (52), laterally to one of the sides of the gate region (57), at least partially through the insulating structure (66, 69); a second current conducting terminal (73; 73') of conductive material extending on and in contact with the semiconductor body (52), laterally to the other side of the gate region (57), at least partially through the insulating structure (66, 69); and a control terminal (68; 68') of conductive material extending on and in contact with the gate region (57), at least partially through the insulating structure (66, 69).

[0155] The sealing area (61) may be made of an insulating material, for example an oxide such as Al2O3, HfO2 and AlON.

[0156] The sealing region (61) may have a thickness comprised between 2 nm and 10 nm, for example 2.5 nm.

[0157] The passivation layer (65) may be made of an insulating material, such as AlN.

[0158] The passivation region (65) may have a thickness comprised between 2 nm and 10 nm, for example 5 nm.

[0159] The passivation region (65) may have a greater thickness than the sealing region (61).

[0160] The HEMT device may also include a spacer region (62) of dielectric material extending laterally and in contact with the sealing region (62), and a passivation layer (65) having a raised portion (65B) extending on the spacer region (62), laterally and at a distance from the sealing region.

[0161] A process for manufacturing a HEMT device (50; 100), the process can be summarized as comprising: forming a gate region (57) on a semiconductor body (52) having a semiconductor heterostructure (54, 56), the gate region comprising a semiconductor material and arranged on the semiconductor body (52), the gate region having a side surface; forming a sealing region (61) of a non-conductive material on and in contact with the side surface of the gate region (57); and forming a passivation layer (65) of a non-conductive material, the passivation layer having a surface portion (65A) extending on the semiconductor body (52), laterally and at a distance from the side surface of the gate region, the sealing region (61) and the passivation layer (65) having different geometric parameters and / or being made of different materials.

[0162] Forming the sealing region (61) may include: forming a sealing layer (61) on the gate region (57) and on the semiconductor body (52); forming a spacer region (62) on the sealing layer and adjacent to the gate region; and selectively removing the sealing layer (61) exposed on the semiconductor body (52).

[0163] Selectively removing the sealing layer (61) may include using an etchant that is selective with respect to the semiconductor body (52).

[0164] Forming the passivation layer (65) may include: depositing the passivation layer (65) on the semiconductor body (52), on the spacer region (62), and on the top surface of the gate region (57); and selectively removing the passivation layer (65) from the top surface of the gate region.

[0165] Selectively removing the passivation layer (65) may include: forming a first insulating layer (66) on the passivation layer (65); forming a control opening (67) in the first insulating layer (66) above the gate region (57); and removing the passivation layer (65) in the control opening (67); the process may also include: forming a control terminal (68) of conductive material on the gate region, the control terminal extending in the control opening (67); forming a second insulating layer (69) on the first insulating layer (66) and the control terminal (68); forming a first conductive opening (82) and a second conductive opening (83) through the first and second insulating layers (66, 69) laterally to the sealing region (61); and forming a first current conducting terminal and a second current conducting terminal (72, 73) of conductive material on and in contact with the semiconductor body (52) in the first and second conductive openings (82, 83), respectively.

[0166] The process may also include: forming a first insulating layer (66) on the passivation layer (65); forming a first conduction opening (82') and a second conduction opening (83') through the first insulating layer (66) laterally to the sealing area (62); forming a first current conduction terminal and a second current conduction terminal (72', 73') of conductive material in the first conduction opening and the second conduction opening (82', 83') on and in contact with the semiconductor body (52); forming a second insulating layer (69) on the first insulating layer (66) and the first and second current conduction terminals (72', 73'); forming a control opening (67') through the first and second insulating layers (66, 69) above the gate area (57), wherein forming the control opening (67') may include selectively removing the passivation layer (65); and forming a control terminal (68') of conductive material on the gate area (57), the control terminal extending in the control opening (67').

[0167] The sealing region (61) may be made of a first insulating material, for example an oxide such as Al2O3, HfO2 and AlON, and the passivation region (65) is made of a second insulating material, such as AlN.

[0168] In an embodiment, a process for manufacturing a HEMT device includes: forming a gate region on a semiconductor body having a semiconductor heterostructure, the gate region including a semiconductor material and arranged on the semiconductor body, the gate region having multiple sides; forming multiple sealing regions of a first non-conductive material on and in contact with the multiple sides of the gate region, including: forming a sealing layer on the gate region and the semiconductor body; forming multiple spacer regions on the sealing layer and adjacent to the gate region; and selectively removing the sealing layer on the semiconductor body; and forming a passivation layer of a second non-conductive material, the passivation layer having a surface portion extending on the semiconductor body, laterally and at a distance from the multiple sides of the gate region, the multiple sealing regions having different geometric parameters from the passivation layer.

[0169] In some embodiments, forming the passivation layer is performed after selectively removing the sealing layer.

[0170] In some embodiments, selectively removing the sealing layer includes using an etchant that is selective with respect to the semiconductor body.

[0171] In some embodiments, forming the passivation layer includes: depositing the passivation layer on the semiconductor body, on the plurality of spacer regions, and on a top surface of the gate region; and selectively removing the passivation layer from the top surface of the gate region.

[0172] In some embodiments, selectively removing the passivation layer includes: forming a first insulating layer on the passivation layer; forming a control opening in the first insulating layer above the gate region; and removing the passivation layer in the control opening.

[0173] In some embodiments, the process also includes: forming a first insulating layer on the passivation layer; forming a first conduction opening and a second conduction opening through the first insulating layer, lateral to the multiple sealing areas; forming a first current conduction terminal and a second current conduction terminal in the first conduction opening and the second conduction opening respectively on the semiconductor body and in contact with the semiconductor body; forming a second insulating layer on the first insulating layer and on the first current conduction terminal and the second current conduction terminal; forming a control opening through the first insulating layer and the second insulating layer above the gate region, wherein forming the control opening includes the selective removal of the passivation layer; and forming a control terminal on the gate region, the control terminal extending in the control opening.

[0174] In some embodiments, the plurality of sealing regions are made of Al2O3, HfO2, or AlON, and the passivation region is made of AlN.

[0175] In some embodiments, the plurality of sealing regions are made of a first insulating material, and the passivation region is made of a second insulating material different from the first insulating material.

[0176] In some embodiments, the process also includes: forming a control terminal on the gate region, the control terminal extending in the control opening; forming a second insulating layer on the first insulating layer and on the control terminal; forming first and second conductive openings through the first and second insulating layers, lateral to the multiple sealing areas; and forming first and second current conductive terminals in the first and second conductive openings, respectively, on the semiconductor body and in contact with the semiconductor body.

[0177] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications, and publications to provide further embodiments.

[0178] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalent forms granted by these claims. Therefore, the claims are not limited by the present disclosure.

Claims

1. A HEMT device, characterized in that: include: A semiconductor body having a semiconductor heterostructure; a gate region on the semiconductor body, the gate region having a plurality of side surfaces; a plurality of sealing regions of a first non-conductive material extending over and contacting the plurality of sides of the gate region; as well as a passivation layer of a second non-conductive material having a surface portion extending over the semiconductor body laterally and at a distance from the side faces of the gate region, The plurality of sealing regions have different geometric parameters from the passivation layer; as well as A plurality of spacer regions extend laterally and contact the plurality of sealing regions, and the passivation layer has a raised portion extending on the plurality of spacer regions, laterally and at a distance from the plurality of sealing regions.

2. The HEMT device according to claim 1, further comprising: an insulating structure extending above the semiconductor body, laterally and on top of the gate region; The first non-conductive material and the second non-conductive material are different materials; a first current conducting terminal extending laterally to a first side of the plurality of side surfaces of the gate region on the semiconductor body and in contact with the semiconductor body, at least partially through the insulating structure; a second current conducting terminal extending laterally to a second side of the plurality of side surfaces of the gate region on the semiconductor body and in contact with the semiconductor body, at least partially through the insulating structure; as well as A control terminal extends over and contacts the gate region and at least partially passes through the insulating structure. The HEMT device according to claim 1 , wherein the sealing region is made of an insulating material. 4 . The HEMT device of claim 1 , wherein the plurality of sealing regions have a thickness between 2 nm and 10 nm. The HEMT device according to claim 1 , wherein the passivation layer is made of an insulating material.

6. The HEMT device of claim 1, wherein the passivation layer has a thickness between 2 nm and 10 nm. 7 . The HEMT device of claim 1 , wherein the passivation layer has a greater thickness than the plurality of sealing regions.

8. The HEMT device of claim 6, wherein the plurality of spacer regions are made of oxide.

9. A HEMT device, characterized in that: include: A semiconductor body having a semiconductor heterostructure; a gate region on the semiconductor body, the gate region having a plurality of side surfaces; a plurality of sealing regions of a first non-conductive material extending over and contacting the plurality of sides of the gate region; as well as a passivation layer of a second non-conductive material having a surface portion extending over the semiconductor body laterally and at a distance from the side faces of the gate region, The plurality of sealing regions and the passivation layer are made of different materials; as well as A plurality of spacer regions extend laterally and contact the plurality of sealing regions, and the passivation layer has a raised portion extending on the plurality of spacer regions, laterally and at a distance from the plurality of sealing regions.

10. The HEMT device according to claim 9, comprising: an insulating structure extending laterally over the semiconductor body and on top of the gate region; a first current conducting terminal extending laterally to a first side of the plurality of side surfaces of the gate region on the semiconductor body and in contact with the semiconductor body, at least partially through the insulating structure; a second current conducting terminal extending laterally to a second side of the plurality of side surfaces of the gate region on the semiconductor body and in contact with the semiconductor body, at least partially through the insulating structure; as well as A control terminal extends over and contacts the gate region and at least partially passes through the insulating structure. 11 . The HEMT device of claim 9 , wherein the plurality of sealing regions and the passivation layer have different geometric parameters.

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