Integrated circuit driver and integrated circuit

Abstract

An integrated circuit driver includes a cascode arrangement of first type transistors coupled in series with a cascode arrangement of second type transistors, the second type transistors being different from the first type transistors. Each splice arrangement includes: an active region extending in a first direction; a gate structure extending perpendicular to the first direction and overlying the active region at a position corresponding to the stacked transistors; first to fourth metal segments extending in a first direction in a first metal layer of the IC; a first via and a second via electrically coupling the corresponding first gate structure and second gate structure to the first metal segment and the second metal segment; the third through hole is used for electrically coupling the spliced source terminal to the third metal section; and the fourth through hole is used for electrically coupling the spliced drain terminal to the fourth metal section. The third metal segment and the fourth metal segment are aligned along the first direction.

Description

Technical Field

[0001] The embodiment of the utility model relates to an integrated circuit driver and an integrated circuit. Background Art

[0002] The trend toward continuous miniaturization of integrated circuits (ICs) has resulted in smaller and smaller devices that consume less power but provide more functionality at higher speeds than earlier technologies. This miniaturization is achieved through design and manufacturing innovations coupled with increasingly stringent specifications. Various electronic design automation (EDA) tools are used to generate, revise, and verify the design of semiconductor devices while ensuring that the IC structural design specifications and manufacturing specifications are met. Utility Model Content

[0003] The present invention provides an integrated circuit (IC) driver including a stacked arrangement of a first type of transistor coupled in series with a stacked arrangement of a second type of transistor, the second type of transistor being different from the first type of transistor. Each of the stacked arrangement of the first type of transistor and the stacked arrangement of the second type of transistor includes: an active region extending in a first direction; a plurality of gate structures extending in a second direction perpendicular to the first direction and overlying the active region at a position corresponding to the transistors of the stacked arrangement; a first metal segment, a second metal segment, a third metal segment, and a fourth metal segment extending in the first direction in a first metal layer of the IC; a first through hole and a second through hole configured to electrically couple a corresponding first gate structure and a corresponding second gate structure of the plurality of gate structures to the first metal segment and the second metal segment, respectively; a third through hole configured to electrically couple a source terminal of the stacked arrangement to the third metal segment; and a fourth through hole configured to electrically couple a drain terminal of the stacked arrangement to the fourth metal segment, wherein the third metal segment is aligned with the fourth metal segment along the first direction.

[0004] The present invention provides an integrated circuit (IC) including a stacked arrangement of transistors. The stacked arrangement of transistors includes: a first active region, a second active region, a third active region, and a fourth active region extending in a first direction; a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, a fifth gate structure, and a sixth gate structure extending in a second direction perpendicular to the first direction and overlying each of the first active region, the second active region, the third active region, and the fourth active region at a position corresponding to the stacked arrangement of transistors; a first metal segment, a second metal segment, and a third metal segment overlying the first gate structure, the second gate structure, the third gate structure , a first metal layer on the fourth gate structure, the fifth gate structure and the sixth gate structure extending in a first direction; a first plurality of aligned metal segments, a second plurality of aligned metal segments, a third plurality of aligned metal segments, a fourth plurality of aligned metal segments and a fifth plurality of aligned metal segments extending in a first direction in the first metal layer overlying the first gate structure, the second gate structure, the third gate structure, the fourth gate structure, the fifth gate structure and the sixth gate structure; a first through hole and a second through hole configured to electrically couple the first gate structure and the second gate structure to the first metal segment; a third through hole and a fourth through hole configured to electrically couple the first gate structure and the second gate structure to the first metal segment The third gate structure and the fourth gate structure are electrically coupled to the second metal segment; the fifth through hole and the sixth through hole are configured to electrically couple the fifth gate structure and the sixth gate structure to the third metal segment; the seventh through hole, the eighth through hole, the ninth through hole, the tenth through hole and the eleventh through hole are configured to electrically couple the first source terminal of the stacked arrangement to the first alignment metal segment in each of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments and the fifth plurality of alignment metal segments; the twelfth through hole, the thirteenth through hole, the fourteenth through hole, the fifteenth through hole and the sixteenth through hole are configured to electrically couple the first source terminal of the stacked arrangement to the first alignment metal segment in each of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments and the fifth plurality of alignment metal segments; a through hole configured to electrically couple the drain terminal of the stacked arrangement to the second alignment metal segment in each of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments, and the fifth plurality of alignment metal segments; and a seventeenth through hole, an eighteenth through hole, a nineteenth through hole, a twentieth through hole, and a twenty-first through hole configured to electrically couple the second source terminal of the stacked arrangement to the third alignment metal segment in each of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments, and the fifth plurality of alignment metal segments. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0006] Figure 1 is a diagram of an IC output circuit according to some embodiments.

[0007] Figure 2A is a schematic diagram of an IC driver device according to some embodiments.

[0008] Figure 2B is a diagram of an IC driver layout and an IC driver device according to some embodiments.

[0009] Figure 2C is a diagram of an IC driver layout and an IC driver device according to some embodiments.

[0010] Figure 2D is a diagram of an IC driver layout and an IC driver device according to some embodiments.

[0011] Figure 2E and Figure 2F is a plan view of an IC driver layout and an IC driver device according to some embodiments.

[0012] Figure 2G is a cross-sectional view of an IC driver layout and an IC driver device according to some embodiments.

[0013] FIG. 3A to FIG. 3D is a plan view of an IC layout diagram and a corresponding IC driver device according to some embodiments.

[0014] FIG. 4A to FIG. 4D is a plan view of an IC layout diagram and a corresponding IC driver device according to some embodiments.

[0015] Figure 5 is a flow chart of a method of manufacturing an IC driver device according to some embodiments.

[0016] Figure 6 is a flow chart of a method of generating an IC layout diagram according to some embodiments.

[0017] Figure 7 is a block diagram of an IC layout generation system according to some embodiments.

[0018] Figure 8 is a block diagram of an IC manufacturing system and an IC manufacturing flow associated with the IC manufacturing system according to some embodiments. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. The following describes specific examples of components, values, steps, operations, materials, arrangements or similar elements to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. It is expected that there are other components, values, operations, materials, arrangements or similar elements. For example, the following description may include an embodiment in which the first feature and the second feature are formed to be directly in contact with each other by forming a first feature on the second feature or on the second feature, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than the relationship between the various embodiments and / or configurations discussed by itself.

[0020] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another (other) element or feature as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0021] In various embodiments, an IC driver device based on an IC layout diagram includes an aligned first metal layer segment with a discontinuity (e.g., corresponding to a cut-metal region), whereby source terminals and drain terminals of a stacked transistor arrangement can be aligned along the discontinuous first metal segment. By including the aligned metal segment divided into source and drain connections, the stacked transistor arrangement can include a greater number of parallel connections than the stacked transistor arrangement in other approaches, thereby reducing back-end (BE) path resistance and improving speed performance, especially when included in a driver stage of an output circuit (e.g., an input / output (I / O) circuit based only on a core transistor of a manufacturing process).

[0022] As discussed below, Figure 1 is a schematic diagram of an output circuit including an embodiment of a driver circuit, Figure 2A is a schematic diagram of an embodiment of a cascaded transistor arrangement, and FIG. 2B to FIG. 4DEach of the drawings depicts a plan view and / or a cross-sectional view of a corresponding device / layout embodiment, wherein reference numerals denote both IC device features and IC layout features that are used in a manufacturing process (e.g., as described below for Figure 5 The method 500 discussed and / or in conjunction with the following Figure 8 In some embodiments, FIG. 2B to FIG. 4D One or more of the following is performed on Figure 6 Some or all of the operations of the method 600 discussed (e.g., using the following instructions for Figure 7 Some or all of the IC layouts generated by the system 700 discussed above. FIG. 2B to FIG. 4D Each of represents a plan view or a cross-sectional view of both an IC layout diagram and a corresponding IC device.

[0023] For illustrative purposes, the various figures herein (eg, FIG. 2B to FIG. 4D ) are simplified. The figures are views of IC structures and IC devices, including and excluding various features for the convenience of the following discussion. In various embodiments, except FIG. 2B to FIG. 4D In addition to the features illustrated, the IC structure, device and / or layout diagram also includes one or more features corresponding to power distribution structures, metal interconnects, contacts, through-holes, gate structures, source / drain (S / D) structures, block connections or other transistor elements, isolation structures or similar structures.

[0024] Figure 1 is a schematic diagram of an output circuit 100 according to some embodiments. The output circuit 100 (also referred to as circuit 100 or input / output (I / O) circuit 100 in some embodiments) is an integrated circuit (IC) including a driver 100D (also referred to as driver stage 100D or post-driver 100D in some embodiments) configured to output a signal OUT on an output node OUTP (also referred to as output terminal OUTP or output pad OUTP in some embodiments).

[0025] exist Figure 1In the embodiment shown in FIG. 1 , the circuit 100 includes logic circuits L1 to L3 and level shifters LS1 to LS3, power supply nodes VDD, VDDL and VDDPST configured to receive respective power supply voltages VDD, VDDL and VDDPST, and reference nodes VSS and VSSH configured to receive respective power supply voltages VDD and VSSH. In some embodiments, one or both of the power supply reference voltages VSS or VSSH have a voltage level of 0 volts (Volt, V) (e.g., a ground voltage level).

[0026] The logic circuit L1 is configured to receive a power supply voltage VDD, a power supply reference voltage VSS, and one or more input signals (not labeled). The level shifter LS1 is coupled to the logic circuit L1 and is configured to receive a power supply voltage VDDL, a power supply reference voltage VSS, and an output signal (not labeled) from the logic circuit L1. The level shifter LS2 is coupled to the level shifter LS1 in series with the logic circuit L2, and is configured to receive a power supply voltage VDDPST, a power supply reference voltage VSSH, and an output signal (not labeled) from the level shifter LS1 and output a gate control signal GP to the driver 100D. The level shifter LS3 is coupled to the logic circuit L1 in series with the logic circuit L3, and is configured to receive a power supply voltage VDDL, a power supply reference voltage VSS, and an output signal (not labeled) from the logic circuit L1 and output a gate control signal GN to the driver 100D.

[0027] The circuit 100 is thus configured to generate gate control signals GP and GN based on the one or more input signals and the voltage levels of the supply voltages VDD, VDDL, and VDDPST and the voltage levels of the supply reference voltages VSS and VSSH.

[0028] The power supply voltage VDD has a core voltage level corresponding to a core power domain of an IC including the circuit 100. In some embodiments, the circuit 100 includes only transistors (e.g., transistors P1, P2, N1, and N2 discussed below) that are configured to operate at the core voltage level and may be damaged by voltages higher than the core voltage level.

[0029] In some embodiments, each of the power supply voltages VDD, VDDL, and VDDPST has a core voltage level (e.g., 0.75 volts), each of the power supply reference voltages VSS and VSSH has a ground voltage level, and the circuit 100 is configured to output a signal OUT based on the core voltage level relative to ground.

[0030] In some embodiments, one or both of the power supply voltages VDDL or VDDPST have one or more voltage levels higher than the core voltage level (e.g., 0.75 volts and 1.2 volts, respectively), the power supply reference voltage VSSH has a voltage level higher than the voltage level of the power supply reference voltage VSS (e.g., ground) (e.g., 0.45 volts), and the circuit 100 is configured to output a signal OUT based on the voltage level of the power supply voltage VDDPST relative to the power supply reference voltage VSS.

[0031] The driver 100D includes a stacked arrangement of p-type metal-oxide-semiconductor (PMOS) transistors P1 and P2 coupled between a power supply node VDDPST and an output node OUTP and configured to receive a gate control signal GP, and a stacked arrangement of n-type metal-oxide-semiconductor (NMOS) transistors N1 and N2 coupled between the output node OUTP and a reference node VSS and configured to receive a gate control signal GN. Each of the stacked transistor arrangements of the driver 100D includes the following for FIG. 2A to FIG. 4D One of the IC driver devices 200 - 400D (also referred to as IC drivers 200 - 400D in some embodiments) is discussed.

[0032] Figure 1 The configuration of the circuit 100 including the driver 100D shown in FIG. 1 (including two PMOS transistors P1 and P2 as first type transistors and two NMOS transistors N1 and N2 as second type transistors) is a non-limiting example provided for illustration purposes. In various embodiments, the circuit 100 includes the driver 100D, the driver 100D includes more than two PMOS transistors P1 and P2 and more than two NMOS transistors N1 and N2, and the logic circuits L2 and L3 are configured to output corresponding numbers of gate control signals GP and GN, respectively.

[0033] In some embodiments, circuit 100 includes a driver 100D, which includes a first type transistor different from a PMOS transistor (e.g., a p-type transistor different from a PMOS transistor or an NMOS transistor) and / or a second type transistor different from an NMOS transistor (e.g., an n-type transistor different from an NMOS transistor or a PMOS transistor).

[0034] In various embodiments, circuit 100 includes power supply nodes, reference nodes, logic circuits, level shifters, and / or additional circuits that are otherwise configured to output gate control signals GP and GN to driver 100D.

[0035] By including a driver 100D including a cascaded transistor arrangement that includes an instance of the IC driver devices 200 to 400D, the circuit 100 is able to achieve the benefits of the IC driver devices 200 to 400D discussed below.

[0036] Figure 2A is a schematic diagram of an IC driver device 200 according to some embodiments; Figure 2B A plan view of a corresponding device / layout diagram of an IC driver device 200 (also referred to as IC layout diagram 200 or IC layout / IC device 200 ) is depicted; Figure 2C and Figure 2D depicts plan views of IC layouts / IC devices 200 - 1 and 200 - 2 , which are non-limiting examples of IC layouts / IC devices 200 ; and Figure 2E to Figure 2G Depicted are a plan view and corresponding cross-sectional views of an embodiment of an IC layout / IC device 200 in accordance with some embodiments.

[0037] Each of the IC layouts / IC devices 200, 200-1, and 200-2 corresponds to a stacked arrangement of transistors that can be included in the driver 100D of the circuit 100 discussed above. Each transistor in the stacked arrangement of transistors includes a parallel configuration of multiple transistor implementations, each implementation including at least two active area portions intersecting with a corresponding gate structure (discussed below).

[0038] like Figure 2A , the IC driver device 200 includes a stacked arrangement of a total of x transistors T1 to Tx coupled between a node NS and a node ND (also referred to as a source node NS and a drain node ND in some embodiments), and the transistors T1 to Tx include corresponding gate regions / gate structures G1 to Gx configured to receive corresponding gate control signals G1 to Gx. In various embodiments, the IC driver device 200 includes a total number of transistors x=2, 3, or more.

[0039] The transistor T1 (and thus the cascaded arrangement of transistors T1 to Tx) includes one or more source terminals electrically coupled to the node NS. The transistor Tx (and thus the cascaded arrangement of transistors T1 to Tx) includes one or more drain terminals electrically coupled to the node ND.

[0040] In some embodiments, the transistors T1 to Tx including the gate regions / gate structures G1 to Gx configured to receive the gate control signals G1 to Gx include PMOS transistors (e.g., transistors P1 and P2 configured to receive the gate control signal GP), the node NS corresponds to a power supply voltage node (e.g., the power supply voltage node VDDPST), and the node ND corresponds to an output node (e.g., the output node OUTP), the transistors and the nodes are each described above with respect to Figure 1 Discuss.

[0041] In some embodiments, the transistors T1 to Tx including the gate regions / gate structures G1 to Gx configured to receive the gate control signals G1 to Gx include NMOS transistors (e.g., transistors N1 and N2 configured to receive the gate control signals GN), the node NS corresponds to a power reference node (e.g., a reference node VSS), and the node ND corresponds to an output node (e.g., an output node OUTP), the transistors and the nodes are each described above with respect to Figure 1 Discuss.

[0042] FIG. 2B to FIG. 2F Each of the diagrams depicts a plan view of features of various embodiments of the IC layout / IC device 200 along the X-direction and the Y-direction. FIG. 2B to FIG. 2D In the embodiment illustrated in , the IC layout / IC device 200 includes one or more instances of metal regions / metal segments MS and / or instances of active regions / active areas AA, wherein the metal regions / metal segments MS and the active regions / active areas AA each extend in the X direction and are aligned with another of the one or more instances of metal regions / metal segments MS and / or instances of active regions / active areas AA along the Y direction, as discussed below.

[0043] In some embodiments, Figure 2E As shown in FIG. 2B to FIG. 2D The examples of metal regions / metal segments MS shown in FIG. 1 are separated into examples of metal portions MP by examples of metal cut regions CM. In some embodiments, FIG. 2B to FIG. 2D The examples of metal regions / metal segments MS illustrated in FIG. 1 correspond to multiple individually defined metal regions / metal segments (denoted as metal regions / metal segments MP) separated by spaces (greater than or equal to the minimum spacing rule distance) rather than examples of metal cut regions CM, as shown in FIG. Figure 2F as shown in . Figure 2E and Figure 2F Each of the plan views shown in Figure 2G The cross-sectional view shown in .

[0044] like Figures 2B to 2GAs shown in FIG. 2 , the IC layout / IC device 200 also includes instances of via regions / via structures VS, VD, and VG (also referred to as source terminal vias VS, drain terminal vias VD, and gate vias VG in some embodiments), instances of gate regions / gate structures G1 to Gx and GS, and instances of metal-like defined (MD) regions / MD segments MDS1, MDS2, MDD, and MD. In some embodiments, the MD regions / MD segments MDS1, MDS2, and MDD are referred to as source terminals MDS1 and MDS2, and drain terminal MDD, respectively.

[0045] In some embodiments, the IC layout / IC device 200 includes Figures 2B to 2G Various features other than those shown in FIG. 1, such as one or more power rails or other metal interconnects, one or more additional instances of metal regions / segments MS, and / or active regions / areas AA (e.g., as described below for FIG. 3A to FIG. 4D One or more examples of active areas / regions AA1 to AA4) are discussed.

[0046] An active area / region (e.g., active area / region AA or AA1 to AA4) is a region included in the manufacturing process as part of defining active areas in a semiconductor substrate (also referred to as oxide diffusion OD or oxide definition OD) in an IC layout diagram, the semiconductor substrate being directly located or located in an n-well region / n-well region or a p-well region / p-well region (not shown for clarity) in which one or more IC device features (e.g., S / D structures) are formed. In some embodiments, the active region is an n-type active region or a p-type active region of a planar transistor, a fin field-effect transistor (FinFET), or a gate-all-around (GAA) transistor. In various embodiments, the active region (active structure) includes one or more of a semiconductor material (e.g., silicon (Si), silicon-germanium (SiGe), silicon carbide (SIC), or similar materials), a dopant material (e.g., boron (B), phosphorus (P), arsenic (As), gallium (Ga)), or another suitable material.

[0047] In some embodiments, the active area is a region that is included in the manufacturing process as part of defining a nanosheet structure (e.g., a continuous volume of one or more layers of one or more semiconductor materials having n-type or p-type doping) in an IC layout. In various embodiments, individual nanosheet layers include a single monolayer or multiple monolayers of a given semiconductor material.

[0048] An MD region / segment (e.g., region / segment MDS1, MDS2, MDD, or MD) is a conductive region included in the manufacturing process as part of defining an MD segment (also referred to as a conductive segment or MD conductive line or conductive trace) in and / or on a semiconductor substrate in an IC layout. In some embodiments, the MD segment includes a portion of at least one metal layer (e.g., a contact layer) that overlies and contacts the substrate and has a sufficiently small thickness to enable an insulating layer to be formed between the MD segment and an overlying metal layer (e.g., a first metal layer). In various embodiments, the MD segment includes one or more of copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or another metal or material suitable for providing a low-resistance electrical connection (i.e., a resistance level below a predetermined threshold value, the predetermined threshold value corresponding to one or more tolerance levels of resistance-based effects on circuit performance) between IC structural elements.

[0049] In various embodiments, the MD segment includes a segment of a semiconductor substrate and / or an epitaxial layer, the segment having a doping level sufficient to make the segment have a low resistance level, for example, based on an implantation process. In various embodiments, the doped MD segment includes a doping concentration of about 1*10 16 per cubic centimeter (cm -3 ) or greater than 1*10 16 One or more dopant materials per cubic centimeter.

[0050] In some embodiments, a manufacturing process includes two MD layers, and an MD zone / MD segment refers to one or both of the two MD layers in the manufacturing process.

[0051] In some embodiments, the location where the MD region / MD segment overlaps the active region / active area corresponds to the S / D region / S / D structure of the transistor including the corresponding active region / active area and the relevant portion of the MD region / MD segment.

[0052] A gate region / gate structure (e.g., gate region / gate structure G1 to Gx or GS) is an area in an IC layout diagram that is included in the manufacturing process as part of defining a gate structure. A gate structure is a volume that includes one or more conductive segments (e.g., a gate electrode) comprising one or more conductive materials (e.g., polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials) substantially surrounded by one or more insulating materials, whereby the one or more conductive segments are configured to control a voltage provided to an adjacent gate dielectric layer.

[0053] A dielectric layer (e.g., a gate dielectric layer) is a volume comprising one or more insulating materials (e.g., silicon dioxide, silicon nitride (Si3N4)) and / or one or more other suitable materials (e.g., a low dielectric constant material having a dielectric constant value (k value) less than 3.8 or a high dielectric constant material having a dielectric constant value greater than 3.8 or 7.0 (e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), or titanium oxide (TiO2))), which is suitable for providing high resistance (i.e., a resistance level above a predetermined threshold value, the predetermined threshold value corresponding to one or more tolerance levels based on the effect of resistance on circuit performance) between IC structural elements.

[0054] A metal region / metal segment (e.g., metal region / metal segment MS) is a region included in a manufacturing process as part of defining a metal segment structure in an IC layout diagram, wherein the metal segment structure includes one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials in a given metal layer of the manufacturing process. In various embodiments, the metal region / metal segment corresponds to the first metal layer (also referred to as metal zero layer in some embodiments) or the second metal layer or higher metal layer of the manufacturing process.

[0055] A metal cut region (eg, metal cut region CM) is a region included in the manufacturing process as part of defining a break in a given metal segment in an IC layout diagram, thereby electrically isolating corresponding adjacent metal segment portions (eg, metal portions MP) from each other.

[0056] A via region / via structure (e.g., via region / via structure VS, VD, or VG) is a region in an IC layout diagram that is included in the manufacturing process as part of defining a via structure comprising one or more conductive materials that are configured to provide an electrical connection between an overlying conductive structure (e.g., metal segment MS) and an underlying conductive structure. The underlying conductive structure corresponds to an MD segment or S / D structure in the case of a via region / via structure VS or VD and corresponds to a gate electrode in the case of a via region / via structure VG.

[0057] Each via region / via structure VS is included in an electrical connection (not shown for clarity) between an underlying MD region / MD segment corresponding to a source terminal of the stacked arrangement and a node NS, and each via region / via structure VD is included in an electrical connection (not shown for clarity) between an underlying MD region / MD segment corresponding to a drain terminal of the stacked arrangement and a node ND. In some embodiments, the electrical connection includes one or more via regions / via structures and one or more metal regions / metal segments, the metal regions / metal segments overlapping or overlying the corresponding via region / via structure VS or VD.

[0058] like Figure 2B As shown in the figure, an instance of the through-hole region / through-hole structure VS is aligned with the MD region / MD segment MDS1 in the Y direction, which indicates an electrical connection between the instance of the through-hole region / through-hole structure VS and the MD region / MD segment MDS1, an instance of the through-hole region / through-hole structure VD is aligned with the MD region / MD segment MDD in the Y direction, which indicates an electrical connection between the instance of the through-hole region / through-hole structure VD and the MD region / MD segment MDD, and an instance of the through-hole region / through-hole structure VS is aligned with the MD region / MD segment MDS2 in the Y direction, which indicates an electrical connection between the instance of the through-hole region / through-hole structure VS and the MD region / MD segment MDS2.

[0059] In various embodiments, an instance of a via region / via structure is located at a position overlapping / overlying the active region / active area AA or offset relative to the active region / active area AA in the Y direction (e.g., relative to another active region / active area (not in the Y direction) corresponding to a parallel transistor configuration). Figure 2B ) overlaps / overlies the other active region / active area) and is electrically connected to the corresponding MD region / MD segment, the other active region / active area being, for example, the following for FIG. 3A to FIG. 4D The active areas / regions AA1 to AA4 are discussed.

[0060] Figures 2A to 2GThe number of via regions / via structures VS and VD, the number of corresponding MD regions / MD segments MDS1, MDD and MDS2, and the number of active regions / active areas AA shown in the figure are non-limiting examples provided for illustrative purposes. Other numbers of corresponding features are also within the scope of the present disclosure.

[0061] exist Figure 2B In the embodiment illustrated in , an instance of each of the gate regions / gate structures G1 to Gx and a corresponding instance of the MD regions / MD segments (not labeled for clarity) intersects the active region / active area AA between the MD regions / MD segments MDD (the drain terminal of the stacked arrangement of the transistor) and each of the MD regions / MD segments MDS1 and MDS2 (the source terminals of the stacked arrangement of the transistor). In some embodiments, one or more additional instances of each of the gate regions / gate structures G1 to Gx and a corresponding instance of the MD regions / MD segments intersects the active region / active area AA between the MD regions / MD segments MDS1 and / or MDS2 and / or other MD regions / MD segments that are configured as additional drain terminals and / or additional source terminals of the stacked arrangement of the transistor.

[0062] exist Figure 2B In the embodiments illustrated in FIG. 1 , a single instance of a source terminal or a drain terminal (e.g., an MD region / segment MDS1, MDS2, or MDD) corresponds to a single instance of a corresponding via region / via structure VS or VD. FIG. 3A to FIG. 4D In the discussed IC layouts / IC devices 300A to 400D), a single instance of a source terminal or a drain terminal corresponds to multiple instances of corresponding via regions / via structures VS or VD electrically connected in parallel between the corresponding source terminal or drain terminal and the node NS or ND.

[0063] like Figure 2B As shown in FIG. 1 , instances of via regions / via structures VS and VD are located along metal regions / metal segments MS at positions corresponding to respective instances of source and drain terminals (e.g., MD regions / MD segments MDS1, MDS2, and MDD) in the X direction. Between each of the positions, the metal region / metal segment MS is separated into two or more metal portions MP by one or more metal cut regions CM, the number of metal portions MP being one more than the number of metal cut regions CM.

[0064] exist Figures 2A to 2GIn the embodiment shown in FIG. 2 , the metal region / metal segment MS is located in the first metal layer of the manufacturing process for forming the IC device 200, and the metal cutting area CM corresponds to the first metal layer. In some embodiments, the metal region / metal segment MS is referred to as the metal zero region / metal zero segment MS, and the metal cutting area CM is referred to as the metal cutting zero area CM.

[0065] In some embodiments, FIG. 2B to FIG. 2E and FIG. 3A to FIG. 4D As shown in FIG. 1 , the corresponding IC layout diagram includes each metal cut region CM corresponding to a break in a metal segment (eg, metal segment MS), so that adjacent metal portions (eg, metal portion MP) in the corresponding IC device are aligned in the X direction and electrically isolated from each other.

[0066] In some embodiments, FIG. 2B to FIG. 2D , Figure 2F and FIG. 3A to FIG. 4D A given metal segment depicted in represents two or more electrically isolated metal regions / metal segments (e.g., metal regions / metal segments MP) in the corresponding layout diagram / device, the two or more electrically isolated metal regions / metal segments being aligned in the X direction and separated by interruptions other than metal cut regions (e.g., natural ends of metal regions / metal segments based on metal regions that at least partially define a discontinuous portion of the given metal segment). In such an embodiment, the corresponding IC layout diagram does not include instances of metal cut regions CM, and references to metal portions (e.g., metal portions MP) in the following discussion correspond to instances of metal regions / metal segments (e.g., metal regions / metal segments MP).

[0067] exist Figure 2B In the embodiment depicted in FIG, the metal region / metal segment MS is divided into a total of four metal portions MP corresponding to three metal cut regions CM (or other interruptions) between instances of the via region / via structure VS and VD. In various embodiments, the metal region / metal segment MS is divided into a total of less than four or more than four metal portions MP based on a corresponding number of less than one metal cut regions CM (or other interruptions) between instances of the via region / via structure VS and VD.

[0068] A given metal portion MP located between metal cut regions CM (or other interruptions) and not electrically connected to a source terminal or a drain terminal is configured to be electrically isolated from other IC features in addition to being electrically isolated from adjacent metal portions MP and is thus configured to be electrically floating. Therefore, the total number N-1 of floating metal portions MP between instances of via regions / via structures VS and VD is one less than the total number N of metal cut regions CM (or other interruptions) between instances of via regions / via structures VS and VD.

[0069] For a given dielectric material positioned between adjacent metal portions MP, the maximum difference in corresponding voltage levels depends on the width C of the corresponding metal cut region CM (or other discontinuity). The overall maximum difference in node NS / ND voltages further depends on the total number N-1 of floating metal portions MP between instances of via regions / via structures VS and VD, such that the maximum difference in node NS / ND voltage differences increases as the number N-1 of floating metal portions MP increases.

[0070] As the value of width C increases, the maximum difference in the corresponding voltage level that can be sustained over width C also increases. In some embodiments, width C corresponds to metal cut area CM and has a value in the range of 3 nanometers (nm) to 30 nanometers. In some embodiments, width C corresponds to metal cut area CM and has a value in the range of 5 nanometers to 20 nanometers. In some embodiments, width C corresponds to the natural end of metal portion MP and has a value in the range of 30 nanometers to 75 nanometers. In some embodiments, width C corresponds to the natural end of metal portion MP and has a value in the range of 35 nanometers to 60 nanometers.

[0071] The distance between the via region / via structure VS and the via region / via structure VD depends on the total number x of transistors T1 to Tx, and thus depends on the gate regions / gate structures G1 to Gx and the contact poly-pitch (cpp) (the distance between the centers of adjacent gate regions / gate structures G1 to Gx). Along the X direction, the metal portion MP electrically connected to the via region / via structure VD has a width A, the metal portion MP electrically connected to the via region / via structure VS has a width B, the metal cut region CM (or other interruption) has a width C, and the floating metal portion MP has a width F. In various embodiments, each of the widths A, B, and F has the same value, one of the widths A, B, or F has a value different from the value of the other of the widths A, B, or F, or each of the widths A, B, and F has a unique value.

[0072] For embodiments in which the total number x of transistors is greater than or equal to two, Figure 2B The distance between the centers of adjacent instances of the via region / via structure VS depicted in FIG. 1 is given by the following equation:

[0073] 2*cpp*x = A+ B + 2*N*C + 2*(N - 1)*F (1)

[0074] In some embodiments, it is thus possible to determine the value of the total number N of metal cutting areas CM (or other interruptions) positioned between instances of via areas / via structures VS and VD based on the overall maximum difference in node NS / ND voltages, the number x of transistors T1 to Tx in the stacked arrangement, and the size and spacing design rules of the manufacturing process used to form the IC layout / IC device 200.

[0075] Figure 2C A non-limiting example of an IC layout / IC device 200 (IC layout / IC device 200-1) is depicted in which the distance C is large enough to be able to maintain the entire maximum node VS / VD voltage difference, so that the total number N of metal cut regions CM (or other interruptions) between instances of via regions / via structures VS and VD is equal to 1. Therefore, the IC layout / IC device 200-1 does not include a floating metal portion MP, and the distance between the entrances of adjacent instances of via regions / via structures VS is given by the following equation

[0076] 2*cpp*x = A+ B + 2*C (2)

[0077] Figure 2D A non-limiting example (IC layout / IC device 200-2) of the IC layout / IC device 200 is depicted, wherein the distance C is not large enough to be able to maintain the overall maximum node VS / VD voltage difference, but is large enough so that the total number N of metal cut regions CM (or other interruptions) between the instance via regions / via structures VS and VD is equal to 2 to be able to maintain the overall maximum node VS / VD voltage difference. Thus, the IC layout / IC device 200-2 includes a single instance of a floating metal portion MP between adjacent via regions / via structures VS and via regions / via structures VD, and the distance between the entrances of adjacent instances of via regions / via structures VS is given by the following equation

[0078] 2*cpp*x = A+ B + 4*C + 2*F (3)

[0079] Figure 2C and Figure 2D Each of the gate regions / gate structures G1 (in Figure 2A and Figure 2B2 ). The four instances of via regions / via structures VG are aligned along the metal regions / metal segments MS in the X direction, with a first pair of via regions / via structures VG proximate to a first instance of via regions / via structures VS and a second pair of via regions / via structures VG proximate to a second instance of via regions / via structures VS. Two instances of metal cut regions CM (or other interruptions) are positioned between the two pairs of via regions / via structures VG, such that a single instance of a floating metal portion MP is positioned proximate to an instance of a via region / via structure VD between the two pairs of via regions / via structures VG.

[0080] By including such a floating metal portion MP, Figure 2C and Figure 2D The instances of the metal region / metal segment MS shown in the figure can be positioned adjacent to each other so that the difference between the voltage on the metal portion MP corresponding to the via region / via structure VD and the voltage on the metal portion MP corresponding to the via region / via structure VG can exceed the value of the whole based on the second instance of the metal region / metal segment MS electrically connected to the via region / via structure VG.

[0081] Figure 2C and Figure 2D The embodiment of the second instance of the metal region / metal segment MS depicted in is a non-limiting example provided for illustration purposes. In some embodiments, more than two instances of the metal cut region CM (or other interruption) are positioned between the two pairs of via regions / via structures VG, such that two or more corresponding instances of the floating metal portion MP are positioned between the two pairs of via regions / via structures VG. In some embodiments, an instance of the metal cut region CM (or other interruption) is positioned between a single instance of the via region / via structure VG. In some embodiments, the second instance of the metal region / metal segment MS corresponds to one of the gate regions / gate structures G2 to Gx.

[0082] Figure 2E and Figure 2F Each of which depicts a plan view, and Figure 2GA non-limiting representative subset of features of the IC layout / IC device 200 provided for illustration purposes is depicted with associated cross-sectional views along line PP' (including X and Z directions). Each of the plan view and cross-sectional view includes an active area / active region AA, an instance of a gate region / gate structure GS and an MD region / MD structure MD overlapping / overlying the active area / active region AA, an instance of a via region / via structure VD overlapping / overlying the instance of the MD region / MD structure MD, and an instance of a metal portion MP or metal region / metal segment MP (metal region / metal segment MP of an instance of a metal region / metal segment MS) overlapping / overlying the instance of the via region / via structure VD.

[0083] exist Figure 2E In the embodiment illustrated in FIG. 1 , an instance of metal portion MP corresponds to a single instance of metal cut region CM having width C that intersects an instance of metal region / segment MS. Figure 2F In the embodiment depicted in FIG. 1 , the example of metal region / metal segment MP corresponds to a break in metal region / metal segment MS without metal cut region CM and having width C. Figure 2E and Figure 2F Each of these corresponds to Figure 2G The metal portions MP or metal regions / segments MP depicted in the cross-sectional view are electrically isolated and aligned along the X-direction.

[0084] Through the configuration discussed above (in which one or more metal cutting areas CM (or other interruptions) are positioned in the metal segment MS between instances of the through-hole area / through-hole structure VS and VD), the metal portions MP corresponding to the through-hole structure VS adjacent to the through-hole structure VD are electrically isolated from each other, thereby enabling the through-hole area / through-hole structure VS and VD to be included in the electrical connection of the node NS and the node ND configured to carry different voltage levels.

[0085] The single metal segment MS including both source and drain electrical connections enables the stacked arrangement of transistors of the IC layout / IC device 200 to include a greater number of parallel source and drain electrical connections for a given circuit area, compared to an approach in which the single metal segment does not include both source and drain electrical connections, thereby reducing back-end (BE) source and drain path resistances and improving speed performance, especially when the stacked transistor arrangement is included in a driver stage of an output circuit (e.g., an input / output (I / O) circuit based on core transistors of a manufacturing process alone).

[0086] FIG. 3A to FIG. 4D4 is a plan view of a corresponding IC layout diagram and a corresponding IC driver device 300A to 400D (also referred to as IC layout / IC device 300A to 400D) according to some embodiments. Each IC layout / IC device 300A to 400D corresponds to the above Figures 2A to 2G The embodiment of the IC layout / IC device 200 discussed herein includes a stacked arrangement of three transistors T1 to T3 (for clarity, the transistors T1 to T3 are shown in FIG. FIG. 3A to FIG. 4D (not marked in the figure).

[0087] FIG. 3A to FIG. 3D The embodiment shown in FIG. 1 corresponds to the embodiment shown in FIG. Figure 2C The IC layout / IC device 200-1 discussed above, and FIG. 4A to FIG. 4D The embodiment shown in FIG. 1 corresponds to the embodiment shown in FIG. Figure 2D An IC layout / IC device 200 - 2 is discussed.

[0088] Each of the IC layouts / IC devices 300A-400D includes instances of each of the active areas / active regions AA1-AA4, MD regions / MD segments MD1-MD7, gate regions / gate structures G1A-G3A and G1B-G3B, metal regions / metal segments M1-M15, via regions / via structures VS, VD, and VG (representative instances labeled for clarity), and instances of metal cut regions CM (representative instances labeled for clarity). Portions of the metal regions / metal segments M1-M15 positioned between instances of the metal cut regions CM correspond to instances of metal portions MP and are not labeled for clarity. In some embodiments, one or more of the IC layouts 300A-400D do not include one or more of the metal cut region CM instances, and corresponding portions of the metal regions / metal segments M1-M15 correspond to one or more separately defined metal regions / metal segments (e.g., as described above for Figure 2F and Figure 2G The metal region / metal segment in question).

[0089] exist FIG. 3A to FIG. 4D In each of the embodiments illustrated in , transistor T1 includes eight parallel transistor implementations corresponding to the intersection of gate regions / gate structures G1A and G1B and each of active regions / active areas AA1 to AA4, transistor T2 includes eight parallel transistor implementations corresponding to the intersection of gate regions / gate structures G2A and G2B and each of active regions / active areas AA1 to AA4, and transistor T3 includes eight parallel transistor implementations corresponding to the intersection of gate regions / gate structures G3A and G3B and each of active regions / active areas AA1 to AA4. MD regions / MD segments MD1, MD4, and MD7 correspond to respective first source terminals, drain terminals, and second source terminals of the stacked arrangement of transistors T1 to T3.

[0090] According to IC layout / IC device 200-1, IC layout / IC devices 300A to 300D include a single instance of a metal cut region CM (or other interruption) between a via region / via structure VD corresponding to the drain terminal and a via region / via structure VS corresponding to the first and second source terminals.

[0091] According to the IC layout / IC device 200-2, the IC layout / IC device 400A to 400D includes two instances of a metal cut region CM (or other interruption) between each via region / via structure VD corresponding to the drain terminal and the corresponding via region / via structure VS corresponding to the first source terminal and the second source terminal, thereby defining an instance of a floating metal portion MP between each of the two instances of the metal cut region CM (or other interruption).

[0092] Each of the IC layout devices 300A and 400A includes: an instance of a via region / via structure VS configured to electrically connect each of the MD regions / MD segments MD1 and MD7 to each of a total of five metal regions / metal segments M3, M6, M8, M10, and M13 as a portion of a source terminal connection; an instance of a via region / via structure VD configured to electrically connect the MD region / MD segment MD4 to each of the metal regions / metal segments M3, M6, M8, M10, and M13 as a portion of a drain terminal connection; an instance of a via region / via structure VG, An instance of a via region / via structure VG configured to electrically connect each of the gate regions / gate structures G1A and G1B to the metal region / metal segment M15 as a portion of the gate connection portion of transistor T1; an instance of a via region / via structure VG configured to electrically connect each of the gate regions / gate structures G2A and G2B to the metal region / metal segment M1 as a portion of the gate connection portion of transistor T2; and an instance of a via region / via structure VG configured to electrically connect each of the gate regions / gate structures G3A and G3B to the metal region / metal segment M4 as a portion of the gate connection portion of transistor T3.

[0093] Each of the IC layout devices 300B and 400B includes: an instance of a via region / via structure VS configured to electrically connect each of the MD regions / MD segments MD1 and MD7 to each of a total of five metal regions / metal segments M2, M6, M8, M10, and M14 as a portion of a source terminal connection; an instance of a via region / via structure VD configured to electrically connect the MD region / MD segment MD4 to each of the metal regions / metal segments M2, M6, M8, M10, and M14 as a portion of a drain terminal connection; an instance of a via region / via structure VG, An instance of a via region / via structure VG configured to electrically connect each of the gate regions / gate structures G1A and G1B to the metal region / metal segment M12 as a portion of the gate connection portion of transistor T1; an instance of a via region / via structure VG configured to electrically connect each of the gate regions / gate structures G2A and G2B to the metal region / metal segment M4 as a portion of the gate connection portion of transistor T2; and an instance of a via region / via structure VG configured to electrically connect each of the gate regions / gate structures G3A and G3B to the metal region / metal segment M1 as a portion of the gate connection portion of transistor T3.

[0094] Each of the IC layout devices 300C and 400C includes: an instance of a via region / via structure VS configured to electrically connect each of the MD regions / MD segments MD1 and MD7 to each of a total of six metal regions / metal segments M4, M6, M8, M10, M12, and M14 as a portion of a source terminal connection; an instance of a via region / via structure VD configured to electrically connect the MD region / MD segment MD4 to each of the metal regions / metal segments M4, M6, M8, M10, M12, and M14 as a portion of a drain terminal connection; and a via region / via structure VD configured to electrically connect the MD region / MD segment MD4 to each of the metal regions / metal segments M4, M6, M8, M10, M12, and M14 as a portion of a drain terminal connection. An instance of G is configured to electrically connect each of the gate region / gate structure G1A and G1B to the metal region / metal segment M1 as a part of the gate connection portion of transistor T1; an instance of the through-hole region / via structure VG is configured to electrically connect each of the gate region / gate structure G2A and G2B to the metal region / metal segment M2 as a part of the gate connection portion of transistor T2; an instance of the through-hole region / via structure VG is configured to electrically connect each of the gate region / gate structure G3A and G3B to the metal region / metal segment M3 as a part of the gate connection portion of transistor T3.

[0095] Each of the IC layout devices 300D and 400D includes: an instance of a via region / via structure VS configured to electrically connect each of the MD regions / MD segments MD1 and MD7 to each of a total of six metal regions / metal segments M3, M5, M7, M9, M11, and M13 as a portion of a source terminal connection; an instance of a via region / via structure VD configured to electrically connect the MD region / MD segment MD4 to each of the metal regions / metal segments M3, M5, M7, M9, M11, and M13 as a portion of a drain terminal connection; and an instance of a via region / via structure VG configured to electrically connect the MD region / MD segment MD4 to each of the metal regions / metal segments M3, M5, M7, M9, M11, and M13 as a portion of a drain terminal connection. An example of a through-hole region / via structure VG, configured to electrically connect each of the gate regions / gate structures G1A and G1B to the metal region / metal segment M15 as a portion of the gate connection portion of transistor T1; an example of a through-hole region / via structure VG, configured to electrically connect each of the gate regions / gate structures G2A and G2B to the metal region / metal segment M1 as a portion of the gate connection portion of transistor T2; and an example of a through-hole region / via structure VG, configured to electrically connect each of the gate regions / gate structures G3A and G3B to the metal region / metal segment M2 as a portion of the gate connection portion of transistor T3.

[0096] IC layouts / IC devices 300A-400D corresponding to IC layouts / IC devices 200-1 and 200-2 are non-limiting examples provided for illustration purposes. Other stacked transistor arrangements according to IC layouts / IC devices 200-1 and 200-2 are also within the scope of the present disclosure.

[0097] By including the source and drain connections along a single instance of metal regions / metal segments M1 to M15 discussed above, each of IC layouts / IC devices 300A to 400D is able to achieve the benefits discussed above for IC layout / IC device 200 including IC layouts / IC devices 200-1 and 200-2.

[0098] Figure 5 is a flow chart of a method 500 for manufacturing an IC device according to some embodiments. The method 500 may be operated to form the above FIG. 2A to FIG. 4D One or more of the IC devices 200, 200-1, 200-2, or 300A-400D are discussed.

[0099] In some embodiments, Figure 5 The operations of method 500 are performed in the order shown in FIG. Figure 5In some embodiments, the operations of method 500 may be performed in an order different from the order depicted in FIG. 8 . In some embodiments, one or more additional operations are performed before, during, and / or after the operations of method 500. In some embodiments, performing some or all of the operations of method 500 includes performing the following steps for IC manufacturing system 800 and Figure 8 One or more operations are discussed.

[0100] At operation 510, in some embodiments, MD segments and gate structures are formed overlying the active area, the MD segments corresponding to first and second source terminals and drain terminals of the stacked transistor arrangement, and the gate structures corresponding to gates of the transistors. In some embodiments, forming the MD segments and gate structures overlying the active area includes forming MD segments MDS1, MDD, and MDS2 overlying the active area AA, as described above for Figures 2A to 2G In some embodiments, forming MD segments and gate structures overlying active areas includes forming MD segments MD1 to MD7 overlying active areas AA1 to AA4, as described above with respect to FIG. 3A to FIG. 4D Discussed.

[0101] In various embodiments, forming the MD segments and gate structures includes performing a plurality of fabrication operations, such as one or more of photolithography, diffusion, deposition, etching, planarization, or other operations suitable for depositing and forming one or more conductive materials and dielectric materials configured to form a continuous low resistance MD structure and gate structure, as described above with respect to Figures 2A to 2G Discussed.

[0102] At operation 520, a via is formed on each of the first source terminal and the second source terminal and the drain terminal of the MD segment and on the gate structure. In some embodiments, forming the via on the first source terminal and the second source terminal and the drain terminal of the MD segment and on the gate structure includes forming via structures VS and VD on the MD segments MDS1, MDD, and MDS2 and forming vias VG on the gate structures G1 to Gx, as described above for Figures 2A to 2G In some embodiments, forming vias on the first source terminal and the second source terminal and the drain terminal of the MD segments and on the gate structures includes forming via structures VS and VD on instances of the MD segments MD1 to MD7 and forming vias VG on instances of the gate structures G1A to G13A and G1B to G3B, as described above for FIG. 3A to FIG. 4D Discussed.

[0103] In various embodiments, forming the vias includes performing a plurality of fabrication operations such as photolithography, diffusion, deposition, etching, planarization, or other processes suitable for the above-described method. FIG. 2B to FIG. 4DThe configuration discussed is used to construct one or more of the other operations of the via structure.

[0104] At operation 530, a plurality of metal segments are formed on the vias, the plurality of metal segments including three aligned segments formed on the vias electrically connected to each of the first source terminal and the second source terminal and the drain terminal. In some embodiments, forming the metal segments on the vias includes forming instances of metal segments MS on vias VS, VD, and VG, at least one instance of metal segment MS including the above-described alignment segments for Figures 2A to 2G In some embodiments, forming metal segments on the vias includes forming metal segments M1 to M15 on vias VS, VD, and VG, as described above for FIG. 3A to FIG. 4D Discussed.

[0105] In various embodiments, forming the metal segments includes performing a plurality of fabrication operations such as photolithography, diffusion, deposition, etching, planarization, or other processes suitable for the above-described method. FIG. 2B to FIG. 4D The configuration discussed is used to construct one or more of the other operations of the metal segment.

[0106] In some embodiments, forming the aligned metal segments includes forming the aligned metal segments based on the metal cutting area (e.g., FIG. 2B to FIG. 4D The metal cutting operation is performed after the metal cutting area CM discussed above forms the corresponding metal segment. In some embodiments, as part of forming the corresponding metal segment, forming the aligned metal segment includes forming the metal segment (for example, FIG. 2B to FIG. 4D A natural end is formed on the metal region / metal segment MP) discussed.

[0107] At operation 540, in some embodiments, additional electrical connections are constructed, the additional electrical connections being configured to include a stacked transistor arrangement in the driver circuit. In some embodiments, the additional electrical connections include constructing a through hole and a through hole overlying the through hole (e.g., as described above for FIG. 2A to FIG. 4D The IC device 200 discussed above is configured to include the metal segments on the through holes VS, VD and VG) and electrically connected to the through holes. Figure 1 The cascaded transistor arrangement in circuit 100 is discussed.

[0108] In various embodiments, forming the additional electrical connections includes performing a plurality of fabrication operations such as photolithography, diffusion, deposition, etching, planarization, or other processes suitable for the above-described embodiments. Figures 1 to 4D The configuration discussed is used to construct one or more of the other operations of vias and metal segments.

[0109] By performing some or all of the operations of method 500, a stacked arrangement of transistors is formed, which includes source and drain connections along a single instance of a metal segment, and thereby enables the beneficial effects discussed above for IC device 200 including IC devices 200-1 and 200-2 to be achieved.

[0110] Figure 6 The IC layout diagram is generated according to some embodiments (for example, the above FIG. 2A to FIG. 4D 2. A flow chart of a method 600 of the IC layout diagrams 200, 200-1, 200-2, and / or 300A-400D discussed above.

[0111] In some embodiments, generating an IC layout diagram includes generating an IC device (eg, FIG. 2A to FIG. 4D IC layout diagrams corresponding to the IC devices 200, 200-1, 200-2 and / or 300A to 400D) discussed above.

[0112] In some embodiments, some or all of method 600 is executed by a processor of a computer (e.g., Figure 7 The discussed IC layout diagram generation system 700 executes the processor 702 .

[0113] Some or all of the operations of method 600 can be performed as part of a design house (e.g., Figure 8 It is performed as part of a design procedure executed in the design mechanism 820 discussed above.

[0114] In some embodiments, Figure 6 The operations of method 600 are performed in the order shown in FIG. Figure 6 The operations of method 600 are performed simultaneously in the order shown in Figure 6 The operations of method 600 may be performed in an order different from the order depicted in FIG. In some embodiments, one or more operations are performed before, between, during, and / or after one or more operations of method 600 are performed.

[0115] At operation 610, in some embodiments, a via region overlapping with an MD region and a gate region intersecting the active region is arranged in an IC layout diagram, the MD region corresponding to a first source terminal and a second source terminal and a drain terminal of a stacked transistor arrangement, and the gate region corresponds to a gate of the transistor. In some embodiments, arranging the via region includes arranging via regions VS, VD, and VG overlapping with MD regions MDS1, MDS2, and MDD intersecting the active region AA and gate regions G1 to Gx in an IC layout diagram of a stacked transistor arrangement, the gate region corresponding to the above-described via region. Figures 2A to 2G The gates G1 to Gx are discussed.

[0116] In some embodiments, arranging the through-hole region includes FIG. 3A to FIG. 4D In one of the discussed IC layout diagrams 300A to 400D, via regions VS, VD, and VG overlapping MD regions MD1 to MD7 intersecting active regions AA1 to AA4 and gate regions G1A to G3A and G1B to G3B are arranged.

[0117] At operation 620, first metal regions are arranged on the via regions, at least one of the first metal regions including portions or alignment regions overlapping the via regions corresponding to each of the first source terminal and the second source terminal and the drain terminal, wherein the at least one first metal region includes interruptions located between the portions or regions.

[0118] In some embodiments, arranging the first metal region includes arranging an instance of the metal region MS overlapping the via regions VS, VD, and VG, at least one instance of the metal region MS including the above Figures 2A to 2G In some embodiments, arranging the first metal region includes the following steps: FIG. 3A to FIG. 4D An example of disposing metal regions M1 to M15 on via regions VS, VD, and VG is discussed.

[0119] In some embodiments, including a break between the portions includes arranging a metal cutting area at a position corresponding to the break, such as the above FIG. 2A to FIG. 4D In some embodiments, including a discontinuity between the portions includes arranging a first metal region including a natural end of a metal portion or metal region at a location corresponding to the discontinuity.

[0120] In some embodiments, arranging the first metal region including interruptions between the portions includes determining the number of continua based on one or more maximum voltage differences, one or more feature sizes, and one or more manufacturing spacing rules, as described above for widths A, B, C, and F, and Figures 2B to 2G Discussed.

[0121] At operation 630, in some embodiments, the stacked transistor IC layout diagram is included in the driver circuit IC diagram (e.g., as described above for Figure 1 The circuit 100 discussed corresponds to the IC driver circuit diagram).

[0122] At operation 640, in some embodiments, the IC layout diagram including the stacked transistor arrangement is stored in a storage device. In some embodiments, storing the IC layout diagram including the stacked transistor arrangement in the storage device includes storing the cell in an IC layout library (e.g., as described below for Figure 7 The IC layout library 707 of the IC layout diagram generation system 700 discussed above.

[0123] In various embodiments, storing the IC layout in a storage device includes storing the IC layout in a non-volatile computer readable memory and / or includes storing the IC layout via a network (e.g., Figure 7 The network 714 of the discussed IC layout generation system 700 stores IC layouts.

[0124] At operation 650, in some embodiments, one or more manufacturing operations are performed based on the IC layout diagram. In some embodiments, performing the one or more manufacturing operations includes performing one or more photolithography exposures based on the IC layout diagram. Performing one or more manufacturing operations (e.g., one or more photolithography exposures) based on the IC layout diagram is described above with respect to Figure 5 Discuss and in the following Figure 8 Discuss.

[0125] By performing some or all of the operations of method 600, an IC layout diagram corresponding to a stacked arrangement of transistors including source connections and drain connections along a single instance of a metal segment is generated, and thereby the beneficial effects discussed above for IC device 200 including IC devices 200-1 and 200-2 can be achieved.

[0126] Figure 7 is a block diagram of an IC layout generation system 700 according to some embodiments. The method of designing an IC layout according to one or more embodiments described herein may be implemented, for example, using the IC layout generation system 700 according to some embodiments.

[0127] In some embodiments, IC layout generation system 700 is a general purpose computing device that includes a hardware processor 702 and a non-transitory computer readable storage medium 704. Storage medium 704 is encoded with (i.e., stores) computer programming code 706, i.e., a set of executable instructions. The execution of instructions 706 by hardware processor 702 (at least in part) represents an EDA tool that implements, for example, the EDA tool described above for Figure 6The method of generating an IC layout diagram described above (hereinafter referred to as the mentioned process and / or method) and other methods may be a part or all of the method.

[0128] The processor 702 is electrically coupled to the computer readable storage medium 704 via a bus 708. The processor 702 is also electrically coupled to an I / O interface 710 via the bus 708. A network interface 712 is also electrically connected to the processor 702 via the bus 708. The network interface 712 is connected to a network 714 so that the processor 702 and the computer readable storage medium 704 can be connected to external components via the network 714. The processor 702 is configured to execute computer programming code 706 encoded in the computer readable storage medium 704 so that the IC layout generation system 700 can be used to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the processor 702 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0129] In one or more embodiments, the computer-readable storage medium 704 is an electronic system, a magnetic system, an optical system, an electromagnetic system, an infrared system, and / or a semiconductor system (or an apparatus or device). For example, the computer-readable storage medium 704 includes a semiconductor memory or a solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 704 includes a compact disk-read only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disc (DVD).

[0130] In one or more embodiments, the computer-readable storage medium 704 stores computer programming code 706, which is configured to cause the IC layout diagram generation system 700 (where such execution (at least in part) represents an EDA tool) to be used to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the computer-readable storage medium 704 also stores information that facilitates the execution of part or all of the processes and / or methods mentioned. In one or more embodiments, the computer-readable storage medium 704 stores information including such IC layout diagrams disclosed herein (e.g., the above for FIG. 2A to FIG. 4D An IC layout library 707 of IC layout drawings including the IC layout drawings 200, 200-1, 200-1, and 300A to 400D discussed above.

[0131] IC layout generation system 700 includes an I / O interface 710. I / O interface 710 is coupled to external circuitry. In one or more embodiments, I / O interface 710 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor arrow keys for transmitting information and commands to processor 702.

[0132] The IC layout generation system 700 also includes a network interface 712 coupled to the processor 702. The network interface 712 enables the system 700 to communicate with a network 714 connected to one or more other computer systems. The network interface 712 includes: a wireless network interface, such as BLUETOOTH, wireless fidelity (WIFI), World Interoperability for Microwave Access (WIMAX), General Packet Radio Service (GPRS), or Wideband Code Division Multiple Access (WCDMA); or a wired network interface, such as Ethernet (ETHERNET), Universal Serial Bus (USB), or Institute of Electrical and Electronics Engineers (IEEE)-1364. In one or more embodiments, part or all of the processes and / or methods mentioned are implemented in two or more IC layout generation systems 700.

[0133] The IC layout generation system 700 is configured to receive information via an I / O interface 710. The information received via the I / O interface 710 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 702. The information is transmitted to the processor 702 via a bus 708. The IC layout generation system 700 is configured to receive information related to a user interface (UI) via the I / O interface 710. The information is stored in the computer readable medium 704 as a user interface (UI) 742.

[0134] In some embodiments, part or all of the processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in for a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by the IC layout diagram generation system 700. In some embodiments, the IC layout diagram generation system 700 is implemented using, for example, a software application available from Cadence Design Systems, Inc. etc. or another suitable layout generation tool to generate a layout diagram including standard cells.

[0135] In some embodiments, the process is considered to be a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage units or memory units, such as one or more of optical disks (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs, RAMs, memory cards), and the like.

[0136] Figure 8 is a block diagram of an IC manufacturing system 800 and an IC manufacturing process associated with the IC manufacturing system 800 according to some embodiments. In some embodiments, based on an IC layout diagram, the manufacturing system 800 is used to fabricate at least one of: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0137] exist Figure 8In the present invention, the IC manufacturing system 800 includes entities such as a design organization 820, a mask house 830, and an IC manufacturer / fabricator ("fab") 850, which interact with each other in the design, development, and manufacturing cycles and / or services associated with manufacturing IC devices 860. The entities in the system 800 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired communication channels and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from the one or more of the other entities. In some embodiments, two or more of the design organization 820, the mask house 830, and the IC fab 850 are owned by a single larger company. In some embodiments, two or more of the design organization 820, the mask house 830, and the IC fab 850 are simultaneously present in a shared facility and use shared resources.

[0138] The design organization (or design team) 820 generates an IC design layout diagram 822. The IC design layout diagram 822 includes various geometric patterns (e.g., FIG. 2A to FIG. 4D The IC layout diagram 200, 200-1, 200-2 or 300A to 400D discussed). The geometric pattern corresponds to the pattern of the metal layer, oxide layer or semiconductor layer that constitutes the various components of the IC device 860 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout diagram 822 includes various IC features to be formed in a semiconductor substrate (e.g., a silicon wafer) (e.g., active areas, gate electrodes, source and drain electrodes, metal lines or through holes for interconnects between layers, and openings for bonding pads) and various material layers disposed on the semiconductor substrate. The design organization 820 implements an appropriate design program to form the IC design layout diagram 822. The design program includes one or more of a logical design, a physical design, or a placement and routing. The IC design layout diagram 822 is presented as one or more data files having information of a geometric pattern. For example, the IC design layout diagram 822 may be expressed in a graphic database system (GDSII) file format or a Design Framework II (DFII) file format.

[0139] The mask mechanism 830 includes data preparation 832 and mask fabrication 844. The mask mechanism 830 uses the IC design layout drawing 822 to manufacture one or more masks 845 for various layers to be used to manufacture the IC device 860 according to the IC design layout drawing 822. The mask mechanism 830 performs mask data preparation 832, wherein the IC design layout drawing 822 is translated into a representative data file ("representative data file, RDF"). The mask data preparation 832 provides the RDF to the mask fabrication 844. The mask fabrication 844 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 845 or a semiconductor wafer 853. The design layout drawing 822 is manipulated by the mask data preparation 832 to comply with the specific characteristics of the mask writer and / or the requirements of the IC fabrication plant 850. In Figure 8 , mask data preparation 832 and mask production 844 are shown as separate elements. In some embodiments, mask data preparation 832 and mask production 844 may be collectively referred to as mask data preparation.

[0140] In some embodiments, mask data preparation 832 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors such as image errors that may be caused by diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout 822. In some embodiments, mask data preparation 832 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0141] In some embodiments, mask data preparation 832 includes a mask rule checker (MRC) that uses a set of mask creation rules including specific geometric constraints and / or connectivity constraints to check the IC design layout 822 after it has been through each process in OPC to ensure that there is a margin sufficient to account for variability and similar factors in semiconductor manufacturing processes. In some embodiments, MRC modifies the IC design layout 822 to compensate for restrictions during mask production 844, which can relieve some of the modifications performed by OPC to satisfy the mask creation rules.

[0142] In some embodiments, mask data preparation 832 includes lithography process checking (LPC), which simulates the processing to be performed by the IC manufacturing plant 850 to make the IC device 860. LPC simulates this processing based on the IC design layout 822 to create a simulated manufactured device (e.g., IC device 860). The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus ("depth of focus, DOF"), mask error enhancement factor ("mask error enhancement factor, MEEF"), other suitable factors, and the like, or combinations thereof. In some embodiments, after creating the simulated manufactured device through LPC, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC are repeatedly used to further refine the IC design layout 822.

[0143] It should be understood that the above description of mask data preparation 832 is simplified for the purpose of clarity. In some embodiments, data preparation 832 includes additional features such as logic operations (LOP) to modify IC design layout 822 according to manufacturing rules. In addition, the processes applied to IC design layout 822 during data preparation 832 can be performed in a variety of different orders.

[0144] After mask data preparation 832 and during mask fabrication 844, a mask 845 or a group of masks 845 is fabricated based on the modified IC design layout 822. In some embodiments, mask fabrication 844 includes performing one or more photolithography exposures based on the IC design layout 822. In some embodiments, an electron-beam (e-beam) or multiple electron-beam mechanism is used to form a pattern on a mask (reticle or stencil) 845 based on the modified IC design layout 822. Mask 845 can be formed by various techniques. In some embodiments, mask 845 is formed using binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) or extreme ultraviolet (EUV) beam) used to expose an image-sensitive material layer (e.g., a photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask version of mask 845 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chrome) coated in the opaque areas of the binary mask. In another example, mask 845 is formed using a phase shift technique. In a phase shift mask (PSM) version of mask 845, various features in the pattern formed on the phase shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The masks produced by mask making 844 are used in various processes. For example, such masks are used in an ion implantation process to form various doped regions in semiconductor wafer 853, in an etching process to form various etched regions in semiconductor wafer 853, and / or in other suitable processes.

[0145] IC fabrication plant 850 is an IC fabrication plant that includes one or more fabrication facilities that fabricate various different IC products. In some embodiments, IC fabrication plant 850 is a semiconductor foundry. For example, there may be one fabrication facility for front-end fabrication (front-end-of-line, FEOL) fabrication of multiple IC products, while a second fabrication facility may provide back-end fabrication (back-end-of-line, BEOL) fabrication for interconnection and packaging of IC products, and a third fabrication facility may provide other foundry business services.

[0146] The IC fabrication plant 850 includes a wafer fabrication tool 852 configured to perform various fabrication operations on a semiconductor wafer 853, thereby fabricating an IC device 860 according to the masks (e.g., mask 845). In various embodiments, the fabrication tool 852 includes one or more of a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a chemical vapor deposition (CVD) chamber or a low-pressure chemical vapor deposition (LPCVD) furnace), a chemical mechanical polishing (CMP) system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes discussed herein.

[0147] IC fabrication plant 850 uses mask 845 made by mask mechanism 830 to fabricate IC device 860. Therefore, IC fabrication plant 850 at least indirectly uses IC design layout 822 to fabricate IC device 860. In some embodiments, IC fabrication plant 850 uses mask 845 to fabricate semiconductor wafer 853 to form IC device 860. In some embodiments, IC fabrication includes performing one or more photolithography exposures based at least indirectly on IC design layout 822. Semiconductor wafer 853 includes a silicon substrate or other appropriate substrate with material layers formed thereon. Semiconductor wafer 853 also includes one or more of various doped regions, dielectric features, multilevel interconnects, and similar components (formed at subsequent manufacturing steps).

[0148] In some embodiments, an IC driver includes a stacked arrangement of first type transistors coupled in series with a stacked arrangement of second type transistors, the second type being different from the first type, wherein each of the stacked arrangement of the first type transistors and the stacked arrangement of the second type transistors includes: an active area extending in a first direction; a plurality of gate structures extending in a second direction perpendicular to the first direction and overlying the active area at locations corresponding to the transistors of the stacked arrangement; a first metal segment, a second metal segment, a third metal segment, and a fourth metal segment extending in the first direction in a first metal layer of the IC; a first through-hole and a second through-hole configured to electrically couple a corresponding first gate structure and a corresponding second gate structure of the plurality of gate structures to the first metal segment and the second metal segment, respectively; a third through-hole configured to electrically couple a source terminal of the stacked arrangement to the third metal segment; and a fourth through-hole configured to electrically couple a drain terminal of the stacked arrangement to the fourth metal segment, wherein the third metal segment is aligned with the fourth metal segment along the first direction.

[0149] In some embodiments, each of the stacked arrangement of the first type transistor and the stacked arrangement of the second type transistor further includes: a fifth metal segment extending between the third metal segment and the fourth metal segment and in the first direction, wherein the fifth metal segment is configured to be electrically floating. In some embodiments, the source terminal of each of the stacked arrangement of the first type transistor and the stacked arrangement of the second type transistor is a first source terminal of the stacked arrangement of the corresponding first type transistor or the stacked arrangement of the second type transistor, and each of the stacked arrangement of the first type transistor and the stacked arrangement of the second type transistor further includes: a fifth metal segment along the first direction and aligned with the third metal segment and the fourth metal segment; and a fifth through-hole configured to electrically couple the second source terminal of the stacked arrangement to the fifth metal segment. In some embodiments, each of the stacked arrangement of the first type transistor and the stacked arrangement of the second type transistor further includes: a fifth through-hole configured to couple a third gate structure of the plurality of gate structures to the first metal segment, wherein the first gate structure and the third gate structure of the plurality of gate structures overlie the active area at positions corresponding to the parallel configuration of the corresponding transistors of the stacked arrangement. In some embodiments, the stacked arrangement of the first type transistor and the stacked arrangement of the second type transistor further includes: a fifth metal segment along the first direction and aligned with the first metal segment; and a fifth through-hole configured to couple the third gate structure of the plurality of gate structures to the fifth metal segment. In some embodiments, for each of the stacked arrangement of the first type transistor and the stacked arrangement of the second type transistor: the active area is the first active area of ​​the corresponding stacked arrangement, the position corresponding to the transistor of the stacked arrangement is the first position corresponding to the first transistor of the stacked arrangement, the stacked arrangement also includes a second active area extending in the first direction, and the plurality of gate structures overlie the second active area at a second position corresponding to the second transistor of the stacked arrangement, and the second transistor of the stacked arrangement is configured to be connected in parallel with the first transistor of the stacked arrangement. In some embodiments, each of the stacked arrangement of the first type transistor and the stacked arrangement of the second type transistor further includes: a fifth metal segment and a sixth metal segment aligned along the first direction in the first metal layer; a fifth through hole configured to electrically couple the source terminal of the stacked arrangement to the fifth metal segment; and a sixth through hole configured to electrically couple the drain terminal of the stacked arrangement to the sixth metal segment.In some embodiments, each of the stacked arrangement of the first type transistor and the stacked arrangement of the second type transistor further includes: a seventh metal segment extending in the first direction between the third metal segment and the fourth metal segment; and an eighth metal segment extending in the first direction between the fifth metal segment and the sixth metal segment, wherein each of the seventh metal segment and the eighth metal segment is configured to be electrically floating. In some embodiments, for at least one of the stacked arrangement of the first type transistor or the stacked arrangement of the second type transistor, the third metal segment is separated from the fourth metal segment by a distance corresponding to a metal cutting operation of a manufacturing process corresponding to the integrated circuit. In some embodiments, the first type transistor and the second type transistor respectively include a p-type metal oxide semiconductor (PMOS) transistor and an n-type metal oxide semiconductor (NMOS) transistor, the source terminal of the stacked arrangement of the first type transistor is electrically coupled to a power supply node of the integrated circuit driver, the source terminal of the stacked arrangement of the second type transistor is electrically coupled to a reference node of the integrated circuit driver, and each of the drain terminal of the stacked arrangement of the first type transistor and the drain terminal of the stacked arrangement of the second type transistor is electrically coupled to an output node of the integrated circuit driver.

[0150] In some embodiments, an IC includes a stacked arrangement of transistors, and the stacked arrangement of the transistors includes: a first active region, a second active region, a third active region, and a fourth active region, extending in a first direction; a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, a fifth gate structure, and a sixth gate structure, extending in a second direction perpendicular to the first direction and overlying each of the first active region, the second active region, the third active region, and the fourth active region at a position corresponding to the transistor of the stacked arrangement; a first metal segment, a second metal segment, and a third metal segment, overlying the first gate structure, the third active region, and the fourth active region; a first metal layer overlying the second gate structure, the third gate structure, the fourth gate structure, the fifth gate structure, and the sixth gate structure, extending in the first direction; a first plurality of alignment metal segments, a second plurality of alignment metal segments, a third plurality of alignment metal segments, a fourth plurality of alignment metal segments, and a fifth plurality of alignment metal segments extending in the first direction in the first metal layer overlying the first gate structure, the second gate structure, the third gate structure, the fourth gate structure, the fifth gate structure, and the sixth gate structure; a first through hole and a second through hole configured to electrically couple the first gate structure and the second gate structure to the first metal segment a third through hole and a fourth through hole configured to electrically couple the third gate structure and the fourth gate structure to the second metal segment; a fifth through hole and a sixth through hole configured to electrically couple the fifth gate structure and the sixth gate structure to the third metal segment; a seventh through hole, an eighth through hole, a ninth through hole, a tenth through hole, and an eleventh through hole configured to electrically couple the first source terminal of the stacked arrangement to a first alignment metal segment in each of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments, and the fifth plurality of alignment metal segments; a twelfth through hole, a thirteenth through hole, a fourteenth through hole, a ten ... The fifth through hole and the sixteenth through hole are configured to electrically couple the drain terminal of the stacking arrangement to the second alignment metal segment in each of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments, and the fifth plurality of alignment metal segments; and the seventeenth through hole, the eighteenth through hole, the nineteenth through hole, the twentieth through hole, and the twenty-first through hole are configured to electrically couple the second source terminal of the stacking arrangement to the third alignment metal segment in each of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments, and the fifth plurality of alignment metal segments.

[0151] In some embodiments, each of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments, and the fifth plurality of alignment metal segments further comprises: a fourth alignment metal segment extending between the first alignment metal segment and the second alignment metal segment; and a fifth alignment metal segment extending between the second alignment metal segment and the third alignment metal segment. In some embodiments, the integrated circuit further comprises: a first type of metal definition (MD) segment, a second type of metal definition segment, a third type of metal definition segment, a fourth type of metal definition segment, a fifth type of metal definition segment, a sixth type of metal definition segment, and a seventh type of metal definition segment extending in the second direction and overlying each of the first active region, the second active region, the third active region, and the fourth active region, wherein the first gate structure, the second gate structure, the third gate structure, the fourth gate structure, the fifth gate structure, and the sixth gate structure are aligned with the first type of metal definition segment, the second type of metal definition segment, the third type of metal definition segment, the fourth type of metal definition segment, and the sixth type of metal definition segment relative to the first direction. The first gate structure, the second gate structure, the third gate structure, the fourth gate structure, the fifth gate structure and the sixth gate structure are located between the first source terminal including the first metal defining segment and the second source terminal including the seventh metal defining segment, the first gate structure, the third gate structure and the fifth gate structure are located between the first source terminal and the drain terminal including the fourth metal defining segment, and the second gate structure, the fourth gate structure and the sixth gate structure are located between the drain terminal and the second source terminal. In some embodiments, the transistor comprises a p-type metal oxide semiconductor (PMOS) transistor, the first source terminal and the second source terminal are electrically coupled to a power supply node of a driver circuit, and the drain terminal is electrically coupled to an output node of the driver circuit. In some embodiments, the transistor comprises an n-type metal oxide semiconductor (NMOS) transistor, the first source terminal and the second source terminal are electrically coupled to a reference node of a driver circuit, and the drain terminal is electrically coupled to an output node of the driver circuit.

[0152] In some embodiments, a method for manufacturing an IC device includes: forming a first through hole, a second through hole, a third through hole, a fourth through hole, and a fifth through hole on a first MD section extending across a first active region, a second active region, a third active region, and a fourth active region in a semiconductor substrate; forming a sixth through hole, a seventh through hole, an eighth through hole, a ninth through hole, and a tenth through hole on a second MD section extending across the first active region, the second active region, the third active region, and the fourth active region; forming an eleventh through hole, a twelfth through hole, a thirteenth through hole, a tenth through hole, a second through hole, a third through hole, a fourth through hole, and a fifth through hole on a third MD section extending across the first active region, the second active region, the third active region, and the fourth active region. a fourth through hole and a fifteenth through hole; a sixteenth through hole, a seventeenth through hole and an eighteenth through hole are formed on the corresponding first gate structure, the second gate structure and the third gate structure, the first gate structure, the second gate structure and the third gate structure extend between the first MD segment and the second MD segment and cross the first active area, the second active area, the third active area and the fourth active area; a nineteenth through hole, a twentieth through hole and a twenty-first through hole are formed on the corresponding fourth gate structure, the fifth gate structure, the sixth gate structure and the seventh gate structure, the fourth gate structure, the fifth gate structure, the sixth gate structure and the seventh gate structure extend between the second MD segment and the second MD segment and cross the first active area, a third MD segment extending across the first active area, the second active area, the third active area, and the fourth active area; forming a first metal segment on the sixteenth through hole and the nineteenth through hole, forming a second metal segment on the seventeenth through hole and the twenty-first through hole, and forming a third metal segment on the eighteenth through hole and the twenty-first through hole; and forming a first alignment metal segment in each of a first plurality of alignment metal segments, a second plurality of alignment metal segments, a third plurality of alignment metal segments, a fourth plurality of alignment metal segments, and a fifth plurality of alignment metal segments on corresponding through holes among the first through hole, the second through hole, the third through hole, the fourth through hole, and the fifth through hole, and forming a first alignment metal segment in each of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments, and the fifth plurality of alignment metal segments on corresponding through holes among the first through hole, the second through hole, the third through hole, the fourth through hole, and the fifth through hole, and forming a second ... The second alignment metal segment of each of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments, and the fifth plurality of alignment metal segments is formed on the corresponding through holes among the sixth through hole, the seventh through hole, the eighth through hole, the ninth through hole, and the tenth through hole, and the third alignment metal segment of each of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments, and the fifth plurality of alignment metal segments is formed on the corresponding through holes among the eleventh through hole, the twelfth through hole, the thirteenth through hole, the fourteenth through hole, and the fifteenth through hole.

[0153] In some embodiments, the forming of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments, and the fifth plurality of alignment metal segments includes performing a metal cutting operation to form a break between the alignment metal segments in each of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments, and the fifth plurality of alignment metal segments. In some embodiments, the forming of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments, and the fifth plurality of alignment metal segments also includes forming a fourth alignment metal segment between the first alignment metal segment and the second alignment metal segment and forming a fifth alignment metal segment between the second alignment metal segment and the third alignment metal segment. In some embodiments, at least one of the forming the first metal segment, the forming the second metal segment, or the forming the third metal segment includes dividing the corresponding first metal segment, the second metal segment, or the third metal segment into a plurality of metal segments by forming an interruption between the corresponding sixteenth through hole and the nineteenth through hole, between the seventeenth through hole and the twenty-third through hole, or between the eighteenth through hole and the twenty-first through hole. In some embodiments, the forming the first plurality of aligned metal segments, the second plurality of aligned metal segments, the third plurality of aligned metal segments, the fourth plurality of aligned metal segments, and the fifth plurality of aligned metal segments includes forming at least one additional metal segment between each of the first plurality of aligned metal segments, the second plurality of aligned metal segments, the third plurality of aligned metal segments, the fourth plurality of aligned metal segments, and the fifth plurality of aligned metal segments.

[0154] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also appreciate that such equivalent structures do not depart from the spirit and scope of the present invention, and various modifications, substitutions, and changes can be made to this document without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit driver, characterized in that: include: a cascaded arrangement of first type transistors coupled in series with a cascaded arrangement of second type transistors, the second type transistors being different from the first type transistors; wherein each of the cascaded arrangement of the first type transistors and the cascaded arrangement of the second type transistors comprises: an active region extending in a first direction; a plurality of gate structures extending in a second direction perpendicular to the first direction and overlying the active region at positions corresponding to the transistors in the stacked arrangement; A first metal segment, a second metal segment, a third metal segment, and a fourth metal segment extending in the first direction in a first metal layer of the integrated circuit; a first through hole and a second through hole configured to electrically couple a corresponding first gate structure and a corresponding second gate structure of the plurality of gate structures to the first metal segment and the second metal segment, respectively; a third via configured to electrically couple a source terminal of the stacked arrangement to the third metal segment; and a fourth via configured to electrically couple a drain terminal of the stacked arrangement to the fourth metal segment, The third metal segment is aligned with the fourth metal segment along the first direction.

2. The integrated circuit driver according to claim 1, characterized in that: Each of the cascaded arrangement of the first type transistors and the cascaded arrangement of the second type transistors further includes: a fifth metal segment, between the third metal segment and the fourth metal segment and extending in the first direction, The fifth metal segment is configured to be electrically floating.

3. The integrated circuit driver according to claim 1, characterized in that: The source terminal of each of the cascaded arrangement of the first type transistors and the cascaded arrangement of the second type transistors is a first source terminal of the corresponding cascaded arrangement of the first type transistors or the cascaded arrangement of the second type transistors, and Each of the cascaded arrangement of the first type transistors and the cascaded arrangement of the second type transistors further includes: a fifth metal segment, along the first direction and aligned with the third metal segment and the fourth metal segment; and A fifth via is configured to electrically couple the second source terminal of the stacked arrangement to the fifth metal segment.

4. The integrated circuit driver according to claim 1, characterized in that: Each of the cascaded arrangement of the first type transistors and the cascaded arrangement of the second type transistors further includes: a fifth through-hole configured to couple a third gate structure of the plurality of gate structures to the first metal segment, The positions where the first gate structure and the third gate structure among the plurality of gate structures overlie the active region correspond to the parallel configuration of corresponding transistors in the stacked arrangement.

5. The integrated circuit driver according to claim 1, characterized in that: The cascaded arrangement of the first type transistors and the cascaded arrangement of the second type transistors further include: a fifth metal segment along the first direction and aligned with the first metal segment; and A fifth via is configured to couple a third gate structure of the plurality of gate structures to the fifth metal segment.

6. The integrated circuit driver according to claim 1, characterized in that: For each of the cascaded arrangement of the first type transistors and the cascaded arrangement of the second type transistors: The active area is the first active area of ​​the corresponding stacked arrangement, The position corresponding to the transistor of the stacked arrangement is a first position corresponding to a first transistor of the stacked arrangement, The stacked arrangement further comprises a second active region extending in the first direction, and The plurality of gate structures overlie the second active region at second locations corresponding to second transistors of the stacked arrangement, the second transistors of the stacked arrangement being configured in parallel with the first transistors of the stacked arrangement.

7. The integrated circuit driver according to claim 6, characterized in that: Each of the cascaded arrangement of the first type transistors and the cascaded arrangement of the second type transistors further includes: a fifth metal segment and a sixth metal segment, aligned along the first direction in the first metal layer; a fifth via configured to electrically couple the source terminal of the stacked arrangement to the fifth metal segment; and A sixth via is configured to electrically couple the drain terminal of the stacked arrangement to the sixth metal segment.

8. The integrated circuit driver according to claim 7, characterized in that: Each of the cascaded arrangement of the first type transistors and the cascaded arrangement of the second type transistors further includes: a seventh metal segment, between the third metal segment and the fourth metal segment and extending in the first direction; and an eighth metal segment, between the fifth metal segment and the sixth metal segment and extending in the first direction, Wherein each of the seventh metal segment and the eighth metal segment is configured to be electrically floating.

9. An integrated circuit comprising a stacked arrangement of transistors, characterized in that: The stacked arrangement of the transistors comprises: The first active region, the second active region, the third active region and the fourth active region extend in a first direction; a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, a fifth gate structure, and a sixth gate structure extending in a second direction perpendicular to the first direction and overlying each of the first active region, the second active region, the third active region, and the fourth active region at a position corresponding to the transistors of the stacked arrangement; A first metal segment, a second metal segment, and a third metal segment extend in the first direction in a first metal layer overlying the first gate structure, the second gate structure, the third gate structure, the fourth gate structure, the fifth gate structure, and the sixth gate structure; a first plurality of alignment metal segments, a second plurality of alignment metal segments, a third plurality of alignment metal segments, a fourth plurality of alignment metal segments, and a fifth plurality of alignment metal segments extending in the first direction in the first metal layer overlying the first gate structure, the second gate structure, the third gate structure, the fourth gate structure, the fifth gate structure, and the sixth gate structure; a first through-hole and a second through-hole configured to electrically couple the first gate structure and the second gate structure to the first metal segment; a third through hole and a fourth through hole configured to electrically couple the third gate structure and the fourth gate structure to the second metal segment; a fifth through hole and a sixth through hole configured to electrically couple the fifth gate structure and the sixth gate structure to the third metal segment; a seventh through-hole, an eighth through-hole, a ninth through-hole, a tenth through-hole, and an eleventh through-hole configured to electrically couple a first source terminal of the stacked arrangement to a first alignment metal segment in each of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments, and the fifth plurality of alignment metal segments; a twelfth through-hole, a thirteenth through-hole, a fourteenth through-hole, a fifteenth through-hole, and a sixteenth through-hole configured to electrically couple the drain terminal of the stacked arrangement to a second alignment metal segment in each of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments, and the fifth plurality of alignment metal segments; and The seventeenth through hole, the eighteenth through hole, the nineteenth through hole, the twentieth through hole and the twenty-first through hole are configured to electrically couple the second source terminal of the stacked arrangement to the third alignment metal segment in each of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments and the fifth plurality of alignment metal segments.

10. The integrated circuit according to claim 9, characterized in that Each of the first plurality of alignment metal segments, the second plurality of alignment metal segments, the third plurality of alignment metal segments, the fourth plurality of alignment metal segments, and the fifth plurality of alignment metal segments further comprises: a fourth alignment metal segment extending between the first alignment metal segment and the second alignment metal segment; and A fifth alignment metal segment extends between the second alignment metal segment and the third alignment metal segment.

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