Semiconductor device

Abstract

The present disclosure relates to a semiconductor device. A non-active gate structure over a shallow trench isolation region adjacent to at least one fin structure of a semiconductor device including a fin transistor. The non-active gate structure includes at least one support structure extending from the gate in a direction substantially orthogonal to a direction in which the body of the non-active gate structure extends. This support structure provides structural support for the inactive gate structure, which increases the stability of the inactive gate structure relative to a gate structure that does not include the support structure.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Fin transistors (e.g., fin field effect transistors (finFETs) and nanostructures (e.g., nanowire transistors, nanosheet transistors, gate all around (GAA) transistors, multi bridge channel transistors, nanoribbon transistors) are three-dimensional structures that include a channel region in a fin (or portion thereof) that extends above a semiconductor substrate as a three-dimensional structure. A gate structure is configured to control the flow of charge carriers in the channel region, surrounding the fin of semiconductor material. As an example, in a fin field effect transistor, the gate structure surrounds three sides of the fin (and the channel region), thereby enabling enhanced control of the channel region (and thereby switching the fin field effect transistor). As another example, in a nanostructure transistor, the gate structure surrounds multiple channel regions in the fin structure, such that the gate structure surrounds each of the multiple channel regions. Source / drain regions (e.g., epitaxial regions) are located on opposite sides of the gate structure. Utility Model Content

[0003] The present disclosure provides a semiconductor device. The semiconductor device includes one or more fin structures extending above a substrate, wherein the one or more fin structures extend in a first direction in a top-down view of the semiconductor device. The semiconductor device includes an active gate structure surrounding the one or more fin structures on at least three sides of the one or more fin structures, wherein the active gate structure extends in a second direction substantially perpendicular to the first direction in a top-down view of the semiconductor device. The semiconductor device includes a non-active gate structure located on a shallow trench isolation region, wherein the non-active gate structure is adjacent to multiple ends of the one or more fin structures, wherein the non-active gate structure includes a main body extending in a second direction and one or more support structures extending from the main body in a first direction.

[0004] The present disclosure provides a semiconductor device. The semiconductor device includes a fin structure, a shallow trench isolation region, a dummy gate layer, a first dummy gate structure, and a second dummy gate structure. A plurality of fin structures are located on a substrate of the semiconductor device, wherein the plurality of fin structures extend in a first direction in a top-down view of the semiconductor device. A shallow trench isolation region is located between the plurality of fin structures and on a substrate adjacent to the plurality of ends of the plurality of fin structures, wherein the plurality of fin structures extend above the shallow trench isolation region. One or more dummy gate layers are located in the shallow trench isolation region and surround the plurality of fin structures. One or more dummy gate layers are etched according to a pattern to form one or more first dummy gate structures and one or more second dummy gate structures. The one or more first dummy gate structures extend in a second direction substantially perpendicular to the first direction in a top-down view of the semiconductor device, and the one or more first dummy gate structures surround the plurality of fin structures on at least three sides of the plurality of fin structures. One or more second dummy gate structures extend in the second direction and are located in the shallow trench isolation region and adjacent to multiple ends of multiple fin structures. One or more second dummy gate structures include a body extending in the second direction and one or more support structures extending from the body in the first direction.

[0005] The present disclosure provides a semiconductor device. The semiconductor device includes one or more first fin structures extending above a substrate, wherein the one or more first fin structures extend in a first direction in a top-down view of the semiconductor device. The semiconductor device includes a first active gate structure surrounding the one or more first fin structures on at least three sides of the one or more first fin structures, wherein the first active gate structure extends in a second direction substantially perpendicular to the first direction in a top-down view of the semiconductor device. The semiconductor device includes a first non-active gate structure located on a shallow trench isolation region, wherein the first non-active gate structure is adjacent to multiple ends of the one or more first fin structures, and the first non-active gate structure includes a first body extending in a second direction and one or more first support structures extending from the first body in a first direction. The semiconductor device includes one or more second fin structures extending above the substrate, wherein the one or more second fin structures extend in a first direction. The semiconductor device includes a second active gate structure surrounding the one or more second fin structures on at least three sides of the one or more second fin structures, wherein the second active gate structure extends in a second direction. The semiconductor device includes a second non-active gate structure located on the shallow trench isolation region and adjacent to the first non-active gate structure, wherein the second non-active gate structure is adjacent to multiple ends of one or more second fin structures, and the second non-active gate structure includes a second body extending in a second direction and one or more second support structures extending from the second body in a first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure can be more fully understood by reading the detailed description of the following embodiments and referring to the accompanying drawings. It should be emphasized that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic diagram of an example environment in which the systems and / or methods described herein may be implemented;

[0008] Figure 2 A schematic diagram of an example of a semiconductor device disclosed herein;

[0009] FIG. 3A to FIG. 3D is a schematic diagram of an embodiment of the present disclosure;

[0010] Figures 4A to 4K is a schematic diagram of an embodiment of the present disclosure;

[0011] FIG. 5A to FIG. 5E is a schematic diagram of an embodiment of the present disclosure;

[0012] FIG. 6A to FIG. 6C is a schematic diagram of an embodiment of the present disclosure;

[0013] Fig. 7A and Figure 7B is a schematic diagram of an embodiment of the present disclosure;

[0014] FIG. 8A to FIG. 8D A schematic diagram of an embodiment of the present disclosure;

[0015] 9A to 9D is a schematic diagram of an embodiment of the present disclosure;

[0016] Fig.10 A schematic diagram of an example of device components of the present disclosure;

[0017] Fig.11 A flowchart of an example process for forming a semiconductor device is provided.

[0018]

Explanation of symbols

[0019] 100: Sample Environment

[0020] 102: Deposition equipment

[0021] 104: Exposure equipment

[0022] 106: Development equipment

[0023] 108: Etching equipment

[0024] 110: Flattening equipment

[0025] 112: Electroplating equipment

[0026] 114: Wafer / bare crystal transport equipment

[0027] 200: Semiconductor devices

[0028] 202: Installation area

[0029] 204: Substrate

[0030] 206: Fin structure

[0031] 208: Shallow Trench Isolation Area

[0032] 210: Virtual gate structure

[0033] 210a: Dummy gate structure

[0034] 210b: Dummy gate structure

[0035] 212: Gate electrode layer

[0036] 214: Hard Mask Layer

[0037] 216: Covering layer

[0038] 218: Source / drain region

[0039] 300: Example

[0040] 302: Shallow Trench Isolation Layer

[0041] 400: Example

[0042] 402: Polysilicon layer

[0043] 404: Hard Mask Layer

[0044] 406: Covering layer

[0045] 408: Photoresist layer

[0046] 410a: Subject

[0047] 410b: Support structure

[0048] 412: Sealing spacer

[0049] 414: Body spacer

[0050] 416: Groove

[0051] 418: Source / drain region

[0052] 500: Example

[0053] 502: Contact etch stop layer

[0054] 504: Interlayer dielectric layer

[0055] 506a: Groove

[0056] 506b: Groove

[0057] 508a: Active gate structure

[0058] 508b: Non-active gate structure

[0059] 600: Example

[0060] 602: Opening

[0061] 602a: Bottom

[0062] 602b: Sidewall

[0063] 606: Conductive structure

[0064] 604: Pre-cleaner

[0065] 700: Example

[0066] 702: Fin set

[0067] 710: Example

[0068] 800: Example

[0069] 810: Example

[0070] 820: Example

[0071] 830: Example

[0072] 802a: First inactive gate structure

[0073] 812a: First inactive gate structure

[0074] 822a: first inactive gate structure

[0075] 832a: First inactive gate structure

[0076] 802b: Second inactive gate structure

[0077] 812b: Second inactive gate structure

[0078] 822b: Second inactive gate structure

[0079] 832b: Second inactive gate structure

[0080] 900: Example

[0081] 902a: First inactive gate structure

[0082] 912a: First inactive gate structure

[0083] 922a: first inactive gate structure

[0084] 932a: First inactive gate structure

[0085] 902b: Second inactive gate structure

[0086] 912b: Second inactive gate structure

[0087] 922b: Second inactive gate structure

[0088] 932b: Second inactive gate structure

[0089] 910: Example

[0090] 920: Example

[0091] 930: Example

[0092] 1000: Installation

[0093] 1010: Bus

[0094] 1020: Processor

[0095] 1030: Memory

[0096] 1040: Input Components

[0097] 1050: Output components

[0098] 1060: Communication components

[0099] 1100: Craftsmanship

[0100] 1110: Box

[0101] 1120: Box

[0102] 1130: Box

[0103] 1140: Box

[0104] D1: Dimensions

[0105] D2: Dimensions

[0106] D3: Dimensions

[0107] D4: Dimensions

[0108] D5: Dimensions

[0109] AA: Cross section

[0110] BB: Cross section DETAILED DESCRIPTION

[0111] The following disclosure provides many different embodiments or examples for realizing the different features of the disclosure. In order to simplify the disclosure, specific examples of components and configurations are described below. Of course, these are just examples and are not meant to be restrictive. For example, the formation of the first feature on the second feature in the following description may include an embodiment in which the first and second features are directly in contact, and may also include an embodiment in which additional features are formed between the first and second features, so that the first and second features may not directly contact. In addition, the disclosure may repeat component numbers and / or symbols in various examples. This repetition is for simplicity and clarity, and does not limit the relationship between the various embodiments and / or configurations discussed.

[0112] In addition, for ease of description, spatially relative terms, such as "below", "beneath", "below", "above", "above", etc., may be used herein to describe the relationship of one (or some) element or feature to another (or some) element or feature shown in the figure. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figure. The device may be oriented in other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptive symbols used herein may be interpreted accordingly.

[0113] As the semiconductor manufacturing process of fin-type semiconductor devices continues to advance with the reduction of dimensions such as fin-to-fin spacing and gate length (also known as polycrystalline critical dimension (CD)), various process challenges may arise. For example, reducing the length of the gate structure in a fin-type transistor may result in an increase in the aspect ratio of the gate structure thickness to length ratio. The increase in aspect ratio may result in reduced stability of the gate structure, resulting in peeling and collapse of the gate structure. In particular, the larger the aspect ratio, the smaller the amount of force that may be required to topple the gate structure. This may cause the gate structure to be more susceptible to peeling and collapse, increasing the possibility of failure of the fin transistor included in the semiconductor device.

[0114] Gate structures adjacent to the fin structures of the fin transistor (e.g., not included in the fin structures) may be particularly susceptible to spalling and collapse as aspect ratios increase. Because in semiconductor processes for semiconductor devices, these gate structures (referred to herein as non-active gate structures) are often included to protect other gate structures in the fin structures (referred to herein as active gate structures). Non-active gate structures may be subject to greater forces than active gate structures, resulting in a greater likelihood of spalling and collapse of the non-active gate structures.

[0115] In some embodiments described herein, a non-active gate structure is formed above a shallow trench isolation region adjacent to at least one fin structure of a semiconductor device including a fin transistor. The non-active gate structure includes at least one support structure extending from the gate in a direction that is substantially orthogonal to the direction in which the main body of the non-active gate structure extends. The support structure provides structural support for the non-active gate structure, which increases the stability of the non-active gate structure relative to a gate structure that does not include a support structure.

[0116] As such, the support structure reduces the likelihood of non-active gate structures peeling and collapsing. This reduces the likelihood of defects forming in the semiconductor device. Additionally, this allows the aspect ratio of the non-active gate structure (e.g., the ratio of the thickness to the length of the non-active gate structure) to be increased without increasing the likelihood of non-active gate structures peeling and collapsing, thereby increasing the density of gate structures in the semiconductor device.

[0117] Figure 1 FIG. 1 is a schematic diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown, the example environment 100 may include a plurality of semiconductor process equipment 102-112 and a wafer / die transport device 114. The plurality of semiconductor process equipment 102-112 may include a deposition device 102, an exposure device 104, a development device 106, an etching device 108, a planarization device 110, a plating device 112 and / or other types of semiconductor process equipment. The equipment included in the example environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor process facility and / or a manufacturing facility in other examples.

[0118] The deposition device 102 is a semiconductor process device, including a semiconductor process chamber and one or more devices capable of depositing various materials onto a substrate. In some embodiments, the deposition device 102 includes a spin coating device capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, the deposition device 102 includes a chemical vapor deposition (CVD) device, for example, a plasma-enhanced CVD (PECVD) device, a high-density plasma CVD (HDP-CVD) device, a sub-atmospheric CVD (SACVD) device, a low-pressure CVD (LPCVD) device, an atomic layer deposition (ALD) device, a plasma-enhanced ALD (PEALD) device, or other types of CVD devices. In some embodiments, the deposition device 102 includes a physical vapor deposition (PVD) device, such as a sputtering device or other types of PVD devices. In some embodiments, the deposition device 102 includes an epitaxial device configured to form layers and / or regions of a device by epitaxial growth. In some embodiments, the example environment 100 includes multiple types of deposition devices 102.

[0119] The exposure device 104 is a semiconductor process device that can expose the photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep ultraviolet light source, an extreme ultraviolet light (EUV) source, and / or a similar ultraviolet light source), an X-ray source, an electron beam (e-beam) source, and / or a similar radiation source. The exposure device 104 can expose the photoresist layer to the radiation source to transfer a pattern from the mask to the photoresist layer. The pattern may include a pattern of one or more semiconductor device layers for forming one or more semiconductor devices, may include a pattern for forming one or more structures of a semiconductor device, may include a pattern for etching various parts of a semiconductor device, and / or similar patterns. In some embodiments, the exposure device 104 includes a scanner, a stepper, or a similar type of exposure device.

[0120] The developing device 106 is a semiconductor process device capable of developing the photoresist layer that has been exposed to the radiation source to develop the pattern transferred from the exposure device 104 to the photoresist layer. In some embodiments, the developing device 106 develops the pattern by removing the unexposed portion of the photoresist layer. In some embodiments, the developing device 106 develops the pattern by removing the exposed portion of the photoresist layer. In some embodiments, the developing device 106 develops the pattern by dissolving the exposed or unexposed portion of the photoresist layer using a chemical developer.

[0121] The etching apparatus 108 is a semiconductor processing apparatus capable of etching various types of substrates, wafers, or semiconductor device materials. For example, the etching apparatus 108 may include a wet etching apparatus, a dry etching apparatus, and / or the like. In some embodiments, the etching apparatus 108 includes a chamber filled with an etchant, and a substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching apparatus 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using an ionized gas to etch the one or more portions isotropically or directionally.

[0122] The planarization device 110 is a semiconductor process device capable of polishing or planarizing the layers of a wafer or semiconductor device. For example, the planarization device 110 may include a chemical mechanical planarization (CMP) device and / or another type of planarization device for polishing or planarizing a layer or surface of a deposited or plated material. The planarization device 110 may polish or planarize the surface of a semiconductor device using a combination of chemical and mechanical forces (e.g., chemical etching and abrasive-free polishing). The planarization device 110 may be used in combination with abrasive and corrosive chemical slurries and polishing pads and retaining rings (e.g., typically larger than the diameter of the semiconductor device). The polishing pad and the semiconductor device may be pressed by a dynamic polishing head and fixed in position by a retaining ring. The dynamic polishing head may rotate with different rotation axes to remove material and even out any irregularities of the semiconductor so that the semiconductor device is flat or planar.

[0123] The electroplating apparatus 112 is a semiconductor processing apparatus capable of electroplating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion thereof with one or more metals. For example, the electroplating apparatus 112 may include a copper electroplating apparatus, an aluminum electroplating apparatus, a nickel electroplating apparatus, a tin electroplating apparatus, a composite material or alloy (e.g., tin-silver, tin-lead, and / or similar alloys) electroplating apparatus, and / or an electroplating apparatus for one or more other types of conductive materials, metals, and / or similar types of materials.

[0124] The wafer / bare die transport equipment 114 includes a mobile robot, a robotic arm, a tram or rail car, an overhead hoist transport (OHT) system, an automated material handling system (AMHS) and / or other types of devices. The wafer / bare die transport equipment is configured to transport substrates and / or semiconductor devices between semiconductor process equipment 102-112, to transport substrates and / or semiconductor devices between process chambers of the same semiconductor process equipment, and / or to transport substrates and / or semiconductor devices between other locations such as wafer racks and storage rooms, and / or similar purposes. In some embodiments, the wafer / bare die transport equipment 114 can be set as a program device that travels a specific path and / or can operate semi-autonomously or autonomously. In some embodiments, the example environment 100 includes multiple wafer / bare die transport equipment 114.

[0125] For example, the wafer / die transport equipment 114 may be included in a cluster equipment or in another equipment including multiple process chambers. Furthermore, the wafer / die transport equipment may be configured to transport substrates and / or semiconductor devices between multiple process chambers, between a process chamber and a buffer, between a process chamber and an interface device (such as an equipment front end module (EFEM)), and / or between a process chamber and a transport carrier (e.g., a front-opening unified pod (FOUP)) in other examples, etc. In some embodiments, the wafer / die transport equipment 114 may be included in a multi-chamber (or cluster) deposition equipment 102, which may include a pre-cleaning process chamber (e.g., for cleaning or removing oxides, oxidation and / or other types of contamination or byproducts in substrates and / or semiconductor devices) and multiple types of deposition process chambers (e.g., process chambers for storing different types of materials, process chambers for performing different types of deposition operations). In these embodiments, the wafer / die transport apparatus 114 is configured as described herein to transfer substrates and / or semiconductor devices between process chambers of the deposition apparatus 102 without breaking or removing the vacuum (or at least partial vacuum) between process chambers and / or between process operations in the deposition apparatus 102.

[0126] In some embodiments, one or more of the semiconductor processing equipment 102 - 112 and / or the wafer / die transport equipment 114 may perform one or more semiconductor processing operations described herein. For example, in other examples, one or more of the semiconductor process equipment 102 to 112 and / or the wafer / bare die transport equipment 114 can form multiple fin structures on the substrate of the semiconductor device, wherein the multiple fin structures extend in a first direction in a top-down view of the semiconductor device; a shallow trench isolation region can be formed on the substrate between the multiple fin structures and adjacent to multiple ends of the multiple fin structures, wherein the multiple fin structures extend above the shallow trench isolation region; one or more dummy gate layers can be formed in the shallow trench isolation region and surround the multiple fin structures; one or more dummy gate layers can be etched according to a pattern to form one or more first dummy gate structures extending in a second direction (y direction) substantially perpendicular to the first direction in a top-down view of the semiconductor device, wherein the one or more first dummy gate structures surround at least three sides of the multiple fin structures, and one or more second dummy gate structures extend in the second direction and are located in the shallow trench isolation region and adjacent to multiple ends of the multiple fin structures, wherein the one or more second dummy gate structures include a main body extending in the second direction and one or more support structures extending from the main body in the first direction.

[0127] As another example, one or more of the semiconductor process equipment 102-112 and / or the wafer / bare die transport equipment 114 may perform a wet cleaning operation after etching one or more dummy gate layers, wherein during the wet cleaning operation, one or more support structures support one or more second dummy gate structures. As another example, one or more of the semiconductor process equipment 102-112 and / or the wafer / bare die transport equipment 114 may perform a wet cleaning operation after etching one or more dummy gate layers, wherein during the wet cleaning operation, one or more second dummy gate structures protect one or more first dummy gate structures. As another example, one or more of the semiconductor process equipment 102-112 and / or the wafer / bare die transport equipment 114 may form one or more source / drain regions on one or more fin structures after etching one or more dummy gate layers. After forming one or more source / drain regions, one or more first dummy gate structures and one or more second dummy gate structures are removed, wherein removing the one or more first dummy gate structures leaves one or more first grooves above the multiple fin structures, and removing the one or more second dummy gate structures leaves one or more second grooves above the shallow trench isolation region.

[0128] As another example, one or more of the semiconductor processing equipment 102-112 and / or the wafer / die transport equipment 114 may form one or more active gate structures in one or more first grooves, and / or, one or more inactive gate structures in one or more second grooves. As another example, one or more of the semiconductor processing equipment 102-112 and / or the wafer / die transport equipment 114 may form one or more spacer layers on multiple sidewalls of one or more support structures.

[0129] In other examples, one or more of the semiconductor processing equipment 102-112 and / or the wafer / die transport equipment 114 may perform other semiconductor processing operations described herein, such as FIG. 3A to FIG. 3D , Figures 4A to 4K , FIG. 5A to FIG. 5E , FIG. 6A to FIG. 6C and / or Fig.11 Related.

[0130] Figure 1 The number and arrangement of devices shown are provided as one or more examples. In practice, there may be more than Figure 1 The devices shown may include additional devices, fewer devices, different devices, or devices in a different arrangement. Figure 1 Two or more of the devices shown may be implemented as a single device, or, Figure 1 The individual devices shown may be implemented as multiple separate devices. Additionally or alternatively, one set of devices (eg, one or more devices) of the example environment 100 may perform one or more functions described as being performed by another set of devices of the example environment 100.

[0131] Figure 2 FIG. 2 is a schematic diagram of an example semiconductor device 200 of the present disclosure. In particular, Figure 2 An example of a device region 202 of a semiconductor device 200 is illustrated, which includes one or more transistors or other devices. The transistors may include fin transistors, such as fin field effect transistors (finFETs), nanostructure transistors, and / or other types of transistors. In some embodiments, the device region 202 includes a p-type metal oxide semiconductor (PMOS) region, an n-type metal oxide semiconductor (NMOS) region, a complementary metal oxide semiconductor (CMOS) region, and / or other types of device regions. FIG. 3A to FIG. 3D , Figures 4A to 4K , FIG. 5A to FIG. 5E and / or FIG. 6A to FIG. 6C include Figure 2 Schematic cross-sectional views of various portions of a device region 202 of the semiconductor device 200 are shown and correspond to various process stages of forming a fin transistor in the device region 202 of the semiconductor device 200 .

[0132] The semiconductor device 200 includes a substrate 204. The substrate 204 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate, such as a gallium arsenide (GaAs) substrate, a silicon on insulator (SOI) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, or other types of semiconductor substrates. The substrate 204 may include a circular / round substrate having a diameter of about 200 mm, a diameter of about 300 mm, or another diameter (e.g., 450 mm), etc. The substrate 204 may also be any polygonal, square, rectangular, curved, or other non-circular workpiece, such as a polygonal substrate.

[0133] The fin structure 206 is included on the substrate 204 (and / or extends above the substrate 204) for the device region 202. The fin structure 206 can provide an active region in which one or more devices (e.g., fin transistors) are formed. In some embodiments, the fin structure 206 includes a silicon (Si) material or another basic semiconductor material, such as germanium (Ge). In some embodiments, the fin structure 206 includes an alloy semiconductor material, such as silicon germanium (SiGe), gallium phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium arsenide (GaInP), or a combination thereof. In some embodiments, the fin structure 206 uses n-type and / or p-type dopants.

[0134] The fin structure 206 is manufactured by appropriate semiconductor process technology, such as masking, photolithography and / or etching processes. As an example, the fin structure 206 can be formed by etching a portion of the substrate 204 to form a groove in the substrate. Then, the isolation material can be filled in the groove, recessed or etched to form a shallow trench isolation region 208 above the substrate 204 and between the fin structure 206. Other manufacturing techniques for the shallow trench isolation region 208 and / or for the fin structure 206 can be used. The shallow trench isolation region 208 can electrically isolate adjacent active regions in the fin structure 206. The shallow trench isolation region 208 may include a dielectric material, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), low-k dielectric material and / or other suitable insulating materials. The shallow trench isolation region 208 may include a multilayer structure, for example, having one or more liner layers.

[0135] A dummy gate structure 210 (or a plurality of dummy gate structures 210) is included above (eg, substantially perpendicular to) the fin structure 206 in the device region 202. The dummy gate structure 210 engages the fin structure 206 on three or more sides of the fin structure 206. Figure 2 In the example shown, the dummy gate structure 210 includes a gate electrode layer 212, a hard mask layer 214 and / or a cap layer 216, etc. In some embodiments, the dummy gate structure 210 further includes a cap layer, one or more spacers and / or another suitable layer. The various layers of the dummy gate structure 210 can be formed by suitable deposition techniques and patterned by appropriate photolithography and etching techniques.

[0136] The term "dummy" as used herein refers to a sacrificial structure that will be removed at a later stage and replaced with another structure, such as a high dielectric constant dielectric and metal gate structure in a replacement gate process. The replacement gate process refers to the manufacturing of a gate structure at a later stage of the overall gate manufacturing process. Therefore, Figure 2 The illustrated configuration of the semiconductor device 200 may include an intermediate configuration, and additional semiconductor process operations may be performed on the semiconductor device 200 to further process the semiconductor device 200 .

[0137] The gate electrode layer 212 may include polysilicon (PO) material or other suitable materials. The gate electrode layer 212 may be formed by a suitable deposition process such as LPCVD or PECVD. The hard mask layer 214 may include any suitable material having a specific function / size (e.g., silicon nitride (Si x N y For example, Si3N4) is used to pattern the gate electrode layer 212. The cap layer 216 may include a dielectric oxide layer such as silicon oxide (SiOx, such as SiO2). The dielectric oxide layer may be formed by chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods.

[0138] In some embodiments, the layers of the dummy gate structure 210 are first deposited in the form of a blanket layer, and then the blanket layer is patterned by a process including photolithography and etching processes, a portion of the blanket layer is removed, and the remaining portion is retained on the shallow trench isolation region 208 and the fin structure 206 to form the dummy gate structure 210.

[0139] The source / drain region 218 is disposed at an opposite region of the fin structure 206 relative to the dummy gate structure 210. The source / drain region 218 includes a region of the device region 202 where a source / drain region is formed. The source / drain region may refer to a source or a drain individually or collectively, depending on the context. The source / drain region in the device region 202 includes silicon (Si) having one or more dopants, such as a p-type material (e.g., boron (B) or germanium (Ge), among other examples), an n-type material (e.g., phosphorus (P) or arsenic (As), etc.), and / or another type of dopant. Thus, the device region 202 may include a PMOS transistor with a p-type source / drain region, an NMOS transistor with an n-type source / drain region, and / or other types of transistors.

[0140] Some source / drain regions may be shared between various transistors in device region 202. In some embodiments, each of the source / drain regions may be connected or coupled together so that the fin transistor in device region 202 is implemented as two functional transistors. For example, if adjacent (e.g., as opposed to opposite) source / drain regions are electrically connected, such as by coalescing these regions through epitaxial growth (e.g., coalescing source / drain regions that are adjacent but not on opposite sides of dummy gate structure 210), two functional transistors may be realized. Other configurations in other examples may be implemented with other numbers of functional transistors.

[0141] In other examples, Figure 2 Further explanation of the reference cross-sections used in the following figures includes FIG. 3A to FIG. 3D , Figures 4A to 4K , FIG. 5A to FIG. 5E and / or FIG. 6A to FIG. 6C . Cross section AA is a plane along the fin structure 206 between the opposing source / drain regions 218. Cross section BB is a plane perpendicular to cross section AA and crosses the source / drain regions 218 in the fin structure 206. For clarity, subsequent figures refer to these reference cross sections. In some figures, some reference numbers of components or features shown therein may be omitted for ease of depiction to avoid obscuring other components or features.

[0142] As described herein, in some embodiments, the semiconductor device 200 includes one or more fin structures 206 extending above the substrate, wherein the one or more fin structures 206 extend in a first direction (e.g., an x-direction) in a top-down view of the semiconductor device 200. The semiconductor device 200 includes an active gate structure (replacing the dummy gate structure 210) surrounding at least three sides of the one or more fin structures 206, wherein the active gate structure extends in a second direction (e.g., a y-direction) substantially perpendicular to the first direction in a top-down view of the semiconductor device 200. The semiconductor device 200 includes a non-active gate structure (replacing the dummy gate structure 210) located on the shallow trench isolation region 208, wherein the non-active gate structure is adjacent to multiple ends of the one or more fin structures 206, wherein the non-active gate structure includes a body extending in a second direction and one or more support structures extending from the body in a first direction.

[0143] As mentioned above, Figure 2 Provided as an example, other examples may be Figure 2 Different than described.

[0144] FIG. 3A to FIG. 3D is from Figure 2 The cross-section BB of the device region 202 is shown from a perspective. Figure 3A , embodiment 300 includes semiconductor processing operations performed to form transistors in device region 202 in substrate 204 and / or on substrate 204 .

[0145] like Figure 3B As shown, the fin structure 206 is formed in the substrate 204 of the device area 202. In some embodiments, the pattern in the photoresist layer is used to form the fin structure 206. In these embodiments, the deposition device 102 forms the photoresist layer on the substrate 204. The exposure device 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The development device 106 develops and removes a portion of the photoresist layer to expose the pattern. The etching device 108 etches into the substrate 204 to form the fin structure 206. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, the photoresist removal device removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to the pattern-based formation of the fin structure 206.

[0146] like Figure 3C As shown, a shallow trench isolation layer 302 is formed between the fin structures 206. The deposition equipment 102 uses CVD technology, PVD technology, ALD technology, the above and Figure 1The shallow trench isolation layer 302 is deposited by using a related deposition technique and / or another deposition technique. In some embodiments, the shallow trench isolation layer 302 is formed to a height greater than the fin structure 206. In these embodiments, the planarization device 110 performs a planarization (or polishing) operation to planarize the shallow trench isolation layer 302 so that the upper surface of the shallow trench isolation layer 302 is substantially flat and smooth, and the upper surface of the shallow trench isolation layer 302 is substantially the same height as the upper surface of the fin structure 206. The planarization operation can increase the uniformity of the shallow trench isolation region 208 formed by the shallow trench isolation layer 302 in a subsequent etching operation.

[0147] like Figure 3D As shown, the shallow trench isolation layer 302 is etched during the etching operation to expose a portion of the fin structure 206. The etching equipment 108 etches a portion of the shallow trench isolation layer 302 using a plasma etching technique, a wet chemical etching technique, and / or another etching technique. The remaining portion of the shallow trench isolation layer 302 between the fin structures 206 includes the shallow trench isolation region 208. In some embodiments, the etching of the shallow trench isolation layer 302 causes the height of the exposed portion of the fin structure 206 (e.g., the portion of the fin structure 206 above the upper surface of the shallow trench isolation region 208) to be the same as the height in the device region 202. In some embodiments, etching a first portion of the shallow trench isolation layer 302 in the device region 202 and etching a second portion of the shallow trench isolation layer 302 in the device region 202 causes the height of the exposed portion of the first subset of the fin structure 206 to be different from the height of the exposed portion of the second subset of the fin structure 206, which allows the fin height to be adjusted to achieve specific performance characteristics of the device region 202.

[0148] As mentioned above, FIG. 3A to FIG. 3D Provided as an example, other examples may be FIG. 3A to FIG. 3D Different than described.

[0149] Figures 4A to 4K FIG. 4 is a schematic diagram of an embodiment 400 of the present disclosure. Embodiment 400 includes an example of forming source / drain regions 218 in device region 202 . Figures 4A to 4K The subset is from Figure 2 4. In some embodiments, operations associated with embodiment 400 are performed in conjunction with FIG. 3A to FIG. 3D The related fin formation process is performed afterwards.

[0150] Figure 4A 1 is a cross-sectional view of a portion of the semiconductor device 200 along the cross-section AA, including multiple end portions of the multiple fin structures 206. Figure 4AAs shown, the shallow trench isolation region 208 may extend between the ends of the plurality of fin structures 206 in the x-direction. The plurality of fin structures 206 may extend from the substrate 204 and may also extend onto the shallow trench isolation region 208.

[0151] Figure 4B 1 is a cross-sectional view of a portion of the semiconductor device 200 along the cross section AA. Figure 4B As shown, one or more layers may be formed over the plurality of fin structures 206 and / or over the shallow trench isolation region 208, and / or one or more layers may be formed over the shallow trench isolation region 208 and / or over the shallow trench isolation region 208. For example, a polysilicon layer 402 may be formed over the plurality of fin structures 206 and / or over the plurality of fin structures 206, and / or a polysilicon layer 402 may be formed over the shallow trench isolation region 208 and / or over the shallow trench isolation region 208. As another example, a hard mask layer 404 may be formed over the polysilicon layer 402 and / or over the polysilicon layer 402. As another example, a cap layer 406 may be formed over the hard mask layer 404 and / or over the hard mask layer 404.

[0152] The polysilicon layer 402 may include one or more layers of polysilicon material. The deposition apparatus 102 may be configured to perform PVD operations, ALD operations, CVD operations, epitaxial operations, oxidation operations, and the like. Figure 1 The polysilicon layer 402 is deposited in another type of deposition operation as described and / or in another suitable deposition operation. In some embodiments, the planarization apparatus 110 planarizes the polysilicon layer 402 after the deposition apparatus 102 deposits the polysilicon layer 402 .

[0153] The hard mask layer 404 may include any material suitable for patterning the polysilicon layer 402 with specific dimensions and / or features. In other examples, examples include silicon nitride, silicon nitride, silicon carbon nitride, or a combination thereof. The deposition apparatus 102 may be configured to perform a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, or a combination thereof. Figure 1 Depositing the hard mask layer 404 in another type of deposition operation and / or another suitable deposition operation is described in connection with the present invention. In some embodiments, the planarization apparatus 110 planarizes the hard mask layer 404 after the deposition apparatus 102 deposits the hard mask layer 404 .

[0154] The capping layer 406 may include a dielectric oxide material such as silicon oxide (eg, SiO x For example, SiO2) and / or other suitable dielectric materials. The deposition device 102 can be used in PVD operation, ALD operation, CVD operation, epitaxy operation, oxidation operation, and Figure 1Another type of deposition operation and / or another suitable deposition operation is described in relation to depositing the capping layer 406. In some embodiments, the planarization device 110 planarizes the capping layer 406 after the deposition device 102 deposits the capping layer 406.

[0155] like Figure 4C and Figure 4D As shown, a pattern may be formed in a photoresist (PR) layer. The pattern in the photoresist layer 408 may be used to etch the polysilicon layer 402, the hard mask layer 404 and / or the cap layer 406 to form one or more dummy gate structures 210. Figure 4C As shown, the deposition device 102 can form a photoresist layer 408 on the cap layer 406. The exposure device 104 can expose the photoresist layer 408 to a radiation source to pattern the photoresist layer 408. Figure 4D As shown, the developing device 106 may develop and remove a portion of the photoresist layer 408 to expose the pattern.

[0156] Figure 4E The top-down view of the semiconductor device 200 is shown, wherein the top-down features of the pattern pattern in the photoresist layer 408 are shown. Figure 4E As shown, the remaining portion of the photoresist layer 408 may extend in the y-direction in the semiconductor device 200. A first subset of the remaining portion of the photoresist layer 408 may extend through the one or more fin structures 206, and a second subset of the remaining portion of the photoresist layer 408 may be located adjacent to ends of the one or more fin structures 206 (e.g., the second subset of the remaining portion of the photoresist layer 408 is not located above the fin structures 206).

[0157] like FIG. 4F to FIG. 4H As shown, the etching device 108 can etch the polysilicon layer 402, the hard mask layer 404 and / or the cap layer 406 according to the pattern in the photoresist layer 408 to form the dummy gate structure 210a and the dummy gate structure 210b. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation and / or another type of etching operation. In some embodiments, the photoresist removal device removes the remaining portion of the photoresist layer 408 (for example, using a chemical stripper, plasma ashing and / or another technique).

[0158] like Figure 4F, a top-down view of the semiconductor device 200 is shown, where the dummy gate structure 210a may be located above and / or on top of one or more fin structures 206. The fin structures 206 may extend in an x-direction of the semiconductor device 200, and the dummy gate structure 210a may extend in a y-direction of the semiconductor device 200. The dummy gate structure 210a may be used as a place holder gate structure for a metal gate structure that subsequently replaces the dummy gate structure 210a, which enables a subset of semiconductor process operations to be performed without causing damage to the metal.

[0159] The dummy gate structure 210b may be located in the shallow trench isolation region 208 and adjacent to multiple ends of one or more fin structures 206. In other words, the dummy gate structure 210b is not above and / or on the fin structure 206. The dummy gate structure 210b may be referred to as an edge polysilicon gate structure because the dummy gate structure 210b is located at the edge of one or more fin structures 206. The dummy gate structure 210b may be included to reduce and / or prevent the possibility of damaging the dummy gate structure 210a. The dummy gate structure 210b may fill the space (e.g., unused space) between multiple rows of the fin structure 206. If the dummy gate structure 210b is not included, the space between the multiple ends of the multiple rows of the fin structure 206 may cause end loading during one or more semiconductor process operations. Back-end loading refers to the increase in force applied to the dummy gate structures 210a at or near the ends of the semiconductor device 200 during a semiconductor process operation (e.g., a CMP operation, a wet cleaning operation). The spaces between the ends of the rows of fin structures 206, if not filled with dummy gate structures 210b, may cause process materials and / or chemicals to accumulate and press against the dummy gate structures 210a at or near the ends of one or more fin structures 206. This may increase the likelihood of delamination and / or collapse of the dummy gate structures 210a at or near the ends of one or more fin structures 206.

[0160] like Figure 4F As further shown, one or more of the dummy gate structures 210b may include a body 410a and one or more support structures 410b. The body 410a may extend in a y direction (e.g., a direction substantially perpendicular to the direction in which the fin structure 206 extends). The one or more support structures 410b may extend from the body 410a in an x ​​direction such that the one or more support structures 410b are substantially perpendicular to the body 410a. Figure 4FAs shown, one or more of the dummy gate structures 210b may include a body 410a and one or more support structures 410b. The body 410a may extend in the y direction (e.g., a direction substantially perpendicular to the direction in which the fin structure 206 extends). The one or more support structures 410b may extend from the body 410a in the x direction, such that the one or more support structures 410b are substantially perpendicular to the body 410a.

[0161] One or more support structures 410b may be included to reduce and / or prevent the possibility of delamination, peeling and / or collapse of the dummy gate structure 210b. As described above, the dummy gate structure 210b may be included to reduce and / or prevent the possibility of damaging the dummy gate structure 210a during one or more semiconductor process operations. In these semiconductor process operations, the dummy gate structure 210b absorbs the force that may be applied to the dummy gate structure 210a. Therefore, the dummy gate structure 210b also has the risk of delamination, peeling and / or collapse in the semiconductor process operation. Therefore, one or more support structures 410b may be included to strengthen the dummy gate structure 210b, which increases the ability of the dummy gate structure 210b to absorb forces in the semiconductor process operation, especially the force in the x direction. The support structure 410b may have an approximately square configuration, a circular configuration, an approximately rectangular configuration, an approximately triangular configuration and / or another configuration.

[0162] like Figure 4FAs further shown, the dummy gate structure 210b may include one or more dimensions. An example dimension D1 may correspond to the length of the support structure 410b in the x-direction. Another example dimension D2 may correspond to the width of the support structure 410b in the y-direction. Another example dimension D3 may correspond to the length of the body 410a in the x-direction. In some embodiments, the length of the support structure 410b in the x-direction (e.g., dimension D1) may include a range of about 1.5 times to about 2.5 times the length of the body 410a in the x-direction (e.g., dimension D3) to provide sufficient structural support for the dummy gate structure 210b and achieve a sufficiently low probability of peeling, delamination, and / or collapse of the semiconductor device 200 during semiconductor processing. For example, if the length of the body 410a in the x-direction (e.g., dimension D3) is about 20 nanometers, the length of the support structure 410b in the x-direction (e.g., dimension D1) may include a range of about 30 nanometers to about 50 nanometers. However, other values ​​of this range are also within the scope of the present disclosure. In some embodiments, the width of the support structure 410b in the y-direction (e.g., dimension D2) may include a range of about 1.5 times to about 2.5 times the length of the body 410a in the x-direction (e.g., dimension D3) to provide sufficient structural support for the dummy gate structure 210b and achieve a sufficiently low probability of flaking, delamination, and / or collapse of the semiconductor device 200 during semiconductor processing. For example, if the length of the body 410a in the x-direction (e.g., dimension D3) is about 10 nanometers, the width of the support structure 410b in the y-direction (e.g., dimension D2) may include a range of about 15 nanometers to about 25 nanometers. However, other values ​​of this range are also within the scope of the present disclosure.

[0163] Figure 4G 2 is a perspective view showing a portion of the semiconductor device 200 after forming the dummy gate structure 210a and the dummy gate structure 210b. Figure 4G As shown, each dummy gate structure 210a and dummy gate structure 210b may include a gate electrode layer 212, a hard mask layer 214 and / or a cap layer 216. In some embodiments, the dummy gate structure 210a and / or the dummy gate structure 210b may include different combinations of multiple layers. The dummy gate structure 210a is formed and included on the fin structure 206 and surrounds multiple sides of the fin structure 206, so that the dummy gate structure 210 surrounds the fin structure 206 on at least three sides of the fin structure 206. The dummy gate structure 210b is formed and included adjacent to multiple ends of one or more fin structures 206, and is not included on the fin structure 206 and surrounds multiple sides of the fin structure 206.

[0164] like Figure 4GAs further shown, the bottom surface of the dummy gate structure 210b is located on the upper surface of the shallow trench isolation region 208. The bottom surface of the dummy gate structure 210b may be substantially flat across the entire bottom surface, while the bottom surface of the dummy gate structure 210a may have multiple portions located at different heights in the semiconductor device 200 because the dummy gate structure 210a surrounds one or more fin structures 206. For example, a first portion of the bottom surface of the dummy gate structure 210a may be located at a first height above the shallow trench isolation region 208, while a second portion of the bottom surface of the dummy gate structure 210a may be located at a second height above the fin structure 206, the second height being greater than the first height. The bottom surface of the dummy gate structure 210b (for the body 410a and one or more support structures 410b of the dummy gate structure 210b) may be located at a height in the semiconductor device 200 that is smaller / lower than the second height of the second portion of the bottom surface of the dummy gate structure 210a located on the fin structure 206. The height of the support structure 410 b may be substantially the same as the body 410 a of the dummy gate structure 210 b .

[0165] Figure 4H 1 is a cross-sectional view of a portion of the semiconductor device 200 along the cross section AA. Figure 4H As shown, the dummy gate structure 210a is formed and included above and / or on the fin structure 206. The dummy gate structure 210b is formed and included above and / or on the shallow trench isolation region 208 and adjacent to multiple ends of the fin structure 206. Since one or more supporting structures 410b extending in the x-direction are included, the width of the dummy gate structure 210b along the cross section AA in the x-direction may be greater than the width of the dummy gate structure 210a along the cross section AA in the x-direction.

[0166] In some embodiments, the height of the top surface of the dummy gate structure 210a in the semiconductor device 200 (e.g., may correspond to the top surface of the cap layer 216 included in the dummy gate structure 210a) and the height of the top surface of the dummy gate structure 210b in the semiconductor device 200 (e.g., may correspond to the top surface of the cap layer 216 included in the dummy gate structure 210b) may be substantially the same. In some embodiments, the height of the top surface of the dummy gate structure 210a in the semiconductor device 200 (e.g., may correspond to the top surface of the cap layer 216 included in the dummy gate structure 210a) may be greater than the height of the top surface of the dummy gate structure 210b in the semiconductor device 200 (e.g., may correspond to the top surface of the cap layer 216 included in the dummy gate structure 210b).

[0167] In some embodiments, a wet cleaning operation may be performed after etching the polysilicon layer 402, the hard mask layer 404, and the cap layer 406 to form the dummy gate structure 210a and the dummy gate structure 210b. The wet cleaning operation may include removing residual materials, contaminants, and / or native oxides from the semiconductor device 200 using one or more types of wet chemicals. The dummy gate structure 210b may protect the dummy gate structure 210a during the wet cleaning operation, thereby reducing the end load on the dummy gate structure 210a. In addition, one or more support structures 410b may support the dummy gate structure 210b during the wet cleaning operation, thereby reducing the possibility of peeling, delamination, and / or collapse of the dummy gate structure 210b.

[0168] like Fig. 4I As shown, sealing spacers 412 may be formed on the sidewalls of dummy gate structure 210a and dummy gate structure 210b. Sealing spacers 412 may be conformally deposited (e.g., by deposition apparatus 102) and may include silicon carbide (SiOC), nitrogen-free SiOC, or other suitable materials. In some embodiments, among other deposition techniques, sealing spacers 412 may be formed by an ALD operation, in which various types of precursor gases including silicon (Si) and carbon (C) are sequentially supplied in a plurality of alternating cycles to form sealing spacers 412.

[0169] like Fig. 4I As further shown, body spacer 414 may be formed on sealing spacer 412. Body spacer 414 may be formed of a similar material as sealing spacer 412. However, body spacer 414 may be formed without using the plasma surface treatment used for sealing spacer 412. Also, body spacer 414 may be formed to a greater thickness relative to the thickness of sealing spacer 412.

[0170] In some embodiments, the sealing spacers 412 and the body spacers 414 are conformally deposited on the dummy gate structures 210 a and 210 b and on the fin structure 206. The sealing spacers 412 and the body spacers 414 are then patterned (e.g., by the deposition apparatus 102, the exposure apparatus 104, and the development apparatus 106) and etched (e.g., by the etching apparatus 108) to remove the sealing spacers 412 and the body spacers 414 from the top of the dummy gate structures 210 a and 210 b and from the top of the fin structure 206.

[0171] Figure 4J 2 is a cross-sectional view of a portion of the semiconductor device 200 along the cross-section AA, including the fin structure 206. Figure 4JAs shown, a recess 416 is formed between the dummy gate structures 210a during the etching operation. The etching operation may be referred to as a first strained source / drain (SSD) etching operation, and the recess 416 may be referred to as a strained source / drain recess. In some embodiments, the etching device 108 may perform a first etching operation, which may include a plasma etching technique, a wet chemical etching technique, and / or another etching technique.

[0172] In some embodiments, multiple etching operations are performed to form the recesses 416 for different types of transistors. For example, a photoresist layer can be formed over and / or above a first subset of the fin structures 206 and over and / or above a first subset of the dummy gate structures 210 a so that a second subset of the fin structures 206 is between a second subset of the dummy gate structures 210 a so that p-type source / drain regions and n-type source / drain regions can be formed in separate epitaxial operations.

[0173] like Figure 4K As shown, source / drain region 418 is formed in recess 416 above substrate 204 of semiconductor device 200. Deposition device 102 forms source / drain region 418 by epitaxial operation, wherein epitaxial material layer is deposited in recess 416, so that layer of p-type source / drain region and / or layer of n-type source / drain region are formed by epitaxial growth in a specific crystal orientation. Source / drain region 418 is included in dummy gate structure 210a and is at least partially located below and / or below between dummy gate structures 210a. In addition, source / drain region 418 extends at least partially above the upper surface of fin structure 206.

[0174] The material used to form the source / drain regions 418 (e.g., silicon (Si), gallium (Ga), or other types of semiconductor materials) may be doped with a p-type dopant (e.g., a dopant that includes electron acceptor atoms that create holes in the material), an n-type dopant (e.g., a dopant that includes electron donor atoms that create mobile electrons in the material), and / or another type of dopant. The material may be doped by adding impurities (e.g., p-type dopants, n-type dopants) to the source gas used during the epitaxial operation. In other examples, examples of p-type dopants that may be used in the epitaxial operation include boron (B) or germanium (Ge), among others. The resulting p-type source / drain region material includes silicon germanium (Si x Ge 1-j , where j may be in the range of about 0 to about 100) or other types of p-doped semiconductor materials. In other examples, examples of n-type dopants that may be used in epitaxy operations include phosphorus (P) or arsenic (As), etc. The resulting n-type source / drain region material includes silicon phosphide (Si x P y) or another type of n-doped semiconductor material.

[0175] As mentioned above, Figures 4A to 4K Provided as an example, other examples can be Figures 4A to 4K The description is different.

[0176] FIG. 5A to FIG. 5E Schematic diagram of an embodiment 500 of the present disclosure. Embodiment 500 includes an example of a dummy gate replacement process, wherein the dummy gate structure 210a and the dummy gate structure 210b are replaced with a high-k gate structure and / or a metal gate structure. FIG. 5A to FIG. 5E is from Figure 2 The device region 202 is shown from the perspective of a cross section AA.

[0177] like Figure 5A As shown, a contact etch stop layer 502 (CESL) is conformally deposited (e.g., by deposition equipment 102) on the sidewalls of the source / drain regions 418, the dummy gate structures 210a and 210b, the exposed portions of the shallow trench isolation regions 208, and the main spacer 414. The contact etch stop layer 502 may provide a mechanism for stopping the etching process when forming contacts or vias for the semiconductor device 200. The contact etch stop layer 502 may be composed of a dielectric material having an etching selectivity different from that of adjacent layers or elements. The contact etch stop layer 502 may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Further, in other examples, the contact etch stop layer 502 may include or may be silicon nitride (Si x N y ), silicon carbon nitride (SiCN), carbon nitride (CN), silicon nitride (SiON), silicon oxycarbide (SiCO), or a combination thereof. The deposition device 102 may deposit the contact etch stop layer 502 using a conformal deposition process (eg, ALD, CVD, or other deposition techniques).

[0178] like Figure 5B As shown, an interlayer dielectric (ILD) layer is formed (e.g., by deposition equipment 102) above and / or on the contact etch stop layer 502. The interlayer dielectric layer 504 fills the area between the dummy gate structure 210a and the dummy gate structure 210b, the area above the source / drain region 418, and / or the area of ​​the exposed portion of the shallow trench isolation region 208. The formation of the interlayer dielectric layer 504 enables a replacement gate structure process to be performed in the semiconductor device 200, wherein a metal gate structure is formed to replace the dummy gate structure 210a and the dummy gate structure 210b. The interlayer dielectric layer 504 may be referred to as an ILD0 layer.

[0179] In some embodiments, the interlayer dielectric layer 504 is formed to a certain height (or thickness) so that the interlayer dielectric layer 504 covers the dummy gate structure 210a and / or the dummy gate structure 210b. In these embodiments, a subsequent CMP operation (e.g., performed by the planarization device 110) is performed to planarize the interlayer dielectric layer 504 so that the top surface of the interlayer dielectric layer 504 is substantially the same height as the top surface of the dummy gate structure 210a and / or the dummy gate structure 210b. The CMP operation increases the uniformity of the interlayer dielectric layer 504.

[0180] like Figure 5C As shown, a replacement gate operation is performed (e.g., by one or more of the semiconductor processing equipment 102-112) to remove the dummy gate structure 210a and the dummy gate structure 210b from the semiconductor device 200. Removing the dummy gate structure 210a leaves an opening (or recess 506a) between the body spacers 414 and between the source / drain regions 418. Removing the dummy gate structure 210b leaves an opening (or recess 506b) between the body spacers 414 above the shallow trench isolation region 208. The dummy gate structure 210a and the dummy gate structure 210b can be removed in one or more etching operations, including a plasma etching technique, which may include a wet chemical etching technique and / or another type of etching technique.

[0181] like Figure 5D As shown, the replacement gate operation continues, wherein the deposition apparatus and / or electroplating apparatus 112 forms a replacement gate structure in the recess 506a and the recess 506b. For example, the active gate structure 508a may form the recess 506a between the body spacers 414 and between the source / drain regions 418. The active gate structure 508a may be "active" because the active gate structure 508a may be a gate structure that performs an electrical function for a transistor in the semiconductor device 200. The active gate structure 508a may be included above and / or on one or more fin structures 206, and may surround at least three sides of the one or more fin structures 206. As another example, the non-active gate structure 508b may be formed between the body spacers 414 above the shallow trench isolation region 208. The non-active gate structure 508b may be "non-active" because the non-active gate structure 508b may be a gate structure that does not perform an electrical function for a transistor in the semiconductor device 200. The inactive gate structure 508 b may be a remnant of using the dummy gate structure 210 b. The inactive gate structure 508 b may be located adjacent to ends of one or more of the fin structures 206.

[0182] The active gate structure 508a and the non-active gate structure 508b may include a metal gate structure, a high dielectric constant gate structure, or other types of gate structures. The active gate structure 508a and the non-active gate structure 508b may include an interface layer (not shown), a high dielectric constant dielectric layer 510, a functional function adjustment layer 512, and a metal electrode structure 514 formed therein to form the active gate structure 508a and the non-active gate structure 508b. In some embodiments, the active gate structure 508a and the non-active gate structure 508b may include other compositions of materials and / or layers.

[0183] Figure 5E A top-down view of the semiconductor device 200 is shown after the active gate structure 508a and the inactive gate structure 508b are formed. Figure 5E As shown, the non-active gate structure 508b may include a body 410a and one or more supporting structures 410b. In some embodiments, the one or more non-active gate structures 508b, the body 410a of the non-active gate structure 508b and / or the one or more supporting structures 410b of the non-active gate structure 508b, and / or the non-active gate structure 508b of the one or more supporting structures 410b may include the above-mentioned FIG. 4F to FIG. 4H One or more configurations, features, properties and / or dimensions (eg, dimensions D1 to D3) of the dummy gate structure 210b. In some embodiments, one or more inactive gate structures 508b may be configured as follows in the semiconductor device 200: Fig. 7A , Figure 7B , FIG. 8A to FIG. 8D and / or 9A to 9D One or more configurations described in .

[0184] Thus, in some embodiments, the semiconductor device 200 may include one or more fin structures 206 extending above the substrate, wherein the one or more fin structures 206 extend in a first direction (e.g., x-direction) in a top-down view of the semiconductor device 200; an active gate structure 508a surrounds the one or more fin structures 206 on at least three sides of the one or more fin structures 206, wherein the active gate structure 508a extends in a second direction (e.g., y-direction) substantially perpendicular to the first direction in a top-down view of the semiconductor device 200; and a non-active gate structure 508b is located on the shallow trench isolation region 208, wherein the non-active gate structure 508b is adjacent to multiple ends of the one or more fin structures 206, including a main body 410a extending in the second direction and one or more support structures 410b extending from the main body 410a in the first direction.

[0185] As mentioned above, FIG. 5A to FIG. 5E Provided as an example, other examples may be FIG. 5A to FIG. 5E Different than described.

[0186] FIG. 6A to FIG. 6C 6 is a schematic diagram of an embodiment 600 of the present disclosure. Embodiment 600 includes an example of forming a conductive structure (eg, a metal gate contact or metal source / drain contacts (MDs)) in a device region 202 of a semiconductor device 200 . FIG. 6A to FIG. 6C from Figure 2 A perspective view of cross section AA of device region 202 is shown.

[0187] like Fig. 6A As shown, an opening 602 (or recess) is formed by one or more dielectric layers and the source / drain region 418. In particular, the contact etch stop layer 502 and the interlayer dielectric layer 504 are etched between the active gate structure 508a in the device region 202 to form the opening 602 between the active gate structure 508a and the source / drain region 418. In some embodiments, the opening 602 is formed in a portion of the source / drain region 418 such that the recess extends into a portion of the source / drain region 418. The opening 602 includes a bottom surface 602a corresponding to a top surface of the associated source / drain region 418, and sidewalls 602b corresponding to multiple sides of the contact etch stop layer 502 and / or multiple sides of the interlayer dielectric layer 504.

[0188] In some embodiments, the pattern in the photoresist layer is used to form the opening 602. In these embodiments, the deposition device 102 forms a photoresist layer on the interlayer dielectric layer 504 and the active gate structure 508a. The exposure device 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The development device 106 develops and removes a portion of the photoresist layer to expose the pattern. The etching device 108 etches in the interlayer dielectric layer 504 to form the opening 602. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, the photoresist removal device removes the remaining portion of the photoresist layer (for example, using a chemical stripper, plasma ashing and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to form the opening 602 according to the pattern.

[0189] like Figure 6BAs shown, a pre-cleaning operation is performed to clean the surface in the opening 602. In particular, the semiconductor device 200 can be placed in a first process chamber (e.g., a pre-cleaning process chamber) of the deposition apparatus 102, the first process chamber can be pumped to at least a partial vacuum (e.g., pressurized to a pressure within a range of about 5 Torr to about 10 Torr or another pressure), and the bottom surface 602a and the sidewalls 602b in the opening 602 are cleaned using a plasma and / or chemical pre-cleaning agent 604. The pre-cleaning operation is to clean (e.g., remove) oxides and other contaminants or byproducts on the top surface of the source / drain region 418, which may be formed after the opening 602 is formed.

[0190] like Figure 6C As shown, the conductive structure 606 is formed in the device region 202. In particular, the conductive structure 606 is formed above the opening 602 located between the active gate structures 508a and the source / drain region 418 in the opening 602. The deposition apparatus 102 and / or the electroplating apparatus 112 may be used by CVD technology, PVD technology, ALD technology, electroplating technology and / or the like. Figure 1 Another deposition technique is related. In some embodiments, one or more additional layers are formed before the opening 602 is formed. For example, a metal silicide layer (e.g., titanium silicide (TiSi)) may be formed on the top surface of the source / drain region 418 before the conductive structure 606 is formed. x ) or another metal silicide layer). As another example, one or more barrier layers may be formed on the bottom surface 602a and / or on the opening 602, and then the conductive structure 606 is formed. As another example, one or more adhesion layers may be formed on the bottom surface 602a and / or on the opening 602, and then the conductive structure 606 is formed.

[0191] As mentioned above, FIG. 6A to FIG. 6C Provided as an example. Other examples may be FIG. 6A to FIG. 6C The description is different.

[0192] Fig. 7A and Figure 7B is a schematic diagram of an embodiment of a semiconductor device 200 described herein. Fig. 7A and Figure 7B A top-down view of a semiconductor device 200 is shown, with a non-active gate structure configured as shown. As described herein, a non-active gate structure may include one or more support structures extending from a body of the non-active gate structure.

[0193] Fig. 7A An embodiment 700 of the semiconductor device 200 described herein is shown. Fig. 7AAs shown, the semiconductor device 200 may include a plurality of fin structures 206 extending in the x-direction of the semiconductor device 200. The semiconductor device 200 may also include one or more active gate structures 508a surrounding at least three sides of the one or more fin structures 206. The active gate structures 508a may extend in the y-direction of the semiconductor device 200, and the y-direction may be substantially perpendicular to the x-direction. Fig. 7A As shown, the semiconductor device 200 may include a plurality of inactive gate structures 508 b located adjacent to ends of one or more fin structures.

[0194] like Fig. 7A As further shown, multiple subsets of the fin structures 206 can be arranged in multiple fin groups 702. One fin group 702 can include multiple fin structures 206, and a subset of the active gate structure 508a can span across multiple fin structures 206. In other words, a subset of the active gate structure 508a can extend or span across the fin structures 206 in the fin group 702. In the semiconductor device 200, the fin groups 702 can be adjacent to each other in the x-direction and / or the y-direction.

[0195] like Fig. 7A As further shown, the semiconductor device 200 may include a plurality of non-active gate structures 508b. Each non-active gate structure 508b may be associated with a corresponding fin group 702 and may extend along the corresponding fin group 702. In other words, in the embodiment 700, the non-active gate structure 508b is included in the fin group 702 and does not extend more than one fin group 702 along it.

[0196] For example, a first plurality of fin structures 206 may be included in a first fin group 702, wherein at least one first active gate structure 508a extends through a second fin group 702, wherein a first non-active gate structure 508b extends along the first active gate structure 508a and along a plurality of ends of the fin structures 206 included in the fin group 702. A second plurality of fin structures 206 may be included in a second fin group 702 adjacent to the first fin group 702 and may extend in substantially the same direction as the fin structures 206 in the first fin group 702. A second active gate structure 508a may extend through the second fin group 702 and may surround at least three sides of the fin structures 206 in the second fin group 702. A second non-active gate structure 508b may be adjacent to a plurality of ends of the fin structures in the second fin group 702 and may extend along the second active gate structure 508a and along a plurality of ends of the fin structures 206 in the second fin group 702.

[0197] Each of the first and second inactive gate structures 508 b may be located in the shallow trench isolation region 208 of the semiconductor device 200 and may include a body 410 a extending in the y-direction and one or more support structures 410 b extending from the body 410 a in the x-direction.

[0198] like Fig. 7A As further shown, the non-active gate structure 508b may be included in a region of the semiconductor device 200, wherein the non-active gate structure 508b is adjacent to another active structure in the semiconductor device 200 (e.g., another region associated with the non-active gate structure 508b that is not included in the fin set 702). Here, the distance (denoted as dimension D4) between the non-active gate structure 508b and the other active structure in the semiconductor device 200 satisfies a distance threshold. In some embodiments, the distance threshold (e.g., an amount that may correspond to a threshold of the spacing) may be based on an active gate structure spacing (denoted as dimension D5) of the active gate structure 508a in the semiconductor device 200. The active gate structure spacing may refer to the distance between the same edges of adjacent active gate structures 508a (e.g., the left side of adjacent active gate structures 508a, the right side of adjacent active gate structures 508a). In some embodiments, the distance threshold is at least twice the size of the active gate structure spacing (e.g., dimension D5) of the semiconductor device 200 to provide sufficient distance from the active structure in the semiconductor device 200. However, other values ​​of the distance threshold are also within the scope of the present disclosure.

[0199] Figure 7B An embodiment 710 of the semiconductor device 200 described herein is shown. Figure 7B As shown, an embodiment 710 of the semiconductor device 200 may include Fig. 7A 2. However, Figure 7B The embodiment 710 of the semiconductor device 200 shown in FIG. 7 includes at least one inactive gate structure 508 b extending continuously along the plurality of fin groups 702 .

[0200] For example, the semiconductor device 200 may include a first plurality of fin structures 206 included in a first fin group 702, and a first active gate structure 508a extending through the first fin group 702. The semiconductor device 200 may also include a second plurality of fin structures 206 included in a second fin group 702 adjacent to the first fin group 702 extending in the x-direction, and a second active gate structure 508a extending through the second fin group 702 in the y-direction. Figure 7BAs shown in the example of FIG. 5 , the semiconductor device 200 may further include an inactive gate structure 508 b extending continuously along the first active gate structure 508 a and the second active gate structure 508 a and crossing the first fin set 702 and the second fin set 702 .

[0201] As mentioned above, Fig. 7A and Figure 7B Provided as an example. Other examples can be found with Fig. 7A and Figure 7B In some embodiments, the semiconductor device 200 may include a non-active gate structure 508b extending along a single fin group (eg, Fig. 7A ) and the non-active gate structure 508b extends along a plurality of fin groups (eg, as shown in the embodiment 700 in FIG. 1 ). Figure 7B A combination of the two (as shown in Example 710).

[0202] FIG. 8A to FIG. 8D is a schematic diagram of an embodiment of a semiconductor device 200 described herein. FIG. 8A to FIG. 8D A top-down view of a semiconductor device 200 is shown, illustrating an embodiment of a non-active gate structure configuration. As described herein, a non-active gate structure may include one or more support structures extending from a body of the non-active gate structure. FIG. 8A to FIG. 8D The illustrated embodiment of the semiconductor device 200 includes various inactive gate structures, wherein adjacent inactive gate structures have the same number of support structures and / or a symmetrical arrangement of support structures.

[0203] Fig. 8A An embodiment 800 of a semiconductor device 200 described herein is shown. The semiconductor device 200 may include one or more first fin structures 206 extending above a substrate, wherein the one or more first fin structures 206 extend in a first direction (e.g., an x-direction) in a top-down view of the semiconductor device 200. The semiconductor device 200 may include one or more first active gate structures 508a surrounding at least three sides of the one or more first fin structures 206, wherein the one or more first active gate structures 508a extend in a second direction (e.g., a y-direction) in a top-down view of the semiconductor device 200. The second direction is substantially perpendicular to the first direction (e.g., the x-direction).

[0204] like Fig. 8AAs shown, the semiconductor device 200 may include a first non-active gate structure 802a (e.g., non-active gate structure 508b) on the shallow trench isolation region 208, wherein the first non-active gate structure 802a is adjacent to multiple ends of one or more first fin structures 206. The first non-active gate structure 802a may include a first body 410a extending in a second direction (e.g., y-direction) and one or more first support structures 410b extending in a first direction (e.g., x-direction).

[0205] The semiconductor device 200 may include one or more second fin structures 206 extending above the substrate, wherein the one or more second fin structures 206 extend in a first direction (e.g., in the x-direction). The semiconductor device 200 may include one or more second active gate structures 508a surrounding at least three sides of the one or more second fin structures 206, wherein the one or more second active gate structures 508a extend in a second direction (e.g., in the y-direction).

[0206] like Fig. 8A As shown, the semiconductor device 200 may include a second non-active gate structure 802b (e.g., non-active gate structure 508b) on the shallow trench isolation region 208 and adjacent to the first non-active gate structure 802a. The second non-active gate structure 802b is adjacent to multiple ends of one or more second fin structures 206. The second non-active gate structure 802b may include a second body 410a extending in a second direction (e.g., y-direction) and one or more second support structures 410b extending from a first direction (e.g., x-direction).

[0207] like Fig. 8A As further shown, one or more first support structures 410b may extend from one side of the first body 410a, and one or more support structures 410b may extend from one side of the second body 410a. The side of the first body 410a is different from the side of the second body 410a. In this way, one or more first support structures 410b of the first non-active gate structure 802a and one or more first support structures 410b of the one or more second support structures 410b are opposite to each other. Therefore, one or more first fin structures 206 may be located on the first side of the first body 410a of the first non-active gate structure 802a, and one or more first support structures 410b may be located on the second side of the first body 410a of the first non-active gate structure 802a, wherein the first side and the second side are opposite. In other words, one or more first support structures 410b of the first non-active gate structure 802a may face away from the one or more first fin structures 206 and face the second non-active gate structure 802b.

[0208] One or more second fin structures 206 may be located on a first side of the second body 410a of the second non-active gate structure 802b, and one or more second support structures 410b may be located on a second side of the second body 410a of the second non-active gate structure 802b, wherein the first side and the second side are opposite. In other words, the one or more second support structures 410b of the second non-active gate structure 802b may face away from the one or more second fin structures 206 and toward the first non-active gate structure 802a.

[0209] Alternatively, the one or more first support structures 410 b and / or the one or more second support structures 410 b may be arranged in different configurations. For example, the one or more first support structures 410 b of the first non-active gate structure 802 a may face the one or more fin structures 206 , and / or the one or more second support structures 410 b of the second non-active gate structure 802 b may face the one or more second fin structures 206 .

[0210] like Fig. 8A As further shown, in the embodiment 800, the first non-active gate structure 802a and the second non-active gate structure 802b may include the same number of support structures 410b (e.g., three support structures 410b). In addition, one or more first support structures 410b of the first non-active gate structure 802a and one or more second support structures 410b of the second non-active gate structure 802b may be arranged in a symmetrical configuration, wherein each of the one or more first support structures 410b is aligned along a second direction (e.g., y-direction). In other words, the arrangement of the one or more first support structures 410b and the arrangement of the one or more second support structures 410b are mirror images in the second direction (e.g., y-direction). Alternatively, a subset of the one or more first support structures 410b is related to the one or more second support structures 410b along the second direction (e.g., y-direction).

[0211] Figure 8B An embodiment 810 is shown in which a first non-active gate structure 812a and a second non-active gate structure 812b may include the same number of support structures 410b (e.g., two support structures 410b). The first support structure 410b of the first non-active gate structure 812a may be located at opposite ends of the first body 410a of the first non-active gate structure 812a. The second support structure 410b of the second non-active gate structure 812b may be located at opposite ends of the second body 410a of the second non-active gate structure 812b.

[0212] The first support structures 410b of the first non-active gate structure 812a and the first support structures 410b of the second non-active gate structure 812b may be arranged symmetrically, wherein each of the first support structures 410b is aligned with an associated one of the one or more second support structures 410b along the second direction (e.g., the y-direction). Alternatively, a subset of the first support structures 410b is aligned with an associated one of the second support structures 410b along the second direction (e.g., the y-direction).

[0213] Figure 8C An embodiment 820 is shown in which a first non-active gate structure 822a and a second non-active gate structure 822b may include the same number of support structures 410b (e.g., four support structures 410b). The first support structure 410b of the first non-active gate structure 822a and the first support structure 410b of the second non-active gate structure 822b may be symmetrically configured, wherein each of the first support structures 410b is aligned with an associated one of the one or more second support structures 410b along a second direction (e.g., the y-direction). Additionally and / or alternatively, a subset of the first support structures 410b is aligned with an associated one of the subset of the second support structures 410b along the second direction (e.g., the y-direction). Additionally and / or alternatively, two or more adjacent non-active gate structures in the semiconductor device 200 may include different numbers of support structures.

[0214] Fig.8D An embodiment 830 is shown in which the first non-active gate structure 832a and the second non-active gate structure 832b may include the same number of support structures 410b (e.g., two support structures 410b). The first support structure 410b of the first non-active gate structure 832a may be oriented toward the center of the first body 410a of the first non-active gate structure 832a, rather than being located at opposite ends of the first body 410a as in the embodiment 810. The second support structure 410b of the second non-active gate structure 832b may be oriented toward the center of the second body 410a of the second non-active gate structure 832b, rather than being located at opposite ends of the second body 410a as in the embodiment 810.

[0215] The first support structures 410b of the first non-active gate structure 832a and the first support structures 410b of the second non-active gate structure 832b may be symmetrically arranged, wherein each of the first support structures 410b is aligned with an associated one of the one or more second support structures 410b along the second direction (e.g., the y-direction). Alternatively, a subset of the first support structures 410b is aligned with an associated one of the subset of the second support structures 410b along the second direction (e.g., the y-direction).

[0216] As mentioned above, FIG. 8A to FIG. 8D Provided as an example. Other examples may be FIG. 8A to FIG. 8D For example, in the semiconductor device 200, one or more inactive gate structures may include FIG. 8A to FIG. 8D The embodiments shown have different numbers of support structures and / or different arrangements of support structures.

[0217] 9A to 9D is a schematic diagram of an embodiment of the present disclosure. 9A to 9D A top-down view of a semiconductor device 200 is shown, illustrating an embodiment of a non-active gate structure configuration. As described herein, a non-active gate structure may include one or more support structures extending from a body of the non-active gate structure. 9A to 9D The illustrated embodiments of the semiconductor device 200 include various configurations of inactive gate structures in which support structures of the gate structures are offset and / or mirrored with respect to one another.

[0218] Fig.9A An embodiment 900 of a semiconductor device 200 is shown. The semiconductor device 200 may include one or more first fin structures 206 extending above a substrate, wherein the one or more first fin structures 206 extend in a first direction (e.g., an x-direction) in a top-down view of the semiconductor device 200. The semiconductor device 200 may include one or more first active gate structures 508a surrounding at least three sides of the one or more first fin structures 206, wherein the one or more first active gate structures 508a extend in a second direction (e.g., a y-direction) in a top-down view of the semiconductor device 200. The second direction is substantially perpendicular to the first direction (e.g., the x-direction).

[0219] like Fig.9A As shown, the semiconductor device 200 may include a first non-active gate structure 902a (e.g., non-active gate structure 508b) on the shallow trench isolation region 208, wherein the first non-active gate structure 902a is adjacent to multiple ends of one or more first fin structures 206. The first non-active gate structure 902a may include a first body 410a extending in a second direction (e.g., y-direction) and one or more first support structures 410b extending in a first direction (e.g., x-direction).

[0220] The semiconductor device 200 may include one or more second fin structures 206 extending above the substrate, wherein the one or more second fin structures 206 extend in a first direction (e.g., x-direction). The semiconductor device 200 may include one or more second active gate structures 508a surrounding at least three sides of the one or more second fin structures 206, wherein the one or more second active gate structures 508a extend in a second direction (e.g., y-direction).

[0221] like Fig.9AAs shown, the semiconductor device 200 may include a second non-active gate structure 902b (e.g., non-active gate structure 508b) on the shallow trench isolation region 208 and adjacent to the first non-active gate structure 902a. The second non-active gate structure 902b is adjacent to multiple ends of one or more second fin structures 206. The second non-active gate structure 902b may include a second body 410a extending in a second direction (e.g., y-direction) and one or more second support structures 410b extending in a first direction (e.g., x-direction).

[0222] like Fig.9A As further shown, one or more first support structures 410b may extend from one side of the first body 410a, and one or more support structures 410b may extend from one side of the second body 410a. The side of the first body 410a is different from the side of the second body 410a, so that the one or more first support structures 410b of the first non-active gate structure 902a and the one or more second support structures 410b of the second non-active gate structure 902b are opposite to each other. Therefore, the one or more first fin structures 206 may be located on the first side of the first body 410a of the first non-active gate structure 902a, and the one or more first support structures 410b may be located on the second side of the first body 410a of the first non-active gate structure 902a, wherein the first side and the second side are opposite sides. In other words, the one or more first support structures 410b of the first non-active gate structure 902a may face away from the one or more first fin structures 206 and face the second non-active gate structure 902b.

[0223] One or more second fin structures 206 may be located on a first side of the second body 410a of the second non-active gate structure 802b, and one or more second support structures 410b may be located on a second side of the second body 410a of the second non-active gate structure 902b, wherein the first side and the second side are opposite sides. In other words, the one or more second support structures 410b of the second non-active gate structure 902b may face away from the one or more second fin structures 206 and toward the first non-active gate structure 902a.

[0224] Alternatively, the one or more first support structures 410 b and / or the one or more second support structures 410 b may be arranged in different configurations. For example, the one or more first support structures 410 b of the first non-active gate structure 902 a may face the one or more fin structures 206 , and / or the one or more second support structures 410 b may face the one or more second fin structures 206 .

[0225] like Fig.9AAs further shown, in the embodiment 900, the first non-active gate structure 902a and the second non-active gate structure 902b may include the same number of support structures 410b (e.g., two support structures 410b). In addition, one or more first support structures 410b of the first non-active gate structure 902a and one or more second support structures 410b of the second non-active gate structure 902b may be arranged in an offset configuration, wherein each of the one or more first support structures 410b is offset from the one or more second support structures 410b along a second direction (e.g., y-direction). In other words, each of the one or more first support structures 410b is not aligned with the one or more second support structures 410b along the second direction (e.g., y-direction). Alternatively, a subset of the one or more first support structures 410b may be offset from the one or more second support structures 410b along the second direction (e.g., y-direction). Additionally and / or alternatively, two or more adjacent non-active gate structures in the semiconductor device 200 may include different numbers of support structures.

[0226] like Fig.9A As further shown, the arrangement of the one or more first support structures 410b and the arrangement of the one or more second support structures 410b may be mirror images in a first direction (e.g., the x-direction). In other words, the arrangement of the one or more first support structures 410b and the arrangement of the one or more second support structures 410b may be mirror images of opposite arrangements in the first direction, wherein the arrangement of the one or more first support structures 410b is flipped in the x-direction relative to the arrangement of the one or more second support structures 410b, and vice versa.

[0227] Fig. 9B An embodiment 910 is shown in which the first non-active gate structure 912a and the second non-active gate structure 912b may include the same number of support structures 410b (eg, two support structures 410b). Fig. 9B As further shown, the arrangement of the one or more first support structures 410b of the first non-active gate structure 912a and the arrangement of the one or more second support structures 410b of the second non-active gate structure 912b may be mirror images in a first direction (e.g., the x-direction). In other words, the arrangement of the one or more first support structures 410b and the arrangement of the one or more second support structures 410b may be mirror images in the first direction, wherein the arrangement of the one or more first support structures 410b is flipped in the x-direction relative to the arrangement of the one or more second support structures 410b, and vice versa.

[0228] In addition, one or more first support structures 410b of the first non-active gate structure 912a and one or more second support structures 410b of the second non-active gate structure 912b may be arranged in an offset configuration, wherein each of the one or more first support structures 410b is offset from the plurality of second support structures 410b along a second direction (e.g., y-direction). In other words, each of the one or more first support structures 410b is not aligned with the one or more second support structures 410b along the second direction (e.g., y-direction). Alternatively, a subset of the one or more first support structures 410b may be offset from the one or more second support structures 410b along the second direction (e.g., y-direction).

[0229] Fig. 9C An embodiment 920 is shown in which the first non-active gate structure 922a and the second non-active gate structure 922b may include the same number of support structures 410b (eg, three support structures 410b). Fig. 9C As further shown, the arrangement of the one or more first support structures 410b of the first non-active gate structure 922a and the arrangement of the one or more second support structures 410b of the second non-active gate structure 922b may be mirror images in a first direction (e.g., the x-direction). In other words, the arrangement of the one or more first support structures 410b and the arrangement of the one or more second support structures 410b may be opposite arrangements mirrored in the first direction, wherein the arrangement of the one or more first support structures 410b is flipped in the x-direction relative to the arrangement of the one or more second support structures 410b, and vice versa.

[0230] In addition, a subset of one or more first support structures 410b of the first non-active gate structure 922a and a subset of one or more second support structures 410b of the second non-active gate structure 922b may be arranged in an offset configuration, wherein each subset of the one or more first support structures 410b is offset from a subset of the one or more second support structures 410b along a second direction (e.g., y-direction). Another subset of the one or more first support structures 410b may be aligned with another subset of the one or more second support structures 410b along the second direction (e.g., y-direction).

[0231] Fig.9D An embodiment 930 is shown in which the first non-active gate structure 932a and the second non-active gate structure 932b may include the same number of support structures 410b (eg, three support structures 410b). Fig.9DAs further shown, the arrangement of the one or more first support structures 410b of the first non-active gate structure 932a and the arrangement of the one or more second support structures 410b of the second non-active gate structure 932b may be mirror images in a first direction (e.g., the x-direction). In other words, the arrangement of the one or more first support structures 410b and the arrangement of the one or more second support structures 410b in the first direction may be mirror images of opposite arrangements, wherein the arrangement of the one or more first support structures 410b is flipped in the x-direction relative to the arrangement of the one or more second support structures 410b, and vice versa.

[0232] In addition, a subset of one or more first support structures 410b of the first non-active gate structure 932a and a subset of one or more second support structures 410b of the second non-active gate structure 932b may be arranged in an offset configuration, wherein each subset of the one or more first support structures 410b is offset from a subset of the one or more second support structures 410b along a second direction (e.g., y-direction). Another subset of the one or more first support structures 410b may be aligned with another subset of the one or more second support structures 410b along the second direction (e.g., y-direction).

[0233] As mentioned above, 9A to 9D An example is provided. Other examples can be found with 9A to 9D For example, one or more inactive gate structures included in the semiconductor device 200 may include 9A to 9D The described embodiments have different numbers of support structures and / or different arrangements of support structures.

[0234] Fig.10 1 is a schematic diagram of an example of components of the apparatus 1000 described herein. In some embodiments, one or more semiconductor processing equipment 102-112 and / or wafer / die transport equipment 114 may include one or more apparatuses 1000 and / or one or more components of the apparatus 1000. Fig.10 As shown, device 1000 may include a bus 1010 , a processor 1020 , a memory 1030 , an input component 1040 , an output component 1050 , and / or a communication component 1060 .

[0235] The bus 1010 may include a plurality of bus components that may enable wired or wireless communication between components of the device 1000. ... Fig.10Components are coupled together, such as by operational coupling, communication coupling, electronic coupling, and / or electrical coupling, etc. For example, bus 1010 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless buses. Processor 1020 may include a central process unit, an image process unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable logic gate array, a specific application integrated circuit, and / or another type of process component. Processor 1020 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1020 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

[0236] The memory 1030 may include volatile and / or non-volatile memory. For example, the memory 1030 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and / or another memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 1030 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connection). The memory 1030 may be a non-transitory computer-readable medium. The memory 1030 may store information related to the operation of the device 1000, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, the memory 1030 may include one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 1020), such as via the bus 1010. The communicative coupling between the processor 1020 and the memory 1030 may enable the processor 1020 to read and / or process information stored in the memory 1030 and / or store information in the memory 1030 .

[0237] Input component 1040 enables device 1000 to receive input, such as user input and / or sensory input. For example, input component 1040 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a GPS sensor, a GNSS sensor, an accelerometer, a gyroscope, and / or an actuator. Output component 1050 enables device 1000 to provide output, such as via a display, a speaker, and / or a light emitting diode. Communication component 1060 enables device 1000 to communicate with other devices via a wired connection and / or a wireless connection. For example, communication component 1060 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0238] The device 1000 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 1030) may store a set of instructions (e.g., one or more instructions or codes) for execution by the processor 1020. The processor 1020 may execute the instruction set to perform one or more operations or processes described herein. In some embodiments, a set of instructions is executed by one or more processors 1020, causing one or more processors 1020 and / or the device 1000 to perform one or more operations or processes described herein. In some embodiments, it may be used instead of or in combination with instructions to perform one or more operations or processes described herein. Additionally or alternatively, the processor 1020 may be configured to perform one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuits and software.

[0239] Fig.10 The number and arrangement of components shown are provided as an example. Apparatus 1000 may include Fig.10 The components shown may be more components, fewer components, different components, or components in a different arrangement. Additionally or alternatively, one set of components (eg, one or more components) of device 1000 may perform one or more functions described as being performed by another set of components of device 1000.

[0240] Fig.11 1100 is a flowchart of an example of a process 1100 for forming a semiconductor device. In some embodiments, Fig.11 One or more processes of the block of may be performed by one or more semiconductor process equipment (eg, one or more of the semiconductor process equipment 102-112). Additionally or alternatively, Fig.11 One or more processes of the blocks may be performed by one or more components of the device 1000 , for example, the processor 1020 , the memory 1030 , the input component 1040 , the output component 1050 , and / or the communication component 1060 .

[0241] like Fig.11 As shown, process 1100 may include forming a plurality of fin structures on a substrate of a semiconductor device (block 1110). For example, as described herein, one or more of semiconductor processing equipment 102-112 may form a plurality of fin structures 206 on substrate 204 of semiconductor device 200. In some embodiments, the plurality of fin structures 206 extend in a first direction (e.g., an x-direction) in a top-down view of the semiconductor device.

[0242] like Fig.11As further shown, the process 1100 may include forming a shallow trench isolation region on the substrate between the plurality of fin structures and the plurality of ends adjacent to the plurality of fin structures (block 1120). For example, as described herein, one or more semiconductor processing equipment 102-112 may form a shallow trench isolation region 208 on the substrate 204 between the plurality of fin structures 206 and the plurality of ends adjacent to the plurality of fin structures 206. In some embodiments, the plurality of fin structures extend above the shallow trench isolation region.

[0243] like Fig.11 As further shown, the process 1100 may include forming one or more dummy gate layers in the shallow trench isolation region and surrounding the plurality of fin structures (block 1130). For example, as described herein, one or more semiconductor processing equipment 102-112 may form one or more dummy gate layers (e.g., polysilicon layer 402, hard mask layer 404 and / or cap layer 406) in the shallow trench isolation region 208 and surrounding the plurality of fin structures 206.

[0244] like Fig.11 As further shown, the process 1100 may include etching one or more dummy gate layers according to a pattern to form one or more first dummy gate structures extending in a second direction substantially perpendicular to the first direction in a top-down view of the semiconductor device, and one or more second dummy gate structures extending in the second direction and located in the shallow trench isolation region and adjacent to multiple ends of the multiple fin structures (block 1140). For example, as described herein, one or more of the semiconductor processing equipment 102-112 may etch one or more dummy gate layers according to a pattern to form one or more first dummy gate structures 210a extending in a second direction (e.g., y-direction) substantially perpendicular to the first direction in a top-down view of the semiconductor device 200, and one or more second dummy gate structures 210b extending in the second direction and located in the shallow trench isolation region 208 and adjacent to multiple ends of the multiple fin structures 206. In some embodiments, the one or more first dummy gate structures 210a surround the multiple fin structures 206 on at least three sides of the multiple fin structures 206. In some embodiments, the one or more second dummy gate structures include a body 410 a extending in the second direction and one or more support structures 410 b extending from the body 410 a in the first direction.

[0245] Process 1100 may include additional embodiments, such as any single embodiment or any combination described below and / or in connection with one or more other processes described elsewhere herein.

[0246] In a first embodiment, the process 1100 includes performing a wet cleaning operation after etching the one or more dummy gate layers, wherein the one or more support structures 410 b support the one or more second dummy gate structures 210 b during the wet cleaning operation.

[0247] In a second embodiment, alone or in combination with the first embodiment, the process 1100 includes performing a wet cleaning operation after etching the one or more dummy gate layers, wherein during the wet cleaning operation, the one or more second dummy gate structures 210b protect the one or more first dummy gate structures 210a.

[0248] In a third embodiment, either alone or in combination with the first and second embodiments, the process 1100 includes forming one or more source / drain regions 418 on one or more fin structures 206 after etching the one or more dummy gate layers. After forming the one or more source / drain regions 418, removing the one or more first dummy gate structures 210a and the one or more second dummy gate structures 210b, wherein the removal of the one or more first dummy gate structures 210a leaves one or more first recesses 506a above the plurality of fin structures 206, and the removal of the one or more second dummy gate structures 210b leaves one or more second recesses 506b above the shallow trench isolation region 208.

[0249] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, the process 1100 includes forming one or more active gate structures 508a in the one or more first recesses 506a and forming one or more inactive gate structures 508b in the one or more second recesses 506b.

[0250] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the process 1100 includes forming one or more spacer layers (eg, sealing spacer 412, body spacer 414) on multiple sidewalls of one or more support structures 410b.

[0251] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the ends of the plurality of fin structures 206 are adjacent to a first side of the body 410a. One or more support structures 410b extend from a second side of the body opposite to the first side.

[0252] Although Fig.11 Example blocks of process 1100 are shown, but in some embodiments, process 1100 includes Fig.11 Additional blocks, fewer blocks, different blocks, or differently arranged blocks may be performed in accordance with those described in the process 1100. Additionally or alternatively, two or more blocks of the process 1100 may be performed simultaneously.

[0253] In this way, a non-active gate structure is formed above a shallow trench isolation region, the shallow trench isolation region being adjacent to at least one fin structure of a semiconductor device including a fin transistor. The non-active gate structure includes at least one support structure extending from the gate in a direction that is substantially orthogonal to the direction in which the main body of the non-active gate structure extends. The support structure provides structural support for the non-active gate structure, which increases the stability of the non-active gate structure relative to a gate structure that does not include a support structure.

[0254] As described in more detail above, the present disclosure provides a semiconductor device. The semiconductor device includes one or more fin structures extending above a substrate, wherein the one or more fin structures extend in a first direction in a top-down view of the semiconductor device. The semiconductor device includes an active gate structure surrounding the one or more fin structures on at least three sides of the one or more fin structures, wherein the active gate structure extends in a second direction substantially perpendicular to the first direction in a top-down view of the semiconductor device. The semiconductor device includes a non-active gate structure located on a shallow trench isolation region, wherein the non-active gate structure is adjacent to multiple ends of the one or more fin structures, wherein the non-active gate structure includes a body extending in a second direction and one or more support structures extending from the body in a first direction.

[0255] In some embodiments, the plurality of ends of the one or more fin structures are adjacent to the first side of the body. The one or more support structures extend from a second side of the body opposite the first side.

[0256] In some embodiments, a distance between one or more support structures and another active structure in the semiconductor device satisfies a distance threshold, which is at least twice the size of a pitch of an active gate structure of the semiconductor device.

[0257] In some embodiments, one or more fin structures include a first plurality of fin structures included in a first fin group. The active gate structure includes a first active gate structure extending through the first fin group. The non-active gate structure includes a first non-active gate structure extending along the first active gate structure. The semiconductor device also includes a second plurality of fin structures, a second active gate structure, and a second non-active gate structure. The second plurality of fin structures are included in a second fin group adjacent to the first fin group and extend in a first direction. The second active gate structure extends through the second fin group in a second direction and surrounds at least three sides of the second plurality of fin structures. The second non-active gate structure is adjacent to multiple ends of the second plurality of fin structures and extends along the second active gate structure, wherein the second non-active gate structure includes a main body and one or more support structures. The main body extends in the second direction. One or more support structures extend from the main body of the second non-active gate structure in the first direction.

[0258] In some embodiments, a width of the support structure of the one or more support structures in the second direction comprises a range from about 1.5 times to about 2.5 times the length of the body in the first direction.

[0259] In some embodiments, the one or more fin structures include a first plurality of fin structures included in a first fin group. The active gate structure includes a first active gate structure extending through the first fin group. The semiconductor device also includes a second plurality of fin structures and a second active gate structure. The second plurality of fin structures are included in a second fin group adjacent to the first fin group and extend in a first direction. The second active gate structure extends through the second fin group in a second direction, wherein the non-active gate structure extends continuously along the first active gate structure and the second active gate structure and across the first fin group and the second fin group.

[0260] In some embodiments, the length of the support structure of the one or more support structures in the first direction is in the range of about 1.5 times to about 2.5 times the length of the body in the first direction.

[0261] As described in more detail above, the present disclosure provides a method for forming a semiconductor device. The method includes forming a plurality of fin structures on a substrate of the semiconductor device, wherein the plurality of fin structures extend in a first direction in a top-down view of the semiconductor device. The method includes forming a shallow trench isolation region on the substrate between the plurality of fin structures and adjacent to the plurality of ends of the plurality of fin structures, wherein the plurality of fin structures extend above the shallow trench isolation region. The method includes forming one or more dummy gate layers in the shallow trench isolation region and surrounding the plurality of fin structures. The method includes etching one or more dummy gate layers according to a pattern to form one or more first dummy gate structures extending in a second direction substantially perpendicular to the first direction in a top-down view of the semiconductor device, wherein the one or more first dummy gate structures surround the plurality of fin structures on at least three sides of the plurality of fin structures. The method includes etching one or more dummy gate layers according to a pattern to form one or more second dummy gate structures extending in a second direction and located in a shallow trench isolation region and adjacent to multiple ends of multiple fin structures, wherein the one or more second dummy gate structures include a main body extending in the second direction and one or more supporting structures extending from the main body in a first direction.

[0262] In some embodiments, the method further includes: performing a wet cleaning operation after etching the one or more dummy gate layers, wherein during the wet cleaning operation, the one or more support structures support the one or more second dummy gate structures.

[0263] In some embodiments, the method further includes: performing a wet cleaning operation after etching the one or more dummy gate layers, wherein during the wet cleaning operation, the one or more second dummy gate structures protect the one or more first dummy gate structures.

[0264] In some embodiments, the method further includes: after etching the one or more dummy gate layers, forming one or more source / drain regions on the one or more fin structures. After forming the one or more source / drain regions, removing the one or more first dummy gate structures and the one or more second dummy gate structures, wherein removing the one or more first dummy gate structures leaves one or more first grooves above the multiple fin structures, and removing the one or more second dummy gate structures leaves one or more second grooves above the shallow trench isolation region.

[0265] In some embodiments, the method further includes: forming one or more active gate structures in the one or more first recesses; and forming one or more inactive gate structures in the one or more second recesses.

[0266] In some embodiments, the method further includes forming one or more spacer layers on a plurality of sidewalls of the one or more support structures.

[0267] In some embodiments, the plurality of ends of the plurality of fin structures are adjacent to the first side of the body. The one or more support structures extend from a second side of the body opposite the first side.

[0268] As described in more detail above, the present disclosure provides a semiconductor device. The semiconductor device includes one or more first fin structures extending above a substrate, wherein the one or more first fin structures extend in a first direction in a top-down view of the semiconductor device. The semiconductor device includes a first active gate structure surrounding the one or more first fin structures on at least three sides of the one or more first fin structures, wherein the first active gate structure extends in a second direction substantially perpendicular to the first direction in a top-down view of the semiconductor device. The semiconductor device includes a first non-active gate structure located on a shallow trench isolation region, wherein the first non-active gate structure is adjacent to multiple ends of the one or more first fin structures, the first non-active gate structure includes a first body extending in a second direction and one or more first support structures extending from the first body in a first direction. The semiconductor device includes one or more second fin structures extending above the substrate, wherein the one or more second fin structures extend in the first direction. The semiconductor device includes a second active gate structure surrounding the one or more second fin structures on at least three sides of the one or more second fin structures, wherein the second active gate structure extends in the second direction. The semiconductor device includes a second non-active gate structure located on the shallow trench isolation region and adjacent to the first non-active gate structure, wherein the second non-active gate structure is adjacent to multiple ends of one or more second fin structures, and the second non-active gate structure includes a second body extending in a second direction and one or more second support structures extending from the second body in a first direction.

[0269] In some embodiments, the number of the one or more first support structures and the number of the one or more second support structures are the same number of support structures.

[0270] In some embodiments, the number of the one or more first support structures and the number of the one or more second support structures are different numbers of support structures.

[0271] In some embodiments, each of the one or more first support structures is aligned with an associated one of the one or more second support structures along the second direction.

[0272] In some embodiments, each of the one or more first support structures is offset from one of the one or more second support structures along the second direction.

[0273] In some embodiments, the arrangement of the one or more first support structures is a mirror image of the arrangement of the one or more second support structures in at least one of the first direction or the second direction.

[0274] The present disclosure provides a semiconductor device. The semiconductor device includes a fin structure, a shallow trench isolation region, a dummy gate layer, a first dummy gate structure, and a second dummy gate structure. A plurality of fin structures are located on a substrate of the semiconductor device, wherein the plurality of fin structures extend in a first direction in a top-down view of the semiconductor device. A shallow trench isolation region is located between the plurality of fin structures and on a substrate adjacent to the plurality of ends of the plurality of fin structures, wherein the plurality of fin structures extend above the shallow trench isolation region. One or more dummy gate layers are located in the shallow trench isolation region and surround the plurality of fin structures. One or more dummy gate layers are etched according to a pattern to form one or more first dummy gate structures and one or more second dummy gate structures. The one or more first dummy gate structures extend in a second direction substantially perpendicular to the first direction in a top-down view of the semiconductor device, and the one or more first dummy gate structures surround the plurality of fin structures on at least three sides of the plurality of fin structures. One or more second dummy gate structures extend in the second direction and are located in the shallow trench isolation region and adjacent to multiple ends of multiple fin structures. One or more second dummy gate structures include a body extending in the second direction and one or more support structures extending from the body in the first direction.

[0275] In some embodiments, the semiconductor device further includes one or more source / drain regions located on one or more of the plurality of fin structures.

[0276] In some embodiments, the semiconductor device further includes one or more spacer layers disposed on a plurality of sidewalls of the one or more support structures.

[0277] As used herein, "satisfies a threshold" may refer to a value greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, etc., or the like, depending on the context.

[0278] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of this disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that: include: One or more fin structures extending above a substrate, wherein the one or more fin structures extend in a first direction in a top-down view of the semiconductor device; an active gate structure surrounding the one or more fin structures on at least three sides of the one or more fin structures, wherein the active gate structure, in the top-down view of the semiconductor device, extends in a second direction substantially perpendicular to the first direction; and A non-active gate structure is located on a shallow trench isolation region, wherein the inactive gate structure is adjacent to ends of the one or more fin structures, and The non-active gate structure includes: a main body extending in the second direction; as well as One or more support structures extend from the main body in the first direction.

2. The semiconductor device according to claim 1, wherein wherein a distance between the one or more support structures and another active structure in the semiconductor device satisfies a distance threshold; and The distance threshold is at least twice the size of an active gate structure spacing of the semiconductor device.

3. The semiconductor device according to claim 1, wherein wherein the one or more fin structures include a first plurality of fin structures included in a first fin group; The active gate structure includes a first active gate structure extending through the first fin group; The non-active gate structure includes a first non-active gate structure extending along the first active gate structure; as well as The semiconductor device further comprises: a second plurality of fin structures included in a second fin group adjacent to the first fin group and extending in the first direction; a second active gate structure extending through the second fin set in the second direction and surrounding at least three sides of the second plurality of fin structures; and a second inactive gate structure adjacent to the ends of the second plurality of fin structures and extending along the second active gate structure, The second non-active gate structure includes: a main body extending in the second direction; and One or more support structures extend from the body of the second inactive gate structure in the first direction.

4. The semiconductor device according to claim 1, wherein: wherein the one or more fin structures include a first plurality of fin structures included in a first fin group; The active gate structure includes a first active gate structure extending through the first fin group; as well as The semiconductor device further comprises: a second plurality of fin structures included in a second fin group adjacent to the first fin group and extending in the first direction; and a second active gate structure extending through the second fin set in the second direction, The non-active gate structure continuously extends along the first active gate structure and the second active gate structure and crosses over the first fin group and the second fin group.

5. A semiconductor device, characterized in that: include: A plurality of fin structures are located on a substrate of a semiconductor device, wherein the plurality of fin structures extend in a first direction in a top-down view of the semiconductor device; a shallow trench isolation region located on the substrate between the plurality of fin structures and adjacent to the plurality of ends of the plurality of fin structures, wherein the plurality of fin structures extend above the shallow trench isolation region; One or more dummy gate layers are located in the shallow trench isolation region and surround the plurality of fin structures; as well as The one or more dummy gate layers are etched according to a pattern to form one or more first dummy gate structures and one or more second dummy gate structures, wherein: The one or more first dummy gate structures extend in a second direction substantially perpendicular to the first direction in a top-down view of the semiconductor device, and the one or more first dummy gate structures surround the plurality of fin structures on at least three sides of the plurality of fin structures, The one or more second dummy gate structures extend in the second direction and are located in the shallow trench isolation region and adjacent to the multiple ends of the multiple fin structures, and the one or more second dummy gate structures include: a main body extending in the second direction; and One or more support structures extend from the main body in the first direction.

6. The semiconductor device according to claim 5, wherein: Also included is one or more source / drain regions located on one or more of the plurality of fin structures.

7. The semiconductor device according to claim 5, wherein: Also included is one or more spacer layers located on the sidewalls of the one or more support structures.

8. A semiconductor device, characterized in that: include: One or more first fin structures extending above a substrate, wherein the one or more first fin structures extend in a first direction in a top-down view of the semiconductor device; a first active gate structure surrounding the one or more first fin structures on at least three sides of the one or more first fin structures, wherein the first active gate structure, in the top-down view of the semiconductor device, extends in a second direction substantially perpendicular to the first direction; and a first non-active gate structure located on a shallow trench isolation region, wherein the first inactive gate structure is adjacent to ends of the one or more first fin structures, and The first non-active gate structure includes: a first body extending in the second direction; and One or more first support structures extending from the first body in the first direction; One or more second fin structures extending above the substrate, wherein the one or more second fin structures extend in the first direction; a second active gate structure surrounding the one or more second fin structures on at least three sides of the one or more second fin structures, wherein the second active gate structure extends in the second direction; and a second non-active gate structure located on the shallow trench isolation region and adjacent to the first non-active gate structure, wherein the second inactive gate structure is adjacent to ends of the one or more second fin structures, and The second non-active gate structure includes: a second body extending in the second direction; and One or more second supporting structures extend from the second body in the first direction.

9. The semiconductor device according to claim 8, wherein: Each of the one or more first support structures is aligned with an associated one of the one or more second support structures along the second direction.

10. The semiconductor device according to claim 8, wherein Each of the one or more first support structures is offset from the one of the one or more second support structures along the second direction.

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