Display device

Abstract

A display device includes: a first substrate; a display layer disposed on the first substrate and including a plurality of pixels; a second substrate disposed on the display layer; a first adhesive layer disposed under the first substrate; a main flexible circuit board having an end portion fixed to the first substrate and a side portion fixed to the first adhesive layer; a plate portion disposed under the first adhesive layer and fixed to the first adhesive layer; a second adhesive layer disposed under the plate portion; and a touch flexible circuit board having an end portion fixed to the second substrate and a side portion fixed to the second adhesive layer, in which the first adhesive layer includes an exposed region exposed from the main flexible circuit board, and the board portion overlaps the exposed region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0039040 filed on March 24, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0097703 filed on July 26, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] One or more embodiments relate to a display device, and more particularly, to a display device including a plurality of flexible circuit boards. Background Art

[0004] Mobile electronic devices are widely used to input and output data. These mobile electronic devices may include tablet PCs, mobile phones, and other small electronic devices.

[0005] A mobile electronic device may include a display device. The display device may provide visual information such as an image or video to a user in order to support various functions. As components for driving the display device are miniaturized, the proportion of mobile electronic devices dedicated to the display device has increased, and a flexible structure has been developed. Utility Model Content

[0006] One or more embodiments include a display device having a plate portion fixed to a first substrate without a separate adhesive layer for fixing the main flexible circuit board and the plate portion together.

[0007] However, the purpose of the present disclosure is exemplary, and the purpose of the present disclosure is not limited thereto.

[0008] Additional aspects will be set forth in part in the description and, in part, will be obvious from the description, or may be learned by practice of embodiments of the disclosure.

[0009] According to one or more embodiments, a display device includes: a first substrate; a display layer, which is arranged on the first substrate and includes a plurality of pixels; a second substrate, which is arranged on the display layer; a first adhesive layer, which is arranged under the first substrate; a main flexible circuit board, which has an end portion fixed to the first substrate and a side portion fixed to the first adhesive layer; a board portion, which is arranged under the first adhesive layer and fixed to the first adhesive layer; a second adhesive layer, which is arranged under the board portion; and a touch flexible circuit board, which has an end portion fixed to the second substrate and a side portion fixed to the second adhesive layer; wherein the first adhesive layer includes an exposed area exposed from the main flexible circuit board, and the board portion overlaps with the exposed area.

[0010] In the present embodiment, the size of the exposed area may be larger than the size of the plate portion in a plan view.

[0011] In an embodiment, the plate portion may be disposed spaced apart from the main flexible circuit board in a plan view.

[0012] In an embodiment, the touch flexible circuit board may cover the board portion in a plan view.

[0013] In an embodiment, the touch flexible circuit board may overlap with the main flexible circuit board.

[0014] In an embodiment, a portion of a corner of the exposed area may be disposed spaced apart from the main flexible circuit board in a plan view.

[0015] In an embodiment, the main flexible circuit board may have a notch shape at a boundary with the exposed area in a plan view.

[0016] In an embodiment, in a plan view, the board portion may be disposed on the first adhesive layer in the exposed area, and the main flexible circuit board may surround the exposed area.

[0017] In an embodiment, the display device may further include: a cushion layer disposed between the first substrate and the first adhesive layer, and a side portion of the main flexible circuit board may be fixed to the cushion layer by the first adhesive layer.

[0018] In an embodiment, the display device may further include: a touch sensing layer disposed on the second substrate, and an end portion of the touch flexible circuit board may be fixed to the touch sensing layer.

[0019] According to one or more embodiments, a display device may include: a first substrate; a display layer, which is arranged on the first substrate and includes a plurality of pixels; a second substrate, which is arranged on the display layer; a first adhesive layer, which is arranged below the first substrate; a main flexible circuit board, which has an end portion fixed to the first substrate and a side portion fixed to the first adhesive layer, and has a first opening exposing a portion of the first adhesive layer; a board portion, which is arranged below the first adhesive layer and fixed to the first adhesive layer, and has at least a portion accommodated in the first opening; a second adhesive layer, which is arranged below the board portion; and a touch flexible circuit board, which has an end portion fixed to the second substrate and a side portion fixed to the second adhesive layer.

[0020] In an embodiment, the touch flexible circuit board may cover the board portion in a plan view.

[0021] In an embodiment, the first opening may have a notch shape in a plan view.

[0022] In an embodiment, in a plan view, the board portion may be disposed on the first adhesive layer in the first opening, and the main flexible circuit board may surround the first opening.

[0023] In an embodiment, the display device may further include: a cushion layer disposed between the first substrate and the first adhesive layer, the first adhesive layer may be disposed between the side of the main flexible circuit board and the cushion layer, and the side of the main flexible circuit board may be fixed to the cushion layer by the first adhesive layer.

[0024] In an embodiment, the display device may further include: a touch sensing layer disposed on the second substrate, and an end portion of the touch flexible circuit board may be fixed to the touch sensing layer.

[0025] According to one or more embodiments, a display device may include: a first substrate; a display layer disposed on the first substrate; a second substrate disposed on the display layer; a first adhesive layer disposed under the first substrate; a main flexible circuit board including a first side surface fixed to the first substrate and to the first adhesive layer and a first opening exposing the first adhesive layer; a board portion disposed in the first opening and under the first adhesive layer and fixed to the first adhesive layer in the first opening; a second adhesive layer disposed under the board portion; and a touch flexible circuit board having a first side surface fixed to the second substrate and to the second adhesive layer.

[0026] In an embodiment, the plate portion may be disposed spaced apart from the main flexible circuit board in a plan view.

[0027] In an embodiment, the touch flexible circuit board may cover the board portion in a plan view.

[0028] In an embodiment, the main flexible circuit board may completely surround the board portion in the first opening.

[0029]

[0013] Further aspects, features, and advantages in addition to those described above will become apparent from the following drawings, claims, and detailed description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a schematic plan view of a display device according to an embodiment;

[0032] Figure 2 and Figure 3 is an equivalent circuit diagram of any one pixel of a display device according to an embodiment;

[0033] Figure 4is a schematic cross-sectional view of a display device according to an embodiment;

[0034] Figure 5 is a schematic plan view of a portion of a display device according to an embodiment;

[0035] Figure 6 is a schematic cross-sectional view of a portion of a display device according to an embodiment;

[0036] Figure 7 is a schematic plan view of a portion of a display device according to an embodiment; and

[0037] Figure 8 is a schematic cross-sectional view of a portion of a display device according to an embodiment. DETAILED DESCRIPTION

[0038] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals represent the same elements throughout the specification. In this regard, embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, embodiments are described herein only by reference to the accompanying drawings to illustrate aspects of this description. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout this disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0039] Various modifications may be applied to the embodiments shown in the drawings and described in the detailed description. The effects and features of the embodiments and methods for implementing the same will become clearer with reference to the detailed description in conjunction with the drawings herein. However, the embodiments may be implemented in various forms and may not be limited to the embodiments presented herein.

[0040] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings, and in the description with reference to the accompanying drawings, the same or corresponding elements are denoted by the same reference numerals and a redundant description thereof may be omitted.

[0041] In the following embodiments, it will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0042] In the present disclosure, expressions in the singular number in the present specification include the plurality unless the context clearly dictates otherwise.

[0043] In the present disclosure, it will also be understood that the terms “include” and / or “comprises” used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0044] In the present disclosure, it will be understood that when a layer, region or element is referred to as being "formed on" another layer, region or element, it can be directly or indirectly formed on the other layer, region or element. That is, for example, intervening layers, regions or elements may be present.

[0045] For the convenience of explanation, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the elements in the drawings may be arbitrarily shown for the convenience of explanation, the embodiments are not limited thereto.

[0046] In the present disclosure, the x-axis, y-axis and z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0047] When the embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described successively can be performed substantially simultaneously, or in the reverse order of the described order.

[0048] Figure 1 is a schematic plan view of a display device according to an embodiment.

[0049] refer to Figure 1 , the display device 1 may include a display area DA and a peripheral area PA. The peripheral area PA may be disposed around the display area DA. The display device 1 may generate a specific image by emitting light from a plurality of pixels P. The plurality of pixels P may be disposed in the display area DA.

[0050] The display area DA may include scan lines SL extending in the x direction and pixels P connected to data lines DL extending in the y direction crossing the x direction. Each pixel P may be connected to a driving voltage line PL extending in the y direction.

[0051] Each of the pixels P may include a display device such as an organic light emitting diode OLED. Each pixel P may emit, for example, red light, green light, blue light, or white light via the organic light emitting diode OLED. The pixel P in this specification may be understood as a sub-pixel that emits one of the red light, green light, blue light, and white light as described above. In some embodiments, the organic light emitting diodes OLED included in the pixel P may all emit light of the same color, and the different colors of each pixel P may be realized by a color filter or the like disposed on the organic light emitting diode OLED.

[0052] Each pixel P may be electrically connected to an embedded circuit disposed in the peripheral area PA. An embedded driving circuit unit 40, a terminal unit 30, a first power line 10, and a second power line (not shown) may be disposed in the peripheral area PA.

[0053] The embedded driving circuit unit 40 may include a plurality of thin film transistors. The embedded driving circuit unit 40 may provide a scan signal to each pixel P via a scan line SL. The embedded driving circuit unit 40 may be arranged on both sides of the display area DA with the display area DA between the embedded driving circuit units 40. Some of the pixels P disposed in the display area DA may be electrically connected to the embedded driving circuit unit 40 disposed on a first side, and other pixels P may be electrically connected to the embedded driving circuit unit 40 disposed on a second side opposite to the first side. Figure 1 , the embedded driving circuit unit 40 may include an embedded driving circuit unit 40 disposed on the left side of the display area DA and an embedded driving circuit unit 40 disposed on the right side of the display area DA. In another embodiment, the embedded driving circuit unit 40 may be disposed on one side of the display area DA.

[0054] The terminal unit 30 may be arranged on one side of the substrate 100. The terminal unit 30 may be exposed to the outside. An insulating layer (not shown) may expose the terminal unit 30 to the outside. The terminal unit 30 may be electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal unit 30.

[0055] The printed circuit board PCB may transmit a signal or power of a controller (not shown) to the terminal unit 30. The controller may provide a driving voltage to the first power line 10 via the first connection line 1111. The driving voltage may be provided to each pixel P via a driving voltage line PL connected to the first power line 10. In addition, the controller may provide a common voltage to the second power line (not shown). The common voltage may be provided to an opposite electrode of the pixel P that may be connected to the second power line.

[0056] The control signal generated by the controller may be transmitted to the embedded driving circuit unit 40 via the printed circuit board PCB via the third connection line 41 .

[0057] The data driving circuit 60 may be disposed on a printed circuit board PCB. The data driving circuit 60 may be electrically connected to the data line DL. The data signal of the data driving circuit 60 may be provided to each pixel P via a connection line 51 connected to the terminal unit 30 and a data line DL connected to the connection line 51. In another embodiment, the data driving circuit 60 may be disposed on a substrate 100. For example, the data driving circuit 60 may be disposed between the terminal unit 30 and the first power line 10.

[0058] Figure 2 and Figure 3 is an equivalent circuit diagram of a pixel of a display device according to an embodiment.

[0059] refer to Figure 2 , each pixel P may include a pixel circuit PC and an organic light emitting diode OLED. The pixel circuit PC may be connected to a scan line SL and a data line DL. The organic light emitting diode OLED may be connected to the pixel circuit PC.

[0060] The pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2 and a storage capacitor Cst. The switching thin film transistor T2 may be connected to the scan line SL and the data line DL and may be configured to transmit a data signal Dm inputted via the data line DL to the driving thin film transistor T1 according to a scan signal Sn inputted via the scan line SL.

[0061] The storage capacitor Cst may be connected to the switching thin film transistor T2 and the driving voltage line PL. The storage capacitor Cst may store a voltage corresponding to a difference between a voltage received from the switching thin film transistor T2 and a driving power voltage ELVDD (or driving voltage) supplied to the driving voltage line PL.

[0062] The driving thin film transistor T1 may be connected to the driving voltage line PL and the storage capacitor Cst. The driving thin film transistor T1 may be configured to control a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to a voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light with a certain brightness according to the driving current.

[0063] exist Figure 2 , a case where the pixel circuit PC includes two thin film transistors and one storage capacitor is shown, but the present disclosure is not limited thereto.

[0064] refer to Figure 3 Each pixel P may include an organic light emitting diode OLED and a pixel circuit PC, wherein the pixel circuit PC includes a plurality of thin film transistors configured to drive the organic light emitting diode OLED. The pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, a sensing thin film transistor T3, and a storage capacitor Cst.

[0065] The scan line SL may be connected to the gate electrode of the switching thin film transistor T2 , the data line DL may be connected to the source electrode of the switching thin film transistor T2 , and the first electrode CE1 of the storage capacitor Cst may be connected to the drain electrode of the switching thin film transistor T2 .

[0066] Therefore, the switching thin film transistor T2 may be configured to provide the data voltage of the data line DL to the first node N in response to the scan signal Sn of the scan line SL from each pixel P.

[0067] The gate electrode of the driving thin film transistor T1 may be connected to the first node N, the source electrode thereof may be connected to the first power line PL1 configured to transmit the driving power voltage ELVDD, and the drain electrode thereof may be connected to the anode electrode of the organic light emitting diode OLED.

[0068] Therefore, the driving thin film transistor T1 may be configured to adjust the current flowing through the organic light emitting diode OLED according to the source-gate voltage thereof (ie, the voltage applied between the driving power voltage ELVDD and the first node N).

[0069] The sensing control line SSL may be connected to the gate electrode of the sensing thin film transistor T3, the source electrode of the sensing thin film transistor T3 may be connected to the second node S2, and the drain electrode of the sensing thin film transistor T3 may be connected to the reference voltage line RL. In some embodiments, the sensing thin film transistor T3 may be controlled by the scan line SL, and the sensing thin film transistor T3 may not be controlled by the sensing control line SSL.

[0070] The sensing thin film transistor T3 may be configured to sense the potential of the anode electrode of the organic light emitting diode OLED. The sensing thin film transistor T3 may be configured to provide a precharge voltage from the reference voltage line RL to the second node S2 in response to a sensing signal SSn from the sensing control line SSL, or may be configured to provide the voltage of the anode electrode of the organic light emitting diode OLED to the reference voltage line RL during a sensing period.

[0071] A first electrode CE1 of the storage capacitor Cst may be connected to a first node N, and a second electrode CE2 of the storage capacitor Cst may be connected to a second node S2. The storage capacitor Cst may store a difference voltage between voltages supplied to the first node N and the second node S2, respectively, and provide the difference voltage as a driving voltage of the driving thin film transistor T1. For example, the storage capacitor Cst may be charged according to a difference voltage between a voltage of a data signal Dm supplied to the first node N and the second node S2, respectively, and a precharge voltage (Vpre).

[0072] The bias electrode BSM may be formed to correspond to the driving thin film transistor T1 and may be connected to the source electrode of the sensing thin film transistor T3. The bias electrode BSM may receive a voltage associated with the potential of the source electrode of the sensing thin film transistor T3, and the driving thin film transistor T1 may be stabilized thereby. In some embodiments, the bias electrode BSM may be connected to a separate bias line without being connected to the source electrode of the sensing thin film transistor T3.

[0073] An opposite electrode (eg, cathode) of the organic light emitting diode OLED may receive the common power voltage ELVSS. The organic light emitting diode OLED may emit light by receiving a driving current from the driving thin film transistor T1.

[0074] although Figure 3 Each pixel P is shown to include signal lines SL, SSL and DL, a reference voltage line RL, a first power line PL1 and a second power line PL2, but the present disclosure is not limited thereto. For example, at least one of the signal lines SL, SSL and DL and / or the reference voltage line RL, the first power line PL1 and the second power line PL2 may be shared by adjacent pixels P.

[0075] The pixel circuit PC is not limited to the reference Figure 2 and Figure 3 The number of thin film transistors, the number of storage capacitors, and the circuit design are described and may vary.

[0076] Figure 4 is a schematic cross-sectional view of a display device according to an embodiment, and can be compared with Figure 1 This corresponds to a cross-section of the display device taken along line IV-IV'.

[0077] refer to Figure 4 , the display device 1 may include a substrate 100, a pixel circuit layer PCL, a display element layer DEL, and an encapsulation layer 300. The substrate 100, the pixel circuit layer PCL, the display element layer DEL, and the encapsulation layer 300 may be provided in a stacked structure.

[0078] The substrate 100 may have a multilayer structure including an inorganic layer and a base layer including a polymer resin. For example, the substrate 100 may include a base layer including a polymer resin and a barrier layer as an inorganic insulating layer. For example, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104, which may be stacked in sequence. For example, the first barrier layer 102 may be disposed on the first base layer 101, the second base layer 103 may be disposed on the first barrier layer 102, and the second barrier layer 104 may be disposed on the second base layer 103. Each of the first base layer 101 and the second base layer 103 may include polyimide (PI), polyethersulfone (PES), polyarylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polycarbonate, triacetyl cellulose (TAC), or / and cellulose acetate propionate (CAP). Each of the first barrier layer 102 and the second barrier layer 104 may include an inorganic insulating material such as silicon oxide, silicon oxynitride, and / or silicon nitride. The substrate 100 may have flexibility. For example, the substrate 100 may be bent, rolled, or folded.

[0079] The pixel circuit layer PCL may be disposed on the substrate 100. Figure 4 , the pixel circuit layer PCL may include a thin film transistor TFT, a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, an interlayer insulating layer 114, a first planarizing insulating layer 115, and a second planarizing insulating layer 116. The buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, the interlayer insulating layer 114, the first planarizing insulating layer 115, and the second planarizing insulating layer 116 may be disposed under or / and above the constituent elements of the thin film transistor TFT. The buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, the interlayer insulating layer 114, the first planarizing insulating layer 115, and the second planarizing insulating layer 116 may be stacked in sequence.

[0080] The buffer layer 111 may reduce or block penetration of foreign matter, moisture, or external air from under the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic insulating material such as silicon oxide, silicon oxynitride, or silicon nitride, and may have a single-layer or multi-layer structure including the above materials.

[0081] The thin film transistor TFT on the buffer layer 111 may include a semiconductor layer Act, and the semiconductor layer Act may include polycrystalline silicon (poly-Si). Alternatively, the semiconductor layer Act may include amorphous silicon (a-Si), an oxide semiconductor, or an organic semiconductor. The semiconductor layer Act may include a channel region C and a drain region D and a source region S respectively disposed at both sides of the channel region C. The gate electrode GE may overlap the channel region C.

[0082] The gate electrode GE may include a low resistance metal material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti). The gate electrode GE may be formed as a multi-layer or single-layer including the above materials.

[0083] The first gate insulating layer 112 between the semiconductor layer Act and the gate electrode GE may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x ) inorganic insulating material. ZnO x It may include zinc oxide (ZnO) and / or zinc peroxide (ZnO 2 ).

[0084] The second gate insulating layer 113 may cover the gate electrode GE. Similar to the first gate insulating layer 112, the second gate insulating layer 113 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x ) inorganic insulating material. ZnO x It may include zinc oxide (ZnO) and / or zinc peroxide (ZnO 2 ).

[0085] The upper electrode Cst2 of the storage capacitor Cst may be disposed on the second gate insulating layer 113. The upper electrode Cst2 may overlap the gate electrode GE disposed under the upper electrode Cst2. In this state, the gate electrode GE and the upper electrode Cst2 overlapping each other with the second gate insulating layer 113 disposed therebetween may form a storage capacitor Cst. In other words, the gate electrode GE may serve as the lower electrode Cst1 of the storage capacitor Cst.

[0086] Therefore, the storage capacitor Cst and the thin film transistor TFT may overlap each other in the z direction. In some embodiments, the storage capacitor Cst may be formed not to overlap the thin film transistor TFT.

[0087] The upper electrode Cst2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and may be a single layer or a multilayer including the above materials.

[0088] The interlayer insulating layer 114 may cover the upper electrode Cst2. The interlayer insulating layer 114 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x ). ZnO x It may include zinc oxide (ZnO) and / or zinc peroxide (ZnO 2 ). The interlayer insulating layer 114 may be a single layer or multiple layers including the above-mentioned inorganic insulating material.

[0089] The drain electrode DE and the source electrode SE may each be disposed on the interlayer insulating layer 114. The drain electrode DE may be connected to the drain region D and the source electrode SE may be connected to the source region S via a contact hole formed in the insulating layer thereunder. Each of the drain electrode DE and the source electrode SE may include a conductive material. Each of the drain electrode DE and the source electrode SE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a multilayer or a single layer including the above materials. In an embodiment, the drain electrode DE and the source electrode SE may each have a multilayer structure of Ti / Al / Ti.

[0090] The first planarization insulating layer 115 may cover the drain electrode DE and the source electrode SE. The first planarization insulating layer 115 may be disposed on the interlayer insulating layer 114, the drain electrode DE, and the source electrode SE. The first planarization insulating layer 115 may include an organic insulating material such as a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

[0091] The second planarization insulating layer 116 may be disposed on the first planarization insulating layer 115. The second planarization insulating layer 116 may include the same material as that of the first planarization insulating layer 115, and may include an organic insulating material such as a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

[0092] Although the first gate insulating layer 112 , the second gate insulating layer 113 , and the interlayer insulating layer 114 may be conformal layers, the first planarizing insulating layer 115 and the second planarizing insulating layer 116 cover the thin film transistor TFT and may have a flat upper surface.

[0093] The display element layer DEL may be arranged on the pixel circuit layer PCL having the above structure. The display element layer DEL may include an organic light emitting diode OLED as a display element (i.e., a light emitting element). The organic light emitting diode OLED may include a stack including a pixel electrode 210, an intermediate layer 220, and a common electrode 230. The organic light emitting diode OLED may emit light, such as red light, green light, or blue light, or red light, green light, blue light, or white light. The organic light emitting diode OLED may emit light via an emission region, wherein the emission region may be defined as a pixel P.

[0094] The pixel electrode 210 of the organic light emitting diode OLED may be electrically connected to the thin film transistor TFT via a contact hole formed in the second planarization insulating layer 116 and the first planarization insulating layer 115 and a contact metal CM disposed on the first planarization insulating layer 115. The contact hole in the second planarization insulating layer 116 may overlap with the contact hole in the first planarization insulating layer 115, and the organic light emitting diode OLED may be electrically connected to the thin film transistor TFT via the contact hole formed in the second planarization insulating layer 116 and the first planarization insulating layer 115.

[0095] The pixel electrode 210 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). In another embodiment, the pixel electrode 210 may include a reflective film containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. In another embodiment, the pixel electrode 210 may also include a conductive oxide including ITO, IZO, ZnO or In above / below the above-mentioned reflective film. 2 O 3 membrane.

[0096] A bank layer 117 having an opening 117OP exposing a central portion of the pixel electrode 210 may be disposed on the pixel electrode 210. The bank layer 117 may include an organic insulating material and / or an inorganic insulating material. The opening 117OP may define an emission region of light emitted from the organic light emitting diode OLED. For example, the size / width of the opening 117OP may correspond to the size / width of the emission region. Therefore, the size and / or width of the pixel P may depend on the size and / or width of the opening 117OP of the bank layer 117.

[0097] The intermediate layer 220 may include an emission layer 222 disposed on the pixel electrode 210. The emission layer 222 may include a polymer or a low molecular weight organic material that emits light of a specific color. Alternatively, the emission layer 222 may include an inorganic light emitting material or a quantum dot.

[0098] In an embodiment, the intermediate layer 220 may include a first functional layer 221 and a second functional layer 223. The first functional layer 221 may be disposed below the emission layer 222, and the second functional layer 223 may be disposed on the emission layer 222. The emission layer 222 may be disposed between the first functional layer 221 and the second functional layer 223. The first functional layer 221 may include, for example, a hole transport layer (HTL), or an HTL and a hole injection layer (HIL). The second functional layer 223 disposed on the emission layer 222 may include an electron transport layer (ETL) and / or an electron injection layer (EIL). Similar to the common electrode 230 described below, the first functional layer 221 and / or the second functional layer 223 may be a common layer formed to cover the substrate 100. For example, the first functional layer 221 and / or the second functional layer 223 may completely cover the substrate 100.

[0099] The common electrode 230 may be disposed above the pixel electrode 210 and may overlap with the pixel electrode 210. The common electrode 230 may include a conductive material having a low work function. For example, the common electrode 230 may include a (semi) transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or an alloy thereof. Optionally, the common electrode 230 may also include a (semi) transparent layer including ITO, IZO, ZnO or Indium Oxide disposed on the (semi) transparent layer including the above materials. 2 O 3 The common electrode 230 may be integrally formed to completely cover the substrate 100 .

[0100] The encapsulation layer 300 may be disposed on the display element layer DEL and may cover the display element layer DEL. The encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, Figure 4 It is shown that the encapsulation layer 300 may include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330 which may be sequentially stacked. The first inorganic encapsulation layer 310 may be disposed on the organic light emitting diode OLED, the organic encapsulation layer 320 may be disposed on the first inorganic encapsulation layer 310, and the second inorganic encapsulation layer 330 may be disposed on the organic encapsulation layer 320.

[0101] Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one inorganic material of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may include a polymer-based material. The polymer-based material may include an acrylic resin, an epoxy-based resin, a polyimide, or polyethylene. In an embodiment, the organic encapsulation layer 320 may include an acrylate. The organic encapsulation layer 320 may be formed by curing a monomer or applying a polymer. The organic encapsulation layer 320 may be formed of a transparent material.

[0102] Although not shown, the touch sensor layer may be disposed on the encapsulation layer 300, and the optical function layer may be disposed on the touch sensor layer. The touch sensor layer may obtain coordinate information based on external input (e.g., a touch event). The optical function layer may reduce the reflectivity of light (external light) incident on the display device, and / or may improve the color purity of light emitted from the display device. In an embodiment, the optical function layer may include a retarder and / or a polarizer. The retarder may be of a film type or a liquid crystal coating type, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be of a film type or a liquid crystal coating type. The film type may include a stretchable synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a specific array. Each of the retarder and the polarizer may also include a protective film.

[0103] The adhesive member may be disposed between the touch sensor layer and the optical functional layer. The adhesive member may be any material generally known in the art without limitation. The adhesive member may be a pressure sensitive adhesive (PSA).

[0104] Figure 5 is a schematic plan view of a portion of a display device according to an embodiment. Figure 6 is a schematic cross-sectional view of a portion of a display device according to an embodiment. Figure 6 Can be used with Figure 5 The VI-VI' part corresponds to.

[0105] refer to Figure 5 and Figure 6 The display device 1 may include a first substrate 11, a display layer 12, a second substrate 13, a touch sensing layer 14, a pad layer 15, a first adhesive layer 16, a main flexible circuit board MFPC, a board portion 17, a second adhesive layer 18, a touch flexible circuit board TFPC, a display driving chip DDC and a touch driving chip TDC.

[0106] The display layer 12 may be disposed on the first substrate 11. The first substrate 11 may be Figure 4 The display layer 12 may include a plurality of pixels and may correspond to the substrate 100 described above. Figure 4 The described pixel circuit layer PCL corresponds to the display element layer DEL.

[0107] The second substrate 13 may be disposed on the display layer 12. The second substrate 13 may be an encapsulation substrate. The second substrate 13 may reduce or prevent moisture and / or oxygen from penetrating from the outside.

[0108] The touch sensing layer 14 may be disposed on the second substrate 13. The touch sensing layer 14 may include touch electrodes and touch signal lines configured to transmit signals to and / or receive signals from the touch electrodes. The touch sensing layer 14 may sense touch in various ways. For example, the touch sensing layer 14 may sense touch using a resistive type sensor, a capacitive type sensor, an electromagnetic type (EM) sensor, or an optical type sensor.

[0109] The cushion layer 15 may be disposed under the first substrate 11. The first substrate 11 may be disposed between the cushion layer 15 and the display layer 12. The cushion layer 15 may be disposed on the rear surface of the first substrate 11 and may be fixed to the first substrate 11. The cushion layer 15 may be disposed between the first substrate 11 and the first adhesive layer 16. The cushion layer 15 may support the first substrate 11 and may protect the first substrate 11 from external impact. The cushion layer 15 may include a material having elasticity.

[0110] The first adhesive layer 16 may be disposed under the cushion layer 15, and the plate portion 17 may be disposed under the first adhesive layer 16. The first adhesive layer 16 may be disposed between the first substrate 11 and the plate portion 17. The first adhesive layer 16 may bond the cushion layer 15 and the plate portion 17 together so that an air layer or the like is not formed between the cushion layer 15 and the plate portion 17. The first substrate 11 and the cushion layer 15 may be fixed to each other, and the plate portion 17 may be fixed to the cushion layer 15 by the first adhesive layer 16, and the first adhesive layer 16 may indirectly fix the first substrate 11 and the plate portion 17 together.

[0111] The plate portion 17 may be disposed under the first substrate 11 so as to be fixed to the first adhesive layer 16. The plate portion 17 may function as a heat sink. The plate portion 17 may effectively dissipate heat. The plate portion 17 may transfer heat downward and away from the second substrate 13. For example, the plate portion 17 may include a metal material having high thermal conductivity such as stainless steel, copper, nickel, ferrite, silver, or aluminum.

[0112] An end portion of the main flexible circuit board MFPC may be fixed to the first substrate 11, and a side portion of the main flexible circuit board MFPC may be fixed to the first adhesive layer 16. A side portion of the main flexible circuit board MFPC may be fixed to the pad layer 15 by the first adhesive layer 16. The main flexible circuit board MFPC may include a flexible material, and may be fixed to the first substrate 11 and the first adhesive layer 16 while being bent. A first side surface of the main flexible circuit board MFPC may be fixed to the first substrate 11 and the first adhesive layer 16, wherein the main flexible circuit board MFPC may be bent to the first substrate 11 disposed above the first adhesive layer 16. Signals for controlling the display layer 12 and the display driving chip DDC may be applied via the main flexible circuit board MFPC.

[0113] The first adhesive layer 16 may include an exposed area ARE16 exposed from the main flexible circuit board MFPC. Figure 5 In the plan view, the exposed area ARE16 may not overlap with the main flexible circuit board MFPC. The exposed area ARE16 may be provided at the periphery of the main flexible circuit board MFPC.

[0114] A first opening OPM exposing a portion of the first adhesive layer 16 may be provided in the main flexible circuit board MFPC. In a plan view, the exposed area ARE16 and the first opening OPM may overlap each other. The plate portion 17 may overlap the exposed area ARE16. At least a portion of the plate portion 17 may be accommodated in the first opening OPM and may be fixed to the first adhesive layer 16 in the exposed area ARE16.

[0115] In a plan view, the size of the exposed area ARE16 and the size of the first opening OPM may be larger than the size of the plate portion 17. Therefore, the plate portion 17 may be spaced apart from the main flexible circuit board MFPC. In a plan view, a portion of a corner of the exposed area ARE16 may be spaced apart from the main flexible circuit board MFPC. In other words, in a plan view, the first opening OPM may be provided at an end portion of the main flexible circuit board MFPC. For example, in a plan view, the main flexible circuit board MFPC may have a notch shape at a boundary with the exposed area ARE16.

[0116] The second adhesive layer 18 may be provided under the plate portion 17. The second adhesive layer 18 may bond the plate portion 17 and the touch flexible circuit board TFPC together so that no air layer or the like is formed between the plate portion 17 and the touch flexible circuit board TFPC. The first substrate 11 and the plate portion 17 may be fixed to each other by the first adhesive layer 16, and the plate portion 17 may be fixed to the touch flexible circuit board TFPC by the second adhesive layer 18, and the second adhesive layer 18 may indirectly fix the first substrate 11 and the touch flexible circuit board TFPC.

[0117] An end portion of the touch flexible circuit board TFPC may be fixed to the second substrate 13, and a side portion of the touch flexible circuit board TFPC may be fixed to the second adhesive layer 18. For example, the touch flexible circuit board TFPC may be indirectly fixed to the second substrate 13 in such a manner that an end portion of the touch flexible circuit board TFPC is fixed to the touch sensing layer 14 disposed on the second substrate 13. A first side surface of the touch flexible circuit board TFPC may be fixed to the second substrate 13 and the second adhesive layer 18, wherein the touch flexible circuit board TFPC may be bent to the second substrate 13 disposed above the second adhesive layer 18. The touch flexible circuit board TFPC may transmit a signal to the touch sensing layer 14 or may receive a signal from the touch sensing layer 14. Figure 5In the plan view, the touch flexible circuit board TFPC may cover the plate portion 17. The touch flexible circuit board TFPC may overlap the main flexible circuit board MFPC.

[0118] The display driving chip DDC may be fixed to the first substrate 11 and electrically connected to the first substrate 11. The display driving chip DDC may include driving devices such as a data driving unit for applying a data voltage to the data line, a gate driving unit for applying a gate-on voltage to the gate line, and a signal controller for controlling operations of the data driving unit and the gate driving unit.

[0119] The touch driver chip TDC may be fixed to the touch flexible circuit board TFPC and electrically connected to the touch flexible circuit board TFPC. The touch driver chip TDC may transmit a touch signal to the touch sensing layer 14. In addition, the touch driver chip TDC may receive a touch signal from the touch sensing layer 14 and generate information such as the presence or absence of a touch and a touch position.

[0120] According to reference Figure 5 and Figure 6 In the described embodiment, the plate portion 17 may not be directly fixed to the main flexible circuit board MFPC, and therefore, a separate adhesive layer for fixing the plate portion 17 and the main flexible circuit board MFPC together may be omitted. Therefore, the manufacturing cost of the display device 1 may be reduced. In addition, the plate portion 17 may be fixed to the first adhesive layer 16 while being accommodated in the first opening OPM, and therefore, the thickness of the display device 1 may be reduced.

[0121] Figure 7 is a schematic plan view of a portion of a display device according to an embodiment. Figure 8 is a schematic cross-sectional view of a portion of a display device according to an embodiment. Figure 8 Can be used with Figure 7 VIII-VIII' portion corresponds to.

[0122] refer to Figure 7 and Figure 8 The display device 1 may include a first substrate 11, a display layer 12, a second substrate 13, a touch sensing layer 14, a pad layer 15, a first adhesive layer 16, a main flexible circuit board MFPC, a board portion 17, a second adhesive layer 18, a touch flexible circuit board TFPC, a display driving chip DDC and a touch driving chip TDC.

[0123] Figure 5 , Figure 6 , Figure 7 and Figure 8 The same figure numbers in FIG. 1 denote the same components, and thus, repeated descriptions thereof may be omitted.

[0124] exist Figure 7 In the plan view, the main flexible circuit board MFPC may surround the exposed area ARE16. In other words, the main flexible circuit board MFPC may surround the first opening OPM. Figure 8 , the board portion 17 may be disposed in the first opening OPM. In a plan view, the board portion 17 may be completely surrounded by the main flexible circuit board MFPC in the first opening OPM. The pad layer 15 may be disposed above the first opening OPM, and at least a portion of the touch flexible circuit board TFPC may be disposed below the first opening OPM. However, referring to Figure 5 , Figure 6 , Figure 7 and Figure 8 The described embodiments are merely examples, and each of the exposed area ARE16 and the first opening OPM may have various shapes.

[0125] According to the embodiments, the manufacturing cost of the display device can be reduced, and the thickness thereof can be reduced.

[0126] It should be understood that the embodiments described herein should be considered to be merely descriptive and not for limiting purposes. The description of features or aspects within an embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made in the embodiments without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device, characterized in that: include: a first substrate; A display layer, disposed on the first substrate and comprising a plurality of pixels; A second substrate, disposed on the display layer; a first adhesive layer, disposed below the first substrate; a main flexible circuit board having an end portion fixed to the first substrate and a side portion fixed to the first adhesive layer; a plate portion disposed below the first adhesive layer and fixed to the first adhesive layer; a second adhesive layer disposed below the panel portion; as well as a touch flexible circuit board having an end portion fixed to the second substrate and a side portion fixed to the second adhesive layer, wherein the first adhesive layer includes an exposed area exposed from the main flexible circuit board, and The plate portion overlaps the exposed area.

2. The display device according to claim 1, characterized in that In a plan view, the size of the exposed area is larger than the size of the plate portion.

3. The display device according to claim 1, characterized in that The plate portion is disposed spaced apart from the main flexible circuit board in a plan view.

4. The display device according to claim 1, characterized in that In a plan view, the touch flexible circuit board covers the board portion.

5. The display device according to claim 1, characterized in that The touch flexible circuit board overlaps with the main flexible circuit board.

6. The display device according to claim 1, characterized in that In a plan view, a portion of a corner of the exposed area is disposed spaced apart from the main flexible circuit board.

7. The display device according to claim 6, characterized in that The main flexible circuit board has a notch shape at a boundary with the exposed area in a plan view.

8. The display device according to claim 1, characterized in that In a plan view, the board portion is disposed on the first adhesive layer in the exposed area, and the main flexible circuit board surrounds the exposed area.

9. The display device according to claim 1, characterized in that: Also includes: A cushion layer is disposed between the first substrate and the first adhesive layer, wherein the side portion of the main flexible circuit board is fixed to the cushion layer by the first adhesive layer.

10. The display device according to claim 1, characterized in that Also includes: A touch sensing layer is disposed on the second substrate, wherein the end portion of the touch flexible circuit board is fixed to the touch sensing layer.

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