Semiconductor device

Abstract

The utility model provides a semiconductor device. In one embodiment, a semiconductor device includes an array of memory cells over a substrate, where each of the memory cells includes a respective instance of an access transistor and a respective instance of a memory structure configured to store data bits and electrically connected to a source structure of the respective instance of the access transistor; and a memory monitoring device comprising an additional instance of the access transistor, an additional instance of the memory structure electrically connected to the source structure of the additional instance of the access transistor, and at least one monitoring transistor, the at least one monitoring transistor has a monitoring gate electrode electrically connected to a source structure of an additional instance of the access transistor.

Description

Technical Field

[0001] The utility model relates to a semiconductor device. Background Art

[0002] The voltage at the data storage node may be sensed using a monitoring circuit (also referred to as a sensing circuit) that digitizes the output as either "0" or "1" and, therefore, does not provide any additional data other than the digitized output. It may be difficult to measure the voltage and / or charge on the data storage node. This may be because: in a memory cell, information may be stored as a small charge on a capacitor. The charge stored on these capacitors is very small (on the order of only a few electrons). The capacitors are also very small (typically on the order of a few square microns). Measuring such a small charge on such a small capacitor is a difficult task because the measurement process can easily destroy the charge state of the capacitor, resulting in data loss. Additionally, the measurement equipment needs to be highly sensitive and able to distinguish the tiny charge stored on the capacitor from other sources of electrical noise. Utility Model Content

[0003] The utility model provides a semiconductor device, comprising: an array of memory cells, located on a substrate, wherein each of the memory cells comprises a corresponding instance of an access transistor and a corresponding instance of a memory structure, the corresponding instance of the memory structure is configured to store data bits, and the corresponding instance of the memory structure is electrically connected to a source structure of the corresponding instance of the access transistor; and a memory monitoring device, comprising an additional instance of the access transistor, an additional instance of the memory structure and at least one monitoring transistor, the additional instance of the memory structure is electrically connected to the source structure of the additional instance of the access transistor, and the at least one monitoring transistor has a monitoring gate electrode electrically connected to the source structure of the additional instance of the access transistor.

[0004] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figures 1A to 1C is a circuit diagram of various embodiments of the device structure of the present disclosure.

[0006] Figure 2A is a vertical cross-sectional view of a memory monitoring device region of a first semiconductor structure according to an embodiment of the present disclosure.

[0007] Figure 2Bis a vertical cross-sectional view of a memory array region of a first semiconductor structure according to an embodiment of the present disclosure.

[0008] FIG. 3A to FIG. 3C 2 is a vertical cross-sectional view of various configurations of a memory monitoring device region of a second semiconductor structure according to an embodiment of the present disclosure.

[0009] Figure 3D yes Figure 3C Schematic top view of the configuration of the second semiconductor structure shown in .

[0010] Figure 3E is a vertical cross-sectional view of a memory monitoring device region of a second semiconductor structure according to an embodiment of the present disclosure.

[0011] Figure 3F is a vertical cross-sectional view of a memory array region of a second semiconductor structure according to an embodiment of the present disclosure.

[0012] Figure 4A is a vertical cross-sectional view of a memory monitoring device region of a third semiconductor structure according to an embodiment of the present disclosure.

[0013] Figure 4B is a vertical cross-sectional view of a memory array region of a third semiconductor structure according to an embodiment of the present disclosure.

[0014] Figure 4C It is shown in the Figure 4A and Figure 4B A graph showing voltage-current characteristics during set and reset operations of a memory structure in a third semiconductor structure.

[0015] FIG. 5A to FIG. 5D 2 is a vertical cross-sectional view of various configurations of a memory monitoring device region of a fourth semiconductor structure according to an embodiment of the present disclosure.

[0016] Figure 5E is a vertical cross-sectional view of a memory array region of a fourth semiconductor structure according to an embodiment of the present disclosure.

[0017] Figure 6 is a flow chart showing general processing steps for fabricating the semiconductor structure of the present disclosure. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed.

[0019] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Elements with the same reference number refer to the same element and are assumed to have the same material composition and the same thickness range unless otherwise expressly stated.

[0020] Measuring small amounts of charge, on the order of femto-coulombs, in dynamic random access memory (DRAM) storage nodes can be difficult. This is likely because DRAM cells store information as small charges on capacitors. The charges stored on these capacitors are very small (on the order of only a few electrons). The capacitors are also very small (typically on the order of a few square microns). Measuring such small charges on such small capacitors is a difficult task because the measurement process can easily destroy the charge state of the capacitor, resulting in data loss. Additionally, the measurement equipment needs to be highly sensitive and able to distinguish the tiny charges stored on the capacitors from other sources of electrical noise.

[0021] This is especially true for 1-transistor 1-cell (1T1C) DRAM cells where the signal in the capacitor is amplified by a complex sense amplifier circuit. Similar problems also occur in resistive memory cells with small sizes. The production of such monitoring circuits (also known as sensing circuits) often utilizes a lot of resources and time, which may slow down product development using this technology. Additionally, other structures of DRAM storage nodes only allow reporting of results, not the entire process. This limitation makes it difficult to fully understand the behavior of the storage node. In order to fully understand the storage node, it may be necessary to use alternative methods or techniques.

[0022] Embodiments of the present disclosure provide a new method for in-situ monitoring of storage node potentials. Only one type of transistor (one-doping type, such as an n-type field effect transistor) is required to implement the monitoring circuit of the present disclosure, thereby eliminating the need to form a complementary metal-oxide-semiconductor (CMOS) circuit (i.e., the opposite type of transistor (e.g., a p-type field effect transistor)). Compared to conventional methods, this allows the use of a reduced test pattern size. In addition, this approach provides an efficient and cost-effective solution for monitoring storage node performance. Multiple monitoring transistors with different threshold voltages can be used to quantify the amount of charge in a capacitor or the resistivity of a resistive memory cell.

[0023] Embodiments of the present disclosure provide a method for monitoring the potential of a storage node in a 1-transistor 1-storage-node storage cell, and specifically, provide a method using at least one monitoring transistor for detecting potential changes in the storage node of the storage cell. According to embodiments of the present disclosure, the storage node (SN) of the 1-transistor 1-storage-node storage cell can be connected to each gate electrode of at least one monitoring transistor. The potential of the storage node determines the gate voltage of the at least one monitoring transistor, which in turn generates different device drain currents depending on the magnitude of the potential of the storage node. The potential change of the source node can be amplified via the at least one monitoring transistor, and therefore, it becomes easy to monitor the potential at the storage node at each time point or each stage of the operation of the storage cell.

[0024] In the example shown, the source structure (e.g., N+ diffusion region) can be extended laterally, and two electrical connections to the storage node can be made. One electrical connection can be used to electrically connect the source structure to an electrical node of a memory structure (e.g., a capacitor structure of a resistive memory element), and the other electrical connection can be used to electrically connect the source structure to the gate electrode of the at least one monitoring transistor. This method can utilize a simplified circuit and still effectively monitor the potential at the storage node. Various embodiments of the present disclosure are now described with reference to the accompanying drawings.

[0025] Reference Figure 1A , Figure 1B and Figure 1C , according to an embodiment of the present disclosure, a first circuit schematic diagram, a second circuit schematic diagram, and a third circuit schematic diagram are respectively shown. Each circuit schematic diagram represents a circuit including an array 100 of memory cells 101 and a memory monitoring device 200, and the circuit may include a semiconductor structure formed on the same substrate. Each of the memory cells 101 includes: a respective instance of an access transistor AT; and a respective instance of a memory structure M, which is configured to store a data bit and is electrically connected to a source structure of the respective instance of the access transistor AT. In one embodiment, the array 100 of memory cells 101 may include a two-dimensional array of memory cells 101, and the two-dimensional array of memory cells 101 is configured to be accessed using word lines and bit lines. For example, the array 100 of memory cells 101 can be addressed using M word lines and N bit lines. M and N can be independent positive integers ranging from 2 to 220. The portion of the array 100 shown corresponds to four memory cells addressed by a respective one of the i-th word line WL_i and the (i+1)-th word line WL_(i+1) and by a respective one of the j-th bit line BL_j and the (j+1)-th bit line BL_(j+1). Suitable peripheral circuitry may be provided for the word lines and bit lines. For example, peripheral circuitry such as a word line decoder, a word line driver, a bit line decoder, a bit line driver, and a bit line sensing circuit may be provided. In one embodiment, the bit line sensing circuit may include an operational amplifier using the respective bit line and a reference voltage line as two inputs. The memory structure M may be any memory structure known in the art that may be used to store data, as long as the potentials of the nodes of the memory structure M depend or can be made dependent (during sensing) on ​​the memory bits stored therein.

[0026] The memory monitoring device 200 includes at least one combination of the following devices: an additional instance of an access transistor AT; an additional instance of a memory structure M electrically connected to a source structure of the additional instance of the access transistor AT; and at least one monitoring transistor (MT1, MT2, MT) having a respective monitoring gate electrode electrically connected to the source structure of the additional instance of the access transistor AT. In one embodiment, the memory monitoring device 200 may include multiple combinations of the following devices: an additional instance of an access transistor AT; an additional instance of a memory structure M electrically connected to a source structure of the additional instance of the access transistor AT; and at least one monitoring transistor (MT1, MT2, MT).

[0027] exist Figure 1A In the first configuration shown in , each additional instance of the memory structure M can be electrically connected to a corresponding monitoring transistor (MT1, MT2) and multiple combinations of the following devices: an additional instance of the access transistor AT; an additional instance of the memory structure M; and a monitoring transistor (MT1 or MT2) having a corresponding monitoring gate electrode electrically connected to the source structure of the additional instance of the access transistor AT. Each monitoring transistor (MT1, MT2) monitors the potential of the additional instance of the memory structure M. In this embodiment, each of the monitoring transistors (MT1, MT2) can have a different threshold voltage so that different numbers of monitoring transistors (MT1, MT2) are turned on depending on the voltage at the source node of the additional instance of the memory structure M (i.e., the node electrically connected to the source structure of the additional instance of the access transistor AT). As another option, the magnitude of the current flowing between the source structure and the drain structure of each monitoring transistor (MT1, MT2) under a predetermined source-drain bias voltage condition can be measured to determine the potential at the source node of the additional instance of the memory structure M.

[0028] The memory structure M can be automatically connected to the source node of the additional instance by electrically connecting the gate electrodes of the plurality of monitoring transistors (MT1, MT2) to the source node of the additional instance of the memory structure M. Figure 1A The first configuration shown in Figure 1B. Each monitoring transistor (MT1, MT2) monitors the potential of the same additional instance of the memory structure M. In this embodiment, each of the monitoring transistors (MT1, MT2) may have a different threshold voltage so that different numbers of monitoring transistors (MT1, MT2) are turned on depending on the voltage at the source node of the additional instance of the memory structure M (i.e., the node electrically connected to the source structure of the additional instance of the access transistor AT). As another example, the magnitude of the current flowing between the source structure and the drain structure of each monitoring transistor (MT1, MT2) under a predetermined source-drain bias voltage condition may be measured to determine the potential at the source node of the additional instance of the memory structure M.

[0029] A single additional instance of the memory structure and a single monitoring transistor MT can be used to automatically Figure 1A The first configuration shown in Figure 1B The second configuration shown in Figure 1C In this embodiment, the magnitude of the current flowing between the source and drain structures of the monitoring transistor MT under predetermined source-drain bias voltage conditions can be measured to determine the potential at the source node of the additional instance of the memory structure M.

[0030] In general, the memory monitoring device 200 of the present disclosure may be used to characterize the electrical properties of the memory structure M, including but not limited to the write time of the memory cell 101. During the testing of the semiconductor die of the array 100 including the memory cell 101 and the memory monitoring device 200, the source node and the drain node of each monitoring transistor (MT1, MT2, MT) may be electrically connected to the electrical node of the external tester, and the magnitude of the current between the source node and the drain node of each monitoring transistor (MT1, MT2, MT) may be tested under various test conditions. Alternatively or additionally, the source node and the drain node of each monitoring transistor (MT1, MT2, MT) may be electrically connected to the electrical node of a built-in self-test (BIST) circuit disposed in the same semiconductor die or disposed in another semiconductor die that is bonded to the semiconductor die of the array 100 including the memory cell 101 and the memory monitoring device 200, and various tests may be performed. In some embodiments, a plurality of monitoring transistors (MT1, MT2) (which may include 2 to 16 transistors) with different threshold voltages may be connected to the source node of the access transistor AT in the memory monitoring device 200, and the number of transistors turned on under various programming conditions may be monitored for the memory structure M.

[0031] According to an embodiment of the present disclosure, the semiconductor circuit design of the present disclosure can be stored in a non-temporary machine-readable data storage medium by encoding the non-temporary machine-readable data storage medium with a data set representing the semiconductor circuit design. The "non-temporary" medium described herein refers to all data storage media except infinite space. The "machine-readable" medium described herein refers to any data storage medium that can be read by any machine (electronic machine or non-electronic machine) as known in the art. The "data storage medium" described herein refers to all media in which data can be encoded. As such, non-temporary machine-readable data storage media that can be encoded with a data set representing the semiconductor circuit design of the present disclosure include all portable data storage media or non-portable data storage media, electronic data storage media, magnetic data storage media, optical data storage media, resistive data storage media, or other data storage media known in the art.

[0032] Reference Figure 2A and Figure 2B , showing a first semiconductor structure according to an embodiment of the present disclosure. The first semiconductor structure includes a substrate 8, which may be a semiconductor substrate, such as a commercially available silicon substrate. The substrate 8 may include a semiconductor material layer 9 at its upper portion. The semiconductor material layer 9 may be a surface portion of a bulk semiconductor substrate, or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 includes a single crystal semiconductor material, such as single crystal silicon. In one embodiment, the substrate 8 may include a single crystal silicon substrate including a single crystal silicon material.

[0033] A shallow trench isolation structure 720 including a dielectric material such as silicon oxide may be formed at an upper portion of the semiconductor material layer 9. A suitable doped semiconductor well, such as a p-type well and an n-type well, may be formed in each region laterally surrounded by a portion of the shallow trench isolation structure 720. Field effect transistors (AT, MT) may be formed on the top surface of the semiconductor material layer 9. The field effect transistors may include access transistors AT and monitoring transistors MT. A two-dimensional array of access transistors AT may be formed in the memory array region of the array 100 including the memory cells 101, and at least one additional access transistor AT may be formed in the memory monitoring device region including the memory monitoring device 200.

[0034] For example, each field effect transistor (AT, MT) may include: a source region 732; a drain region 738; a semiconductor channel 735, including a surface portion of the substrate 8 extending between the source region 732 and the drain region 738; and a gate structure 750. The semiconductor channel 735 may include a single crystalline semiconductor material. Each gate structure 750 may include a gate dielectric layer 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. The gate electrode 754 of the monitoring transistor MT is referred to herein as the monitoring gate electrode 754M. A source side metal-semiconductor alloy region 742 may be optionally formed on each source region 732, and a drain side metal-semiconductor alloy region 748 may be optionally formed on each drain region 738. The source region 732 and the optional source side metal-semiconductor alloy region 742 of each field effect transistor (AT, MT) are referred to herein as source structures (732, 742). The drain region 738 and the optional drain-side metal-semiconductor alloy region 748 of each field effect transistor (AT, MT) are referred to herein as drain structures (738, 748). Although the present disclosure is illustrated using planar field effect transistors, embodiments in which fin field effect transistors, all-around gate field effect transistors, or field effect transistors having different configurations are used in place of planar field effect transistors are clearly contemplated.

[0035] In one embodiment, the substrate 8 may include a single crystal silicon substrate, and the field effect transistor (AT, MT) may include a corresponding portion of the single crystal silicon substrate as a semiconducting channel. The "semiconducting" element described herein refers to a device having a capacitance between 1.0×10 -6 S / cm to 1.0×10 5 S / cm. The "semiconductor material" described herein refers to a semiconductor material having a conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5 S / cm, and when appropriately doped with electrical dopants, can produce materials with conductivity ranging from 1.0 S / cm to 1.0×10 5 S / cm. In the embodiment where the semiconductor material layer 9 comprises a single crystalline semiconductor material such as single crystalline silicon, the semiconductor channel 735 of each field effect transistor (AT, MT) may comprise a single crystalline semiconductor channel such as a single crystalline silicon channel. In one embodiment, each access transistor AT may comprise a corresponding source node, which is then electrically connected to a node of a corresponding memory structure to be formed subsequently.

[0036] Various metal interconnect structures embedded in the dielectric material layer are formed on the substrate 8 and the field effect transistor (AT, MT). In an exemplary example, the dielectric material layer may include a first dielectric material layer 601 (also referred to as a contact level dielectric material layer 601) surrounding the contact via structure contacting the source structure (732, 742) and the drain structure (738, 748), a first interconnect level dielectric material layer 610, and a second interconnect level dielectric material layer 620. The metal interconnect structure may include: a device contact via structure 612, formed in the first dielectric material layer 601 and contacting the corresponding component of the field effect transistor (AT, MT); a first metal line structure 618, formed in the first interconnect level dielectric material layer 610; a first metal via structure 622, formed in the lower portion of the second interconnect level dielectric material layer 620; and a second metal line structure 628, formed in the upper portion of the second interconnect level dielectric material layer 620.

[0037] Each of the dielectric material layers (601, 610, 620) may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612, 618, 622, 628) may include at least one conductive material, which may be a combination of a metal liner material (e.g., a metal nitride or a metal carbide) and a metal filler material. Each metal liner material may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liner materials and metal filler materials within the intended scope of the present disclosure may also be used. In one embodiment, the first metal via structure 622 and the second metal line structure 628 may be formed as an integrated line structure and via structure via a dual damascene process. The dielectric material layers (601, 610, 620) are referred to herein as lower-level dielectric material layers. The metal interconnect structures (612, 618, 622, 628) located within the lower-level dielectric material layers are referred to herein as lower-level metal interconnect structures.

[0038] The above can be provided Figure 1A , Figure 1B and Figure 1CThe memory structure M is formed in the dielectric material layer (601, 610, 620) in the manner of one of the semiconductor circuit designs discussed. As such, each memory structure M may be formed such that a source node of the memory structure M is electrically connected to a source structure (732, 742) of a corresponding one of the access transistors AT provided in the memory array region and in the memory monitoring device region. In one embodiment, each memory structure M may include a capacitor structure 660 including a corresponding first electrode 662 electrically connected to the source structure (732, 742) of the corresponding instance of the access transistor AT, a corresponding node dielectric layer 664, and a corresponding second electrode 666.

[0039] In the first semiconductor structure, a substrate 8 includes a semiconductor material layer 9, and each instance of an access transistor AT includes a corresponding single crystalline semiconductor channel. The at least one monitoring transistor MT has a corresponding monitoring gate electrode 754M. An instance of a memory structure (M; 660) is formed, and the instance of the memory structure (M; 660) is configured to store a corresponding data bit therein. Electrical connections are formed to and from the instances of the access transistor AT, the at least one monitoring transistor MT, and the instance of the memory structure (M; 660) so as to form an array 100 of memory cells 101 and a memory monitoring device 200.

[0040] In one embodiment, a metal via structure (e.g., device contact via structure 612) located on the source structure (732, 742) may be formed on each instance of the access transistor AT. In one embodiment, each instance of the memory structure (M; 660) includes a first electrode 662, a node dielectric layer 664, and a second electrode 666, and the first electrode 662 of each instance of the memory structure (M; 660) is electrically connected to the source structure (732, 742) of the corresponding instance of the access transistor AT via the metal via structure (612 or 652). In one embodiment, the bit line 628B may include a subset of the second metal line structure 628, or alternatively, include a subset of the first metal line structure 618.

[0041] In a first semiconductor structure, an array 100 of memory cells 101 may be located above a substrate 8. Each of the memory cells 101 includes: a respective instance of an access transistor AT; and a respective instance of a memory structure (M; 660) configured to store a data bit and electrically connected to a source structure (732, 742) of the respective instance of the access transistor AT. A memory monitoring device 200 may be provided, the memory monitoring device 200 including: at least one additional instance of an access transistor AT; at least one additional instance of a memory structure (M; 660) electrically connected to a source structure (732, 742) of a respective one of the at least one additional instance of the access transistor AT; and at least one monitoring transistor MT having a respective monitoring gate electrode 754M electrically connected to the source structure (732, 742) of the respective one of the at least one additional instance of the access transistor AT.

[0042] In one embodiment, the monitor gate electrode 754M may be electrically connected to the source structure (732, 742) by forming at least one metal via structure and at least one metal line between the monitor gate electrode 754M of the at least one monitor transistor MT and the source structure (732, 742) of the corresponding instance of the access transistor AT. In one embodiment, each monitor gate electrode 754M of the at least one monitor transistor MT is electrically connected to the source structure (732, 742) of the corresponding one of the at least one additional instance of the access transistor AT via at least one metal via structure (e.g., at least one device contact via structure 612) and at least one metal line (e.g., at least one first metal line structure 618). For example, a combination of the following devices can be used to provide a conductive path between each electrical connection pair of the source structure (732, 742) and the monitoring gate electrode 754M: a source contact via structure 6121 in contact with the source structure (732, 742); a connecting metal line structure 648C in contact with the top surface of the source contact via structure 6121; and a gate contact via structure 6122 in contact with the bottom surface of the connecting metal line structure 648C; and the monitoring gate electrode 754M.

[0043] In one embodiment, each memory structure M may include a capacitor structure 660, and the first electrode 662 of each instance of the memory structure (M; 660) may be electrically connected to the source structure (732, 742) of the corresponding instance of the access transistor AT via a metal via structure (e.g., a device contact via structure 612), wherein the metal via structure may be the same as the source contact via structure 6121 or may be different from the source contact via structure 6121.

[0044] Reference FIG. 3A to FIG. 3F , showing various regions and configurations of a second semiconductor structure according to an embodiment of the present disclosure. Figure 3A , Figure 3B , Figure 3C and Figure 3E are vertical cross-sectional views of various configurations of the memory monitor device region of the second semiconductor structure. Figure 3D yes Figure 3C Schematic top view of the configuration of the second semiconductor structure shown in . Figure 3F is a vertical cross-sectional view of a memory array region of a second semiconductor structure. Generally speaking, the second semiconductor structure may include Figure 3F The array 100 of memory cells 101 shown in FIG. Figure 3A , Figure 3B , Figure 3C and Figure 3D or Figure 3E Any configuration of the memory monitoring device 200 shown in .

[0045] In general, the field effect transistor 701 formed on the semiconductor material layer 9 can be used for some other purpose than the access transistor and the monitoring transistor and by connecting the field effect transistor 701 formed on the semiconductor material layer 9 to the interconnection layer 701 at the interconnection level overlying at least one dielectric material layer (601, 610, 620). Figure 1A , Figure 1B or Figure 1C The access transistor AT and the monitoring transistor MT shown in the figure are formed as thin film transistors and the second semiconductor structure is obtained from the first semiconductor structure. The field effect transistor 701 formed on the semiconductor material layer 9 can be used for logic circuits or for another memory array, such as an array of static random access memory (SRAM).

[0046] In addition to forming the field effect transistor 701 for targets other than the access transistor AT and the monitoring transistor MT, the second semiconductor structure also includes additional metal interconnect structures (632, 638, 642, 648, 652, 658) formed in additional dielectric material layers (630, 640, 650). In an illustrative example, the additional dielectric material layers (630, 640, 650) may include a third interconnect level dielectric material layer 630, a fourth interconnect level dielectric material layer 640, and a fifth interconnect level dielectric material layer 650. Additional metal interconnect structures (632, 638, 642, 648, 652, 658) may include: a second metal via structure 632 formed in the lower portion of the third interconnect level dielectric material layer 630; a third metal line structure 638 formed in the upper portion of the third interconnect level dielectric material layer 630; a third metal via structure 642 formed in the lower portion of the fourth interconnect level dielectric material layer 640; a fourth metal line structure 648 formed in the upper portion of the fourth interconnect level dielectric material layer 640; a fourth metal via structure 652 formed in the lower portion of the fifth interconnect level dielectric material layer 650; and a fifth metal line structure 658 formed in the upper portion of the fifth interconnect level dielectric material layer 650.

[0047] Each of the additional dielectric material layers (630, 640, 650) may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the additional metal interconnect structures (632, 638, 642, 648, 652, 658) may include at least one conductive material, which may be a combination of a metal liner material (e.g., a metal nitride or a metal carbide) and a metal filler material. Each metal liner material may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liner materials and metal filler materials within the intended scope of the present disclosure may also be used. In one embodiment, at least one metal via structure (732, 742, 652) and a corresponding overlying metal line structure (638, 648, 658) may be formed as an integrated line structure and via structure via a dual damascene process. The additional dielectric material layer (630, 640, 650) is referred to herein as an upper level dielectric material layer. The additional metal interconnect structure (632, 638, 642, 648, 652, 658) within the upper level dielectric material layer (630, 640, 650) is referred to herein as an upper level metal interconnect structure.

[0048] According to aspects of the present disclosure, thin film transistors (AT, MT) and memory structures M may be formed within the upper level dielectric material layer (630, 640, 650). The thin film transistors (AT, MT) include access transistors AT and monitoring transistors MT. Each of the thin film transistors (AT, MT) may include a gate electrode 15, a gate dielectric 20, a semiconductive metal oxide channel 30, a source structure 52, and a drain structure 58. Each of the access transistors AT includes an access gate electrode 15A, an access gate dielectric 20A, and an access-transistor channel 30A. Each of the monitoring transistors MT includes a monitoring gate electrode 15M, a monitoring gate dielectric 20M, and a monitoring-transistor channel 30M. Each of the access gate electrodes 15A may be part of a corresponding word line within the array 100 of memory elements 101.

[0049] Each of the gate electrodes 15 may include a patterned portion of a gate conductor layer, which may be a metal layer including a gate electrode metal. The gate dielectric 20 includes a gate dielectric material, such as silicon oxide and / or at least one dielectric metal oxide.

[0050] The semiconductive metal oxide channel 30 includes a semiconductive material. The semiconductive metal oxide channel 30 can be formed by depositing a polycrystalline semiconductive metal oxide layer and patterning the polycrystalline semiconductive metal oxide layer. Each instance of the access transistor AT includes a corresponding polycrystalline semiconductive metal oxide channel 30, which includes a corresponding patterned portion of the polycrystalline semiconductive metal oxide layer. Examples of semiconductive materials that can be used for the semiconductive metal oxide channel 30 include, but are not limited to, indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, doped cadmium oxide, and various other doped variants derived therefrom. Alternatively, amorphous silicon, polycrystalline silicon, or a silicon-germanium alloy can be used for the semiconductive metal oxide channel 30. In one embodiment, the semiconductive metal oxide channel 30 can be a polycrystalline semiconductive metal oxide channel.

[0051] The source structure 52 and the drain structure 58 may be formed as a subset of the upper level metal interconnect structures (632, 638, 642, 648, 652, 658). In the example shown, the source structure 52 and the drain structure 58 may be formed as a subset of the third metal via structure 642. According to aspects of the present disclosure, the metal interconnect structures (632, 638, 642, 648, 652, 658) may be used to provide reference Figure 1A , Figure 1B or Figure 1CA subset of the metal interconnect structures (632, 638, 642, 648, 652, 658), such as a subset of the fourth metal line structure 648, can be used as bit line 648B. The second electrode 666 of each capacitor structure 660 can be electrically grounded, such as via a subset of the metal interconnect structures (632, 638, 642, 648, 652, 658) (not shown).

[0052] Although the present disclosure is described using an embodiment in which the thin film transistor (AT, MT) is formed at the level of the fourth interconnect level dielectric material layer 640, the thin film transistor (AT, MT) may be formed at any interconnect level overlying the field effect transistor 701 and embedded in the corresponding back-end-of-line (BEOL) level (i.e., embedded in the dielectric material layer). Figure 1A , Figure 1B and Figure 1C The electrically connected structures in the semiconductor circuit design may include a subset of metal interconnect structures embedded in a dielectric material layer, wherein the dielectric material layer is located at the same level as the thin film transistor (AT, MT), below the thin film transistor (AT, MT) and / or above the thin film transistor (AT, MT).

[0053] A memory structure M may be formed above the thin film transistor (AT, MT), at the same level as the thin film transistor (AT, MT), or below the thin film transistor (AT, MT). In an illustrative example, the memory structure M may include a capacitor structure 660. Each capacitor structure 660 may include: a corresponding first electrode 662 electrically connected to the source structure 52 of the corresponding instance of the access transistor AT; a corresponding node dielectric layer 664; and a corresponding second electrode 666. The memory structure M may be embedded in a dielectric material layer. In the example shown, the memory structure M is embedded in the fifth interconnect level dielectric material layer 650.

[0054] A metal via structure (e.g., source-connected metal via structure 652S) may be formed on the source structure 52 of each instance of the access transistor AT. In one embodiment, the first electrode 662 of each instance of the memory structure (M; 660) is electrically connected to the source structure 52 of the corresponding instance of the access transistor AT via at least the metal via structure (e.g., source-connected metal via structure 652S). In one embodiment, the first electrode 662 of each capacitor structure 660 may be electrically connected to the source node (including the source structure 52) of the corresponding access transistor AT via at least one metal interconnect structure (e.g., a combination of a metal line structure (e.g., source-connected metal line 648S) and a metal via structure (e.g., source-connected metal via structure 652S)).

[0055] In general, the semiconductor device in the second semiconductor structure may include: an array 100 of memory cells 101, located above a substrate 8, wherein each of the memory cells 101 includes a corresponding instance of an access transistor AT and a corresponding instance of a memory structure (M; 660), the corresponding instance of the memory structure (M; 660) being configured to store data bits and electrically connected to a source structure 52 of the corresponding instance of the access transistor AT; and a memory monitoring device 200, including an additional instance of the access transistor AT, an additional instance of the memory structure (M; 660) and at least one monitoring transistor MT, the additional instance of the memory structure (M; 660) being electrically connected to the source structure 52 of the additional instance of the access transistor AT, the at least one monitoring transistor MT having a corresponding monitoring gate electrode 15M electrically connected to the source structure 52 of the additional instance of the access transistor AT.

[0056] The monitoring gate electrode 15M of each monitoring transistor MT can be electrically connected to the source structure 52 of the corresponding access transistor AT. In one embodiment, the monitoring gate electrode 15M of the at least one monitoring transistor MT of the memory monitoring device 200 is electrically connected to the source structure 52 of the additional instance of the access transistor AT via at least one metal via structure 642 and at least one metal line 648, such as Figure 3B , Figure 3C , Figure 3D and Figure 3E The at least one metal line 648 for providing a conductive path between the monitoring gate electrode 15M and the source structure 52 of the at least one monitoring transistor MT may include Figure 3B As another option, the at least one metal line 648 for providing a conductive path between the monitoring gate electrode 15M of the at least one monitoring transistor MT and the source structure 52 may include a connecting metal line structure 648C, which is different from the source-connecting metal line 648S, such as Figure 3C , Figure 3D and Figure 3E as shown in .

[0057] In another embodiment, the source structure 52 of the additional instance of the access transistor AT in the memory monitoring device 200 may be formed directly on the monitoring gate electrode 15M of the at least one monitoring transistor MT in the memory monitoring device 200. In this embodiment, the monitoring gate electrode 15M of the at least one monitoring transistor MT may be in contact with the source structure 52 of the additional instance of the access transistor AT, such as Figure 3A shown.

[0058] In one embodiment, each instance of the memory structure (M; 660) includes a first electrode 662, a node dielectric layer 664, and a second electrode 666. The first electrode 662 of an additional instance of the memory structure (M; 660) is electrically connected to the source structure 52 of the additional instance of the access transistor AT via at least one metal via structure (e.g., source-connection metal via structure 652S).

[0059] In one embodiment, each instance of access transistor AT includes a corresponding polycrystalline semiconducting metal oxide channel (eg, access-transistor channel 30A).

[0060] In one embodiment, the at least one monitoring transistor MT includes a plurality of monitoring transistors MT having different threshold voltages.

[0061] In embodiments where the access transistors AT include thin film transistors including semiconducting metal oxide channels, a low power memory array may be provided that can operate using long refresh cycles. In one embodiment, for routing purposes, the source structure 52 may extend laterally over multiple access-transistor channels 30A, such as Figure 3C and Figure 3D In this embodiment, the plurality of access-transistor channels 30A may have the same periodicity as the array 100 of memory cells 101, and when physically implemented in the second semiconductor structure, the circuit design of the memory monitoring device 200 may be comparable to the circuit design of the array 100 of memory cells 101.

[0062] In some embodiments, the memory monitoring device 200 can be fully implemented in the BEOL level without requiring any front-end-of-line (FEOL) devices such as the field effect transistor 701 .

[0063] Reference Figure 4A and Figure 4B , showing a third semiconductor structure according to an embodiment of the present disclosure. Figure 2A and Figure 2B Each capacitor structure 660 shown in derives a third semiconductor structure from the first semiconductor structure. Each instance of a memory structure (M; 670) in the third semiconductor structure includes: a corresponding first electrode 672 electrically connected to the source structure 52 of the corresponding instance of the access transistor AT; a memory material portion 674 having at least two resistivity states exhibiting different resistivities; and a corresponding second electrode 676.

[0064] Any resistive memory structure known in the art may be used for the resistive memory structure 670 of the present disclosure. A resistive memory device is a non-volatile memory device that utilizes a resistive switching mechanism to store data. Resistive memory devices include metal-insulator-metal (MIM) resistive memory devices, phase change memory (PCM) devices, conductive-bridging resistive memory devices, and filamentary resistive memory devices. MIM resistive memory devices utilize an insulator material having two different resistivity states. PCM devices utilize phase change materials having two different resistivity states (e.g., amorphous and crystalline). Conductive-bridging resistive memory devices use conductive materials (e.g., silver) to reversibly form a conductive filament between two electrodes. Filamentary resistive memory devices utilize conductive filaments formed in a dielectric metal oxide material to modulate conductivity.

[0065] In general, any memory structure known in the art may be used for the memory structure M of the present disclosure, as long as a change in potential is generated at the source node (i.e., a node of the source structure) or a change in potential can be generated when a suitable electrical bias is applied to a node (e.g., the second electrode) of the memory structure M and / or to a node of the access transistor AT in the memory monitoring device 200.

[0066] Figure 4C It is shown in the Figure 4A and Figure 4B Graph of voltage-current characteristics during set and reset operations of a memory structure in a third semiconductor structure shown. The horizontal axis represents the bias voltage V_s applied across the second electrode 676 and the drain structure 58 during a programming operation, and the vertical axis represents the current I_s flowing between the second electrode 676 and the drain structure 58. A bias voltage of a first polarity may be applied to perform a set operation, in which the high resistivity state of the memory material portion 674 is switched to a low resistivity state. A bias voltage of a second polarity (opposite to the first polarity) may be applied to perform a reset operation, in which the low resistivity state of the memory material portion 674 is switched to a high resistivity state. The current-voltage characteristics during a ramp-down of the applied voltage after a set operation or after a reset operation are shown in dashed lines.

[0067] During testing of the memory monitoring device 200, a bias voltage may be applied to the second electrode 676 and the drain structure 58 of the memory monitoring device 200. When the memory material portion 674 is in the low resistivity state, the voltage at the source node (i.e., the voltage at the source structure 52) is almost entirely determined by the voltage applied to the second electrode 676 and is not significantly affected by the voltage applied to the drain structure 58. When the memory material portion 674 is in the high resistivity state, the voltage at the source node (i.e., the voltage at the source structure 52) is not significantly affected by the voltage applied to the second electrode 676 and is almost entirely determined by the voltage applied to the drain structure 58. By applying various combinations of bias voltages to the second electrode 676 and the drain structure 58 during testing, the device characteristics of the memory structure 54 may be characterized.

[0068] Reference Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E , showing various configurations of a fourth semiconductor structure according to an embodiment of the present disclosure. Figure 5A , Figure 5B , Figure 5C and Figure 5D are vertical cross-sectional views of various configurations of the memory monitor device region of the fourth semiconductor structure. Figure 5E is a vertical cross-sectional view of a memory array region of a fourth semiconductor structure. Generally speaking, the fourth semiconductor structure may include Figure 5E The array 100 of memory cells 101 shown in FIG. Figure 5A , Figure 5B , Figure 5C or Figure 5D Any configuration of the memory monitoring device 200 shown in .

[0069] In general, alternative memory structures (such as resistive memory structure 670) may be used instead. FIG. 4A to FIG. 4C Each capacitor structure 660 shown in FIG. FIG. 3A to FIG. 3F Various configurations of the second semiconductor structure shown in the fourth semiconductor structure result in various configurations of the fourth semiconductor structure. Each instance of the memory structure (M; 670) in the fourth semiconductor structure includes: a corresponding first electrode 672 electrically connected to the source structure 52 of the corresponding instance of the access transistor AT; a memory material portion 674 having at least two resistivity states exhibiting different resistivities; and a corresponding second electrode 676. The second electrode 676 of the resistive memory structure 670 can be electrically connected to a corresponding source bias line 658S, which can be implemented as, for example, a subset of the fifth metal line structure 658 or another subset of the metal interconnect structures (632, 638, 642, 648, 652, 658) (not shown).

[0070] The fourth semiconductor structure can be operated in the same manner as the second semiconductor structure, with appropriate changes in using a resistive memory structure 670 instead of the capacitor structure 660. In general, any type of memory structure known in the art can be used to replace the resistive memory structure 670 of each memory cell 101 and each memory monitoring device 200 in the fourth semiconductor structure. The memory structure M can be formed at a suitable metal interconnect level.

[0071] Reference Figure 6 , a flow chart illustrating general processing steps for fabricating the semiconductor structure of the present disclosure.

[0072] Refer to step 605 and Figures 1A to 4B and FIG. 5A to FIG. 5E , an example of an access transistor AT may be formed over the substrate 8 .

[0073] Refer to step 625 and Figures 1A to 4B and FIG. 5A to FIG. 5E , at least one monitoring transistor MT having a corresponding monitoring gate electrode (754M or 15M) can be formed.

[0074] Refer to step 635 and Figures 1A to 4B and FIG. 5A to FIG. 5E , may form an instance of a memory structure (M; 660 or 670), which may be configured to store corresponding data bits therein.

[0075] Refer to step 645 and Figures 1A to 4B and FIG. 5A to FIG. 5E , electrical connections to and from the instance of the access transistor AT, the at least one monitoring transistor MT, and the instance of the memory structure (M; 660 or 670) may be formed before or after forming the instance of the memory structure (M; 660 or 670). An array 100 of memory cells 101 and a memory monitoring device are formed. In one embodiment, each of the memory cells 101 includes: a respective instance of the access transistor AT; and a respective instance of the memory structure (M; 660 or 670), a source structure {(732, 742) or 52} electrically connected to the respective instance of the access transistor AT. In one embodiment, the memory monitoring device 200 includes: an additional instance of the access transistor AT; an additional instance of the memory structure (M; 660 or 670), electrically connected to the source structure {(732, 742) or 52} of the additional instance of the access transistor AT; and the at least one monitoring transistor MT, the corresponding monitoring gate electrode (754M or 15M) of the at least one monitoring transistor MT being electrically connected to the source structure {(732, 742) or 52} of the additional instance of the access transistor AT.

[0076] With reference to all the drawings and according to various embodiments of the present disclosure, there is provided a semiconductor device, the semiconductor device comprising: an array 100 of memory cells 101, located on a substrate 8, wherein each of the memory cells 101 comprises a corresponding instance of an access transistor AT and a corresponding instance of a memory structure (M; 660 or 670), the corresponding instance of the memory structure (M; 660 or 670) being configured to store a data bit and electrically connected to a source structure {(732, 742) or 52} of the corresponding instance of the access transistor AT; and a memory monitor The present invention relates to a detection device 200, comprising an additional instance of an access transistor AT, an additional instance of a memory structure (M; 660 or 670), and at least one monitoring transistor MT, wherein the additional instance of the memory structure (M; 660 or 670) is electrically connected to the source structure {(732, 742) or 52} of the additional instance of the access transistor AT, and the at least one monitoring transistor MT has a corresponding monitoring gate electrode (754M or 15M) electrically connected to the source structure {(732, 742) or 52} of the additional instance of the access transistor AT.

[0077] In one embodiment, the monitoring gate electrode (754M or 15M) of the at least one monitoring transistor MT is electrically connected to the source structure {(732, 742) or 52} of the additional instance of the access transistor AT via at least one metal via structure (612 or 642) and at least one metal line (618 or 648).

[0078] In one embodiment, the monitor gate electrode (754M or 15M) of the at least one monitor transistor MT is in contact with the source structure {(732, 742) or 52} of the additional instance of the access transistor AT.

[0079] In one embodiment, each instance of the memory structure (M; 660 or 670) includes a first electrode (662 or 672), a memory material layer 674 or a node dielectric layer 664, and a second electrode (666 or 676); and the first electrode (662 or 672) of an additional instance of the memory structure (M; 660 or 670) is electrically connected to the source structure {(732, 742) or 52} of an additional instance of the access transistor AT via a metal through-hole structure (612 or 652).

[0080] In one embodiment, substrate 8 includes a layer 9 of semiconductor material; and each instance of access transistor AT includes a respective single crystalline semiconductor channel.

[0081] In one embodiment, each instance of access transistor AT includes a respective polycrystalline semiconducting metal oxide channel 30 .

[0082] In one embodiment, the at least one monitoring transistor MT includes a plurality of monitoring transistors MT having different threshold voltages.

[0083] In one embodiment, each instance of a memory structure (M; 660 or 670) includes a corresponding capacitor structure 660, wherein the corresponding capacitor structure 660 includes: a corresponding first electrode (662 or 672), electrically connected to the source structure {(732, 742) or 52} of the corresponding instance of the access transistor AT; a corresponding node dielectric layer 664; and a corresponding second electrode (666 or 676).

[0084] In one embodiment, each instance of a memory structure (M; 660 or 670) includes: a corresponding first electrode (662 or 672) electrically connected to a source structure {(732, 742) or 52} of a corresponding instance of an access transistor AT; a memory material portion 674 having at least two resistivity states exhibiting different resistivities; and a corresponding second electrode (666 or 676).

[0085] According to another aspect of the present disclosure, a non-transitory machine-readable data storage medium is provided, wherein the non-transitory machine-readable data storage medium is encoded with a data set representing a semiconductor circuit design. The data set includes: first data representing an array 100 of memory cells 101 located on a substrate 8, wherein each of the memory cells 101 includes a corresponding instance of an access transistor AT and a corresponding instance of a memory structure (M; 660 or 670), wherein the corresponding instance of the memory structure (M; 660 or 670) is configured to store a data bit and is electrically connected to a source structure {(732, 742) or 52} of the corresponding instance of the access transistor AT; and second data representing a memory monitoring device 200, wherein the memory monitoring device 200 includes an additional instance of an access transistor AT, an additional instance of a memory structure (M; 660 or 670), and at least one monitoring transistor MT, wherein the additional instance of the memory structure (M; 660 or 670) is electrically connected to the source structure {(732, 742) or 52} of the additional instance of the access transistor AT, and the at least one monitoring transistor MT has a corresponding monitoring gate electrode (754M or 15M) electrically connected to the source structure {(732, 742) or 52} of the additional instance of the access transistor AT.

[0086] In one embodiment, within a semiconductor circuit design, the monitoring gate electrode (754M or 15M) of the at least one monitoring transistor MT is electrically connected to the source structure {(732, 742) or 52} of an additional instance of the access transistor AT via at least one metal via structure (612 or 642) and at least one metal line (618 or 648).

[0087] In one embodiment, within the semiconductor circuit design, the monitor gate electrode (754M or 15M) of the at least one monitor transistor MT contacts the source structure {(732, 742) or 52} of the additional instance of the access transistor AT.

[0088] In one embodiment, within a semiconductor circuit design, each instance of a memory structure (M; 660 or 670) includes a first electrode (662 or 672), a memory material layer 674 or a node dielectric layer 664, and a second electrode (666 or 676); and the first electrode (662 or 672) of an additional instance of the memory structure (M; 660 or 670) is electrically connected to a source structure {(732, 742) or 52} of an additional instance of an access transistor AT via a metal via structure (612 or 652).

[0089] In one embodiment, within the semiconductor circuit design, the at least one monitoring transistor MT includes a plurality of monitoring transistors MT having different threshold voltages.

[0090] In one embodiment, within a semiconductor circuit design, each instance of a memory structure (M; 660 or 670) includes a corresponding capacitor structure 660, the corresponding capacitor structure 660 including: a corresponding first electrode (662 or 672), electrically connected to a source structure {(732, 742) or 52} of a corresponding instance of an access transistor AT; a corresponding node dielectric layer 664 or a corresponding memory material portion 674; and a corresponding second electrode (666 or 676).

[0091] According to aspects of the present disclosure, a method for forming a semiconductor device is provided. The method includes: forming an instance of an access transistor AT, an additional instance of the access transistor AT, and at least one monitoring transistor MT having a corresponding monitoring gate electrode (754M or 15M) on a substrate 8; and forming an instance of a memory structure (M; 660 or 670) configured to store data bits and an additional instance of the memory structure (M; 660 or 670), thereby forming an array 100 of memory cells 101 and a memory monitoring device 200, and wherein: each of the memory cells 101 includes a corresponding instance of the access transistor AT and a corresponding instance of the memory structure (M; 660 or 670), and the memory structure (M; 660 or 670) is electrically connected to the source structure {(732, 742) or 52} of the corresponding instance of the access transistor AT; and the memory monitoring device 200 includes an additional instance of the access transistor AT, an additional instance of the memory structure (M; 660 or 670) and the at least one monitoring transistor MT, the additional instance of the memory structure (M; 660 or 670) is electrically connected to the source structure {(732, 742) or 52} of the additional instance of the access transistor AT; and the corresponding monitoring gate electrode (754M or 15M) is electrically connected to the source structure {(732, 742) or 52} of the additional instance of the access transistor AT.

[0092] In one embodiment, a method of forming a semiconductor device is provided. The method includes forming an array 100 of memory cells 101 and a memory monitoring device 200 on a substrate 8. Each of the memory cells 101 includes a corresponding instance of an access transistor AT and a corresponding instance of a memory structure (M; 660 or 670), the corresponding instance of the memory structure (M; 660 or 670) being configured to store a data bit and electrically connected to a source structure {(732, 742) or 52} of the corresponding instance of the access transistor AT. The memory monitoring device 200 includes an additional instance of an access transistor AT, an additional instance of a memory structure (M; 660 or 670), and at least one monitoring transistor MT, wherein the additional instance of the memory structure (M; 660 or 670) is electrically connected to the source structure {(732, 742) or 52} of the additional instance of the access transistor AT, and the at least one monitoring transistor MT has a corresponding monitoring gate electrode (754M or 15M) electrically connected to the source structure {(732, 742) or 52} of the additional instance of the access transistor AT.

[0093] Embodiments of the present disclosure provide a new method for in-situ monitoring of the potential of a storage node in a memory cell. The method utilizes a monitoring circuit that uses only one type of transistor (e.g., n-type), thereby eliminating the need for a complementary metal oxide semiconductor (CMOS) circuit. Compared to conventional methods, the test pattern size can be reduced, thereby producing an area-efficient and cost-effective solution for monitoring the performance of storage nodes. Optionally, the memory monitoring circuit of the present disclosure can use multiple monitoring transistors with different threshold voltages to measure the amount of charge in a capacitor or the resistivity of a resistive memory element. The storage node of the memory structure M can be connected to the monitoring gate electrode of at least one monitoring transistor MT, thereby allowing the potential change of the storage node to be amplified to be amplified for easy in-situ monitoring during operation of the array 100 of memory cells 101.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. A semiconductor device, characterized in that: include: an array of memory cells overlying a substrate, wherein each of the memory cells comprises a respective instance of an access transistor and a respective instance of a memory structure, the respective instance of the memory structure being configured to store a data bit and the respective instance of the memory structure being electrically connected to a source structure of the respective instance of the access transistor; as well as A memory monitoring device comprising an additional instance of the access transistor, an additional instance of the memory structure, and at least one monitoring transistor, wherein the additional instance of the memory structure is electrically connected to the source structure of the additional instance of the access transistor, and the at least one monitoring transistor has a monitoring gate electrode electrically connected to the source structure of the additional instance of the access transistor.

2. The semiconductor device according to claim 1, wherein: Wherein the monitor gate electrode of the at least one monitor transistor is electrically connected to the source structure of the additional instance of the access transistor via at least one metal via structure and at least one metal line.

3. The semiconductor device according to claim 1, wherein: Wherein the monitor gate electrode of the at least one monitor transistor is in contact with the source structure of the additional instance of the access transistor.

4. The semiconductor device according to claim 1, wherein: in: Each instance of the memory structure includes a first electrode, a memory material layer or a node dielectric layer, and a second electrode; and The first electrode of the additional instance of the memory structure is electrically connected to the source structure of the additional instance of the access transistor via a metal via structure.

5. The semiconductor device according to claim 1, wherein: in: The substrate comprises a layer of semiconductor material; and Each instance of the access transistor includes a corresponding single crystalline semiconductor channel.

6. The semiconductor device according to claim 1, wherein: Each instance of the access transistor includes a corresponding polycrystalline semiconducting metal oxide channel.

7. The semiconductor device according to claim 1, wherein: The at least one monitoring transistor includes a plurality of monitoring transistors having different threshold voltages.

8. The semiconductor device according to claim 1, wherein: wherein each instance of the memory structure comprises a corresponding capacitor structure, the corresponding capacitor structure comprising: a respective first electrode electrically connected to the source structure of the respective instance of the access transistor; a corresponding node dielectric layer; and a corresponding second electrode.

9. The semiconductor device according to claim 1, wherein: Each instance of the memory structure includes: a respective first electrode electrically connected to the source structure of the respective instance of the access transistor; a memory material portion having at least two resistivity states exhibiting different resistivities; and a corresponding second electrode.

10. The semiconductor device according to claim 1, wherein: The source structure is a storage node in the storage unit.

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