Package structure

Abstract

The embodiment of the utility model relates to a packaging structure. The packaging structure comprises a packaging substrate; the packaging module is located on the packaging substrate; a thermal interface material (TIM) layer on the package module; and the packaging cover is positioned on the thermal interface heat dissipation layer. The packaging cover comprises a packaging cover foot part which is attached to the packaging substrate; and a package cover plate portion on the package cover foot portion and including a patterned bottom surface having a plurality of recessed portions, in which at least a portion of the thermal interface heat dissipation layer is located in the plurality of recessed portions.

Description

Technical Field

[0001] The embodiment of the utility model relates to a packaging structure. Background Art

[0002] In semiconductor packaging, a thermal interface material (TIM) layer may be located between the package module (e.g., semiconductor device) and the package cover (e.g., heat sink). The TIM layer can improve thermal contact by filling small gaps and irregularities between surfaces. Sometimes a phenomenon known as "pump-out" occurs, in which the TIM layer shifts from the interface, resulting in a loss of thermal contact and reduced heat transfer efficiency.

[0003] Pumping out of the TIM layer in the package structure may occur in different ways including: lateral flow (the TIM layer may flow laterally away from the interface due to shear forces caused by thermal cycling), vertical flow (the TIM layer may flow vertically away from the interface due to pressure differences caused by thermal cycling), extrusion (the TIM layer may be squeezed out of the interface due to mechanical stress caused by different thermal expansion between the TIM layer, the package module and the package cover), and evaporation (volatile components of the TIM layer may evaporate, causing the TIM layer to shrink and lose its thermal contact with the interface). Utility Model Content

[0004] In one embodiment, the utility model provides a packaging structure, which includes: a packaging substrate; a packaging module located on the packaging substrate; a thermal interface heat dissipation layer located on the packaging module; and a packaging cover located on the thermal interface heat dissipation layer, including: a packaging cover foot portion adhered to the packaging substrate; and a packaging cover plate portion, including a patterned bottom surface having a plurality of recessed portions, wherein at least a portion of the thermal interface heat dissipation layer is located in the plurality of recessed portions.

[0005] In one embodiment, the utility model provides a packaging structure, which includes: a packaging substrate; a packaging module located on the packaging substrate; a packaging cover located on the packaging module, including: a plate portion having a bottom surface including a recessed structure; and a foot portion connected to the plate portion and adhered to the packaging substrate; and a thermal interface heat dissipation layer located between the packaging module and the bottom surface of the plate portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the embodiments of the present invention will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A is a vertical cross-sectional view of a package structure according to one or more embodiments.

[0008] Figure 1B is a plan view (eg, top view) of a package structure according to one or more embodiments.

[0009] Figure 1C is a detailed vertical cross-sectional view of a TIM layer in a package structure according to one or more embodiments.

[0010] Figure 2A is a plan view (eg, top view) of an underside of a lid portion of a package according to one or more embodiments.

[0011] Figure 2B is a detailed plan view (eg, top view) of an underside of a lid portion of a package according to one or more embodiments.

[0012] Figure 3 A stamping process is shown for forming a patterned bottom surface of a package cap in accordance with one or more embodiments.

[0013] FIG. 4A to FIG. 4I Various bump pads that may be used in a stamping process are shown in accordance with one or more embodiments.

[0014] Figure 5A is a vertical cross-sectional view of an intermediate structure including a package substrate having package substrate upper bonding pads and package substrate lower bonding pads according to one or more embodiments.

[0015] Figure 5B A vertical cross-sectional view of an intermediate structure is shown in which a packaging module may be mounted on a packaging substrate in accordance with one or more embodiments.

[0016] Figure 5C A vertical cross-sectional view of an intermediate structure is shown in which a package underfill layer may be formed on a package substrate in accordance with one or more embodiments.

[0017] Figure 5D A vertical cross-sectional view of an intermediate structure is shown in which a surface mount device may be mounted on a packaging substrate in accordance with one or more embodiments.

[0018] Figure 5E A vertical cross-sectional view of an intermediate structure is shown in which a TIM layer may be attached to (eg, formed on) a packaging module in accordance with one or more embodiments.

[0019] Fig. 5F A vertical cross-sectional view of an intermediate structure is shown in which an adhesive layer may be applied to a package substrate in accordance with one or more embodiments.

[0020] Figure 5G A vertical cross-sectional view of an intermediate structure is shown in which a package lid may be attached to (eg, mounted on) a package substrate in accordance with one or more embodiments.

[0021] Figure 5H A vertical cross-sectional view of an intermediate structure is shown in which a plurality of solder balls may be formed on a package substrate in accordance with one or more embodiments.

[0022] Figure 6 is a flow chart illustrating a method of forming a package structure according to one or more embodiments.

[0023] Figure 7 is a vertical cross-sectional view of a package structure having a first alternative design according to one or more embodiments.

[0024] Figure 8 is a vertical cross-sectional view of a package structure having a second alternative design according to one or more embodiments.

[0025] Fig. 9 is a vertical cross-sectional view of a package structure having a third alternative design according to one or more embodiments.

[0026] Fig.10 is a vertical cross-sectional view of a package structure having a fourth alternative design according to one or more embodiments. DETAILED DESCRIPTION

[0027] The following disclosure provides many different embodiments or examples for implementing the different features of the provided target. Specific examples of components and arrangements are described below to simplify the embodiments of the utility model. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the embodiments of the utility model may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0028] In addition, for ease of description, spatially relative terms such as "below," "lower," "upper," and "upper" may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless otherwise expressly stated, each component having the same reference number is assumed to have the same material composition and have a thickness within the same thickness range.

[0029] The thermal interface material (TIM) layer or the pumping out problem of the thermal interface material layer may be particularly present when the TIM layer has a low melting point. In this case, when the package structure is powered on, the temperature of the package structure may rise, causing the TIM layer to melt (e.g., local phase change or local melting) and turn into a liquid at a hot spot (e.g., a silicon hot spot). Such a condition may induce a pumping out failure of the package structure, in which the molten TIM layer may be pumped out from the space between the package cover and the package module.

[0030] Pumping out can lead to increased thermal resistance (e.g., interface resistance) and temperature rise, which can affect the reliability and performance of the package structure. To alleviate the problem, various techniques can be used, including using more stable and flexible materials in the TIM layer, optimizing the thickness and composition of the TIM layer, and applying mechanical force to hold the TIM layer in place.

[0031] One or more embodiments of the utility model may include a packaging structure (e.g., a high-performance packaging structure) and a packaging cover. The packaging structure may include a packaging substrate and a packaging module located on the packaging substrate. The packaging structure may also include, for example, a flip chip-chip scale package (FC-CSP) design, a three-dimensional integrated packaging design (e.g., a fan-out design), etc. A thermal interface material (TIM) layer may be located (e.g., integrated) between the packaging module (e.g., a silicon die) and the packaging cover to improve heat dissipation. The TIM layer may include, for example, a grease-type TIM layer, a gel-type TIM layer, a graphite film TIM layer, a liquid metal TIM layer (e.g., a gallium-rich TIM layer), a PCM-type TIM layer, etc. The PCM-type TIM layer may include, for example, a polymer-based PCM TIM layer or a low melting temperature metal TIM layer. Compared with other materials of the TIM layer, the PCM-type TIM layer can improve gap and delamination problems, enhance thermal contact resistance, and improve thermal performance in the packaging structure. In at least one embodiment, the PCM-type TIM layer may change its phase from solid to high viscosity semi-liquid at around 60°C.

[0032] A package cover (e.g., a heat sink) may be attached to the package substrate on the package module. The package cover may be made of ceramic, polymer, or metal (e.g., copper, nickel, etc.). The package cover may help suppress warping of the package structure (e.g., minimize warping of the package structure).

[0033] The package cover may include a patterned bottom surface. In at least one embodiment, the patterned bottom surface may include a honeycomb design. In at least one embodiment, the patterned bottom surface may include a plurality of recessed portions. In at least one embodiment, the shape of the recessed portion may include a hexagon, a square, an octagon, a circle, an ellipse, a capsule, a ladder, etc. The patterned bottom surface may contact the TIM layer on the package module in the package structure. The area of ​​the patterned bottom surface (e.g., the honeycomb area) may substantially correspond to (e.g., substantially align with) the area of ​​the package module (e.g., the chip on wafer (CoW) area, the integrated fan-out (InFO) die area, etc.). The depth of the recessed portion of the patterned bottom surface (e.g., the honeycomb depth) may be in the range of about 0.2 times to 0.8 times (e.g., about 0.5 times) the thickness of the TIM layer (e.g., the incoming thickness of the TIM layer).

[0034] A patterned bottom surface (e.g., a honeycomb design) of the package cover can help suppress pumping out of the TIM layer. In at least one embodiment, the package structure may include a PCM-type TIM layer that provides good heat dissipation performance, and the patterned bottom surface can help suppress pumping out of silicon grains in the package module of the package structure at hot spots. The patterned bottom surface can also increase the contact area between the package cover and the TIM layer and enhance the interfacial thermal conductivity. The patterned bottom surface can also provide additional spacing between the package cover and the package module, which can help suppress the TIM layer from seeping out of the space. In at least one embodiment, the package structure may include one or more surface mount devices (SMDs) adjacent to the package module on the package substrate. In the case, the patterned bottom surface can help suppress the TIM layer from seeping out and from touching the SMD, which can cause electrical failures in the package structure.

[0035] Therefore, a package structure having a package cap with a patterned bottom surface (e.g., a honeycomb design) may have several advantages and benefits. Specifically, the package structure may help inhibit pumping out of the TIM layer, thereby reducing the risk of pumping out. The patterned bottom surface of the package cap may also increase the contact surface area between the package cap and the TIM layer, thereby helping to provide good heat dissipation. The patterned bottom surface of the package cap may also provide additional spacing to prevent pumping out / seepage of the TIM layer.

[0036] Figure 1A is a vertical cross-sectional view of a package structure 100 according to one or more embodiments. Figure 1B is a plan view (eg, top view) of a package structure 100 according to one or more embodiments. Figure 1A The vertical section view is along Figure 1B The line A-A' is intercepted. Figure 1C is a detailed vertical cross-sectional view of the TIM layer 170 in the package structure 100 according to one or more embodiments.

[0037] like Figure 1A As shown, the package structure 100 may include a package substrate 110, a package module 120 located on the package substrate 110, and a package cover 130 located on the package module 120. The package cover 130 may include a package cover plate portion 130p, and the package cover plate portion 130p has a lower side 135 with a patterned bottom surface 131. The patterned bottom surface 131 may help reduce the risk of TIM layer pumping out in the package structure 100.

[0038] The package substrate 110 may include a substrate with a core or without a core. In at least one embodiment, for example, the package substrate 110 may include a core 112, a package substrate upper dielectric layer 114 formed on the core 112 (e.g., a first side or die side of the package substrate 110), and a package substrate lower dielectric layer 116 formed on the core 112 (e.g., a second side or board side of the package substrate 110). Specifically, the package substrate 110 may include a build-up film substrate, such as an Ajinomoto build-up film (ABF) substrate. That is, in at least one embodiment, each of the package substrate upper dielectric layer 114 and the package substrate lower dielectric layer 116 may be described as an ABF layer.

[0039] The core 112 may help provide rigidity to the package substrate 110. The core 112 may include, for example, an epoxy resin, such as a bismaleimide triazine epoxy resin (BT) epoxy resin and / or a woven glass laminate. The core 112 may alternatively or additionally include an organic material, such as a polymer material. Specifically, the core 112 may include a dielectric polymer material, such as a polyimide (PI), a benzocyclo-butene (BCB) polymer, or a polybenzobisoxazole (PBO). Other suitable dielectric materials are also within the contemplated scope of the embodiments of the present invention.

[0040] The core 112 may include one or more through-holes 112a. The through-holes 112a may extend from the lower surface of the core 112 to the upper surface of the core 112. The through-holes 112a may enable electrical connection between the upper dielectric layer 114 of the package substrate and the lower dielectric layer 116 of the package substrate. The through-holes 112a may include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the embodiments of the present invention.

[0041] The upper dielectric layer 114 of the package substrate may be formed on the upper surface of the core 112. The upper dielectric layer 114 of the package substrate may include a plurality of layers, and in particular, may include a laminate film (e.g., ABF). The upper dielectric layer 114 of the package substrate may also include an organic material, such as a polymer material. In particular, the upper dielectric layer 114 of the package substrate may include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are also within the scope of the embodiments of the present invention.

[0042] The upper dielectric layer 114 of the package substrate may include one or more upper bonding pads 114a of the package substrate located on the die side surface of the upper dielectric layer 114 of the package substrate. The upper bonding pads 114a of the package substrate may be exposed on the die side surface of the upper dielectric layer 114 of the package substrate. The upper dielectric layer 114 of the package substrate may also include one or more metal interconnect structures 114b. The metal interconnect structure 114b may be connected to the upper bonding pads 114a of the package substrate and the through-holes 112a in the core 112. The metal interconnect structure 114b may include a metal layer (e.g., a copper trace) and a metal via connecting the metal layer. The upper bonding pads 114a of the package substrate and the metal interconnect structure 114b may include, for example, one or more layers, and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the embodiments of the present invention.

[0043] The package substrate upper passivation layer 110a may be formed on the die-side surface of the package substrate upper dielectric layer 114. The package substrate upper passivation layer 110a may partially cover the package substrate upper bonding pad 114a. The upper passivation layer 110a may include silicon oxide, silicon nitride, a low dielectric constant dielectric material (e.g., carbon-doped oxide), an extremely low dielectric constant dielectric material (e.g., porous carbon-doped silicon dioxide), a combination thereof, or other suitable materials.

[0044] The package substrate lower dielectric layer 116 may be formed on the lower surface of the core 112. The package substrate lower dielectric layer 116 may also include multiple layers, and specifically, may include a laminate film (e.g., ABF). The package substrate lower dielectric layer 116 may also include an organic material, such as a polymer material. Specifically, the package substrate lower dielectric layer 116 may include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are also within the scope of the embodiments of the present invention.

[0045] The lower dielectric layer 116 of the package substrate may include one or more lower bonding pads 116a of the package substrate on the side surface of the lower dielectric layer 116 of the package substrate. Specifically, the lower bonding pads 116a of the package substrate may be exposed on the side surface of the lower dielectric layer 116 of the package substrate. The lower dielectric layer 116 of the package substrate may also include one or more metal interconnect structures 116b. The metal interconnect structure 116b may be connected to the lower bonding pads 116a of the package substrate and the through-holes 112a in the core 112. The metal interconnect structure 116b may include a metal layer (e.g., a copper trace) and a metal through-hole connecting the metal layer. The lower bonding pads 116a of the package substrate and the metal interconnect structure 116b may include, for example, one or more layers, and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the embodiments of the present invention.

[0046] The package substrate lower passivation layer 110b may be formed on the board side surface of the package substrate lower dielectric layer 116. The package substrate lower passivation layer 110b may partially cover the package substrate lower bonding pad 116a. The package substrate lower passivation layer 110b may include silicon oxide, silicon nitride, a low dielectric constant dielectric material (e.g., carbon-doped oxide), an extremely low dielectric constant dielectric material (e.g., porous carbon-doped silicon dioxide), a combination thereof, or other suitable materials.

[0047] A ball-grid array (BGA) including a plurality of solder balls 110c may be formed on the board side surface of the lower dielectric layer 116 of the package substrate. The solder balls 110c may enable the package structure 100 to be securely mounted on a substrate such as a printed circuit board (PCB) and electrically coupled to the PCB substrate. The solder balls 110c may contact the lower bonding pads 116a of the package substrate, respectively. Therefore, the solder balls 110c may be electrically connected to the upper bonding pads 114a of the package substrate through the metal interconnect structure 116b, the through-hole 112a, and the metal interconnect structure 114b.

[0048] The package module 120 may include an interposer 10 and one or more semiconductor dies 140 located on the interposer 10 (see Figure 1B ). The packaging module 120 is not limited to any particular configuration. The packaging module 120 may include, for example, a flip chip die-die level package (FC-CSP) design, a chip-on-wafer-on-substrate (CW-S) design, a ) design, integrated fan-out (InFO) design, etc. In at least one embodiment, the interposer 10 can be omitted from the package module 120. In such embodiments, the semiconductor die 140 can be directly attached to the package substrate 110.

[0049] The package module 120 may be bonded to and electrically coupled to the package substrate 110 via C4 bumps 121 located on the board side surface of the interposer 10. Specifically, the C4 bumps 121 may be formed on the lower bonding pads 14a on the board side surface of the interposer 10, respectively. The C4 bumps 121 may be bonded to the package substrate upper bonding pads 114a of the package substrate 110 using solder reflow, compression bonding, thermocompression bonding, etc. In at least one embodiment, the C4 bumps 121 may include an underbump metallurgy (UBM) layer located on the lower bonding pads 14a and the package substrate upper bonding pads 114a. The C4 bumps 121 may also include contact pads (e.g., copper / nickel contact pads) located on the UBM layer, and solder bumps (e.g., SnAg solder bumps) located on the contact pads.

[0050] like Figure 1A As shown, the packaging substrate 110 may have a length in the x-direction greater than the length of the packaging module 120 in the x-direction. The packaging substrate 110 may also have a width in the y-direction greater than the width of the packaging module 120 in the y-direction.

[0051] The package underfill layer 119 may be formed on the package substrate 110 below and around the package module 120. The package underfill layer 119 may also be formed around the C4 bump 121. The package underfill layer 119 may thus firmly fix the package module 120 to the package substrate 110. The package underfill layer 119 may be formed of an epoxy resin-based polymer material.

[0052] The interposer 10 is not necessarily limited to any particular material or configuration. The interposer 10 may include, for example, an organic material (e.g., a dielectric polymer), an inorganic material (e.g., silicon), a glass substrate, etc. In at least one embodiment, the interposer 10 may include a plurality of polymer layers 12 and a plurality of redistribution layers 12a stacked alternately. The number of polymer layers 12 and / or the number of redistribution layers 12a in the interposer 10 are not limited by the embodiments of the present invention.

[0053] In at least one embodiment, the polymer layer 12 may include, for example, polyimide (PI), epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. In some embodiments, the redistribution layer 12a may include a conductive material. The conductive material may include, for example, a metal such as copper, aluminum, nickel, titanium, a combination thereof, or other suitable metals.

[0054] The redistribution layer 12a may include a metallic connection structure, i.e., a metallic structure that provides electrical connection between nodes in the structure. The redistribution layer 12a may include a metallic seed layer and a metallic filling material located on the metallic seed layer. The metallic seed layer may include, for example, a stack of a titanium barrier layer and a copper seed layer. The titanium barrier layer may have a thickness in the range of 50 nanometers to 500 nanometers, and the copper seed layer may have a thickness in the range of 50 nanometers to 500 nanometers. The metallic filling material used for the redistribution layer 12a may include copper, nickel, or copper and nickel. Other suitable metallic filling materials are also within the scope of the envision of the present utility model embodiment. The thickness of the metallic filling material deposited for each redistribution layer 12a may be in the range of 2 microns to 40 microns, for example, 4 microns to 10 microns, but smaller or larger thicknesses may also be used.

[0055] In at least one embodiment, the redistribution layer 12a may include a plurality of traces (lines) and a plurality of vias connecting the plurality of traces to each other. The traces may be located on the polymer layer 12, respectively, and may extend in the x-direction (first horizontal direction) and the y-direction (second horizontal direction) on the upper surface of the polymer layer 12.

[0056] The upper passivation layer 13 may be formed on the die-side surface of the interposer 10. The upper passivation layer 13 may include silicon oxide, silicon nitride, a low-k dielectric material (e.g., carbon-doped oxide), an extremely low-k dielectric material (e.g., porous carbon-doped silicon dioxide), combinations thereof, or other suitable materials.

[0057] One or more upper bonding pads 13a may be formed in the upper passivation layer 13 on the die-side surface of the interposer 10. The upper passivation layer 13 may at least partially cover the upper bonding pads 13a. That is, the upper bonding pads 13a may be at least partially exposed on the die-side surface of the interposer 10. The upper bonding pads 13a may be connected to the redistribution layer 12a. The upper bonding pads 13a may include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the embodiments of the present invention.

[0058] The lower passivation layer 14 may be formed on the board side surface of the interposer 10. The lower passivation layer 14 may also include silicon oxide, silicon nitride, a low-k dielectric material (e.g., carbon-doped oxide), an extremely low-k dielectric material (e.g., porous carbon-doped silicon dioxide), a combination thereof, or other suitable materials. The lower bonding pad 14a may be bonded to and electrically connected to the redistribution layer 12a. The lower bonding pad 14a may be located in the lower passivation layer 14. The lower passivation layer 14 may at least partially cover the lower bonding pad 14a. That is, the lower bonding pad 14a may be at least partially exposed on the board side surface of the interposer 10. The lower bonding pad 14a may also include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the embodiments of the present invention.

[0059] Semiconductor grains (collectively referred to as semiconductor grains 140) may be attached to the upper surface of the interposer 10. The plurality of semiconductor grains 140 may include a first semiconductor grain 141, a second semiconductor grain 142, a third semiconductor grain 143, a fourth semiconductor grain 144, and a fifth semiconductor grain 145 (see Figure 1B ). Although the packaging module 120 is shown as including a specific number of semiconductor grains 140 having a specific arrangement and a specific size, the number of semiconductor grains 140, the size of semiconductor grains 140, and the arrangement of semiconductor grains 140 are not limited to any specific number, size, and arrangement. Specifically, the packaging module 120 may include any number, size, and arrangement of semiconductor grains 140.

[0060] Generally, the thickness of each of the semiconductor dies 140 in the z direction may be substantially the same. Therefore, the upper surfaces of each of the first semiconductor die 141 and the second semiconductor die 142 may be substantially coplanar (eg, formed in the same xy plane) and are collectively referred to as semiconductor die upper surfaces 140a.

[0061] The semiconductor die 140 may be attached to (e.g., bonded to) the upper bonding pad 13a located on the die side surface of the interposer 10 through the microbumps 128. The microbumps 128 may each include a copper pillar and a solder bump located on the copper pillar. A package module bottom fill layer 129 may be formed (e.g., individually or collectively) under and around each of the semiconductor die 140. The package module bottom fill layer 129 may also be formed around the microbumps 128. The package module bottom fill layer 129 may thereby fix each of the semiconductor die 140 to the interposer 10. The package module bottom fill layer 129 may be formed of an epoxy resin-based polymer material. As described above, in some embodiments in which the interposer 10 is omitted, the semiconductor die 140 may be directly attached to the package substrate 110 through, for example, the C4 bumps 121.

[0062] Each of the semiconductor dies 140 may include, for example, a single semiconductor die structure, a system on chip (SOC) die, or a system on integrated chip (SoIC) die, and may be implemented by a three-dimensional integrated packaging technology (eg, fan-out technology). Specifically, each of the semiconductor dies 140 may include, for example, semiconductor dies or dielets for high performance computing (HPC) applications, artificial intelligence (AI) applications, and fifth generation (5G) cellular network applications, logic dies (e.g., mobile application processors, microcontrollers, etc.), or memory dies (e.g., high-bandwidth memory (HBM) dies, hybrid memory cubes (HMC), dynamic random access memory (DRAM) dies, wide input / output (I / O) dies, magnetic random access memory (M-RAM) dies, resistance random access memory (R-RAM) dies, NAND dies, static random access memory (SRAM), etc.), central processing unit (CPU) dies, graphics processing units (GPUs), etc. unit, GPU) die, field-programmable gate array (FPGA) die, networking die, application-specific integrated circuit (ASIC) die, artificial intelligence / deep neural network (AI / DNN) accelerator die, etc., co-processors, accelerators, on-die memory buffers, high data rate transceiver die, I / O interface die, IPD die, power management die (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) die, etc.RF) die, sensor die, micro-electro-mechanical-system (MEMS) die, signal processing die (e.g., digital signal processing (DSP) die), front-end die (e.g., analog front-end (AFE) die), monolithic three-dimensional (3D) heterogeneous small die stack die, etc. Other die are also within the scope of the embodiments of the present invention. In at least one embodiment, the first semiconductor die 141 may include a main die (e.g., a SOC die), and the second semiconductor die 142, the third semiconductor die 143, the fourth semiconductor die 144, and the fifth semiconductor die 145 may include auxiliary die (e.g., storage / SOC die, HBM die, etc.). ,

[0063] The packaging module 120 may also include an upper molding layer 127 formed around the semiconductor die 140. The upper molding layer 127 may have an outer sidewall substantially aligned with the outer sidewall of the interposer 10. The upper molding layer 127 may also have an upper surface that is substantially uniform (e.g., flat) and substantially coplanar with the upper surface 140a of the semiconductor die 140. The upper molding layer 127 may be formed on the outer sidewall of each of the semiconductor die 140. The upper molding layer 127 may be bonded to the outer sidewall of each of the semiconductor die 140.

[0064] The upper molding layer 127 may also be formed on and around the package module bottom filling layer 129. Figure 1A 1, but the height of the upper surface of the package module bottom fill layer 129 may be less than the height of the semiconductor die 140. In this case, the upper mold layer 127 may also be formed in the die-to-die gap between the semiconductor die 140 and bonded to the inner sidewalls of the semiconductor die 140. The upper mold layer 127 may also be formed on the package module bottom fill layer 129 in the die-to-die gap. The upper mold layer 127 may be bonded to the die side surface (e.g., the upper passivation layer 13) of the interposer 10 and the package module bottom fill layer 129.

[0065] In at least one embodiment, the upper molding layer 127 may be formed of a curable material that can be cured to form a hard solid structure. The upper molding layer 127 may include, for example, an epoxy molding compound (EMC). In at least one embodiment, the upper molding layer 127 may include a material substantially similar to the package bottom fill layer 119 and the package module bottom fill layer 129. In at least one embodiment, the upper molding layer 127 may include a polymeric material, and in particular, an epoxy-based polymeric material. Other suitable molding materials may also be used.

[0066] In at least one embodiment, the upper molding layer 127 may have a coefficient of thermal expansion (CTE) substantially similar to that of the interposer 10. In at least one embodiment, the upper molding layer 127 may include an added material (e.g., a filler material added to a polymer material) for improving the properties (e.g., thermal conductivity, CTE, etc.) of the upper molding layer 127. The added material may include, for example, metal powder, metal oxide powder, etc. Other materials in the upper molding layer 127 are also within the contemplated scope of the embodiments of the present invention.

[0067] The package structure 100 may further include a thermal interface material (TIM) layer 170 located on the package module 120. The TIM layer 170 may be located on the upper surface of the upper molding layer 127 and on the upper surface 140a of the semiconductor die 140. Figure 1A Although not shown, the TIM layer 170 may be formed on the upper surface of the package module underfill layer 129 in the die-to-die gaps between the semiconductor dies 140 .

[0068] The TIM layer 170 may include, for example, a grease-type TIM, a paste-type TIM, a film-type TIM, a gel-type TIM, a graphite film TIM, a liquid metal TIM (e.g., a gallium-rich TIM), a PCM-type TIM, etc. In at least one embodiment, the TIM layer 170 may include a low-melting-temperature (LMT) metal TIM. The PCM-type TIM may include, for example, a polymer-based PCM TIM. The PCM-type TIM may improve void and delamination problems, enhance contact thermal resistance, and improve thermal performance in the package structure 100. In at least one embodiment, the PCM-type TIM may change its phase from a solid to a high-viscosity semi-liquid at around 60°C. In at least one embodiment, the TIM layer 170 may include a gallium base, an indium base, a silver base, a solder base, etc. Other types of TIMs in the TIM layer 170 are also within the scope of the embodiments of the present invention.

[0069] The TIM layer 170 may be formed on the package module 120 to dissipate heat generated during the operation of the package structure 100 (e.g., the operation of the semiconductor die 140). The TIM layer 170 may be attached to the package module 120, for example, by a thermally conductive adhesive. The TIM layer 170 may have a low bulk thermal impedance and a high thermal conductivity. The bond-line-thickness (BLT) (e.g., the distance between the package lid 130 and the package module 120) may be less than about 100 microns, but larger or smaller distances may also be used.

[0070] The package cover 130 may be located on the package module 120 and connected to the package substrate 110. The package cover 130 may include a package cover plate portion 130p formed on the TIM layer 170 on the package module 120. The package cover 130 may also include a package cover foot portion 130a located around the outer periphery of the package cover plate portion 130p. The package cover foot portion 130a may be fixed to the package substrate 110 by an adhesive layer 160.

[0071] The package cover portion 130p may include an outer package cover portion 130p-1 connected to the package cover foot portion 130a. The package cover portion 130p may also include an inner package cover portion 130p-2 located on the package module 120. The package cover portion 130p may also include a lower side 135, which includes a patterned bottom surface 131. The patterned bottom surface 131 may be located in the inner package cover portion 130p-2, but is not necessarily limited to the inner package cover portion 130p-2. The patterned bottom surface 131 may contact the upper surface of the TIM layer 170. The patterned bottom surface 131 may include a recessed portion 131a, and the TIM layer 170 may be formed in or filled in the recessed portion 131a of the patterned bottom surface 131. In at least one embodiment, a portion of the TIM layer 170 (e.g., at least a portion of the TIM layer 170) may be located in the recessed portion 131a. In at least one embodiment, the TIM layer 170 may substantially fill the recessed portion 131 a of the patterned bottom surface 131 .

[0072] In one or more embodiments, the lower side 135 including the patterned bottom surface 131 of the package cover portion 130p may directly contact the entire upper surface of the TIM layer 170. The TIM layer 170 may be compressed between the lower side 135 of the package cover portion 130p and the package module 120. Specifically, the TIM layer 170 may be compressed between the patterned bottom surface 131 and the upper surface of the upper molding layer 127, and between the patterned bottom surface 131 and the upper surface 140a of the semiconductor die 140.

[0073] The package cover 130 may be formed of, for example, a metal, ceramic, or polymer material. In at least one embodiment, the material of the package cover 130 may include copper having a nickel coating surface. The nickel coating surface may have a thickness in the range of 1 micrometer to 10 micrometers. The package cover plate portion 130p may have a plate shape (e.g., a planar shape) and be substantially parallel to the upper surface of the package substrate 110. The package cover plate portion 130p may be, for example, Figure 1A The package cover portion 130p may include an outer sidewall substantially aligned with the outer sidewall of the package cover foot portion 130a. The center of the inner package cover portion 130p-2 in the xy plane may be substantially aligned with the center of the package module 120 in the xy plane in the z direction. The upper surface of the package cover portion 130p may be substantially parallel to the lower side 135 of the package cover portion 130p.

[0074] The adhesive layer 160 may be formed on the package substrate 110 near the sidewall of the package module 120. The adhesive layer 160 may bond the package cover foot portion 130a to the package substrate 110. The thickness of the adhesive layer 160 may be in the range of 50 microns to 200 microns. The adhesive layer 160 may include, for example, a silicone adhesive (e.g., containing aluminum oxide, zinc oxide, resin, etc.) or an epoxy resin adhesive. Other suitable adhesives may also be used. The adhesive layer 160 may contact the backside metal layer, or the recessed upper surface of the upper molding material layer.

[0075] One or more surface mount devices (SMDs) 180 may also be located below the package cap 130 on the die side surface of the package substrate 110. The SMDs 180 may be located between the package cap foot portion 130a and the package module 120 on the package substrate 110. In at least one embodiment, the SMDs 180 may be located substantially equidistantly between the package cap foot portion 130a and the interposer 10 of the package module 120 (e.g., in the x-direction). The SMDs 180 may be attached to the package substrate 110 by surface mount technology (SMT) and electrically connected to the metal interconnect structure 114b in the upper dielectric layer 114 of the package substrate. Therefore, the SMDs 180 may be electrically coupled to the semiconductor die 140 through the package substrate 110 and the interposer 10.

[0076] SMD 180 may include, for example, integrated circuits, passive components (e.g., resistors, capacitors, and inductors), active components (e.g., two-terminal devices, diodes, and three-terminal devices), and electromechanical devices (e.g., switches / relays, connectors, and micromotors). In at least one embodiment, SMD 180 may include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs)), rectifiers, and voltage regulators for power management applications.

[0077] Refer again Figure 1B For ease of understanding, Figure 1B The package cover portion 130p is omitted. Figure 1B As shown, the packaging substrate 110 may have a rectangular shape in a plan view. The center of the packaging module 120 in the x-direction and the y-direction may be substantially aligned with the center of the packaging substrate 110 in the x-direction and the y-direction. The packaging substrate 110 may include a long side substantially parallel to the long side of the packaging module 120, and a short side substantially parallel to the short side of the packaging module 120.

[0078] The package foot portion 130a may also include a long side substantially parallel to the long side of the package module 120, and a short side substantially parallel to the short side of the package module 120. The package foot portion 130a may be continuously attached to the package substrate 110 around the entire periphery of the package module 120. The distance D0 between the package foot portion 130a and the outer periphery (e.g., outer edge) of the package substrate 110 may be substantially uniform around the periphery of the package foot portion 130a. In at least one embodiment, the distance D1 between the upper molding layer 127 of the package module 120 and the package foot portion 130a may be substantially uniform around the entire periphery of the package module 120. In at least one embodiment, the distance D2 between the SMD 180 and the package module 120 may be substantially the same as the distance D3 between the SMD 180 and the package foot portion 130a.

[0079] Refer again Figure 1C, the interface between the outer package cover plate portion 130p-1 and the inner package cover plate portion 130p-2 may be substantially aligned with the outer sidewall 127a of the upper mold layer 127 of the package module 120. The plurality of recessed portions 131a may include an outermost recessed portion 131ao located on the package module 120. The distance D4 between the outer sidewall 127a of the upper mold layer 127 and the outermost recessed portion 131ao of the patterned bottom surface 131 may be in the range of 0.5 mm to 1.0 mm. In at least one embodiment, the lower side 135 may have a substantially uniform (e.g., flat) bottom surface in the outer package cover plate portion 130p-1. The thickness T130p of the package cover plate portion 130p outside the recessed portion 131a may be in the range of 0.5 mm to 3.0 mm.

[0080] The TIM layer 170 may have a first thickness T1 (in the z direction) within the plurality of recessed portions 131a. The first thickness T1 may be in a range of 100 micrometers to 1000 micrometers. The TIM layer 170 may also include a second thickness T2 outside the plurality of recessed portions 131a that is less than the first thickness T1. The second thickness T2 may be in a range of 50 micrometers to 500 micrometers.

[0081] The recessed portion 131a may have a depth D5 (in the z direction) in the range of 50 micrometers to 500 micrometers. The sidewall of the recessed portion 131a may extend in the z direction substantially perpendicular to the upper surface of the package cover portion 130p. The ratio of the depth D5 of the recessed portion 131a to the first thickness T1 of the TIM layer 170 may be in the range of 0.2 to 0.8. The width W of the recessed portion 131a may be in the range of 100 micrometers to 1000 micrometers. Figure 1C As shown, the plurality of recessed portions 131a may be substantially filled with the TIM layer 170. However, in at least one embodiment, one or more of the recessed portions 131a may not be substantially filled with the TIM layer 170 (e.g., only partially filled with the TIM layer 170). In at least one embodiment, one or more recessed portions 131a (e.g., each of the recessed portions 131a) may be filled with 85% to 95% by the TIM layer 170.

[0082] The depth D5, width W, and number of the recessed portions 131a in the patterned bottom surface 131 of the package cover portion 130p may depend on the type of TIM layer 170 used. For example, for a TIM layer 170 having a higher CTE, the patterned bottom surface 131 may include a higher number of recessed portions 131a having a larger depth D5 and a larger width W, while for a TIM layer 170 having a lower CTE, the patterned bottom surface 131 may include a lower number of recessed portions 131a having a smaller depth D5 and a smaller width W. As another example, for a TIM layer 170 having a lower thermal conductivity, the patterned bottom surface 131 may include a higher number of recessed portions 131a having a larger depth D5 and a larger width W, while for a TIM layer 170 having a higher thermal conductivity, the patterned bottom surface 131 may include a lower number of recessed portions 131a having a smaller depth D5 and a smaller width W.

[0083] Figure 2A 1 is a plan view (eg, top view) of the underside 135 of the package cover portion 130p according to one or more embodiments. Figure 2A As shown, the outer perimeter of the patterned bottom surface 131 may substantially correspond to the outer perimeter of the inner package cover portion 130p-2. The patterned bottom surface 131 may have an outer shape substantially corresponding to the outer shape of the package cover 130 and the outer shape of the package cover portion 130p. The outer shape of the patterned bottom surface 131 may include a rectangular shape, a square shape, etc. The center of the patterned bottom surface 131 may be substantially aligned with the center of the package cover portion 130p.

[0084] The recessed portions 131a may be uniformly arranged in the patterned bottom surface 131. The concentration of the recessed portions 131a may be substantially uniform across the patterned bottom surface 131. The recessed portions 131a may be formed in a plurality of columns 132 forming an array of the recessed portions 131a. The plurality of columns 132 may each extend longitudinally in the y-direction. In at least one embodiment, the array may include a staggered array, and the columns 132 may include a first column 132a, and a second column 132b staggered with the first column 132a in the y-direction (e.g., offset from the first column 132a). The first column 132a and the second column 132b may be alternately formed in the x-direction on the patterned bottom surface 131.

[0085] The outer shape of each of the recessed portions 131a may include, for example, one or more of a hexagonal shape, a circular shape, an elliptical shape, a capsule shape, a ladder shape, a square shape, a rectangular shape, a triangle shape, a trapezoidal shape, and a diamond shape. Other suitable shapes may also be used. Although Figure 2AThe recessed portions 131a having the same shape (e.g., hexagonal) are shown, but the recessed portions 131a may also have different shapes. In at least one embodiment, the shape of the recessed portion 131a may be determined based on the expected thermal performance of the packaging module 120. For example, the recessed portion 131a located in a position of the patterned bottom surface 131 corresponding to the hot spot of the packaging module 120 may have a first shape (e.g., a hexagonal shape), while the recessed portion 131a located in a position of the patterned bottom surface 131 that does not correspond to the hot spot of the packaging module 120 may have a second shape (e.g., a circular shape).

[0086] In at least one embodiment, the patterned bottom surface 131 may have a honeycomb design. A surface having a honeycomb design is typically composed of a regular pattern of recessed portions 131a (e.g., a honeycomb). The recessed portions 131a may have a hexagonal shape, but other suitable shapes may also be used. The walls between the recessed portions 131a may be substantially uniform. The honeycomb design may be highly symmetrical and highly regular, with a substantially constant distance between the walls of adjacent recessed portions. The honeycomb design may also have a large surface area-to-volume ratio, which may enable efficient heat transfer and fluid flow (e.g., flow of the TIM layer 170) into the recessed portions 131a.

[0087] Figure 2B Detailed plan view (e.g., top view) of patterned bottom surface 131 according to one or more embodiments. Recessed portion 131a may have substantially the same width W in both the x-direction and the y-direction. In at least one embodiment, recessed portion 131a may have a width W in the x-direction that is different from that in the y-direction (or have an off-axis width when measured point-to-point, for example, in an embodiment where the recessed portion is hexagonal in shape, the width may not always be parallel to the x-direction and the y-direction). The width W of recessed portion 131a in both the x-direction and the y-direction may be in the range of 100 microns to 1000 microns (e.g., about 300 microns).

[0088] In addition, the recessed portions 131a in the columns 132a, 132b of the plurality of columns 132 may be separated in the y direction by a distance D6 (e.g., a column spacing distance) ranging from 100 micrometers to 1000 micrometers (e.g., about 260 micrometers). The columns 132a, 132b of the plurality of columns 132 may be separated in the x direction by a distance D7 (e.g., a column spacing distance) ranging from 100 micrometers to 1000 micrometers (e.g., about 300 micrometers).

[0089] In at least one embodiment, the width W in the y direction may be substantially the same as the distance D7 between the columns 132a and 132b. In at least one embodiment, the distance D6 between the recessed portions 131a in the columns 132 may be less than the width W in the y direction. In at least one embodiment, the distance D6 between the recessed portions 131a in the columns 132 may be less than the distance D7 between the columns 132a and 132b. In at least one embodiment, the distance D6 between the recessed portions 131a in the columns 132a may be different from the distance D6 between the recessed portions 131a in the columns 132b.

[0090] The patterned bottom surface 131 of the package cover portion 130p can suppress pumping of the TIM layer 170. The TIM layer 170 (e.g., a PCM-type TIM layer) can provide good heat dissipation performance, and the patterned bottom surface 131 can help suppress pumping of one or more semiconductor dies 140 in the package module 120 of the package structure 100 at hot spots. The patterned bottom surface 131 can increase the contact area between the package cover portion 130p and the TIM layer 170 and enhance the interfacial thermal conductivity. The patterned bottom surface 131 can also provide additional space between the package cover portion 130p and the package module 120, which can help suppress the TIM layer 170 from seeping out of the space. In addition, in the case where the package structure 100 includes an SMD 180 adjacent to the package module 120 on the package substrate 110, the patterned bottom surface 131 can help suppress the TIM layer 170 from pumping out (sometimes referred to as seeping out) and suppressing its contact with the SMD 180. Such pumping out may cause electrical failure in the package structure 100. Therefore, the patterned bottom surface 131 can reduce the risk of pumping out that may cause increased thermal resistance and temperature rise, improve heat dissipation by increasing the contact area of ​​the package lid portion 130p, and provide additional space to prevent the seepage of the TIM layer 170.

[0091] Figure 3 A stamping process is shown for forming the patterned bottom surface 131 of the package cap 130 in accordance with one or more embodiments. FIG. 4A to FIG. 4I Various raised pads 302 are shown that may be used in a stamping process in accordance with one or more embodiments.

[0092] After forming the package cover 130 , for example, by grinding using a computer numerical control (CNC) grinder, or by molding or stamping, a patterned bottom surface 131 may be formed on the lower side 135 of the package cover plate portion 130 p . Figure 3The patterned bottom surface 131 is shown to be formed by a stamping process. However, the patterned bottom surface 131 may be formed by other suitable methods such as an etching process. In the etching process, for example, a patterned photoresist mask may be formed on the lower side 135 of the package cover plate portion 130p. The photoresist mask may include a recessed portion 131a (see FIG. 1 ) having a position and shape similar to that of the patterned bottom surface 131. Figure 2A ) is formed in a position and shape corresponding to the opening. Then, an etching process can be performed through the opening in the photoresist mask to form a recessed portion 131a of the patterned bottom surface 131.

[0093] like Figure 3 As shown, a stamp 300 used in a stamping process may include a protruding pad 302 formed on the bottom of the stamp 300. The protruding pad 302 may include a plurality of protrusions 302a (see FIG. 4A to FIG. 4I ), the plurality of protrusions 302a can transfer the pattern to the lower side 135 of the package cover plate portion 130p. In the stamping process, the package cover 130 can be inverted and placed on a rigid structure with a flat surface (e.g., a tabletop). Then, the punch 300 can be positioned on the lower side 135 of the package cover plate portion 130p, and the punch 300 can be lowered into the package cover 130 so that the protrusion pads 302 are in contact with the lower side 135 of the package cover plate portion 130p. Then, the punch 300 can be forced to move downward using a pressing force so that the protrusions 302a are pressed into the lower side 135 of the package cover plate portion 130p. The pressing force can be applied with sufficient magnitude and duration so that the shape of the protrusions 302a in the protrusion pads 302 is imprinted into the surface of the lower side 135, and thereby forming the patterned bottom surface 131. The depth of the recessed portion 131 a may be proportional to the magnitude and duration of the applied pressing force.

[0094] like FIG. 4A to FIG. 4I As shown, the protrusion pad 302 may include a hexagonal protrusion 302a ( Figure 4A ), a rounded rectangular protrusion 302a ( Figure 4B ), the trapezoidal protrusion 302a ( Figure 4C ), octagonal protrusion 302a ( Figure 4D ), the oval-shaped protrusion 302a ( Figure 4E ), triangular protrusion 302a ( Figure 4F ), square-shaped protrusion 302a ( Figure 4G ), rectangular protrusion 302a ( Figure 4H ) and rhombus-shaped protrusions 302a ( Fig. 4I). Other shapes of the protrusion 302a are also within the contemplated scope of the embodiments of the present invention. In some embodiments, the shape of the protrusion (and the resulting recessed portion 131a) may be substantially uniform. In some embodiments, the shape of the protrusion (and the resulting recessed portion 131a) may vary. In at least one embodiment, the protrusion pad 302 may be removably secured to the bottom of the punch 300 so that the protrusion pad 302 can be easily replaced with a protrusion pad 302 having a different design.

[0095] FIG. 5A to FIG. 5H Various intermediate structures are shown in a method of forming package structure 100 according to one or more embodiments. Figure 5A 1 is a vertical cross-sectional view of an intermediate structure including a package substrate 110 having a package substrate upper bonding pad 114a and a package substrate lower bonding pad 116a according to one or more embodiments. A package substrate 110 including a core 112, a package substrate upper dielectric layer 114, and a package substrate lower dielectric layer 116 may be provided.

[0096] The upper bonding pad 114a of the package substrate may be formed, for example, on the uppermost dielectric layer of the upper dielectric layer 114 of the package substrate. The upper bonding pad 114a of the package substrate may be formed to contact the metal interconnect structure 114b. The upper bonding pad 114a of the package substrate may be formed by depositing a metal layer (e.g., copper, aluminum, or other suitable conductive materials) on the upper surface of the upper dielectric layer 114 of the package substrate. The metal layer may then be patterned by etching (e.g., by wet etching, dry etching, etc.) to form the upper bonding pad 114a of the package substrate. Other suitable metal layer materials and etching processes may also be within the scope of the envision of the embodiments of the present utility model.

[0097] The package substrate lower bonding pad 116a may be formed, for example, on the lowermost dielectric layer of the package substrate lower dielectric layer 116. The package substrate lower bonding pad 116a may be formed to contact the metal interconnect structure 116b. The package substrate lower bonding pad 116a may be formed in a manner similar to the manner in which the package substrate upper bonding pad 114a is formed (e.g., depositing a metal layer, patterning the metal layer by etching, etc.).

[0098] After formation, the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a may be subjected to a surface roughening treatment (e.g., CZ (copper zarazara) treatment) as appropriate. In the surface roughening treatment, the surface (e.g., copper surface) of the package substrate upper bonding pad 114a and the surface (e.g., copper surface) of the package substrate lower bonding pad 116a may be etched by an organic acid-based micro-etching solution to generate an ultra-roughened surface (e.g., copper surface). The unique roughened copper surface morphology of the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a may help achieve high copper-resin adhesion.

[0099] Then, the package substrate upper passivation layer 110a and the package substrate lower passivation layer 110b may be formed on the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a, respectively. In at least one embodiment, the package substrate upper passivation layer 110a may include a solder resist layer (e.g., a polymer material) also referred to as a solder mask. The package substrate upper passivation layer 110a may also be referred to as an upper solder resist layer, and the package substrate lower passivation layer 110b may also be referred to as a lower solder resist layer.

[0100] The upper passivation layer 110a of the package substrate and the lower passivation layer 110b of the package substrate can be applied simultaneously. The upper passivation layer 110a of the package substrate and the lower passivation layer 110b of the package substrate can be applied, for example, as a liquid photo-imageable film. The liquid photo-imageable film can be applied, for example, by silk-screening or by spraying the liquid photo-imageable film onto the surface of the package substrate 110. The liquid photo-imageable film can be applied to the upper bonding pad 114a of the package substrate and the lower bonding pad 116a of the package substrate. The upper passivation layer 110a of the package substrate and the lower passivation layer 110b of the package substrate can be applied as a dry film photo-imageable film as an alternative, and the dry film photo-imageable film can be vacuum laminated onto the surface of the package substrate 110, and the upper bonding pad 114a of the package substrate and the lower bonding pad 116a of the package substrate, respectively. The package substrate upper passivation layer 110 a and the package substrate lower passivation layer 110 b may alternatively or additionally be formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, lamination, or other suitable deposition techniques.

[0101] The package substrate upper passivation layer 110a and the package substrate lower passivation layer 110b may be applied to have a thickness slightly greater than the thickness of the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a, respectively. Alternatively, the package substrate upper passivation layer 110a and the package substrate lower passivation layer 110b may be applied to have upper surfaces substantially coplanar with upper surfaces of the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a, respectively.

[0102] Then, an opening O110a may be formed in the upper passivation layer 110a of the package substrate to expose the upper surface of the upper bonding pad 114a of the package substrate. An opening O110b may be formed in the lower passivation layer 110b of the package substrate to expose the upper surface of the lower bonding pad 116a of the package substrate. The opening O110a and the opening O110b may be formed, for example, using a photolithography process. In at least one embodiment, the opening O110a and the opening O110b may be formed in separate photolithography processes.

[0103] The photolithography process (e.g., multiple processes) for forming the opening O110a may include: forming a patterned photoresist mask (not shown) on the upper passivation layer 110a of the package substrate, and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the upper passivation layer 110a of the package substrate through the opening in the photoresist mask. The photoresist mask may then be removed by ashing, dissolving, or consuming the photoresist mask during the etching process.

[0104] The photolithography process (e.g., multiple processes) for forming the opening O110b may include: forming a patterned photoresist mask (not shown) on the package substrate lower passivation layer 110b, and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the package substrate lower passivation layer 110b through the opening in the photoresist mask. The photoresist mask may then be removed by ashing, dissolving, or consuming the photoresist mask during the etching process.

[0105] After forming an opening O110a in the upper passivation layer 110a of the packaging substrate and forming an opening O110b in the lower passivation layer 110b of the packaging substrate, the upper passivation layer 110a (upper solder resist layer) of the packaging substrate and the lower passivation layer 110b (lower solder resist layer) of the packaging substrate can be cured, for example, by thermal curing or ultraviolet (UV) curing.

[0106] Figure 5BA vertical cross-sectional view of an intermediate structure according to one or more embodiments is shown, wherein a package module 120 may be mounted on a package substrate 110. The package module 120 may be mounted on the package substrate 110, for example, by a flip chip bonding (FCB) process. The semiconductor die module (C4 bump 121) may be positioned on the package substrate 110, for example, by an electromechanical pick-and-place (PNP) machine. The C4 bump 121 on the semiconductor die module (C4 bump 121) may then be lowered onto the package substrate upper bonding pad 114a of the package substrate 110 and heated so as to collapse the C4 bump 121 and bond the C4 bump 121 to the package substrate upper bonding pad 114a.

[0107] Figure 5C FIG. 1 shows a vertical cross-sectional view of an intermediate structure according to one or more embodiments, wherein a package underfill layer 119 may be formed on a package substrate 110. The package underfill layer 119 may be formed of an epoxy resin-based polymer material. Figure 5C As shown, a package underfill layer 119 may be formed (e.g., injected) to the package substrate 110 under and around the package module 120 and the C4 bumps 121. The package underfill layer 119 may then be cured, for example, in a box oven at a temperature in a range of 120° C. to 180° C. for a duration in a range of 60 minutes to 120 minutes to provide the package underfill layer 119 with sufficient rigidity and mechanical strength.

[0108] Figure 5D A vertical cross-sectional view of an intermediate structure according to one or more embodiments is shown, wherein an SMD 180 may be mounted on a package substrate 110. The SMD 180 may then be positioned on the package substrate 110, for example, by a electromechanical pick-and-place (PNP) machine. The SMD 180 (e.g., under the control of a PNP machine) may then be lowered onto the package substrate 110 and attached to the package substrate 110 by an adhesive (not shown). The adhesive may be substantially similar to the adhesive layer 160. The SMD 180 may include bonding pads (not shown) that may be bonded to the package substrate upper bonding pads 114a of the package substrate 110.

[0109] Figure 5EA vertical cross-sectional view of an intermediate structure according to one or more embodiments is shown, wherein a TIM layer 170 may be attached to (e.g., formed on) a packaging module 120. Depending on the type of TIM layer 170 used, a thermally conductive adhesive may or may not be applied to the upper surface of the packaging module 120. The material of the TIM layer 170 may be in the form of a grease, gel, paste, etc., in which case the material may be dispensed onto the thermally conductive adhesive (if present) or dispensed onto the upper surface of the packaging module. If the TIM layer 170 is solid, the TIM layer 170 may be pressed onto the packaging module 120 or onto the adhesive (if present).

[0110] Fig. 5F A vertical cross-sectional view of an intermediate structure according to one or more embodiments is shown, wherein an adhesive layer 160 may be applied to a packaging substrate 110. The adhesive layer 160 may be dispensed onto the packaging substrate 110 using a dispensing tool (e.g., an automatic dispensing tool). The dispensing tool may dispense the adhesive layer 160 in a frame shape around the packaging module 120. When applied, the adhesive layer 160 may be rigid enough to form a semi-solid bead on the surface of the packaging substrate 110. In at least one embodiment, the viscosity of each adhesive layer 160 when applied may be 50,000 centipoise (cp) or greater. The shape of the semi-solid bead may remain substantially unchanged between the time of application by the dispensing tool and the time when the packaging cover 130 is subsequently attached. The position of the frame shape of the adhesive layer 160 may correspond to the position of the foot portion 130a of the packaging cover 130 (e.g., see Figure 1B ). Pressing the packaging cover 130 onto the adhesive layer 160 may cause the adhesive layer 160 to deform.

[0111] Figure 5G A vertical cross-sectional view of an intermediate structure is shown in accordance with one or more embodiments, wherein package cap 130 may be attached to (e.g., mounted on) package substrate 110. After patterned bottom surface 131 has been formed on underside 135 of package cap portion 130p (see Figures 3 to 4I), the encapsulation cover 130 may be attached to the encapsulation substrate 110. In at least one embodiment, the encapsulation substrate 110 with the encapsulation module 120 may be placed on a surface. Then, the encapsulation cover 130 may be positioned on the encapsulation substrate 110, for example, by an electromechanical pick-and-place (PNP) machine. Then, the encapsulation cover 130 may be lowered onto the encapsulation module 120 and onto the encapsulation substrate 110. Then, the foot portion 130a of the encapsulation cover 130 may be aligned with the adhesive layer 160 formed on the encapsulation substrate 110. Then, by applying a downward pressing force on the encapsulation cover 130, the encapsulation cover 130 may be pressed downward onto the TIM layer 170, so that the foot portion 130a of the encapsulation cover 130 may be attached to the encapsulation substrate 110 through the adhesive layer 160.

[0112] By pressing the package cap 130 onto the TIM layer 170, the TIM layer 170 can be forced to flow (as indicated by the directional arrow) into the recessed portion 131a of the patterned bottom surface 131. The amount (e.g., volume) of the TIM layer 170 dispensed on the package module 120 can be sufficient to substantially fill the recessed portion 131a while leaving sufficient spacing space between the package cap plate portion 130p and the package module 120.

[0113] Then, the package cover 130 may be clamped to the package substrate 110 for a period of time to allow the adhesive layer 160 to cure and form a strong bond between the package substrate 110 and the package cover 130. Clamping the package cover 130 to the package substrate 110 may be performed, for example, using a heat clamp module. The heat clamp module may apply a uniform force on the upper surface of the package cover 130. In one or more embodiments, the heat clamp module may apply a pressing force to the package cover 130.

[0114] Figure 5H A vertical cross-sectional view of an intermediate structure according to one or more embodiments is shown, wherein a plurality of solder balls 110c may be formed on a package substrate 110. The plurality of solder balls 110c may be formed on a package substrate lower bonding pad 116a through an opening O110b in a package substrate lower passivation layer 110b. The solder balls 110c may be formed, for example, by an electroplating process. For example, the solder balls 110c may be formed to be located below the foot portion 130a and below the package module 120 and between the two. The plurality of solder balls 110c may constitute a ball grid array (BGA), which may enable the package structure 100 to be securely mounted (e.g., by surface mounting technology (SMT)) on a substrate such as a printed circuit board and electrically coupled to the substrate. The formation of the solder balls 110c may complete the formation of the package structure 100.

[0115] Figure 66 is a flow chart showing a method of forming a package structure 100 according to one or more embodiments. Step 610 includes forming a package cover, the package cover including a package cover foot portion, and a package cover plate portion located on the package cover foot portion, wherein the package cover plate portion includes a patterned bottom surface having a plurality of recessed portions. Step 620 includes attaching a package module to a package substrate. Step 630 includes placing a thermal interface material (TIM) layer on the package module. Step 640 includes attaching the package cover to the package substrate so that the package cover plate portion is located on the package module and the TIM layer is formed in the plurality of recessed portions. Figure 6 The method shown is not intended to limit the method to a particular order of steps. For example, forming the package cap in step 610 may occur at any time before attaching the package cap 130 to the package substrate 110, but not necessarily before step 620 of attaching the package module 120 to the package substrate 110 and / or placing the TIM layer 170 on the package module 120.

[0116] Figure 7 FIG. 1 is a vertical cross-sectional view of a package structure 100 having a first alternative design according to one or more embodiments. Figure 7 As shown, in a first alternative design, the recessed portion 131a may have a plurality of different depths. Specifically, the recessed portion 131a may include a first recessed portion 131a1 having a first depth, and a second recessed portion 131a2 having a second depth greater than the first depth. In at least one embodiment, the second depth may be in the range of 1.1 to 2.0 times the first depth.

[0117] The second recessed portion 131a2 may provide a larger contact area between the package cover portion 130p and the TIM layer 170. Therefore, the patterned bottom surface 131 may be designed such that the second recessed portion 131a2 is located on an area of ​​the package module 120 that generates more heat than other areas of the package module 120. Figure 7 It is shown that the second recessed portion 131a2 having a greater depth is formed at the center of the package cover 130, but the second recessed portion 131a2 may also be located in different positions on the package cover 130. For example, the second recessed portion 131a2 may be offset from the center of the package cover 130. In addition, there may be a plurality of regions in the package cover 130 where the second recessed portion 131a2 may be formed.

[0118] Figure 8 FIG. 1 is a vertical cross-sectional view of a package structure 100 having a second alternative design according to one or more embodiments. Figure 8As shown, in a second alternative design, the recessed portions 131a may have varying concentrations in the patterned bottom surface 131. Specifically, the recessed portions 131a may include third recessed portions 131a3 having a first concentration, and fourth recessed portions 131a4 having a second concentration greater than the first concentration. In at least one embodiment, the second concentration may be in a range of 1.1 to 2.0 times the first concentration. Although Figure 8 The third recessed portion 131a3 and the fourth recessed portion 131a4 are shown to be located in various positions of the package cover 130, but both the third recessed portion 131a3 and the fourth recessed portion 131a4 may be located at different positions on the package cover 130. In addition, there may be multiple regions of the third recessed portion 131a3 and the fourth recessed portion 131a4 located in various positions within the package cover 130. For example, there may be two areas where the fourth recessed portion 131a4 may be positioned to have a greater recessed portion density.

[0119] The fourth recessed portion 131a4 may provide a larger contact area between the package cover portion 130p and the TIM layer 170. Therefore, the patterned bottom surface 131 may be designed such that the fourth recessed portion 131a4 is located on an area of ​​the package module 120 that generates more heat than other areas of the package module 120.

[0120] Fig. 9 FIG. 1 is a vertical cross-sectional view of a package structure 100 having a third alternative design according to one or more embodiments. Fig. 9 As shown, in the third alternative design, the package cover portion 130p may have a first thickness T1130p and a second thickness T2130p greater than the first thickness T1130p. In at least one embodiment, the second thickness T2130p may be in the range of 1.1 times to 2.0 times the first thickness T1130p. The recessed portion 131a may include a fifth recessed portion 131a5 located in the first thickness T1130p of the package cover portion 130p, and a sixth recessed portion 131a6 located in the second thickness T2130p of the package cover portion 130p.

[0121] The sixth recessed portion 131a6 may provide a larger contact area between the package cover portion 130p and the TIM layer 170. Therefore, the patterned bottom surface 131 may be designed such that the sixth recessed portion 131a6 is located on an area of ​​the package module 120 that generates more heat than other areas of the package module 120.

[0122] Fig.10 FIG. 1 is a vertical cross-sectional view of a package structure 100 having a fourth alternative design according to one or more embodiments. Fig.10As shown, in a fourth alternative design, the patterned bottom surface 131 may include a localized patterned bottom surface 131 located only on a portion of the package module 120 (e.g., located only in a portion of the inner package cover portion 130p-2). The package cover portion 130p may be designed so that the localized patterned bottom surface 131 may be located on an area of ​​the package module 120 that generates more heat than other areas of the package module 120.

[0123] Now refer to Figures 1A to 10 The package structure 100 may include a package substrate 110, a package module 120 located on the package substrate 110, a thermal interface material (TIM) layer 170 located on the package module 120, and a package cover 130 located on the TIM layer 170. The package cover 130 may include a package cover foot portion 130a and a package cover plate portion 130p, wherein the package cover foot portion 130a is attached to the package substrate 110, and the package cover plate portion 130p is located on the package cover foot portion 130a and includes a patterned bottom surface 131 having a plurality of recessed portions 131a, wherein at least a portion of the TIM layer 170 may be located in the plurality of recessed portions 131a.

[0124] In one embodiment, the TIM layer 170 may include one of a polymer-based phase change material or a low melting temperature metal. In one embodiment, the TIM layer 170 may have a first thickness at the plurality of recessed portions 131a, and have a second thickness less than the first thickness outside the plurality of recessed portions 131a, and the first thickness may be in a range of 50 micrometers to 1000 micrometers. In one embodiment, a ratio of the depth of the plurality of recessed portions 131a to the first thickness of the TIM layer 170 may be in a range of 0.2 to 0.8. The plurality of recessed portions 131a may be substantially filled by the TIM layer 170. In one embodiment, the width of the plurality of recessed portions 131a may be in a range of 100 micrometers to 1000 micrometers. In one embodiment, the plurality of recessed portions 131a may be arranged in a staggered array having a plurality of columns 132, wherein the plurality of recessed portions 131a within a column 132 of the plurality of columns 132 may be separated by a distance in a range of 100 micrometers to 1000 micrometers. In one embodiment, a column 132 of the plurality of columns 132 may be separated from an adjacent column of the plurality of columns 132 by a distance in a range of 100 micrometers to 1000 micrometers. In one embodiment, the density of the plurality of recessed portions 131a may vary on the patterned bottom surface 131. In one embodiment, the plurality of recessed portions 131a may include one of a hexagonal shape, a circular shape and an elliptical shape, a capsule shape, a rounded rectangular shape, a square shape, a rectangular shape, a triangular shape, a trapezoidal shape, and a rhombus shape. In one embodiment, the package structure 100 may further include a surface mount device (SMD) 180 attached to the package substrate 110 between the package foot portion 130a and the package module 120. In one embodiment, the SMD 180 may include one of a rectifier, a capacitor, or a voltage regulator. In one embodiment, the outermost recessed portion 131ao of the plurality of recessed portions 131a may be located on the package module 120. In one embodiment, the distance between the outer sidewall of the packaging module 120 and the outermost recessed portion 131 ao may be in the range of 0.5 mm to 1.0 mm.

[0125] Refer again Figures 1A to 10 , a method for forming a packaging structure 100 may include: forming a packaging cover 130, the packaging cover 130 including a packaging cover foot portion 130a, and a packaging cover plate portion 130p located on the packaging cover foot portion 130a, wherein the packaging cover plate portion 130p may include a patterned bottom surface 131 having a plurality of recessed portions 131a; attaching a packaging module 120 to a packaging substrate 110; placing a thermal interface material (TIM) layer 170 on the packaging module 120; and attaching the packaging cover 130 to the packaging substrate 110, so that the packaging cover plate portion 130p may be located on the packaging module 120, and the TIM layer 170 may be formed in the plurality of recessed portions 131a.

[0126] In one embodiment, attaching the package cap 130 to the package substrate 110 may include pressing the patterned bottom surface 131 of the package cap plate portion 130p onto the TIM layer 170 so that the plurality of recessed portions 131a may be substantially filled with the TIM layer 170. In one embodiment, forming the package cap 130 may include forming the plurality of recessed portions 131a to have a width in a range of 100 micrometers to 1000 micrometers. In one embodiment, forming the package cap 130 may include forming the plurality of recessed portions 131a to be arranged in a staggered array having a plurality of columns 132, wherein the plurality of recessed portions 131a within one of the plurality of columns may be separated by a distance in a range of 100 micrometers to 1000 micrometers. In one embodiment, forming the package cap 130 may include forming a column 132 of the plurality of columns to be separated from an adjacent column 132 of the plurality of columns 132 by a distance in a range of 100 micrometers to 1000 micrometers.

[0127] Refer again Figures 1A to 10 The packaging structure 100 may include: a packaging substrate 110; a packaging module 120, located on the packaging substrate 110; a packaging cover 130, located on the packaging module 120, including a board portion 130p and a foot portion 130a, the board portion 130p having a bottom surface 131 including a recessed portion 131a, the foot portion 130a being connected to the board portion 130p and adhered to the packaging substrate 110; and a thermal interface material (TIM) layer 170, located between the packaging module 120 and the bottom surface 131 of the board portion 130p.

[0128] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the embodiments of the present invention. Those skilled in the art should understand that they can easily use the embodiments of the present invention as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the embodiments of the present invention, and they can make various changes, substitutions and modifications to them herein without departing from the spirit and scope of the embodiments of the present invention.

Claims

1. A packaging structure, characterized in that: include: Package substrate; A packaging module, located on the packaging substrate; A thermal interface heat dissipation layer, located on the packaging module; as well as The packaging cover is located on the thermal interface heat dissipation layer and includes: A package cover foot portion, attached to the package substrate; as well as The package cover plate portion comprises a patterned bottom surface having a plurality of recessed portions, wherein at least a portion of the thermal interface heat dissipation layer is located in the plurality of recessed portions.

2. The packaging structure according to claim 1, characterized in that: The thermal interface heat dissipation layer has a first thickness at the plurality of recessed portions and a second thickness less than the first thickness outside the plurality of recessed portions, and the first thickness is in a range of 50 micrometers to 1000 micrometers.

3. The packaging structure according to claim 1, characterized in that: The plurality of recessed portions are substantially filled with the thermal interface heat sink layer.

4. The packaging structure according to claim 1, characterized in that: The width of the plurality of recessed portions is in a range of 100 micrometers to 1000 micrometers.

5. The packaging structure according to claim 1, characterized in that: The plurality of recessed portions are arranged in a staggered array having a plurality of columns, wherein the plurality of recessed portions within one of the plurality of columns are separated by a distance in a range of 100 microns to 1000 microns.

6. The packaging structure according to claim 1, characterized in that: The concentration of the plurality of recessed portions varies on the patterned bottom surface.

7. The packaging structure according to claim 1, characterized in that: The plurality of recessed portions include one of a hexagonal shape, a circular shape, an elliptical shape, a capsule shape, a rounded rectangular shape, a square shape, a rectangular shape, a triangular shape, a trapezoidal shape, and a rhombus shape.

8. The packaging structure according to claim 1, characterized in that: Also includes: A surface mount device is attached to the package substrate between the package foot portion and the package module.

9. The packaging structure according to claim 1, characterized in that: An outermost recessed portion among the plurality of recessed portions is located on the packaging module.

10. A packaging structure, characterized in that: include: Package substrate; A packaging module, located on the packaging substrate; A packaging cover, located on the packaging module, comprises: a plate portion having a bottom surface including a recessed structure; and a foot portion connected to the plate portion and attached to the package substrate; and A thermal interface heat dissipation layer is located between the packaging module and the bottom surface of the board portion.

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