Control circuit based on drive signal series interlocking and corresponding circuit board

Abstract

The utility model provides a control circuit based on drive signal series interlocking and a corresponding circuit board. A CPU module outputs U-phase upper arm bridge and lower arm bridge small current signals, V-phase upper arm bridge and lower arm bridge small current signals and W-phase upper arm bridge and lower arm bridge small current signals. The buffer module increases the current of the six small current signals to generate six large current signals. And the series interlocking module performs series interlocking on the U-phase high-current signals of the upper arm bridge and the lower arm bridge, performs series interlocking on the V-phase high-current signals of the upper arm bridge and the lower arm bridge, and performs series interlocking on the W-phase high-current signals of the upper arm bridge and the lower arm bridge. The driving module inputs power supply power of an external power supply and performs power conversion on the power supply power to generate U-phase, V-phase and W-phase output power. U-phase output power is adjusted by a U-phase upper arm bridge or lower arm bridge large current signal, V-phase output power is adjusted by a V-phase upper arm bridge or lower arm bridge large current signal, and W-phase output power is adjusted by a W-phase upper arm bridge or lower arm bridge large current signal.

Description

Technical Field

[0001] The utility model relates to the technical field of circuits, and in particular to a control circuit based on series interlocking of driving signals and a corresponding circuit board. Background Art

[0002] In industrial control, in order to achieve automatic control, more and more equipment needs to be precisely controlled. The phase sequence drive control of power devices generally uses multiple PWM signals to control the output level of each phase separately, and maintains a certain phase deviation between each phase to achieve drive control between different phase sequences. In the case of phase deviation control, the power device can accurately control the output state according to the phase difference.

[0003] The driving signals of power devices currently on the market are controlled by upper and lower arm bridges, and each phase uses two sets of driving signals to control the upper and lower arm bridges respectively. However, the existing driving control method requires the timing of the driving control signal to be accurate and effective. Therefore, there is a technical problem that the existing driving control method has high requirements for the fault tolerance of the control signal software program.

[0004] Therefore, it is necessary to provide a control circuit based on series interlocking of drive signals and a corresponding circuit board to solve the above technical problems. Utility Model Content

[0005] The utility model provides a control circuit based on serial interlocking of driving signals and a corresponding circuit board, which effectively solves the technical problem that the existing driving control method has high fault tolerance requirements on the control signal software program.

[0006] The utility model provides a control circuit based on series interlocking of drive signals, which comprises:

[0007] CPU module, used for outputting enable signal, U-phase upper arm bridge small current signal, V-phase upper arm bridge small current signal, W-phase upper arm bridge small current signal, U-phase lower arm bridge small current signal, V-phase lower arm bridge small current signal, W-phase lower arm bridge small current signal;

[0008] A buffer module, based on the conduction of the enable signal, is used to perform a current boosting operation on the U-phase upper arm bridge small current signal to generate a U-phase upper arm bridge large current signal; is used to perform a current boosting operation on the V-phase upper arm bridge small current signal to generate a V-phase upper arm bridge large current signal; is used to perform a current boosting operation on the W-phase upper arm bridge small current signal to generate a W-phase upper arm bridge large current signal; is used to perform a current boosting operation on the U-phase lower arm bridge small current signal to generate a U-phase lower arm bridge large current signal; is used to perform a current boosting operation on the V-phase lower arm bridge small current signal to generate a V-phase lower arm bridge large current signal; is used to perform a current boosting operation on the W-phase lower arm bridge small current signal to generate a W-phase lower arm bridge large current signal;

[0009] A series interlocking module, used for series interlocking the U-phase upper arm bridge high current signal and the U-phase lower arm bridge high current signal, so as to effectively output one of the signals; used for series interlocking the V-phase upper arm bridge high current signal and the V-phase lower arm bridge high current signal, so as to effectively output one of the signals; used for series interlocking the W-phase upper arm bridge high current signal and the W-phase lower arm bridge high current signal, so as to effectively output one of the signals;

[0010] A driving module, which inputs power from an external power source, is used to perform power conversion operations on the power source power to generate U-phase output power, and the driving module adjusts the power size of the U-phase output power based on the U-phase upper arm bridge large current signal or the U-phase lower arm bridge large current signal; is used to perform power conversion operations on the power source power to generate V-phase output power, and the driving module adjusts the power size of the V-phase output power based on the V-phase upper arm bridge large current signal or the V-phase lower arm bridge large current signal; is used to perform power conversion operations on the power source power to generate W-phase output The driving module adjusts the power of the W-phase output power based on the W-phase upper arm bridge high current signal or the W-phase lower arm bridge high current signal, and is used to provide stable U-phase output power, V-phase output power, and W-phase output power for the power equipment (such as the motor) at the subsequent stage, and reduces the limit requirements of the CPU pin driving current and the functional limit of the driving pin, and can select a variety of different CPUs; the driving signals are interlocked in series, effectively maintaining the correctness of the driving control of the upper and lower arm bridges of the power device, improving the reliability of the overall control, and avoiding external factors or program software errors from affecting the normal use of the product. Reduce the complexity of software design logic protection for software engineers, and do not increase much hardware costs.

[0011] Furthermore, the driving module includes a driving chip, which includes a positive input pin, a negative input pin, a U-phase output pin, a V-phase output pin and a W-phase output pin, the positive input pin is connected to the positive pole of the external power supply, the negative input pin is connected to the negative pole of the external power supply, the U-phase output pin is used to output the U-phase output power, the V-phase output pin is used to output the V-phase output power, and the W-phase output pin is used to output the W-phase output power.

[0012] Further, the buffer module includes a buffer chip, and the buffer chip includes an enable pin, a 1A4 pin, a 1A3 pin, a 1A2 pin, a 1A1 pin, a 2A1 pin, and a 2A2 pin;

[0013] The enable pin is used to receive the enable signal, the 1A4 pin is used to receive the U-phase upper arm bridge small current signal, the 1A3 pin is used to receive the V-phase upper arm bridge small current signal, the 1A2 pin is used to receive the W-phase upper arm bridge small current signal, the 1A1 pin is used to receive the U-phase lower arm bridge small current signal, the 2A1 pin is used to receive the V-phase lower arm bridge small current signal, and the 2A2 pin is used to receive the W-phase lower arm bridge small current signal;

[0014] The buffer chip is used to increase the current of the U-phase upper arm bridge small current signal, the buffer chip is used to increase the current of the V-phase upper arm bridge small current signal, the buffer chip is used to increase the current of the W-phase upper arm bridge small current signal, the buffer chip is used to increase the current of the U-phase lower arm bridge small current signal, the buffer chip is used to increase the current of the V-phase lower arm bridge small current signal, and the buffer chip is used to increase the current of the W-phase lower arm bridge small current signal;

[0015] The series interlocking module includes a first U-phase optocoupler, a second U-phase optocoupler, a first V-phase optocoupler, a second V-phase optocoupler, a first W-phase optocoupler, and a second W-phase optocoupler; the buffer chip also includes a 1Y4 pin, a 1Y3 pin, a 1Y2 pin, a 1Y1 pin, a 2Y1 pin, and a 2Y2 pin; the 1Y4 pin is used to output the U-phase upper arm bridge high current signal, the 1Y3 pin is used to output the V-phase upper arm bridge high current signal, the 1Y2 pin is used to output the W-phase upper arm bridge high current signal, the 1Y1 pin is used to output the U-phase lower arm bridge high current signal, the 2Y1 pin is used to output the V-phase lower arm bridge high current signal, and the 2Y2 pin is used to output the W-phase lower arm bridge high current signal;

[0016] The 1Y4 pin is connected to the negative input terminal of the first U-phase optocoupler and the positive input terminal of the second U-phase optocoupler, the 1Y3 pin is connected to the negative input terminal of the first V-phase optocoupler and the positive input terminal of the second V-phase optocoupler, the 1Y2 pin is connected to the negative input terminal of the first W-phase optocoupler and the positive input terminal of the second W-phase optocoupler, the 1Y1 pin is connected to the positive input terminal of the first U-phase optocoupler and the negative input terminal of the second U-phase optocoupler, the 2Y1 pin is connected to the positive input terminal of the first V-phase optocoupler and the negative input terminal of the second V-phase optocoupler, and the 2Y2 pin is connected to the positive input terminal of the first W-phase optocoupler and the negative input terminal of the second W-phase optocoupler;

[0017] The driver chip also includes a Vup pin, a Vvp pin, a Vwp pin, a UN pin, a VN pin, and a WN pin; the Vup pin is used to receive the U-phase upper arm bridge high current signal, the Vvp pin is used to receive the V-phase upper arm bridge high current signal, the Vwp pin is used to receive the W-phase upper arm bridge high current signal, the UN pin is used to receive the U-phase lower arm bridge high current signal, the VN pin is used to receive the V-phase lower arm bridge high current signal, and the WN pin is used to receive the W-phase lower arm bridge high current signal;

[0018] The output end of the first U-phase optocoupler is connected to the Vup pin, the output end of the first V-phase optocoupler is connected to the Vvp pin, the output end of the first W-phase optocoupler is connected to the Vwp pin, the output end of the second U-phase optocoupler is connected to the UN pin, the output end of the second V-phase optocoupler is connected to the VN pin, and the output end of the second W-phase optocoupler is connected to the WN pin.

[0019] Furthermore, the buffer module further includes a first current limiting resistor, a second current limiting resistor, a third current limiting resistor, a fourth current limiting resistor, a fifth current limiting resistor, and a sixth current limiting resistor;

[0020] One end of the first current limiting resistor is connected to the 1Y4 pin, and the other end of the first current limiting resistor is connected to the negative input terminal of the first U-phase optocoupler and the positive input terminal of the second U-phase optocoupler; one end of the second current limiting resistor is connected to the 1Y3 pin, and the other end of the second current limiting resistor is connected to the negative input terminal of the first V-phase optocoupler and the positive input terminal of the second V-phase optocoupler; one end of the third current limiting resistor is connected to the 1Y2 pin, and the other end of the third current limiting resistor is connected to the negative input terminal of the first W-phase optocoupler and the positive input terminal of the second W-phase optocoupler; One end of the fourth current limiting resistor is connected to the 1Y1 pin, and the other end of the fourth current limiting resistor is connected to the input positive end of the first U-phase optocoupler and the input negative end of the second U-phase optocoupler; one end of the fifth current limiting resistor is connected to the 2Y1 pin, and the other end of the fifth current limiting resistor is connected to the input positive end of the first V-phase optocoupler and the input negative end of the second V-phase optocoupler; one end of the sixth current limiting resistor is connected to the 2Y2 pin, and the other end of the sixth current limiting resistor is connected to the input positive end of the first W-phase optocoupler and the input negative end of the second W-phase optocoupler.

[0021] Further, the series interlocking module also includes a first filter capacitor, a second filter capacitor, a third filter capacitor, a fourth filter capacitor, a fifth filter capacitor, and a sixth filter capacitor;

[0022] The positive power terminal of the first U-phase optocoupler, the positive power terminal of the second U-phase optocoupler, the positive power terminal of the first V-phase optocoupler, the positive power terminal of the second V-phase optocoupler, the positive power terminal of the first W-phase optocoupler, and the positive power terminal of the second W-phase optocoupler are all connected to the positive electrode of the optocoupler power supply, and the negative power terminal of the first U-phase optocoupler, the negative power terminal of the second U-phase optocoupler, the negative power terminal of the first V-phase optocoupler, the negative power terminal of the second V-phase optocoupler, the negative power terminal of the first W-phase optocoupler, and the negative power terminal of the second W-phase optocoupler are all connected to the negative electrode of the optocoupler power supply, and the optocoupler power supply is used to supply power to the first U-phase optocoupler, the second U-phase optocoupler, the first V-phase optocoupler, the second V-phase optocoupler, the first W-phase optocoupler, and the second W-phase optocoupler;

[0023] The first filter capacitor is connected between the positive power terminal of the first U-phase optocoupler and the negative power terminal of the first U-phase optocoupler, the second filter capacitor is connected between the positive power terminal of the first V-phase optocoupler and the negative power terminal of the first V-phase optocoupler, the third filter capacitor is connected between the positive power terminal of the first W-phase optocoupler and the negative power terminal of the first W-phase optocoupler, the fourth filter capacitor is connected between the positive power terminal of the second U-phase optocoupler and the negative power terminal of the second U-phase optocoupler, the fifth filter capacitor is connected between the positive power terminal of the second V-phase optocoupler and the negative power terminal of the second V-phase optocoupler, and the sixth filter capacitor is connected between the positive power terminal of the second W-phase optocoupler and the negative power terminal of the second W-phase optocoupler.

[0024] Furthermore, the buffer module also includes a seventh filter capacitor, and the buffer chip also includes a VCC pin, the VCC pin is connected to a chip power supply, the chip power supply is used to power the buffer chip, one end of the seventh filter capacitor is connected to the VCC pin, and the other end of the seventh filter capacitor is grounded, and the seventh filter capacitor is used to filter the voltage output by the chip power supply.

[0025] Furthermore, the driving module also includes a current detection unit, one end of the current detection unit is connected to the U-phase output pin and the V-phase output pin, or to the U-phase output pin and the W-phase output pin, or to the V-phase output pin and the W-phase output pin, and the other end of the current detection unit is connected to the CPU module, and the current detection unit is used to detect the magnitude of the output current of the driving module.

[0026] Furthermore, the driving module also includes a temperature detection unit, the driving chip includes an NC pin and a VNC pin, one end of the temperature detection unit is connected to the NC pin, and one end of the temperature detection unit is connected to the VNC pin, and the temperature detection unit is used to detect the temperature of the driving chip, so that the driving chip performs a fault alarm operation based on the temperature value of the driving chip.

[0027] Furthermore, the driving module also includes a power supply current detection resistor, a delay resistor and a delay capacitor, and the driving chip also includes a CIN pin, one end of the power supply current detection resistor is connected to the negative electrode of the external power supply, one end of the power supply current detection resistor is connected to the CIN pin, the power supply current detection resistor is used to detect the output current of the external power supply, and the driving chip performs a short-circuit protection operation based on the current value of the external power supply output current, one end of the delay capacitor is connected to the negative electrode of the external power supply, the other end of the delay capacitor is the CIN pin, one end of the delay resistor is connected to the CIN pin, and the other end of the delay resistor is connected to the negative input pin, and the delay resistor and the delay capacitor are used for the short-circuit protection delay operation of the driving chip.

[0028] A circuit board comprises any of the above-mentioned control circuits based on serial interlocking of drive signals.

[0029] Compared with the prior art, the utility model has the following beneficial effects: the utility model provides a control circuit based on the serial interlocking of the driving signal, and the control circuit based on the serial interlocking of the driving signal includes a buffer module, a serial interlocking module, and a driving module. The buffer module is used to perform a current-boosting operation on the small current signal of the upper arm bridge of the U phase, and the buffer module generates a large current signal of the upper arm bridge of the U phase. The buffer module is used to perform a current-boosting operation on the small current signal of the upper arm bridge of the V phase, and the buffer module generates a large current signal of the upper arm bridge of the V phase. The buffer module is used to perform a current-boosting operation on the small current signal of the upper arm bridge of the W phase, and the buffer module generates a large current signal of the upper arm bridge of the W phase. The buffer module is used to perform a current-boosting operation on the small current signal of the lower arm bridge of the U phase, and the buffer module generates a large current signal of the lower arm bridge of the U phase. The buffer module is used to perform a current-boosting operation on the small current signal of the lower arm bridge of the V phase, and the buffer module generates a large current signal of the lower arm bridge of the V phase. The buffer module is used to perform a current-boosting operation on the small current signal of the lower arm bridge of the W phase, and the buffer module generates a large current signal of the lower arm bridge of the W phase. Since the buffer module can be used to increase the current of the signal, users can choose some CPU modules with low drive output current. The setting of the buffer module reduces the limitation of the CPU module and effectively improves the versatility and selectivity of the CPU module. In addition, before the initial power-on of the buffer module, the buffer chip can be enabled and disconnected. After the CPU module is initialized and runs normally, the buffer chip can be enabled and turned on to avoid accidental operation of the buffer chip due to the uncertainty of the power-on pin.

[0030] The series interlocking module is used to interlock the U-phase upper arm bridge high current signal and the U-phase lower arm bridge high current signal in series, so as to effectively output one of the signals. The series interlocking module is used to interlock the V-phase upper arm bridge high current signal and the V-phase lower arm bridge high current signal in series, so as to effectively output one of the signals. The series interlocking module is used to interlock the W-phase upper arm bridge high current signal and the W-phase lower arm bridge high current signal in series, so as to effectively output one of the signals. In the prior art, if the program is wrong or the program is abnormal, the upper arm bridge signal and the lower arm bridge signal are output at the same time, thereby causing a short circuit to damage the subsequent power device. However, after the upper arm bridge signal and the lower arm bridge signal are input into the series interlocking module, the series interlocking module will only output one of the signals. Therefore, the control circuit based on the series interlocking of the drive signal has low fault tolerance requirements for the software program. It effectively solves the technical problem that the existing drive control method has high fault tolerance requirements for the control signal software program.

[0031] The driving module inputs the power supply power of the external power supply, and the driving module is used to perform power conversion operations on the power supply power, and the driving module generates U-phase output power, V-phase output power, and W-phase output power. Based on the U-phase upper arm bridge large current signal or the U-phase lower arm bridge large current signal, the driving module adjusts the power size of the U-phase output power. Based on the V-phase upper arm bridge large current signal or the V-phase lower arm bridge large current signal, the driving module adjusts the power size of the V-phase output power. Based on the W-phase upper arm bridge large current signal or the W-phase lower arm bridge large current signal, the driving module adjusts the power size of the W-phase output power. Therefore, the control circuit based on the series interlocking of the drive signal can provide stable U-phase output power, V-phase output power, and W-phase output power for the power equipment (such as a motor) of the subsequent stage. Furthermore, the control circuit based on the series interlocking of the drive signal can stably drive the power equipment of the subsequent stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. The drawings described below are only drawings corresponding to some embodiments of the utility model.

[0033] Figure 1 It is a block diagram of an embodiment of a control circuit based on series interlocking of drive signals of the present utility model.

[0034] Figure 2 It is a circuit diagram of a buffer module of an embodiment of a control circuit based on serial interlocking of driving signals of the present utility model.

[0035] Figure 3 It is a circuit diagram of a series interlocking module of an embodiment of a control circuit based on series interlocking of driving signals of the present utility model.

[0036] Figure 4 It is a circuit diagram of a driving module of an embodiment of a control circuit based on serial interlocking of driving signals of the present utility model.

[0037] In the figure, 10, control circuit; 11, CPU module; 12, buffer module; 13, series interlocking module; 14, drive module; 141, current detection unit; 142, temperature detection unit; 15, external power supply; 16, chip power supply; 17, optocoupler power supply. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.

[0039] Directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", "top" and "bottom", are only used for reference to the directions of the drawings. The directional terms used are used to illustrate and understand the present invention, and are not used to limit the present invention.

[0040] The words "first", "second" and the like in the terminology of the present invention are used for descriptive purposes only and should not be understood as indicating or implying relative importance, and should not be construed as limiting the order of precedence.

[0041] In the figures, structurally similar elements are denoted by the same reference numerals.

[0042] Please refer to Figure 1 The utility model provides a control circuit 10 based on serial interlocking of drive signals. The control circuit 10 based on serial interlocking of drive signals is applied to a circuit board, and the control circuit 10 based on serial interlocking of drive signals includes a CPU module 11, a buffer module 12, a serial interlocking module 12, and a drive module 14. The CPU module 11 is used to output an enable signal, a U-phase upper arm bridge small current signal, a V-phase upper arm bridge small current signal, a W-phase upper arm bridge small current signal, a U-phase lower arm bridge small current signal, a V-phase lower arm bridge small current signal, and a W-phase lower arm bridge small current signal. Generally, after the CPU is initialized and reset, the CPU first outputs an enable signal, and then the CPU outputs the remaining signals.

[0043] Please refer to Figure 1 and Figure 2, the buffer module 12 can be turned on based on the enable signal. The buffer module 12 is used to increase the current operation of the U-phase upper arm bridge small current signal, and the buffer module 12 can generate the U-phase upper arm bridge large current signal. The buffer module 12 is used to increase the current operation of the V-phase upper arm bridge small current signal, and the buffer module 12 can generate the V-phase upper arm bridge large current signal. The buffer module 12 is used to increase the current operation of the W-phase upper arm bridge small current signal, and the buffer module 12 can generate the W-phase upper arm bridge large current signal. The buffer module 12 is used to increase the current operation of the U-phase lower arm bridge small current signal, and the buffer module 12 can generate the U-phase lower arm bridge large current signal. The buffer module 12 is used to increase the current operation of the V-phase lower arm bridge small current signal, and the buffer module 12 can generate the V-phase lower arm bridge large current signal. The buffer module 12 is used to increase the current operation of the W-phase lower arm bridge small current signal, and the buffer module 12 can generate the W-phase lower arm bridge large current signal.

[0044] Please refer to Figure 2 , the buffer module 12 includes a buffer chip U304, and the buffer chip U304 includes an enable pin, a 1A4 pin, a 1A3 pin, a 1A2 pin, a 1A1 pin, a 2A1 pin, and a 2A2 pin. Among them, the enable pin includes 1OE and 2OE pins. The enable pin is used to receive an enable signal, and the 1A4 pin is used to receive a U-phase upper arm bridge small current signal. The 1A3 pin is used to receive a V-phase upper arm bridge small current signal, the 1A2 pin is used to receive a W-phase upper arm bridge small current signal, and the 1A1 pin is used to receive a U-phase lower arm bridge small current signal. The 2A1 pin is used to receive a V-phase lower arm bridge small current signal, and the 2A2 pin is used to receive a W-phase lower arm bridge small current signal.

[0045] Please refer to Figure 2 , the buffer chip U304 is used to increase the current of the U-phase upper arm bridge small current signal, and the buffer chip U304 is used to increase the current of the V-phase upper arm bridge small current signal. The buffer chip U304 is used to increase the current of the W-phase upper arm bridge small current signal, and the buffer chip U304 is used to increase the current of the U-phase lower arm bridge small current signal. The buffer chip U304 is used to increase the current of the V-phase lower arm bridge small current signal, and the buffer chip U304 is used to increase the current of the W-phase lower arm bridge small current signal. The buffer chip U304 uses an eight-way buffer with enable control, and its enable control is a low-level effective signal control, that is, the enable signal is low-level effective. When the buffer chip U304 does not receive the enable signal, even if the input pin of the buffer chip U304 has a signal input, the buffer chip U304 has no signal output. When the buffer chip U304 receives the enable signal, the buffer chip U304 can output a signal.

[0046] Please refer to Figure 2, the buffer module 12 also includes a pull-up resistor R310. One end of the pull-up resistor R310 is connected to the chip power supply 16, and the other end of the pull-up resistor R310 is connected to the enable pin. The setting of the pull-up resistor R310 can ensure that the enable pin receives a high-level signal when the power is initially turned on, thereby limiting the output of the buffer chip U304. The buffer module 12 can increase the current of the signal, so that the signal can effectively control the optical coupler of the subsequent stage. In addition, the current of the increased signal can also meet the driving requirements of the subsequent optical coupler isolation circuit, and can also improve the anti-interference ability of the signal. The buffer chip U304 has an enable control, which can avoid abnormal output of the CPU module 11 and damage the power device at the back end. The buffer chip U304 can increase the current of the signal, so that the signal can stably drive the optical coupler of the subsequent stage, and can also improve the anti-interference ability of the signal, reducing the risk of the driving signal causing malfunction of the subsequent control due to interference spikes.

[0047] Please refer to Figure 1 and Figure 3 The series interlocking module 12 is used to perform series interlocking of the U-phase upper arm bridge high current signal and the U-phase lower arm bridge high current signal, so that the series interlocking module 12 can effectively output one of the signals. The series interlocking module 12 is used to perform series interlocking of the V-phase upper arm bridge high current signal and the V-phase lower arm bridge high current signal, so that the series interlocking module 12 can effectively output one of the signals. The series interlocking module 12 is used to perform series interlocking of the W-phase upper arm bridge high current signal and the W-phase lower arm bridge high current signal, so that the series interlocking module 12 can effectively output one of the signals.

[0048] Please refer to Figure 2 and Figure 3 The series interlocking module 12 includes a first U-phase optocoupler OP1, a second U-phase optocoupler OP4, a first V-phase optocoupler OP2, a second V-phase optocoupler OP5, a first W-phase optocoupler OP3, and a second W-phase optocoupler OP6. The buffer chip U304 also includes 1Y4 pin, 1Y3 pin, 1Y2 pin, 1Y1 pin, 2Y1 pin, and 2Y2 pin. The 1Y4 pin is used to output the U-phase upper arm bridge high current signal. The 1Y3 pin is used to output the V-phase upper arm bridge high current signal, the 1Y2 pin is used to output the W-phase upper arm bridge high current signal, the 1Y1 pin is used to output the U-phase lower arm bridge high current signal, the 2Y1 pin is used to output the V-phase lower arm bridge high current signal, and the 2Y2 pin is used to output the W-phase lower arm bridge high current signal.

[0049] Please refer to Figure 2 and Figure 3, 1Y4 pin is connected to the negative input terminal of the first U-phase optocoupler OP1 and the positive input terminal of the second U-phase optocoupler OP4, 1Y3 pin is connected to the negative input terminal of the first V-phase optocoupler OP2 and the positive input terminal of the second V-phase optocoupler OP5. 1Y2 pin is connected to the negative input terminal of the first W-phase optocoupler OP3 and the positive input terminal of the second W-phase optocoupler OP6, 1Y1 pin is connected to the positive input terminal of the first U-phase optocoupler OP1 and the negative input terminal of the second U-phase optocoupler OP4. 2Y1 pin is connected to the positive input terminal of the first V-phase optocoupler OP2 and the negative input terminal of the second V-phase optocoupler OP5, 2Y2 pin is connected to the positive input terminal of the first W-phase optocoupler OP3 and the negative input terminal of the second W-phase optocoupler OP6.

[0050] Please refer to Figure 3 At the input end of the optocoupler, the upper and lower bridge arm signals of the same phase are input in series, but each phase remains independent of each other. The upper and lower bridge arm signals of the same phase are interlocked in series using two optocoupler isolation chips, such as the U-phase upper arm bridge high current signal and the U-phase lower arm bridge high current signal are interlocked in series through the first U-phase optocoupler OP1 and the second U-phase optocoupler OP4. The V-phase upper arm bridge high current signal and the V-phase lower arm bridge high current signal are interlocked in series through the first V-phase optocoupler OP2 and the second V-phase optocoupler OP5. The W-phase upper arm bridge high current signal and the W-phase lower arm bridge high current signal are interlocked in series through the first W-phase optocoupler OP3 and the second W-phase optocoupler OP6.

[0051] When the U-phase upper arm bridge high current signal is at a high level, and the U-phase lower arm bridge high current signal is at a low level, the second U-phase optocoupler OP4 inputs a high level signal at the positive input end, and the second U-phase optocoupler OP4 inputs a low level signal at the negative input end. Therefore, the second U-phase optocoupler OP4 is turned on, and the output end of the second U-phase optocoupler OP4 outputs the U-phase lower arm bridge high current signal. However, since the first U-phase optocoupler OP1 inputs a low level signal at the positive input end, and the first U-phase optocoupler OP1 inputs a high level signal at the negative input end, the first U-phase optocoupler OP1 is not turned on.

[0052] Similarly, when the U-phase upper arm bridge high current signal is at a low level, and the U-phase lower arm bridge high current signal is at a high level, the input positive end of the first U-phase optocoupler OP1 inputs a high level signal, and the input negative end of the first U-phase optocoupler OP1 inputs a low level signal. Therefore, the first U-phase optocoupler OP1 is turned on, and the output end of the first U-phase optocoupler OP1 outputs the U-phase upper arm bridge high current signal. However, since the input positive end of the second U-phase optocoupler OP4 inputs a low level signal, and the input negative end of the second U-phase optocoupler OP4 inputs a high level signal, the second U-phase optocoupler OP4 is not turned on. Therefore, the setting of the series interlocking module 12 ensures that only one of the upper and lower arm bridge signals is valid. When the U-phase upper arm bridge high current signal and the U-phase lower arm bridge high current signal are both high or low, the first U-phase optocoupler OP1 and the second U-phase optocoupler OP4 are not turned on. In the series interlocking module 12, the upper and lower arm bridges will not be turned on and output at the same time, thus protecting the U-phase output of the U-phase power device.

[0053] When the V-phase upper arm bridge high current signal is at a high level, and the V-phase lower arm bridge high current signal is at a low level, the input positive terminal of the second V-phase optocoupler OP5 inputs a high level signal, and the input negative terminal of the second V-phase optocoupler OP5 inputs a low level signal. Therefore, the second V-phase optocoupler OP5 is turned on, and the output terminal of the second V-phase optocoupler OP5 outputs the V-phase lower arm bridge high current signal. However, since the input positive terminal of the first V-phase optocoupler OP2 inputs a low level signal, and the input negative terminal of the first V-phase optocoupler OP2 inputs a high level signal, the first V-phase optocoupler OP2 is not turned on.

[0054] Similarly, when the V-phase upper arm bridge high current signal is at a low level, and the V-phase lower arm bridge high current signal is at a high level, the input positive end of the first V-phase optocoupler OP2 inputs a high level signal, and the input negative end of the first V-phase optocoupler OP2 inputs a low level signal. Therefore, the first V-phase optocoupler OP2 is turned on, and the output end of the first V-phase optocoupler OP2 outputs the V-phase upper arm bridge high current signal. However, since the input positive end of the second V-phase optocoupler OP5 inputs a low level signal, and the input negative end of the second V-phase optocoupler OP5 inputs a high level signal, the second V-phase optocoupler OP5 is not turned on. Therefore, the setting of the series interlocking module 12 ensures that only one of the upper and lower arm bridge signals is valid. When the V-phase upper arm bridge high current signal and the V-phase lower arm bridge high current signal are both high or low, the first V-phase optocoupler OP2 and the second V-phase optocoupler OP5 are not turned on. In the series interlocking module 12, the upper and lower arm bridges will not be turned on and output at the same time, thus protecting the V-phase output of the V-phase power device.

[0055] When the W-phase upper arm bridge high current signal is at a high level, and the W-phase lower arm bridge high current signal is at a low level, the input positive terminal of the second W-phase optocoupler OP6 inputs a high level signal, and the input negative terminal of the second W-phase optocoupler OP6 inputs a low level signal. Therefore, the second W-phase optocoupler OP6 is turned on, and the output terminal of the second W-phase optocoupler OP6 outputs the W-phase lower arm bridge high current signal. However, since the input positive terminal of the first W-phase optocoupler OP3 inputs a low level signal, and the input negative terminal of the first W-phase optocoupler OP3 inputs a high level signal, the first W-phase optocoupler OP3 is not turned on.

[0056] Similarly, when the W-phase upper arm bridge high current signal is at a low level, and the W-phase lower arm bridge high current signal is at a high level, the input positive end of the first W-phase optocoupler OP3 inputs a high level signal, and the input negative end of the first W-phase optocoupler OP3 inputs a low level signal. Therefore, the first W-phase optocoupler OP3 is turned on, and the output end of the first W-phase optocoupler OP3 outputs the W-phase upper arm bridge high current signal. However, since the input positive end of the second W-phase optocoupler OP6 inputs a low level signal, and the input negative end of the second W-phase optocoupler OP6 inputs a high level signal, the second W-phase optocoupler OP6 is not turned on. Therefore, the setting of the series interlocking module 12 ensures that only one of the upper and lower arm bridge signals is valid. When the W-phase upper arm bridge high current signal and the W-phase lower arm bridge high current signal are both high or low, the first W-phase optocoupler OP3 and the second W-phase optocoupler OP6 are not turned on. In the series interlocking module 12, the upper and lower arm bridges will not be turned on and output at the same time, thus protecting the W-phase output of the W-phase power device. The setting of the series interlocking module 12 can make the upper and lower arm bridge signals drive and control correctly, improve the reliability of the overall control, and avoid the normal use of the product affected by external factors or program software errors. The drive signals of the upper and lower bridge arms of the same phase are connected in series interlocking, so that only one of the two sets of upper and lower arm bridge signals output by the CPU can be turned on.

[0057] Please refer to Figure 1 and Figure 4 , the driving module 14 can input the power of the external power supply 15. The driving module 14 is used to perform power conversion operations on the power, so that the driving module 14 can generate U-phase output power, V-phase output power and W-phase output power. Based on the U-phase upper arm bridge large current signal or the U-phase lower arm bridge large current signal, the driving module 14 can adjust the power size of the U-phase output power. Based on the V-phase upper arm bridge large current signal or the V-phase lower arm bridge large current signal, the driving module 14 can adjust the power size of the V-phase output power. Based on the W-phase upper arm bridge large current signal or the W-phase lower arm bridge large current signal, the driving module 14 can adjust the power size of the W-phase output power.

[0058] Please refer to Figure 1, the control circuit 10 can provide stable U-phase output power, V-phase output power, and W-phase output power for the power equipment (such as motor) at the subsequent stage. In addition, the control circuit 10 can reduce the limit requirements of the CPU pin drive current and the functional limitations of the drive pin, and the user can choose a variety of different CPUs. Moreover, the drive signal is interlocked in series, which effectively maintains the correctness of the drive control of the upper and lower arm bridges of the power device, can improve the reliability of the overall control, and avoid external factors or program software errors affecting the normal use of the product. The setting of the control circuit 10 can reduce the complexity of the software design logic protection of software engineers, and does not increase much hardware cost.

[0059] Please refer to Figure 1 and Figure 4 , the driving module 14 includes a driving chip IPM1, and the driving chip IPM1 includes a positive input pin P, a negative input pin, a U-phase output pin U, a V-phase output pin V, and a W-phase output pin W. Among them, the negative input pin includes a NU pin, an NV pin, and a NW pin. The positive input pin P is connected to the positive pole of the external power supply 15, and the negative input pin is connected to the negative pole of the external power supply 15. The U-phase output pin U is used to output the U-phase output power, the V-phase output pin V is used to output the V-phase output power, and the W-phase output pin W is used to output the W-phase output power. The driving chip IPM1 also includes a Vup pin, a Vvp pin, a Vwp pin, a UN pin, a VN pin, and a WN pin. The Vup pin is used to receive a U-phase upper arm bridge high current signal, and the Vvp pin is used to receive a V-phase upper arm bridge high current signal. The Vwp pin is used to receive a W-phase upper arm bridge high current signal, and the UN pin is used to receive a U-phase lower arm bridge high current signal. The VN pin is used to receive a V-phase lower arm bridge high current signal, and the WN pin is used to receive a W-phase lower arm bridge high current signal. The output end of the first U-phase optocoupler OP1 is connected to the Vup pin, and the output end of the first V-phase optocoupler OP2 is connected to the Vvp pin. The output end of the first W-phase optocoupler OP3 is connected to the Vwp pin, and the output end of the second U-phase optocoupler OP4 is connected to the UN pin. The output end of the second V-phase optocoupler OP5 is connected to the VN pin, and the output end of the second W-phase optocoupler OP6 is connected to the WN pin.

[0060] Please refer to Figure 2, the buffer module 12 also includes a first current limiting resistor R321, a second current limiting resistor R320, a third current limiting resistor R319, a fourth current limiting resistor R318, a fifth current limiting resistor R322, and a sixth current limiting resistor R323. One end of the first current limiting resistor R321 is connected to the 1Y4 pin, and the other end of the first current limiting resistor R321 is connected to the input negative end of the first U-phase optocoupler OP1 and the input positive end of the second U-phase optocoupler OP4. One end of the second current limiting resistor R320 is connected to the 1Y3 pin, and the other end of the second current limiting resistor R320 is connected to the input negative end of the first V-phase optocoupler OP2 and the input positive end of the second V-phase optocoupler OP5. One end of the third current limiting resistor R319 is connected to the 1Y2 pin, and the other end of the third current limiting resistor R319 is connected to the input negative end of the first W-phase optocoupler OP3 and the input positive end of the second W-phase optocoupler OP6.

[0061] Please refer to Figure 2 , one end of the fourth current limiting resistor R318 is connected to the 1Y1 pin, and the other end of the fourth current limiting resistor R318 is connected to the input positive end of the first U-phase optocoupler OP1 and the input negative end of the second U-phase optocoupler OP4. One end of the fifth current limiting resistor R322 is connected to the 2Y1 pin, and the other end of the fifth current limiting resistor R322 is connected to the input positive end of the first V-phase optocoupler OP2 and the input negative end of the second V-phase optocoupler OP5. One end of the sixth current limiting resistor R323 is connected to the 2Y2 pin, and the other end of the sixth current limiting resistor R323 is connected to the input positive end of the first W-phase optocoupler OP3 and the input negative end of the second W-phase optocoupler OP6. The buffer chip U304 can output a large current. If there is no current limit, it is easy to cause the output power consumption of the buffer chip U304 to be too high. Therefore, adding a current limiting resistor at the output end of the buffer chip U304 can effectively solve the technical problem of excessive output power consumption of the buffer chip U304 when multiple outputs are performed.

[0062] Please refer to Figure 3The series interlocking module 12 also includes a first filter capacitor C2, a second filter capacitor C3, a third filter capacitor C4, a fourth filter capacitor C5, a fifth filter capacitor C6, and a sixth filter capacitor C7. The positive power terminal of the first U-phase optical coupler OP1, the positive power terminal of the second U-phase optical coupler OP4, the positive power terminal of the first V-phase optical coupler OP2, the positive power terminal of the second V-phase optical coupler OP5, the positive power terminal of the first W-phase optical coupler OP3, and the positive power terminal of the second W-phase optical coupler OP6 are all connected to the positive electrode of the optical coupler power supply 17, and the negative power terminal of the first U-phase optical coupler OP1, the negative power terminal of the second U-phase optical coupler OP4, the negative power terminal of the first V-phase optical coupler OP2, the negative power terminal of the second V-phase optical coupler OP5, the negative power terminal of the first W-phase optical coupler OP3, and the negative power terminal of the second W-phase optical coupler OP6 are all connected to the negative electrode of the optical coupler power supply 17. The optocoupler power supply 17 is used to power the first U-phase optocoupler OP1 , the second U-phase optocoupler OP4 , the first V-phase optocoupler OP2 , the second V-phase optocoupler OP5 , the first W-phase optocoupler OP3 , and the second W-phase optocoupler OP6 .

[0063] Please refer to Figure 3 , the first filter capacitor C2 is connected between the positive power terminal of the first U-phase optical coupler OP1 and the negative power terminal of the first U-phase optical coupler OP1, and the second filter capacitor C3 is connected between the positive power terminal of the first V-phase optical coupler OP2 and the negative power terminal of the first V-phase optical coupler OP2. The third filter capacitor C4 is connected between the positive power terminal of the first W-phase optical coupler OP3 and the negative power terminal of the first W-phase optical coupler OP3, and the fourth filter capacitor C5 is connected between the positive power terminal of the second U-phase optical coupler OP4 and the negative power terminal of the second U-phase optical coupler OP4. The fifth filter capacitor C6 is connected between the positive power terminal of the second V-phase optical coupler OP5 and the negative power terminal of the second V-phase optical coupler OP5, and the sixth filter capacitor C7 is connected between the positive power terminal of the second W-phase optical coupler OP6 and the negative power terminal of the second W-phase optical coupler OP6. The filter capacitor can filter the ripple of the optical coupler power supply 17, and can effectively improve the flatness of the output voltage waveform of the optical coupler power supply 17. Thus, the optical coupler power supply 17 outputs a voltage with a stable waveform. Therefore, the optocoupler power supply 17 can stably supply power to the optocoupler for a long time.

[0064] Please refer to Figure 2, the buffer module 12 also includes a seventh filter capacitor C316, and the buffer chip U304 also includes a VCC pin. The VCC pin is connected to the chip power supply 16, and the chip power supply 16 is used to power the buffer chip U304. One end of the seventh filter capacitor C316 is connected to the VCC pin, and the other end of the seventh filter capacitor C316 is grounded. The seventh filter capacitor C316 is used to filter the voltage output by the chip power supply 16. The setting of the seventh filter capacitor C316 filters the ripple of the voltage output by the chip power supply 16, effectively improving the flatness of the output voltage waveform. Furthermore, the chip power supply 16 can stably supply power to the buffer chip U304 for a long time.

[0065] Please refer to Figure 4 , the driving module 14 also includes a current detection unit 141. One end of the current detection unit 141 is connected to the U-phase output pin U and the V-phase output pin V, or one end of the current detection unit 141 is connected to the U-phase output pin U and the W-phase output pin W, or one end of the current detection unit 141 is connected to the V-phase output pin V and the W-phase output pin W. The other end of the current detection unit 141 is connected to the U, V, and W phase inputs of the power device (such as a motor) at the subsequent stage, and the current detection unit 141 is used to detect the magnitude of the output current of the driving module 14. Moreover, the current detection unit 141 can convert the collected output current and transmit it to the CPU module 11 for identification. The current detection unit converts the signal at both ends of the first current detection resistor R10 and the signal at both ends of the second current detection resistor R5 into two voltage signals respectively. The two voltage signals are then respectively passed through the optical coupling isolation amplifier, and after isolation and amplification, they can be transmitted to the CPU module 11. Based on the output current of the driver module 14, the CPU module 11 can control the change of the state of the U-phase upper arm bridge small current signal, the V-phase upper arm bridge small current signal, the W-phase upper arm bridge small current signal, the U-phase lower arm bridge small current signal, the V-phase lower arm bridge small current signal, and the W-phase lower arm bridge small current signal. Then the driver chip IPM1 can adjust the output current so that the subsequent power devices are protected. Figure 4 As shown, the current detection unit 141 includes a first current detection resistor R10 and a second current detection resistor R5.

[0066] Please refer to Figure 4, the driving module 14 also includes a temperature detection unit 142, and the driving chip IPM1 includes an NC pin and a VNC pin. One end of the temperature detection unit 142 is connected to the NC pin, and one end of the temperature detection unit 142 is connected to the VNC pin. The temperature detection unit 142 is used to detect the temperature of the driving chip IPM1, so that the driving chip IPM1 performs a fault alarm operation based on the temperature value of the driving chip IPM1. The temperature detection unit 142 is configured with a corresponding temperature detection resistor, and the temperature detection unit 142 can be connected to the input end of the CPU through an optocoupler isolation driving circuit. Therefore, the driving chip IPM1 can transmit the fault alarm signal to the CPU module 11 through the FO pin of the driving module 14.

[0067] Please refer to Figure 4 , the driving module 14 also includes a power current detection resistor R9, a delay resistor R8 and a delay capacitor C9. The driving chip IPM1 also includes a CIN pin, one end of the power current detection resistor R9 is connected to the negative pole of the external power supply 15, and one end of the power current detection resistor R9 is connected to the CIN pin. The power current detection resistor R9 is used to detect the output current of the external power supply 15, and the driving chip IPM1 performs short-circuit protection operation based on the current value of the output current of the external power supply 15. One end of the delay capacitor C9 is connected to the negative pole of the external power supply 15, and the other end of the delay capacitor C9 is the CIN pin. One end of the delay resistor R8 is connected to the C IN pin, and the other end of the delay resistor R8 is connected to the negative input pin. The delay resistor R8 and the delay capacitor C9 are used to delay the short-circuit protection operation of the driving chip IPM1. Moreover, the user can set the delay time by selecting delay capacitors and delay resistors with different parameters. In addition, the device parameters of the delay capacitor, the device parameters of the delay resistor, and the differences in PCB wiring will affect the response time of the short-circuit protection.

[0068] Please refer to Figure 4, the driving module 14 also includes an eighth filter capacitor C8, one end of which is connected to the positive electrode of the external power supply 15. The other end of the eighth filter capacitor C8 is connected to the negative electrode of the external power supply 15, and the eighth filter capacitor C8 can filter the voltage output by the external power supply 15. The driving module 14 also includes a VWFB pin, a VVFB pin, a VUFB pin, a VP1 pin, a VN1 pin, and a VNC pin. These pins are the power input and control pins of the output control power of the upper and lower arm bridges inside the driving module 14, thereby providing control power for the upper and lower arm bridge power control of the rear stage inside the driving module 14. The VWFB pin, VVFB pin, VUFB pin, VP1 pin, VN1 pin, and VNC pin of the driving module 14 generally use multiple groups of switching power supply outputs to provide control power, thereby realizing power isolation. At the same time, these pins can not only provide the control power input allowed by the driving module 14, but also the output of the power device can be fed back inside these pins. The control circuit 10 can realize the function of power supply output, and can also prevent the upper and lower arm bridge signals from being output simultaneously, so that the control circuit 10 can protect the subsequent power devices. The setting of the control circuit 10 simplifies the control logic restrictions of software engineers, reduces external risk factors, and can also protect its own driver chip IPM1.

[0069] The working principle of the utility model is as follows: when the control circuit 10 based on the series interlocking of the driving signal works, the CPU module 11 first outputs the enable signal, and then the buffer module 12 is turned on based on the enable signal. Subsequently, the CPU module 11 outputs the U-phase upper arm bridge small current signal, the V-phase upper arm bridge small current signal, the W-phase upper arm bridge small current signal, the U-phase lower arm bridge small current signal, the V-phase lower arm bridge small current signal, and the W-phase lower arm bridge small current signal.

[0070] Next, the buffer module 12 performs a current boosting operation on the U-phase upper arm bridge small current signal, and the buffer module 12 generates a U-phase upper arm bridge large current signal. The buffer module 12 is used to perform a current boosting operation on the V-phase upper arm bridge small current signal, and the buffer module 12 generates a V-phase upper arm bridge large current signal. The buffer module 12 performs a current boosting operation on the W-phase upper arm bridge small current signal, and the buffer module 12 generates a W-phase upper arm bridge large current signal. The buffer module 12 performs a current boosting operation on the U-phase lower arm bridge small current signal, and the buffer module 12 generates a U-phase lower arm bridge large current signal. The buffer module 12 performs a current boosting operation on the V-phase lower arm bridge small current signal, and the buffer module 12 generates a V-phase lower arm bridge large current signal. The buffer module 12 performs a current boosting operation on the W-phase lower arm bridge small current signal, and the buffer module 12 generates a W-phase lower arm bridge large current signal.

[0071] Subsequently, the series interlocking module 12 performs series interlocking on the U-phase upper arm bridge high current signal and the U-phase lower arm bridge high current signal, so that the series interlocking module 12 effectively outputs one of the signals. The series interlocking module 12 performs series interlocking on the V-phase upper arm bridge high current signal and the V-phase lower arm bridge high current signal, so that one of the signals is effectively output. The series interlocking module 12 performs series interlocking on the W-phase upper arm bridge high current signal and the W-phase lower arm bridge high current signal, so that the series interlocking module 12 effectively outputs one of the signals.

[0072] At the same time, the driving module 14 inputs the power supply power of the external power supply 15. The driving module 14 performs power conversion operation on the power supply power, and then the driving module 14 generates U-phase output power, V-phase output power, and W-phase output power. Based on the U-phase upper arm bridge large current signal or the U-phase lower arm bridge large current signal, the driving module 14 can adjust the power size of the U-phase output power. Based on the V-phase upper arm bridge large current signal or the V-phase lower arm bridge large current signal, the driving module 14 can adjust the power size of the V-phase output power. Based on the W-phase upper arm bridge large current signal or the W-phase lower arm bridge large current signal, the driving module 14 can adjust the power size of the W-phase output power. Therefore, the control circuit 10 based on the series interlocking of the drive signal can provide stable U-phase output power, V-phase output power, and W-phase output power for the power equipment (such as a motor) of the subsequent stage.

[0073] The utility model provides a control circuit based on serial interlocking of driving signals, and the control circuit based on serial interlocking of driving signals includes a buffer module, a serial interlocking module, and a driving module. The buffer module is turned on based on an enable signal, and the buffer module is used to perform a current-enhancing operation on a small current signal of an upper arm bridge of a U phase, and the buffer module generates a large current signal of an upper arm bridge of a U phase. The buffer module is used to perform a current-enhancing operation on a small current signal of an upper arm bridge of a V phase, and the buffer module generates a large current signal of an upper arm bridge of a V phase. The buffer module is used to perform a current-enhancing operation on a small current signal of an upper arm bridge of a W phase, and the buffer module generates a large current signal of an upper arm bridge of a W phase. The buffer module is used to perform a current-enhancing operation on a small current signal of a lower arm bridge of a U phase, and the buffer module generates a large current signal of a lower arm bridge of a U phase. The buffer module is used to perform a current-enhancing operation on a small current signal of a lower arm bridge of a V phase, and the buffer module generates a large current signal of a lower arm bridge of a V phase. The buffer module is used to perform a current-enhancing operation on a small current signal of a lower arm bridge of a W phase, and the buffer module generates a large current signal of a lower arm bridge of a W phase. Since the buffer module can be used to enhance the current of the signal, the user can select some CPU modules with low drive output current. The setting of the buffer module reduces the limitation of the CPU module and effectively improves the versatility and selectivity of the CPU module. In addition, before the buffer module is initially powered on, the buffer chip can be enabled and disconnected. After the CPU module is initialized and runs normally, the buffer chip can be enabled and turned on to avoid accidental operation of the buffer chip due to the uncertainty of the power-on pin.

[0074] The series interlocking module is used to interlock the U-phase upper arm bridge high current signal and the U-phase lower arm bridge high current signal in series, so as to effectively output one of the signals. The series interlocking module is used to interlock the V-phase upper arm bridge high current signal and the V-phase lower arm bridge high current signal in series, so as to effectively output one of the signals. The series interlocking module is used to interlock the W-phase upper arm bridge high current signal and the W-phase lower arm bridge high current signal in series, so as to effectively output one of the signals. In the prior art, if the program is wrong or the program is abnormal, the upper arm bridge signal and the lower arm bridge signal are output at the same time, thereby causing a short circuit to damage the subsequent power device. However, after the upper arm bridge signal and the lower arm bridge signal are input into the series interlocking module, the series interlocking module will only output one of the signals. Therefore, the control circuit based on the series interlocking of the drive signal has low fault tolerance requirements for the software program. It effectively solves the technical problem that the existing drive control method has high fault tolerance requirements for the control signal software program.

[0075] The driving module inputs the power supply power of the external power supply, and the driving module is used to perform power conversion operations on the power supply power, and the driving module generates U-phase output power, V-phase output power, and W-phase output power. Based on the U-phase upper arm bridge large current signal or the U-phase lower arm bridge large current signal, the driving module adjusts the power size of the U-phase output power. Based on the V-phase upper arm bridge large current signal or the V-phase lower arm bridge large current signal, the driving module adjusts the power size of the V-phase output power. Based on the W-phase upper arm bridge large current signal or the W-phase lower arm bridge large current signal, the driving module adjusts the power size of the W-phase output power. Therefore, the control circuit based on the series interlocking of the drive signal can provide stable U-phase output power, V-phase output power, and W-phase output power for the power equipment (such as a motor) of the subsequent stage. Furthermore, the control circuit based on the series interlocking of the drive signal can stably drive the power equipment of the subsequent stage.

[0076] In summary, although the present invention has been disclosed as above in terms of preferred embodiments, the above preferred embodiments are not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined in the claims.

Claims

1. A control circuit based on serial interlocking of drive signals, characterized in that: These include, CPU module, used for outputting enable signal, U-phase upper arm bridge small current signal, V-phase upper arm bridge small current signal, W-phase upper arm bridge small current signal, U-phase lower arm bridge small current signal, V-phase lower arm bridge small current signal, W-phase lower arm bridge small current signal; A buffer module, which is turned on based on the enable signal, and is used to perform a current boost operation on the U-phase upper arm bridge small current signal to generate a U-phase upper arm bridge large current signal; Used to perform a current boosting operation on the V-phase upper arm bridge small current signal to generate a V-phase upper arm bridge large current signal; used to perform a current boosting operation on the W-phase upper arm bridge small current signal to generate a W-phase upper arm bridge large current signal; used to perform a current boosting operation on the U-phase lower arm bridge small current signal to generate a U-phase lower arm bridge large current signal; Used to perform current boosting operation on the V-phase lower arm bridge small current signal to generate a V-phase lower arm bridge large current signal; Used to perform a current boosting operation on the W-phase lower arm bridge small current signal to generate a W-phase lower arm bridge large current signal; A series interlocking module, used for series interlocking the U-phase upper arm bridge high current signal and the U-phase lower arm bridge high current signal, so as to effectively output one of the signals; used for series interlocking the V-phase upper arm bridge high current signal and the V-phase lower arm bridge high current signal, so as to effectively output one of the signals; used for series interlocking the W-phase upper arm bridge high current signal and the W-phase lower arm bridge high current signal, so as to effectively output one of the signals; A driving module, which inputs power from an external power source, is used to perform power conversion operations on the power supply power to generate U-phase output power, and the driving module adjusts the power size of the U-phase output power based on the U-phase upper arm bridge large current signal or the U-phase lower arm bridge large current signal; is used to perform power conversion operations on the power supply power to generate V-phase output power, and the driving module adjusts the power size of the V-phase output power based on the V-phase upper arm bridge large current signal or the V-phase lower arm bridge large current signal; is used to perform power conversion operations on the power supply power to generate W-phase output power, and the driving module adjusts the power size of the W-phase output power based on the W-phase upper arm bridge large current signal or the W-phase lower arm bridge large current signal.

2. The control circuit based on serial interlocking of driving signals according to claim 1, characterized in that: The driving module includes a driving chip, which includes a positive input pin, a negative input pin, a U-phase output pin, a V-phase output pin and a W-phase output pin. The positive input pin is connected to the positive pole of the external power supply, the negative input pin is connected to the negative pole of the external power supply, the U-phase output pin is used to output the U-phase output power, the V-phase output pin is used to output the V-phase output power, and the W-phase output pin is used to output the W-phase output power.

3. The control circuit based on serial interlocking of driving signals according to claim 2, characterized in that: The buffer module includes a buffer chip, and the buffer chip includes an enable pin, a 1A4 pin, a 1A3 pin, a 1A2 pin, a 1A1 pin, a 2A1 pin, and a 2A2 pin; The enable pin is used to receive the enable signal, the 1A4 pin is used to receive the U-phase upper arm bridge small current signal, the 1A3 pin is used to receive the V-phase upper arm bridge small current signal, the 1A2 pin is used to receive the W-phase upper arm bridge small current signal, the 1A1 pin is used to receive the U-phase lower arm bridge small current signal, the 2A1 pin is used to receive the V-phase lower arm bridge small current signal, and the 2A2 pin is used to receive the W-phase lower arm bridge small current signal; The buffer chip is used to increase the current of the U-phase upper arm bridge small current signal, the buffer chip is used to increase the current of the V-phase upper arm bridge small current signal, the buffer chip is used to increase the current of the W-phase upper arm bridge small current signal, the buffer chip is used to increase the current of the U-phase lower arm bridge small current signal, the buffer chip is used to increase the current of the V-phase lower arm bridge small current signal, and the buffer chip is used to increase the current of the W-phase lower arm bridge small current signal; The series interlocking module includes a first U-phase optocoupler, a second U-phase optocoupler, a first V-phase optocoupler, a second V-phase optocoupler, a first W-phase optocoupler, and a second W-phase optocoupler; the buffer chip also includes a 1Y4 pin, a 1Y3 pin, a 1Y2 pin, a 1Y1 pin, a 2Y1 pin, and a 2Y2 pin; the 1Y4 pin is used to output the U-phase upper arm bridge high current signal, the 1Y3 pin is used to output the V-phase upper arm bridge high current signal, the 1Y2 pin is used to output the W-phase upper arm bridge high current signal, the 1Y1 pin is used to output the U-phase lower arm bridge high current signal, the 2Y1 pin is used to output the V-phase lower arm bridge high current signal, and the 2Y2 pin is used to output the W-phase lower arm bridge high current signal; The 1Y4 pin is connected to the negative input terminal of the first U-phase optocoupler and the positive input terminal of the second U-phase optocoupler, the 1Y3 pin is connected to the negative input terminal of the first V-phase optocoupler and the positive input terminal of the second V-phase optocoupler, the 1Y2 pin is connected to the negative input terminal of the first W-phase optocoupler and the positive input terminal of the second W-phase optocoupler, the 1Y1 pin is connected to the positive input terminal of the first U-phase optocoupler and the negative input terminal of the second U-phase optocoupler, the 2Y1 pin is connected to the positive input terminal of the first V-phase optocoupler and the negative input terminal of the second V-phase optocoupler, and the 2Y2 pin is connected to the positive input terminal of the first W-phase optocoupler and the negative input terminal of the second W-phase optocoupler; The driver chip also includes a Vup pin, a Vvp pin, a Vwp pin, a UN pin, a VN pin, and a WN pin; the Vup pin is used to receive the U-phase upper arm bridge high current signal, the Vvp pin is used to receive the V-phase upper arm bridge high current signal, the Vwp pin is used to receive the W-phase upper arm bridge high current signal, the UN pin is used to receive the U-phase lower arm bridge high current signal, the VN pin is used to receive the V-phase lower arm bridge high current signal, and the WN pin is used to receive the W-phase lower arm bridge high current signal; The output end of the first U-phase optocoupler is connected to the Vup pin, the output end of the first V-phase optocoupler is connected to the Vvp pin, the output end of the first W-phase optocoupler is connected to the Vwp pin, the output end of the second U-phase optocoupler is connected to the UN pin, the output end of the second V-phase optocoupler is connected to the VN pin, and the output end of the second W-phase optocoupler is connected to the WN pin.

4. The control circuit based on serial interlocking of driving signals according to claim 3, characterized in that: The buffer module also includes a first current limiting resistor, a second current limiting resistor, a third current limiting resistor, a fourth current limiting resistor, a fifth current limiting resistor, and a sixth current limiting resistor; One end of the first current limiting resistor is connected to the 1Y4 pin, and the other end of the first current limiting resistor is connected to the negative input end of the first U-phase optocoupler and the positive input end of the second U-phase optocoupler; One end of the second current limiting resistor is connected to the 1Y3 pin, and the other end of the second current limiting resistor is connected to the negative input end of the first V-phase optocoupler and the positive input end of the second V-phase optocoupler; One end of the third current limiting resistor is connected to the 1Y2 pin, and the other end of the third current limiting resistor is connected to the negative input end of the first W-phase optocoupler and the positive input end of the second W-phase optocoupler; One end of the fourth current limiting resistor is connected to the 1Y1 pin, and the other end of the fourth current limiting resistor is connected to the input positive end of the first U-phase optocoupler and the input negative end of the second U-phase optocoupler; one end of the fifth current limiting resistor is connected to the 2Y1 pin, and the other end of the fifth current limiting resistor is connected to the input positive end of the first V-phase optocoupler and the input negative end of the second V-phase optocoupler; one end of the sixth current limiting resistor is connected to the 2Y2 pin, and the other end of the sixth current limiting resistor is connected to the input positive end of the first W-phase optocoupler and the input negative end of the second W-phase optocoupler.

5. The control circuit based on serial interlocking of driving signals according to claim 3, characterized in that: The series interlocking module also includes a first filter capacitor, a second filter capacitor, a third filter capacitor, a fourth filter capacitor, a fifth filter capacitor, and a sixth filter capacitor; The positive power terminal of the first U-phase optocoupler, the positive power terminal of the second U-phase optocoupler, the positive power terminal of the first V-phase optocoupler, the positive power terminal of the second V-phase optocoupler, the positive power terminal of the first W-phase optocoupler, and the positive power terminal of the second W-phase optocoupler are all connected to the positive electrode of the optocoupler power supply, and the negative power terminal of the first U-phase optocoupler, the negative power terminal of the second U-phase optocoupler, the negative power terminal of the first V-phase optocoupler, the negative power terminal of the second V-phase optocoupler, the negative power terminal of the first W-phase optocoupler, and the negative power terminal of the second W-phase optocoupler are all connected to the negative electrode of the optocoupler power supply, and the optocoupler power supply is used to supply power to the first U-phase optocoupler, the second U-phase optocoupler, the first V-phase optocoupler, the second V-phase optocoupler, the first W-phase optocoupler, and the second W-phase optocoupler; The first filter capacitor is connected between the positive power terminal of the first U-phase optocoupler and the negative power terminal of the first U-phase optocoupler, the second filter capacitor is connected between the positive power terminal of the first V-phase optocoupler and the negative power terminal of the first V-phase optocoupler, the third filter capacitor is connected between the positive power terminal of the first W-phase optocoupler and the negative power terminal of the first W-phase optocoupler, the fourth filter capacitor is connected between the positive power terminal of the second U-phase optocoupler and the negative power terminal of the second U-phase optocoupler, the fifth filter capacitor is connected between the positive power terminal of the second V-phase optocoupler and the negative power terminal of the second V-phase optocoupler, and the sixth filter capacitor is connected between the positive power terminal of the second W-phase optocoupler and the negative power terminal of the second W-phase optocoupler.

6. The control circuit based on serial interlocking of driving signals according to claim 3, characterized in that: The buffer module also includes a seventh filter capacitor, and the buffer chip also includes a VCC pin, the VCC pin is connected to a chip power supply, and the chip power supply is used to power the buffer chip, one end of the seventh filter capacitor is connected to the VCC pin, and the other end of the seventh filter capacitor is grounded, and the seventh filter capacitor is used to filter the voltage output by the chip power supply.

7. The control circuit based on serial interlocking of driving signals according to claim 2, characterized in that: The driving module also includes a current detection unit, one end of which is connected to the U-phase output pin and the V-phase output pin, or to the U-phase output pin and the W-phase output pin, or to the V-phase output pin and the W-phase output pin, and the other end of the current detection unit is connected to the CPU module. The current detection unit is used to detect the magnitude of the output current of the driving module.

8. The control circuit based on serial interlocking of driving signals according to claim 2, characterized in that: The driving module also includes a temperature detection unit, the driving chip includes an NC pin and a VNC pin, one end of the temperature detection unit is connected to the NC pin, and one end of the temperature detection unit is connected to the VNC pin. The temperature detection unit is used to detect the temperature of the driving chip, so that the driving chip performs a fault alarm operation based on the temperature value of the driving chip.

9. The control circuit based on serial interlocking of driving signals according to claim 2, characterized in that: The driving module also includes a power supply current detection resistor, a delay resistor and a delay capacitor. The driving chip also includes a CIN pin. One end of the power supply current detection resistor is connected to the negative electrode of the external power supply. One end of the power supply current detection resistor is connected to the CIN pin. The power supply current detection resistor is used to detect the output current of the external power supply. The driving chip performs a short-circuit protection operation based on the current value of the output current of the external power supply. One end of the delay capacitor is connected to the negative electrode of the external power supply. The other end of the delay capacitor is the CIN pin. One end of the delay resistor is connected to the CIN pin. The other end of the delay resistor is connected to the negative input pin. The delay resistor and the delay capacitor are used for the short-circuit protection delay operation of the driving chip.

10. A circuit board, characterized in that: It includes the control circuit based on serial interlocking of drive signals as described in any one of claims 1-9.

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