Semiconductor device and integrated circuit device

Abstract

Some embodiments disclosed by the utility model provide a semiconductor device, which comprises a group of external connectors arranged in a plurality of rows and columns, and the external connectors comprise a plurality of receiving connectors and a plurality of transmitting connectors which are correspondingly configured to input information to the semiconductor device and output information from the semiconductor device. The receiving connector comprises a first receiving connector group of a plurality of first continuous receiving connectors and a second receiving connector group of a plurality of second continuous receiving connectors. The transmitting connector comprises a first transmitting connector group of a plurality of first continuous transmitting connectors and a second transmitting connector group of a plurality of second continuous transmitting connectors. The first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group are arranged to face each other in a row direction. The utility model also discloses an integrated circuit device.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to semiconductor devices, and more particularly, to external connectors in semiconductor devices. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various components (e.g., optoelectronic devices, electronic components, etc.). In order to adapt to the miniaturization scale of semiconductor devices (also referred to as dies in this specification), various technologies and applications involving more different components with different functions have been developed for wafer-level packaging. One method is to use an interconnect structure to couple multiple dies so as to accommodate higher processing capabilities in a smaller package. Utility Model Content

[0003] Some embodiments of the present disclosure provide a semiconductor device, which includes a group of external connectors, which are arranged in multiple rows and columns. This group of external connectors includes multiple receiving connectors and multiple transmitting connectors. The receiving connector and the transmitting connector are correspondingly configured to input information to the semiconductor device and output information from the semiconductor device. The receiving connector includes a first receiving connector group of multiple first continuous receiving connectors in the receiving connector and a second receiving connector group of multiple second continuous receiving connectors in the receiving connector. The transmitting connector includes a first transmitting connector group of multiple first continuous transmitting connectors in the transmitting connector and a second transmitting connector group of multiple second continuous transmitting connectors in the transmitting connector. The first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group are arranged relative to each other in a row direction along multiple rows.

[0004] In some embodiments, the plurality of rows include: a first row set having a first serial receiving connector arranged therein; a second row set having a second serial receiving connector arranged therein; a third row set having a first serial transmitting connector arranged therein; and a fourth row set having a second serial transmitting connector arranged therein; and the first row set to the fourth row set do not overlap with each other.

[0005] In some embodiments, the first serial receive connector corresponds to the first serial transmit connector; and the second serial receive connector corresponds to the second serial transmit connector.

[0006] In some embodiments, the second serial receive connector is continuous with the first serial receive connector; and the second serial transmit connector is continuous with the first serial transmit connector.

[0007] In some embodiments, this group of external connectors further includes multiple power external connectors; and the power external connectors include, in multiple rows, at least one row of power external connectors between each pair of adjacent groups among the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group; and two end rows of power external connectors in which the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group are arranged.

[0008] In some embodiments, this group of external connectors further includes: multiple power supply external connectors; and multiple grounding external connectors; the power supply external connectors include, in multiple columns, at least one entire column of power supply external connectors between each pair of adjacent groups among the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group; and two end columns of power supply external connectors with the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group arranged therebetween; and the grounding external connectors include, in multiple columns, at least one entire column of grounding external connectors between each pair of adjacent groups; and two end columns of grounding external connectors with the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group arranged therebetween.

[0009] In some embodiments, the second serial receive connector and the second serial transmit connector are disabled.

[0010] In some embodiments, the set of external connectors corresponds to a universal dielet interconnect express protocol; and each of the first receive connector set, the second receive connector set, the first transmit connector set, and the second transmit connector set includes exactly 32 consecutive main band data external connectors.

[0011] Some embodiments of the present disclosure provide an integrated circuit device, which includes a first die and a second die. Each of the first die and the second die includes a group of external connectors arranged in multiple rows and multiple columns. This group of external connectors includes multiple receiving connectors, multiple transmitting connectors, and multiple power external connectors. The receiving connector includes a first receiving connector group of multiple first receiving connectors in the receiving connector. The transmitting connector includes a first transmitting connector group of multiple first transmitting connectors in the transmitting connector. The power external connector includes, in multiple columns, a first complete row of power external connectors between the first receiving connector group and the first transmitting connector group. The first receiving connector of the first die is correspondingly coupled to the first transmitting connector of the second die. The first transmitting connector of the first die is correspondingly coupled to the first receiving connector of the second die.

[0012] In some embodiments, in the first chip, the receiving connector further includes a second receiving connector group of multiple second receiving connectors in the receiving connector; the transmitting connector further includes a second transmitting connector group of multiple second transmitting connectors in the transmitting connector, the first receiving connector group is arranged between the second receiving connector group and the first transmitting connector group along a row direction of multiple rows; the first transmitting connector group is arranged between the second transmitting connector group and the first receiving connector group along the row direction; the power external connector further includes: a second complete row of power external connectors between the first receiving connector group and the second receiving connector group; a third complete row of power external connectors between the first transmitting connector group and the second transmitting connector group; and two complete end rows of power external connectors with the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group arranged in between. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] When reading the accompanying drawings, the various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that the various features are not necessarily drawn to scale. In fact, the size of the various features may be arbitrarily enlarged or reduced to make a clear description.

[0014] Figure 1 is a block diagram of an integrated circuit (IC) device according to some embodiments.

[0015] Figure 2A as well as Figure 2B is an enlarged schematic plan view showing an arrangement of various external connectors for input / output (I / O) terminals of a semiconductor device according to some embodiments.

[0016] Figure 2C as well as Figure 2D is an enlarged schematic plan view of various portions of one or more interconnect structures according to some embodiments.

[0017] Figure 3A is a schematic plan view of an I / O terminal of a semiconductor device according to some embodiments.

[0018] Figure 3B According to some embodiments, Figure 3A Schematic plan view of an I / O terminal having reduced bandwidth.

[0019] Figure 3C According to some embodiments, Figure 3A A bump map of an I / O terminal in FIG. 1 is a schematic plan view of a bump map of an I / O terminal that produces a bump map of an I / O terminal with reduced bandwidth.

[0020] 4A to 4D is a schematic plan view of various integrated circuit devices according to some embodiments.

[0021] Figure 5A as well as Figure 5B is a schematic diagram of various bump mappings for I / O terminals of a semiconductor device according to some embodiments.

[0022] Figure 6 is a schematic cross-sectional view of a portion of a semiconductor device according to some embodiments.

[0023] FIG. 7A to FIG. 7G is a schematic cross-sectional view of an integrated circuit device at various stages in a manufacturing process according to some embodiments.

[0024] Figure 8 is a flow chart of a method according to some embodiments.

[0025] Fig. 9 is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0026] Fig.10 is a block diagram of an integrated circuit device manufacturing system and an integrated circuit manufacturing flow associated therewith according to some embodiments.

[0027] The reference numerals are described as follows:

[0028] 100: Integrated circuit devices

[0029] 110: Grain

[0030] 111: Functional Circuit

[0031] 112: I / O terminal

[0032] 113: I / O terminal

[0033] 114: Edge

[0034] 120: Grain

[0035] 121: Functional Circuit

[0036] 122: I / O terminal

[0037] 124: Edge

[0038] 130: Grain

[0039] 131: Functional Circuit

[0040] 133: I / O terminal

[0041] 142: Interconnection Structure

[0042] 143: Interconnection Structure

[0043] 200A: I / O terminal

[0044] 200B: I / O terminal

[0045] 200C: Interconnection Structure

[0046] 200D: Interconnection structure

[0047] 205: External connector

[0048] 210: Semiconductor devices

[0049] 214: Edge

[0050] 251: OK

[0051] 251C: Center Row

[0052] 252: Column

[0053] 253: OK

[0054] 253C: Center Row

[0055] 254: Column

[0056] 259: OK

[0057] 260: OK

[0058] 261: External connector

[0059] 262: External connector

[0060] 263: External connector

[0061] 264: External connector

[0062] 265: External connector

[0063] 266: External connector

[0064] 271: Channel

[0065] 272: Channel

[0066] 273: Channel

[0067] 274: Channel

[0068] 275: Channel

[0069] 276: Channel

[0070] 277: Part 1

[0071] 278: Part 2

[0072] 281: Channel

[0073] 282: Channel

[0074] 283: Channel

[0075] 291: Channel

[0076] 292: Channel

[0077] 293: Channel

[0078] 300A: I / O terminal

[0079] 300B: I / O terminal

[0080] 300C: I / O terminal

[0081] 310: Semiconductor devices

[0082] 314: Edge

[0083] 321: The first column set

[0084] 322: Second column set

[0085] 331: The third column set

[0086] 332: The fourth column set

[0087] 341: Column

[0088] 342: Column

[0089] 343: Column

[0090] 344: Column

[0091] 345: Column

[0092] 350C: Center Row

[0093] 362: Arrow

[0094] 363: Arrow

[0095] 381: Power external connector column

[0096] 383: Power external connector column

[0097] 385: Power external connector column

[0098] 400A: Integrated Circuit Devices

[0099] 400B: Integrated Circuit Devices

[0100] 400C: Integrated Circuit Devices

[0101] 410: I / O terminal

[0102] 411: Channel

[0103] 412: Channel

[0104] 414: Edge

[0105] 420: I / O terminal

[0106] 421: Channel

[0107] 422: Channel

[0108] 424: Edge

[0109] 430: I / O terminal

[0110] 434: Channel

[0111] 436: Channel

[0112] 440: I / O terminal

[0113] 443: Channel

[0114] 460: I / O terminal

[0115] 463: Channel

[0116] 467: Channel

[0117] 470: I / O terminal

[0118] 476: Channel

[0119] 500A: Bump Mapping

[0120] 500B: Bump Mapping

[0121] 521, 521': Column

[0122] 522,522': Column

[0123] 531, 531': Column

[0124] 532,532': Column

[0125] 541, 541': Column

[0126] 542,542': Column

[0127] 543,543': Column

[0128] 544,544': Column

[0129] 545, 545': Column

[0130] 561: Pattern

[0131] 562: Pattern

[0132] 571: Pattern

[0133] 572: Pattern

[0134] 581: Column

[0135] 582: Column

[0136] 583: Column

[0137] 584: Column

[0138] 600: Semiconductor devices

[0139] 610: Substrate

[0140] 611: Transistor

[0141] 612: Source / drain region

[0142] 613: Source / drain region

[0143] 614: Gate dielectric layer

[0144] 615: Gate electrode

[0145] 616: Spacer

[0146] 617: Metal to device contact structure

[0147] 618: Guide hole

[0148] 619: Guide hole

[0149] 620: Redistribution Layer

[0150] 629: Interlayer Dielectric

[0151] 654: Conductive pattern

[0152] 655: Guide hole

[0153] 656: Contact pad

[0154] 660: Under Bump Metal Structure

[0155] 662: Bump

[0156] 700: Integrated circuit devices

[0157] 700A, 700B, 700C, 700D, 700E, 700F, 700G: Structure

[0158] 702: First carrier substrate

[0159] 710: First redistribution layer

[0160] 711: Dielectric layer

[0161] 712: Guide hole

[0162] 713: Conductive traces

[0163] 715: Top dielectric layer

[0164] 716: Conductive pad

[0165] 717: Conductive pad

[0166] 720: Through hole

[0167] 730: Interconnection Structure

[0168] 731: Small pitch redistribution layer

[0169] 732: Interconnect vias

[0170] 733: Connector

[0171] 734: Welding materials

[0172] 736: Bottom filling material

[0173] 738: First packaging material

[0174] 740: Second redistribution layer

[0175] 746: Conductive pad

[0176] 748: Solder Bump

[0177] 750: Intermediate substrate

[0178] 752: Second carrier substrate

[0179] 761: First set of external connectors

[0180] 762: Second set of external connectors

[0181] 763: External connector

[0182] 764: External connector

[0183] 771: I / O terminal

[0184] 772: I / O terminal

[0185] 776: Bottom filling material

[0186] 778: Second packaging material

[0187] 780: Solder Bump

[0188] 800: Methods

[0189] 805: Operation

[0190] 815: Operation

[0191] 825: Operation

[0192] 900: Electronic Design Automation System

[0193] 902: Processor

[0194] 904: Storage Media

[0195] 906: Computer Program Code

[0196] 907: Database

[0197] 908: Bus

[0198] 910: I / O interface

[0199] 912: Network interface

[0200] 914: Network

[0201] 942: User Interface

[0202] 1000: Integrated Circuit Manufacturing System

[0203] 1020: Design Company

[0204] 1022: Integrated Circuit Design Layout

[0205] 1030: Photomask Company

[0206] 1032: Data Preparation

[0207] 1044: Mask Manufacturing

[0208] 1045: Photomask

[0209] 1050: Integrated Circuit Manufacturing Plant

[0210] 1052: Manufacturing tools

[0211] 1053: Semiconductor wafer

[0212] 1060: Integrated circuit devices

[0213] C: row direction

[0214] R: Column direction DETAILED DESCRIPTION

[0215] The following disclosure provides many different embodiments or examples to implement different features of the subject matter provided. Specific examples of various components, materials, values, steps, operations, materials, arrangements, etc. are described below to simplify the present disclosure. Of course, the examples are for illustration purposes only and are not intended to be limited thereto. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, if the specification describes that a first feature is formed above or on a second feature, it means that an embodiment in which the first feature is in direct contact with the second feature may be included, and an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature is not in direct contact with the second feature may also be included. In addition, in various examples, the present disclosure may use repeated reference symbols and / or letters. Such repetition is for the purpose of simplification and clarity and does not represent the association between the various embodiments and / or configurations discussed.

[0216] In addition, spatially relative terms used in this specification, such as "below", "below", "lower", "above", "higher", etc., are used to facilitate the description of the relationship between one element or feature and another element or features in the drawings. In addition to the orientation shown in the drawings, these spatially relative terms are intended to include different orientations of the device in use or operation. The device can be turned to different orientations (rotated 90 degrees or other orientations), and the spatially relative terms used herein can also be interpreted in the same way. Depending on the context, source / drain can refer to the source or drain, individually or collectively.

[0217] In a semiconductor package (also referred to as an integrated circuit device in one or more embodiments), two adjacently placed dies are coupled to each other via an interconnect structure. Each die has an I / O terminal (also referred to as an I / O module or an I / O interface). The I / O terminal includes a plurality of external connectors, and the die is coupled to the interconnect structure via these external connectors. The external connector includes a receiving connector and a transmitting connector, which are used to receive information from other dies and send information to others via the interconnect structure, respectively.

[0218] In some embodiments, in an I / O end of a semiconductor device or die, the receiving connectors are grouped into a plurality of receiving connector groups, and the transmitting connectors are grouped into a corresponding plurality of transmitting connector groups. Thus, in at least some embodiments, the I / O end can be reconfigured by enabling or disabling some receiving connector groups and corresponding transmitting connector groups to have a desired bandwidth that matches the bandwidth of the I / O end of other dies. In at least some embodiments, a new arrangement of external connectors (also referred to as a bump map in one or more embodiments) can be generated for the I / O end by simply copying the desired number of receiving connector groups and corresponding transmitting connector groups of an existing bump map into a new bump map. In some embodiments, grouping the receiving connectors and transmitting connectors into corresponding groups improves interoperability between I / O ends of different form factors, packages, or bandwidths, which is superior to other methods. Some embodiments achieve one or more further advantages over other methods, including but not limited to better routing, better signal integrity, more uniform placement of external connectors, better line density distribution, better clock placement, etc.

[0219] Figure 1 is a block diagram of an integrated circuit device 100 according to some embodiments.

[0220] Integrated circuit device 100 includes die 110, 120, 130. In some embodiments, die 110, 120, 130 are also referred to as chips, cores, etc. Each die includes a functional circuit and one or more I / O terminals. For example, die 110 includes functional circuit 111 and I / O terminals 112, 113. Die 120 includes functional circuit 121 and I / O terminal 122. I / O terminals 112, 122 are arranged along facing edges 114, 124 of die 110, 120 and are coupled to each other by an interconnect structure schematically represented by 142. Die 130 includes functional circuit 131 and I / O terminal 133. I / O terminals 113, 133 are arranged along facing edges (not given symbols) of die 110, 130 and are coupled to each other by another interconnect structure 143. The number of dies and / or the number and / or physical arrangement of I / O terminals in each die described are examples. Other configurations are within the scope of various embodiments. For example, in at least some embodiments, die 110 includes another I / O terminal (not shown) along the same edge 114 as I / O terminal 112 and is configured to couple to other dies (not shown).

[0221] Each of the functional circuits 111, 121, 131 includes a plurality of circuit elements electrically coupled to each other to perform one or more operations and / or functions of the corresponding die 110, 120, 130. Examples of circuit elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, P-channel metal oxide semiconductors (PMOS), N-channel metal oxide semiconductors (NMOS), bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, P-channel and / or N-channel field effect transistors (PFETs / NFETs), fin field effect transistors (FinFET), planar MOS transistors with convex source / drain, nanosheet FETs, nanowire FETs, etc. In some embodiments, the dies 110, 120, 130 are different or similar chips having corresponding operations and / or functions performed by corresponding functional circuits 111, 121, 131. Examples of dies or cores include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), accelerated processing units (APUs), memory controllers, motherboard controllers, bridge devices, I / O devices for communicating with other integrated circuit devices, etc.

[0222] The I / O terminals 112, 122, 113, 133 are configured to exchange information in the die 110, 120, 130. A pair of I / O terminals coupled to each other corresponds to the same protocol. For example, the I / O terminal pair 112, 122 corresponds to the same first protocol, and the I / O terminal pair 113, 133 corresponds to the same second protocol, and the second protocol may be the same as or different from the first protocol. In at least some embodiments, the I / O terminal pair 112, 122 and / or the I / O terminal pair 113, 133 correspond to the Universal Chiplet Interconnect express (UCIe) protocol. Other protocols for interconnecting multiple chips are within the scope of various embodiments. Examples of interconnect structures 142, 143 include, but are not limited to, local silicon interconnects (LSIs, also known as silicon bridges), interposers, fan-out organic interposers, redistribution layers (RDLs), etc.

[0223] Figure 2A is an enlarged schematic plan view showing an example external connector arrangement for I / O terminal 200A according to some embodiments.

[0224] In some embodiments, I / O terminal 200A corresponds to any one of I / O terminals 112, 122, 113, 133. For example, I / O terminal 200A corresponds to I / O terminal 112 and is arranged along edge 214 of semiconductor device 210, semiconductor device 210 corresponds to die 110, and edge 214 corresponds to edge 114.

[0225] I / O terminal 200A includes a set of external connectors 205. For simplicity, in one or more embodiments of the present specification, the external connectors are sometimes referred to as bumps. Examples of external connectors include, but are not limited to, solder balls, ball grid array (BGA) connectors, micro bumps (e.g., μ bumps), controlled collapse chip connection (controlledcollapase chip connection, C4) bumps, etc. Other configurations of the external connectors are within the scope of various embodiments.

[0226] In the I / O terminal 200A, the external connectors 205 are arranged in a non-staggered manner in a plurality of rows 251 and a plurality of columns 252. In such a non-staggered arrangement, each row 251 includes the same number of external connectors 205, and each column 252 includes the same number of external connectors 205. The rows 251 extend along a row direction C, and the columns 252 extend along a column direction R. The column direction R and the columns 252 extend along an edge 214 of the semiconductor device 210. The row direction C and the rows 251 extend transversely to the edge 214. In at least some embodiments, the columns 252 are parallel to the edge 214 and / or the rows 251 are perpendicular to the edge 214. The rows 251 include a center row or more center rows located at the center of the I / O terminal 200A along the column direction R. In Figure 2A In an exemplary configuration, I / O end 200A includes an even number of rows 251, which includes an even number of (e.g., two) center rows 251C. In at least some embodiments where I / O end 200A includes an odd number of rows 251, there is an odd number of center rows. The number of external connectors 205, rows 251, columns 252, and / or center rows 251C described are examples. Other configurations are within the scope of various embodiments.

[0227] Figure 2B is an enlarged schematic plan view showing another exemplary arrangement of an external connector for an I / O terminal 200B according to some embodiments. Figure 2A as well as Figure 2B The corresponding components in .

[0228] The difference between the I / O terminal 200B and the I / O terminal 200A is that the external connectors 205 in the I / O terminal 200B are arranged in a staggered manner. Specifically, the external connectors 205 in the I / O terminal 200B are arranged in a plurality of rows 253 along the row direction C, and in a plurality of columns 254 along the column direction R. In such a staggered arrangement, the odd rows and the even rows in the rows 253 include different numbers of external connectors 205, and the odd columns and the even columns in the columns 254 include different numbers of external connectors 205. The columns 254 extend along the edge 214 of the semiconductor device 210, and the rows 253 extend laterally to the edge 214. In at least some embodiments, the columns 254 are parallel to the edge 214 and / or the rows 253 are perpendicular to the edge 214. The rows 253 include a center row or more center rows located at the center of the I / O terminal 200B along the column direction R. Figure 2BIn an exemplary configuration, I / O end 200B includes an odd number of rows 253, which includes an odd number of (e.g., three) center rows 253C. In at least some embodiments where I / O end 200B includes an even number of rows 253, there is an even number of center rows. The number of external connectors 205, rows 253, columns 254, and / or center rows 253C described are examples. Other configurations are within the scope of various embodiments.

[0229] The I / O end is configured with an external connector (e.g., I / O end 200A or I / O end 200B) to transmit and receive different data and / or signals, including but not limited to main band data, side band data, power, clock, track, valid, etc. The I / O end of one die is coupled to the corresponding external connector of the I / O end of other die with an external connector through corresponding conductive traces (also called lanes), and the conductive traces are provided by the interconnect structure described herein. For example, main band data is transmitted and / or received via a main band data channel, and side band data is transmitted and / or received via a side band data channel, etc. Reference Figure 2C as well as Figure 2D Describes several channel configurations.

[0230] The main band data channel is configured to provide a main data path between coupled dies. The number of main band data channels included in the main data path corresponds to the bandwidth of the connection between the dies. For example, an X64 connection between two dies corresponds to 64 main band data channels from one dies to other dies, for a total of 128 main band data channels. In this X64 example, the I / O end of each die includes 64 main band data external connectors, which are configured to transmit the main band data to other dies, and the 64 main band data external connectors are configured to receive the main band data from other dies. For simplicity, the main band data external connector configured to transmit the main band data is referred to as a transmitting connector in this specification, and the main band data external connector configured to receive the main band data is referred to as a receiving connector in this specification. The 64 transmitting connectors of one die are coupled to the 64 receiving connectors of other dies by means of the corresponding 64 main band data channels, and vice versa. In an example of an X32 connection between two die, the I / O end of each die includes 32 transmit connectors and 32 receive connectors, and the 32 transmit connectors of one die are coupled to the 32 receive connectors of the other die by corresponding 32 main band data channels, and vice versa. In an example of an X16 connection between two die, the I / O end of each die includes 16 transmit connectors and 16 receive connectors, and the 16 transmit connectors of one die are coupled to the 16 receive connectors of the other die by corresponding 16 main band data channels, and vice versa. The described X64, X62, and X16 connections are examples. Other connections with different bandwidths and / or different numbers of main band data channels are within the scope of various embodiments.

[0231] In some embodiments, the sideband data channel is configured for parameter exchange, link training, link management, debugging, compliance, etc. The power channel is configured for providing power supply and / or ground voltage, etc. The clock channel is configured for clock signal distribution, synchronization, etc. The tracking and valid channels are correspondingly configured for tracking and valid signals. In some embodiments, one or more external connectors of the I / O terminal are redundant external connectors, which are configured to establish one or more redundant channels for repairing one or more defective main band data channels, sideband data channels, etc. when necessary. In some embodiments, one or more external connectors described for sideband data, power, clock, track, valid, redundancy / repair, etc. are omitted in the I / O terminal.

[0232] Figure 2C is an enlarged schematic plan view of a portion of an interconnect structure 200C, according to some embodiments.

[0233] The interconnect structure 200C is configured to couple a first I / O terminal of a first semiconductor device to a second I / O terminal of a second semiconductor device. The interconnect structure 200C includes a first set of external connectors and a second set of external connectors, wherein the first set of external connectors is a mirror image of the set of external connectors of the first I / O terminal of the first semiconductor device, and the second set of external connectors is a mirror image of the set of external connectors of the second I / O terminal of the second semiconductor device. Figure 2C In the exemplary configuration of FIG. 1 , a portion of a first set of external connectors of an interconnect structure 200C is shown, which is configured to couple to an I / O terminal 200A. Specifically, the interconnect structure 200C includes a plurality of external connectors arranged in a plurality of rows and columns in a mirror image of the rows 251 and columns 252 of the I / O terminal 200A. For example, Figure 2C The interconnect structure 200C is shown with two adjacent rows 259, 260 of external connectors corresponding to two adjacent rows in the row 251 of the I / O terminals 200A.

[0234] The interconnect structure 200C further includes a plurality of metal layers (the metal layers include a plurality of conductive traces or channels), Figure 2C 2 is coupled to a corresponding external connector of a second set of external connectors (not shown), where the second set of external connectors will be coupled to other dies. For example, the interconnect structure 200C includes channels 271 to 276, which are correspondingly coupled to the external connectors 261 to 266 in the row 260. The channels 271 to 276 all extend across the adjacent edge 214 of the semiconductor device 210 and further toward another semiconductor device. However, for simplicity, the channels 271 to 276 are not shown in FIG. Figure 2C The channels 272 , 274 , 276 are illustrated in FIG. 2 to indicate that they extend across the adjacent edge 214 .

[0235] Each channel includes a first portion along the column direction R and a second portion along the row direction C. For example, channel 276 includes a first portion 277 along the column direction R and a second portion 278 along the row direction C. The first portion and the second portion of the channel are not necessarily formed in the same metal layer in the interconnect structure 200C. In some examples, the first portion 277 includes one or more conductive patterns and / or one or more vias in one or more metal layers to couple the external connector 266 to the start of the second portion 278. The second portion (e.g., 278) of each channel is significantly longer than the corresponding first portion (e.g., 277) and defines the effective length of the channel, and the signal travels across the channel between the coupled semiconductor devices (or dies). In some embodiments, the second portions of all main band data channels are configured to have the same or substantially the same length to ensure uniform signal delay across all main band data channels. For simplicity, unless otherwise specified in this specification, when describing a channel, the second portion of the channel (along the row direction C) is described.

[0236] exist Figure 2C In an exemplary configuration of , channels 271, 273, 275 (i.e., the second portion thereof) are formed in the first metal layer of the interconnect structure 200C, and channels 272, 274, 276 (i.e., the second portion thereof) are formed in the second metal layer of the interconnect structure 200C. The second metal layer is below the first metal layer. The number of channels that can be formed in each metal layer of the interconnect structure 200C depends on various design rules, including but not limited to via enclosures, via diameters, metal widths, metal pitches, bump pitches between adjacent rows of external connectors, etc. Given the number of channels to be formed to couple the external connectors in a row to another semiconductor device and the number of channels that can be formed in each metal layer, it may be possible to determine the number of metal layers required to form the channels in the interconnect structure 200C. In some embodiments, by forming the required number of channels for the I / O terminals in a dispersed manner across all rows, it may be possible to reduce the number of metal layers required to form the channels in the corresponding interconnect structure, thereby reducing manufacturing costs and / or manufacturing time.

[0237] Figure 2D is an enlarged schematic plan view of a portion of an interconnect structure 200D according to some embodiments. In some embodiments, the interconnect structure 200D is the same as the interconnect structure 200C, that is, Figure 2C as well as Figure 2D Portions of the same interconnect structure are depicted.

[0238] exist Figure 2DIn an exemplary configuration of , the interconnect structure 200D includes channels 281, 282, 283 in one metal layer and channels 291, 292, 293 in another metal layer. Channels 281, 283, 291, 293 are primary data channels, while channels 282, 292 are power channels and are wider than primary data channels 281, 283, 291, 293. Each of the power channels 282, 292 is configured to carry a power supply voltage or a ground voltage. In some embodiments, the power channels 282, 292 are configured to carry the same voltage, for example, two power channels 282, 292 are configured to carry a power supply voltage, or two power channels 282, 292 are configured to carry a ground voltage. In at least some embodiments, the power channels 282 , 292 are configured to carry different voltages, for example, one of the power channels 282 , 292 is configured to carry a ground voltage while the other of the power channels 282 , 292 is configured to carry a power supply voltage.

[0239] The power channel 282 is arranged between the main strip data channels 281, 283 and overlaps the main strip data channel 293 in the thickness direction of the interconnect structure 200D. The power channel 292 is arranged between the main strip data channels 291, 293 and overlaps the main strip data channel 281 in the thickness direction. In some embodiments, the arrangement of the power channels between adjacent main strip data channels in the same metal layer and / or the overlap with the main strip data channels in another metal layer provides a shielding effect, which reduces crosstalk between adjacent main strip data channels and improves signal integrity.

[0240] Figure 3A is a schematic plan view of an I / O terminal 300A of a semiconductor device according to some embodiments.

[0241] In some embodiments, I / O terminal 300A corresponds to any of I / O terminals 112, 122, 113, 133. For example, I / O terminal 300A corresponds to I / O terminal 112 and is arranged along edge 314 of semiconductor device 310, semiconductor device 310 corresponds to die 110, and edge 314 corresponds to edge 114. I / O terminal 300A includes a set of external connectors for main band data, and for one or more of side band data, power, clock, track, valid, redundancy / repair, etc., as described in this specification. In some embodiments, I / O terminal 300A is arranged with external connectors in a non-staggered manner as described with respect to I / O terminal 200A. In one or more embodiments, I / O terminal 300A is arranged with external connectors in a staggered manner as described with respect to I / O terminal 200B.

[0242] A set of external connectors of the I / O terminal 300A includes a plurality of receiving connectors and a plurality of transmitting connectors, which are correspondingly configured to input information to and output information from the semiconductor device 310. The receiving connectors and the transmitting connectors of the I / O terminal 300A are grouped into a plurality of groups. Figure 3A In the exemplary configuration of , the multiple receiving connectors of the I / O terminal 300A include a first receiving connector group Rx_1 and a second receiving connector group Rx_2, and the multiple transmitting connectors of the I / O terminal 300A include a first transmitting connector group Tx_1 and a second transmitting connector group Tx_2. The first receiving connector group Rx_1, the second receiving connector group Rx_2, the first transmitting connector group Tx_1, and the second transmitting connector group Tx_2 are arranged relative to each other along the row direction C.

[0243] The first receive connector group Rx_1 includes a first receive connector, and the second receive connector group Rx_2 includes a second receive connector. For example, the first receive connector group Rx_1 includes k receive connectors, and the second receive connector group Rx_2 includes l receive connectors, where k+l is the total number of all receive connectors of the I / O terminal 300A. The k receive connectors in the first receive connector group Rx_1 correspond to the first k bits of data to be received by the semiconductor device 310, and the l receive connectors in the second receive connector group Rx_2 correspond to the subsequent l bits of data to be received by the semiconductor device 310. For example, the k receive connectors in the first receive connector group Rx_1 correspond to bits 0 to (k-1), and the l receive connectors in the second receive connector group Rx_2 correspond to bits k to (k+l-1). In other words, the first receive connector group Rx_1 includes k consecutive receive connectors, and the second receive connector group Rx_2 includes l consecutive receive connectors, which are consecutive to the k consecutive receive connectors in the first receive connector group Rx_1. In some embodiments, k is equal to l, that is, the first receiving connector group Rx_1 and the second receiving connector group Rx_2 include the same number of receiving connectors. In at least some embodiments, k is different from l. In some embodiments, for an X64 connection between the semiconductor device 310 and another semiconductor device, k=l=32. For an X32 connection between the semiconductor device 310 and another semiconductor device, k=l=16. For an X16 connection between the semiconductor device 310 and another semiconductor device, k=l=8. The number of receiving connector groups described and / or the number of receiving connectors per receiving connector group are examples. Other configurations are within the scope of various embodiments.

[0244] The first transmit connector group Tx_1 includes a first transmit connector, which corresponds to the first receive connector in the first receive connector group Rx_1, and the second transmit connector group Tx_2 includes a second transmit connector, which corresponds to the second receive connector in the second receive connector group Rx_2. For example, when the first receive connector group Rx_1 includes k receive connectors and the second receive connector group Rx_2 includes l receive connectors, the first transmit connector group Tx_1 includes k transmit connectors and the second transmit connector group Tx_2 includes l transmit connectors. The k transmit connectors in the first transmit connector group Tx_1 correspond to the first k bits of data to be transmitted by the semiconductor device 310, and the l transmit connectors in the second transmit connector group Tx_2 correspond to the subsequent l bits of data to be transmitted by the semiconductor device 310. For example, the k transmit connectors in the first transmit connector group Tx_1 correspond to bits 0 to (k-1), and the l transmit connectors in the second transmit connector group Tx_2 correspond to bits k to (k+l-1). In other words, the first transmission connector group Tx_1 includes k consecutive transmission connectors, and the second transmission connector group Tx_2 includes l consecutive transmission connectors, which are consecutive to the k consecutive receiving connectors in the first transmission connector group Tx_1. In some embodiments, k is equal to l, that is, the first transmission connector group Tx_1 and the second transmission connector group Tx_2 include the same number of transmission connectors. In at least some embodiments, k is different from l. In some embodiments, for the X64 connection between the semiconductor device 310 and another semiconductor device, k=l=32. For the X32 connection between the semiconductor device 310 and another semiconductor device, k=l=16. For the X16 connection between the semiconductor device 310 and another semiconductor device, k=l=8. The number of transmission connector groups described and / or the number of transmission connectors per transmission connector group are examples. Other configurations are within the scope of various embodiments.

[0245] The multiple rows of external connectors of the I / O terminal 300A include a first row set 321 in which the receiving connectors of the first receiving connector group Rx_1 are arranged, a second row set 322 in which the receiving connectors of the second receiving connector group Rx_2 are arranged, a third row set 331 in which the transmitting connectors of the first transmitting connector group Tx_1 are arranged, and a fourth row set 332 in which the transmitting connectors of the second transmitting connector group Tx_2 are arranged. The first row set 321, the second row set 322, the third row set 331, and the fourth row set 332 are non-overlapping, that is, they do not overlap with each other.

[0246] The multiple rows of external connectors of the I / O terminal 300A further include one or more rows of external connectors between each pair of adjacent groups of the first receiving connector group Rx_1, the second receiving connector group Rx_2, the first transmitting connector group Tx_1, and the second transmitting connector group Tx_2. Specifically, the row set 321 including the first receiving connector group Rx_1 is separated from the row set 322 including the second receiving connector group Rx_2 by one or more rows of external connectors (schematically indicated by 344). The row set 321 including the first receiving connector group Rx_1 is separated from the row set 331 including the first transmitting connector group Tx_1 by one or more rows of external connectors (schematically indicated by 343). The row set 331 including the first transmitting connector group Tx_1 is separated from the row set 332 including the second transmitting connector group Tx_2 by one or more rows of external connectors (schematically indicated by 342).

[0247] The multiple rows of external connectors of the I / O terminal 300A further include one or more first end rows (schematically labeled as 341) of the external connector and one or more second end rows (schematically labeled as 345) of the external connector, and the second end rows are adjacent to the edge 314 of the semiconductor device 310. The second receiving connector set Rx_2, the first receiving connector set Rx_1, the first transmitting connector set Tx_1, and the second transmitting connector set Tx_2 are sequentially arranged along the row direction C between the one or more first end rows 341 and the one or more second end rows 345.

[0248] In some embodiments, in addition to the receiving connector of the first receiving connector group Rx_1, the column set 321 further includes one or more external connectors, which are configured for one or more functions other than transmitting and receiving main band data. As described in this specification, these other functions include but are not limited to sideband data, power, clock, tracking, validity, etc. The external connectors configured for functions other than sending and receiving main band data are referred to as other function external connectors in this specification. In some embodiments, the column set 321 includes one or more other function external connectors in one or more center rows 350C. In at least some embodiments, one or more center rows 350C correspond to center row 251C or center row 253C. For example, the column set 321 includes one or more external connectors (hereinafter referred to as clock external connectors) for clock distribution in one or more center rows 350C.

[0249] In some embodiments, in addition to the receiving connector of the second receiving connector group Rx_2, the column set 322 further includes one or more other functional external connectors. In some embodiments, the column set 322 includes one or more other functional external connectors in one or more center rows 350C. For example, the column set 322 includes one or more external connectors (hereinafter referred to as power external connectors) for power distribution in one or more center rows 350C. The power external connector configured to be coupled to the power supply voltage is called the power external connector. The power external connector configured to be coupled to the ground voltage is called the ground external connector. In at least some embodiments, the power external connector in the column set 322 includes only the power supply external connector, or, only the ground external connector, or, includes a combination of the power external connector and the ground external connector.

[0250] In some embodiments, in addition to the transmission connectors of the first transmission connector group Tx_1, the column set 331 further includes one or more other functional external connectors. In some embodiments, the column set 331 includes one or more other functional external connectors in one or more center rows 350C. For example, the column set 331 includes one or more clock external connectors in one or more center rows 350C.

[0251] In some embodiments, in addition to the transmission connectors of the second transmission connector group Tx_2, the column set 332 further includes one or more other functional external connectors. In some embodiments, the column set 332 includes one or more other functional external connectors in one or more center rows 350C. For example, the column set 332 includes one or more external power connectors in one or more center rows 350C.

[0252] In some embodiments, the arrangement of the clock external connectors and the power external connectors in one or more center rows 350C directly improves the clock distribution tree in a less deep manner. In some embodiments, the power external connectors in one or more center rows 350C include a ground external connector to ensure that the clock signal is less affected by power supply transients.

[0253] In some embodiments, columns 341 to 345 include power external connectors. In at least some embodiments, one or more columns 341 include at least one entire column of power external connectors, and / or one or more columns 342 include at least one entire column of power external connectors, and / or one or more columns 343 include at least one entire column of power external connectors, and / or one or more columns 344 include at least one entire column of power external connectors, and / or one or more columns 345 include at least one entire column of power external connectors. A complete column of power external connectors is a column in which every external connector is a power external connector. Thus, in at least some embodiments, a robust electrical grid is provided, and / or as described with respect to Figure 2D What is described can achieve effective masking of main band data.

[0254] In some embodiments, in addition to the power external connector, one or more of the columns 341 to 345 further include one or more other functional external connectors. In some examples, one or more of the columns 341 include external connectors for sideband data. For simplicity, the columns 341 to 345 and the description of the external connectors in this specification are not limited to the external connectors. Figure 3B , Figure 3C , 4A to 4D A similar column described is referred to as a power external connector column, although a power external connector column may include one or more other functional external connectors.

[0255] In some embodiments, the I / O terminal 300A corresponds to the Universal Chipset Interconnect Express protocol and is configured to provide an X64 connection. In such a configuration, each of the first receiving connector group Rx_1, the second receiving connector group Rx_2, the first transmitting connector group Tx_1, and the second transmitting connector group Tx_2 includes exactly 32 consecutive main band data external connectors.

[0256] Figure 3A The described configuration, in which the receive connectors and transmit connectors of the I / O end are grouped into two receive connector groups and two transmit connector groups, is an example. A greater number of groups are within the scope of various embodiments. For example, in one or more embodiments in which the I / O end includes three receive connector groups and three transmit connector groups, the third receive connector group is located above the power external connector column 345, and the third transmit connector group is located between the power external connector column 341 and the edge 314 of the semiconductor device 310. Other configurations are within the scope of various embodiments.

[0257] Figure 3B According to some embodiments, Figure 3A Schematic plan view of the I / O terminal 300A in FIG. 3 having a reduced bandwidth I / O terminal 300B. For simplicity, the same symbols are used to represent Figure 3A as well as Figure 3BThe corresponding components in .

[0258] I / O terminal 300B is the same as I / O terminal 300A except that the receiving connectors in column set 322 and the corresponding transmitting connectors in column set 332 are disabled. In other words, the second receiving connector group Rx_2 and the second transmitting connector group Tx_2 of I / O terminal 300A are disabled in I / O terminal 300B and become the disabled second receiving connector group Dis_Rx_2 and the disabled second transmitting connector group Dis_Tx_2 respectively. In some embodiments, I / O terminal 300B is used to connect to another semiconductor device that does not require as high bandwidth as provided by I / O terminal 300A. In some examples, when k is equal to 1, the bandwidth of I / O terminal 300B is half the bandwidth of I / O terminal 300A.

[0259] In at least some embodiments, the disabled second receiving connector group Dis_Rx_2 and / or the disabled second transmitting connector group Dis_Tx_2 still include corresponding receiving connectors and / or transmitting connectors. However, the corresponding main band data channel is not formed in the interconnect structure. Therefore, the disabled receiving connector and the transmitting connector are not coupled to other semiconductor devices. In other examples, the disabled external connector is not manufactured. In at least some embodiments, by not having to form unnecessary external connectors or corresponding channels in the interconnect structure, the manufacturing cost and / or manufacturing time of the integrated circuit device including the dies coupled by the interconnect structure is reduced.

[0260] In at least some embodiments, the disabled second receiving connector group Dis_Rx_2 and / or the disabled second transmitting connector group Dis_Tx_2 still include corresponding receiving connectors and / or transmitting connectors, which are still coupled to other semiconductor devices via corresponding main band data channels in the interconnect structure. However, the receiving circuit and / or the transmitting circuit are configured to drive the disabled receiving connector and / or the disabled transmitting connector, or are configured or controlled to operate in a sleep or low power mode. Therefore, the disabled second receiving connector group Dis_Rx_2 and / or the disabled second transmitting connector group Dis_Tx_2 do not receive and / or send main band data. In at least some embodiments, power consumption is reduced by not operating unnecessary main band data channels.

[0261] In some embodiments, the arrangement of the external connectors of the I / O terminal 300B can be obtained from the bump map of the I / O terminal 300A (also referred to as the bump map in this specification), and only the second receiving connector group Rx_2 and the second transmitting connector group Tx_2 of the I / O terminal 300A need to be marked as disabled. In at least some embodiments, such marking is performed by one or more processors, for example, a processor of an electronic design automation system as described in this specification. In one or more embodiments, no further modification or redesign or repositioning of the external connector is required in the bump map thus obtained. Therefore, the scalability of the I / O terminal is improved in one or more embodiments. Because the receiving connectors and the transmitting connectors in the I / O terminal 300A are grouped into multiple groups arranged in a non-overlapping column set, improved scalability can be achieved in one or more embodiments. Therefore, it is possible and simple to disable the receiving connector group or the transmitting connector group by disabling the column of the receiving connector or the transmitting connector including the group to be disabled. In at least some embodiments, this is an improvement over other methods that do not group receive connectors and transmit connectors, so it is difficult to disable unnecessary receive connectors and / or transmit connectors, ie, it is difficult to scale one bump map to obtain another bump map.

[0262] In some embodiments, the I / O terminal 300B corresponds to the Universal Wafer Interconnect Express protocol and is configured to provide an X32 connection. In this configuration, each of the first receiving connector group Rx_1 and the first transmitting connector group Tx_1 in the I / O terminal 300B includes exactly 32 consecutive main band data external connectors.

[0263] Figure 3C According to some embodiments, Figure 3A The bump mapping of the I / O terminal 300A in FIG. 1 produces a schematic plan view of the bump mapping of the I / O terminal 300C with reduced bandwidth. For simplicity, the same symbols are used to represent Figure 3A as well as Figure 3C The corresponding components in .

[0264] In order to generate the bump map of the I / O terminal 300C, the column set 321 including the first receiving connector group Rx_1 of the I / O terminal 300A and the column set 331 including the first transmitting connector group Tx_1 are copied to the bump map of the I / O terminal 300C, as schematically represented by arrows 362 and 363. The second receiving connector group Rx_2 and the second transmitting connector group Tx_2 of the I / O terminal 300A are not copied to the I / O terminal 300C. Therefore, compared with the I / O terminal 300A, the I / O terminal 300C has a reduced bandwidth. In one or more embodiments, when the bump map of the I / O terminal 300C is generated from the bump map of the I / O terminal 300A, it is not necessary to modify and / or reposition the receiving connector and the transmitting connector for the main band data. In at least some embodiments, the duplication of the described multiple columns of external connectors is performed by one or more processors (e.g., by a processor of an electronic design automation system), as described in this specification.

[0265] I / O terminal 300C further includes power external connector rows 381, 383, 385, which are similar to power external connector rows 341, 343, 345 of I / O terminal 300A. In some embodiments, generating a bump map of I / O terminal 300C includes duplicating one or more of the external power connector rows 341, 343, 345, which are correspondingly used as power external connector rows 381, 383, 385 in the bump map of I / O terminal 300C, by further modifying or relocating one or more other functional external connectors in the power external connector rows 381, 383, 385 to ensure that I / O terminal 300C with reduced bandwidth has proper functionality.

[0266] The I / O terminal 300C has the same bandwidth as the I / O terminal 300B. In some embodiments, the I / O terminal 300C corresponds to the Universal Wafer Interconnect Express protocol and is configured to provide an X32 connection. In this configuration, each of the first receiving connector group Rx_1 and the first transmitting connector group Tx_1 in the I / O terminal 300C includes exactly 32 consecutive main band data external connectors.

[0267] In at least some embodiments, one or more advantages of I / O terminal 300A and / or I / O terminal 300B described in this specification can be achieved by I / O terminal 300C. In addition, in one or more embodiments, compared with I / O terminal 300A and I / O terminal 300B, I / O terminal 300C has a smaller size or form factor, which further reduces manufacturing cost and / or manufacturing time.

[0268] Figure 4A is a schematic plan view of an integrated circuit device 400A according to some embodiments.

[0269] Integrated circuit device 400A includes two semiconductor devices or dies coupled to each other by an interconnect structure, namely, die 1 and die 2. Die 1 has an I / O terminal 410 adjacent to edge 414 of die 1. Die 2 has an I / O terminal 420 adjacent to edge 424 facing edge 414 of die 1. In some embodiments, die 1, I / O terminal 410, edge 414, die 2, I / O terminal 420, edge 424 correspond to Figure 1 The die 110, I / O terminal 112, edge 114, die 120, I / O terminal 122, edge 124 are described. Figure 4A In the exemplary configuration of , each of the I / O terminal 410 and the I / O terminal 420 has the configuration of the I / O terminal 300A.

[0270] The corresponding external connectors in the I / O terminal 410 and the I / O terminal 420 are coupled to each other by corresponding channels in the interconnect structure. For simplicity, the interconnect structure is not fully illustrated and is schematically represented by the main band data channels 411, 412, 421, 422. The interconnect structure includes further channels for one or more other functions, such as sideband, power, clock, tracking, validation, etc. For simplicity, in Figure 4A Channels used for these other functions are omitted.

[0271] Specifically, the transmit connectors in the first transmit connector group Tx_1 of die 1 are correspondingly coupled to the receive connectors in the first receive connector group Rx_1 of die 2 via the main band data channel 411. The transmit connectors in the second transmit connector group Tx_2 of die 1 are correspondingly coupled to the receive connectors in the second receive connector group Rx_2 of die 2 via the main band data channel 412. The transmit connectors in the first transmit connector group Tx_1 of die 2 are correspondingly coupled to the receive connectors in the first receive connector group Rx_1 of die 1 via the main band data channel 421. The transmit connectors in the second transmit connector group Tx_2 of die 2 are correspondingly coupled to the receive connectors in the second receive connector group Rx_2 of die 1 via the main band data channel 422. In some embodiments, the lengths of the main band data channels 411, 412, 421, 422 along the row direction C are the same or substantially the same, so as to advantageously ensure uniform signal delay across all main band data channels, such as with respect to Figure 2C In at least some embodiments, one or more advantages described in this specification can be achieved by the integrated circuit device 400A.

[0272] Figure 4B FIG. 4 is a schematic plan view of an integrated circuit device 400B according to some embodiments. Figure 4A as well as Figure 4B The corresponding components in .

[0273] exist Figure 4B In an exemplary configuration of , die 1 has an I / O terminal 430, die 2 has a corresponding I / O terminal 440, and each of the I / O terminal 430 and the I / O terminal 440 has a configuration of the I / O terminal 300B. The transmit connectors in the first transmit connector group Tx_1 of die 1 are correspondingly coupled to the receive connectors in the first receive connector group Rx_1 of die 2 via a main band data channel 434 formed in the interconnect structure. The transmit connectors in the first transmit connector group Tx_1 of die 2 are correspondingly coupled to the receive connectors in the first receive connector group Rx_1 of die 1 via a main band data channel 443 formed in the interconnect structure. The receive connectors and the transmit connectors in the disabled second transmit connector group Dis_Tx_2 and the disabled second receive connector group Dis_Rx_2 of die 1 and die 2 are not coupled to each other. In some embodiments, the lengths of the main band data channels 434, 443 along the row direction C are the same or substantially the same. In at least some embodiments, one or more advantages described in this specification may be achieved by the integrated circuit device 400B.

[0274] Figure 4C FIG. 4 is a schematic plan view of an integrated circuit device 400C according to some embodiments. Figure 4B as well as Figure 4C The corresponding components in .

[0275] exist Figure 4C In the exemplary configuration of , die 1 has an I / O terminal 430 configured as an I / O terminal 300B, and die 2 has a corresponding I / O terminal 460 configured as an I / O terminal 300C. The transmit connectors in the first transmit connector group Tx_1 of die 1 are correspondingly coupled to the receive connectors in the first receive connector group Rx_1 of die 2 by means of a main band data channel 436 formed in the interconnect structure. The transmit connectors in the first transmit connector group Tx_1 of die 2 are correspondingly coupled to the receive connectors in the first receive connector group Rx_1 of die 1 by means of a main band data channel 463 formed in the interconnect structure. The receive connectors and the transmit connectors in the disabled second transmit connector group Dis_Tx_2 and the disabled second receive connector group Dis_Rx_2 of die 1 are not coupled to die 2. In some embodiments, the lengths C of the main band data channels 436, 463 along the row direction are the same or substantially the same. In at least some embodiments, one or more advantages described in this specification can be achieved by the integrated circuit device 400C.

[0276] Figure 4DFIG. 4 is a schematic plan view of an integrated circuit device 400D according to some embodiments. Figure 4C as well as Figure 4D The corresponding components in .

[0277] exist Figure 4D In the exemplary configuration of , die 1 has an I / O terminal 470 configured as an I / O terminal 300C, and die 2 also has a corresponding I / O terminal 460 configured as an I / O terminal 300C. The transmitting connectors in the first transmitting connector group Tx_1 of die 1 are correspondingly coupled to the receiving connectors in the first receiving connector group Rx_1 of die 2 via a main band data channel 476 formed in the interconnect structure. The transmitting connectors in the first transmitting connector group Tx_1 of die 2 are correspondingly coupled to the receiving connectors in the first receiving connector group Rx_1 of die 1 via a main band data channel 467 formed in the interconnect structure. In some embodiments, the lengths of the main band data channels 476, 467 along the row direction C are the same or substantially the same. In at least some embodiments, one or more advantages described in this specification can be achieved by the integrated circuit device 400C.

[0278] As this manual about FIG. 3A to FIG. 3C as well as 4A to 4D As described, in one or more embodiments, it is possible and / or simple to scale an I / O terminal to use only a portion (e.g., half) of its design bandwidth and interface with a corresponding smaller bandwidth I / O terminal on other dies. In some embodiments, the described scalability is applicable to obtaining I / O terminals of various bandwidths and / or form factors.

[0279] Figure 5A FIG. 5 is a schematic diagram of a bump map 500A for an I / O terminal of a semiconductor device according to some embodiments. In some embodiments, the bump map 500A is applicable to the I / O terminal 300A.

[0280] Bump map 500A includes a set of external connectors or bumps arranged in a plurality of rows and a plurality of columns. The rows of bump map 500A are numbered from row 0 to row 9. For simplicity, the columns of bump map 500A are not numbered. The external connectors of bump map 500A are arranged in a staggered manner, as shown in FIG. Figure 2B as described.

[0281] The bump map 500A includes a first receive connector group Rx_1 including consecutive receive connectors rxdata0 to rxdata31 arranged in a first row set 521 in a pattern or sequence 561. The bump map 500A further includes a second receive connector group Rx_2 including consecutive receive connectors rxdata32 to rxdata63 arranged in a second row set 522 in a pattern or sequence 562. The receive connectors rxdata32 to rxdata63 are subsequent to the receive connectors rxdata0 to rxdata31 in the first receive connector group Rx_1. The bump map 500A further includes a first transmit connector group Tx_1 including consecutive transmit connectors txdata0 to txdata31 arranged in a third row set 531 in a pattern or sequence 571. Bump map 500A further includes a second transmit connector set Tx_2 including consecutive transmit connectors txdata32 to txdata63 arranged in a fourth column set 532 in a pattern or sequence 572. Transmit connectors txdata32 to txdata63 follow transmit connectors txdata0 to txdata31 in the first transmit connector set Tx_1.

[0282] The pattern 571 in the first transmitting connector group Tx_1 corresponds to the pattern 561 in the first receiving connector group Rx_1 rotated 180 degrees around a certain point. The pattern 572 in the second transmitting connector group Tx_2 corresponds to the pattern 562 in the second transmitting connector group Tx_2 rotated 180 degrees around a certain point. Therefore, in some embodiments, when the I / O terminal with the bump map 500A is coupled to another (corresponding to the pattern 561 in the first receiving connector group Rx_1 rotated 180 degrees around a certain point), the pattern 572 in the second transmitting connector group Tx_2 corresponds to the pattern 562 in the second transmitting connector group Tx_2 rotated 180 degrees around a certain point. Figure 4A The corresponding main band data channels all have the same length.

[0283] In addition to corresponding receive and transmit connectors, column set 521 and column set 531 further include clock external connectors schematically represented as Clock 1 and Clock 2 in corresponding areas in center row 4 and row 5. In some embodiments, one or more of the areas where Clock 1 and Clock 2 are located include other functional external connectors, such as external connectors for valid and / or tracking signals. As described in this specification, in one or more embodiments, the arrangement of the clock external connectors in the center row provides one or more advantages, such as clean clock distribution.

[0284] Bump map 500A further includes power external connector rows 541 to 545 corresponding to the power external connector rows 541 to 545. Figure 3A The power external connector columns 341 to 345 described. The power external connectors in the power external connector columns 541 to 545 include a ground external connector vss and power supply external connectors vccio and vccfwdio. In some embodiments, vccio and vccfwdio correspond to different power supply voltages. Each of the power external connector columns 541 to 545 includes at least one entire column of power external connectors having the same voltage, for example, at least one entire column of ground external connectors vss, at least one entire column of power supply external connectors vccio, and / or at least one entire column of power supply external connectors vccfwdio. Therefore, and as described in this specification, a shielding effect for signal crosstalk can be obtained in one or more embodiments.

[0285] In addition to corresponding receive and transmit connectors, column set 522 and column set 532 further include ground external connectors vss in center row 4 and row 5. Therefore, and as described herein, it is possible in one or more embodiments to shield the clock distribution path from power supply transients. Power external connector column 545 further includes external connectors for sideband data in corresponding areas (schematically labeled Side Band 1, Side Band 2). In some embodiments, bump map 500A corresponds to Universal Chiplet Interconnect Express protocol and X64 die-to-die connections.

[0286] In some embodiments, in order to obtain a bump map of the I / O terminals with reduced bandwidth, for example, for X32 die-to-die connections, the column set 522 including the second receiving connector group Rx_2 and the column set 532 including the second transmitting connector group Tx_2 may be substantially disabled, as described with respect to Figure 3B as described.

[0287] In some embodiments, to generate a bump map of an I / O terminal with reduced bandwidth, for example, for an X32 die-to-die connection, the column set 521 including the first receiving connector group Rx_1 and the column set 531 including the first transmitting connector group Tx_1 are copied in the bump map to be generated, as shown in FIG. Figure 3C In at least some embodiments, one or more advantages described in this specification can be achieved by the I / O terminal having the bump map 500A. In addition, the main band data channels are at least evenly distributed in the rows other than the center row 4 and row 5. Therefore, and, as described with respect to Figure 2C As described, the number of metal layers required in an interconnect structure is optimized and / or minimized.

[0288] Figure 5B is a schematic diagram of a bump map 500B for an I / O terminal of a semiconductor device according to some embodiments. For simplicity, components in bump map 500B having corresponding components in bump map 500A are represented by reference symbols of bump map 500A, but with a prime (') and / or double prime (").

[0289] The difference between the bump map 500B and the bump map 500A is that a whole column 581, 582, 583, 584 of the power external connector is included in the column sets 532', 542', 521', 522' of the second transmitting connector group Tx_2', the first transmitting connector group Tx_1', the first receiving connector group Rx_1', and the second receiving connector group Rx_2', respectively. Therefore, in one or more embodiments, the shielding effect on crosstalk is further improved.

[0290] As described in this specification, some embodiments provide an arrangement or bump mapping of external connectors that is suitable for die-to-die connections via an interconnect structure. In at least some embodiments, the bump mapping is scalable for various bandwidths and / or form factors. In some embodiments, scaling is simple without the need to redesign and / or reposition at least the main band data bumps. Therefore, in one or more embodiments, it is possible to perform chip integration using low-cost packaging technology when appropriate. In at least some embodiments, one or more advantages can be achieved, including but not limited to compliance with advanced protocols such as general-purpose chiplet interconnect fast protocols, robust power delivery, clean clock distribution, improved wiring and signal integrity, improved shielding effects, etc.

[0291] Figure 6 is a schematic cross-sectional view of a portion of a semiconductor device 600 according to some embodiments. In some embodiments, the semiconductor device 600 corresponds to Figure 1 , FIG. 3A to FIG. 3C , 4A to 4D Any semiconductor device or die described by one or more of the foregoing.

[0292] The semiconductor device 600 includes a substrate 610, wherein a functional circuit of the semiconductor device 600 is formed on the substrate 610. The functional circuit of the semiconductor device 600 includes a plurality of circuit elements electrically coupled to each other to perform one or more operations or functions. Figure 6, transistor 611 is illustrated as an exemplary circuit element of a functional circuit of semiconductor device 600. Transistor 611 includes source / drain regions 612, 613, which are P-doped regions or N-doped regions formed by adding P-type or N-type dopants to substrate 610. In some embodiments, the P-doped region or N-doped region is formed in an N-well or P-well. In some embodiments, an isolation structure is formed between adjacent P-well / P-doped regions and N-well / N-doped regions. For simplicity, Figure 6 The isolation structure is omitted. The transistor 611 further includes a gate stack, and the gate stack includes a gate dielectric layer 614 and a gate electrode 615. In at least some embodiments, the gate dielectric layer includes a plurality of gate dielectric layers. Example materials for the gate dielectric layer include HfO2, ZrO2, etc. Example materials for the gate electrode 615 include polysilicon, metal, etc. Spacers 616 are formed on the sidewalls of the gate stack. Example materials for the spacer 616 include, but are not limited to, silicon nitride, oxynitride, silicon carbide, etc. A contact structure (sometimes referred to as a metal-to-device (MD) structure) is formed above the source / drain region of the transistor 611 to define an electrical connection from the transistor 611 to other circuit elements. Figure 6 , metal-to-device contact structure 617 is depicted as being above and electrically coupled to source / drain region 613. For simplicity, metal-to-device contact structures above and electrically coupled to source / drain region 612 are omitted. Via 618 is above and electrically contacts metal-to-device contact structure 617. Via 618 is sometimes referred to as via-to-device (VD). Via 619 is above and electrically contacts gate electrode 615. Via 619 is sometimes referred to as via-to-gate (VG). Example materials for VD and VG vias include metals.

[0293] The semiconductor device 600 further includes a redistribution layer 620 disposed above the substrate 610 along a thickness direction of the substrate 610. Figure 6 The redistribution layer 620 includes a plurality of metal layers and guide hole layers, which are arranged alternately in sequence above the VD and VG guide holes along the Z axis. The redistribution layer 620 further includes an interlayer dielectric (ILD) 629 in which the metal layers and guide hole layers are buried. Figure 6In the exemplary configuration in FIG. 1 , the functional circuit represented by transistor 611 is coupled to a conductive pattern 654 adjacent to the top of a redistribution layer 620 via various metal layers and via layers, then coupled to vias 655, and then coupled to contact pads 656. Example materials of contact pads 656 include, but are not limited to, aluminum, copper, silver, gold, tungsten, nickel, alloys of the foregoing metals, multiple layers of the foregoing metals, and the like.

[0294] Under-bump-metallurgy (UBM) structure 660 is above and electrically contacts contact pad 656. Under-bump-metallurgy structure 660 is configured to receive bump 662 for physically coupling semiconductor device 600 and electrically coupling to another device, such as an interconnect structure, an interposer, etc. Example materials of under-bump-metallurgy structure 660 include, but are not limited to, one or more layers of copper, tantalum, titanium, nickel, copper, alloys of the aforementioned metals, etc. Example materials of bump 662 include, but are not limited to, one or more layers of solder, tin, lead, copper, gold, silver, zinc, bismuth, magnesium, antimony, indium, alloys of the aforementioned metals, etc. In some embodiments, semiconductor device 600 further includes a passivation layer (not shown), and contact pad 656 and / or under-bump-metallurgy structure 660 are partially buried in the passivation layer. Example materials of the passivation layer include, but are not limited to, silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), undoped silicate glass (USG), polymers, multiple layers of the aforementioned materials, etc. Exemplary polymers include, but are not limited to, epoxy resins, polyimides, benzocyclobutene (BCB), polybenzo Polybenzoxazole (PBO), multilayers of the foregoing materials, and the like.

[0295] In some embodiments, the semiconductor device 600 includes a plurality of bumps 662 arranged according to the bump mapping of the I / O terminals described in this specification.

[0296] FIG. 7A to FIG. 7G is a schematic cross-sectional view of an integrated circuit device 700 at various stages of a manufacturing process according to some embodiments. In some embodiments, the integrated circuit device 700 corresponds to Figure 1 as well as 4A to 4D One or more of the described integrated circuit devices.

[0297] exist Fig. 7AIn the embodiment of the present invention, a first redistribution layer 710 is formed on a first carrier substrate 702. For example, a release layer (not shown) is deposited on the first carrier substrate 702. A dielectric layer 711 is deposited on the release layer and then patterned to form a via opening. A conductive material (e.g., metal) is filled into the opening and patterned to form a conductive via 712 and a conductive trace 713. Thus, a structure 700A is obtained.

[0298] exist Figure 7B In the process, additional dielectric layers and conductive materials are deposited, and as described with respect to Fig. 7A Patterning is performed as described to build further conductive vias and traces of the first redistribution layer 710. The completed first redistribution layer 710 comprises a top dielectric layer 715 with conductive pads 716, 717 thereon. A through hole 720 is formed above the conductive pad 716, for example by an electroplating process. Thus, a structure 700B is obtained.

[0299] exist Figure 7C In the embodiment, an interconnect structure 730, such as a local silicon interconnect or a silicon bridge, is separately fabricated and attached to the conductive pad 717. In some embodiments, the interconnect structure 730 includes a fine-pitch redistribution layer 731 formed in a semiconductor substrate (not numbered) by, for example, a dual damascene process. In some embodiments, the interconnect structure 730 corresponds to Figures 1 to 4D One or more of the interconnect structures described, and the fine pitch redistribution layer 731 includes conductive traces or channels for coupling the I / O terminals of the die as described in this specification. The interconnect structure 730 further includes an interconnection through hole 732 above the fine pitch redistribution layer 731 and coupled to the fine pitch redistribution layer 731. The interconnect structure 730 further includes a connector 733, such as a microbump, below the fine pitch redistribution layer 731 and coupled to the fine pitch redistribution layer 731. The connector 733 is attached to the corresponding conductive pad 717 by a solder material 734, thereby attaching the interconnect structure 730 to the first redistribution layer 710. The bottom fill material 736 is deposited between the interconnect structure 730 and the first redistribution layer 710. Thus, the structure 700C is obtained.

[0300] exist Fig.7D , the interconnect structure 730 and the via 720 are encapsulated in a first encapsulant 738. A second redistribution layer 740 is constructed on top of the first encapsulant 738 in a manner similar to that described with respect to the first redistribution layer 710. The completed second redistribution layer 740 includes a top conductive pad 746, which is coupled to the via 720 and the interconnect structure 730 by means of a plurality of metal layers and a via layer of the second redistribution layer 740. A solder bump 748, such as a C4 bump, is formed on top of the conductive pad 746. Thus, a structure 700D is obtained.

[0301] In FIG. 7E , an interposer substrate 750 is attached to the solder bump 748. The first carrier substrate 702 is separated, the remaining structure is flipped, and the interposer substrate 750 is releasably attached to the second carrier substrate 752. As a result of flipping the structure, the vias 712 of the first redistribution layer 710 are exposed. An external connector 760 is formed above the exposed vias 712. In some embodiments, a conductive trace (not shown) is formed above the exposed vias 712, and then the external connector 760 is formed above the conductive trace. The external connector 760 includes a first group of external connectors 761 and a second group of external connectors 762, the first group of external connectors 761 being connected to the I / O terminal of the first die, and the second group of external connectors 762 being connected to the I / O terminal of the second die. In some embodiments, the first group of external connectors 761 and the second group of external connectors 762 correspond to one or more of the bump mappings described in this specification. The external connector 760 further includes external connectors 763, 764. Thus, a structure 700E is obtained.

[0302] In FIG. 7F , the first die, namely, die 1 having I / O terminal 771, is bonded to the first set of external connectors 761 and external connector 763. The external connector of I / O terminal 771 is bonded to the first set of external connectors 761 correspondingly. The second die, namely, die 2 having I / O terminal 772, is bonded to the second set of external connectors 762 and external connector 764. The external connector of I / O terminal 772 is bonded to the second set of external connectors 762 correspondingly. In some embodiments, die 1 and die 2 are connected by means of a plurality of external connectors. Figure 6 Then, the die 1 and the die 2 are separately manufactured by the process described. Figure 1 , Figure 2C as well as Figure 2D , 4A to 4D The described means are coupled to each other by means of an interconnect structure 730. Thus, a structure 700F is obtained.

[0303] exist Figure 7G In the embodiment, bottom fill material 776 is deposited between first redistribution layer 710 and the die. Then, the die is encapsulated in second encapsulation material 778. Second carrier substrate 752 is separated to expose the surface of interposer substrate 750, and solder bumps 780 are formed over the exposed surface of interposer substrate 750. Thus, structure 700G is obtained.

[0304] The processes described are examples. Other configurations and / or processes are within the scope of various embodiments. For example, an interconnect structure 730 (e.g., a silicon bridge) with a small pitch redistribution layer 731 provides improved routing capabilities and is suitable for high-speed, high-bandwidth applications or integrated circuit devices. However, it is relatively expensive to manufacture such a silicon bridge. For low-cost applications or integrated circuit devices that do not require high speed or high bandwidth, other interconnect structure configurations (e.g., redistribution layers and / or intermediate substrates) are used instead to couple the die. The scalability described in accordance with some embodiments provides flexibility in the design and manufacturing of integrated circuit devices or packages to meet different considerations.

[0305] Figure 8 800 according to some embodiments. In some embodiments, the method 800 is at least partially performed by one or more processors. In some examples, according to some embodiments, the method 800 may be at least partially performed by an electronic design automation system 900 ( Fig. 9 , described later) and / or integrated circuit manufacturing system 1000 ( Fig.10 , described later) implementation.

[0306] In operation 805, a second bump map is generated based on the first bump map. In some embodiments, the set of columns including the first receiving bump and the first transmitting bump in the first bump map is copied to the second bump map. Figure 3C As described, the first bump map of the I / O terminal 300A includes the first receiving bump column set 321 of the first receiving connector group Rx_1 and the first transmitting bump column set 331 of the first transmitting connector group Tx_1 are copied to the second bump map of the I / O terminal 300C. In at least some embodiments, such copying is performed by one or more processors, for example, an electronic design automation system as described in this specification.

[0307] In some embodiments, the second receiving bump and the second transmitting bump of the first bump map are disabled to obtain the second bump map. Figure 3BAs described, the receiving bumps in the second receiving connector group Rx_2 and the transmitting bumps in the second transmitting connector group Tx_2 in the first bump mapping of the I / O terminal 300A are disabled to obtain the second bump mapping of the I / O terminal 300B. In at least some embodiments, the receiving bumps and the transmitting bumps are marked as disabled by one or more processors (e.g., an electronic design automation system), as described in this specification. In some examples, when the receiving bumps and the transmitting bumps are marked as disabled, the wiring of the disabled receiving bumps and the transmitting bumps is not performed by the electronic design automation system, and the corresponding channels are not formed by the integrated circuit manufacturing system. Other configurations for disabling unnecessary receiving bumps and transmitting bumps are within the scope of various embodiments.

[0308] In operation 815, the generated second bump map is stored in a non-transitory computer-readable storage medium. In some embodiments, the first bump map is also stored in a non-transitory computer-readable storage medium.

[0309] In operation 825, an integrated circuit device is manufactured based on the first bump map and the second bump map. For example, the first bump map and the second bump map are retrieved and used by an electronic design automation system to design I / O terminals of dies to be coupled to each other and / or to design interconnect structures configured to couple the dies to each other. Based on the design of the dies and / or the interconnect structures, the dies and the interconnect structures are manufactured and coupled to each other (e.g., by an integrated circuit manufacturing system) to obtain an integrated circuit device, such as, for example, as described with respect to FIG. 7A to FIG. 7G In at least some embodiments, one or more advantages described in this specification can be achieved by performing the bump map and / or integrated circuit device obtained by performing the method 800.

[0310] The described methods include example operations, but they do not necessarily need to be performed in the order shown. According to the spirit and scope of the embodiments of the present disclosure, operations can be appropriately added, replaced, changed in order and / or deleted. For those with ordinary knowledge in the art, embodiments and / or different embodiments incorporating different features are within the scope of the present disclosure and will be apparent after reading the present disclosure.

[0311] In some embodiments, at least one of the methods discussed above is performed in whole or in part by at least one electronic design automation system. In some embodiments, the electronic design automation system may be used as part of a design room of an integrated circuit manufacturing system discussed below.

[0312] Fig. 9 is a block diagram of an electronic design automation system 900 according to some embodiments.

[0313] In some embodiments, in some embodiments, electronic design automation system 900 includes an APR system. According to one or more embodiments, methods of designing layout diagrams representing wiring arrangements described herein may be implemented (eg, using electronic design automation system 900 according to some embodiments).

[0314] In some embodiments, the electronic design automation system 900 is a general-purpose computing device including a hardware processor 902 and a non-transitory computer-readable storage medium 904. The storage medium 904 is encoded (i.e., stores), among other things, with computer program code 906 (i.e., a set of executable instructions). The execution of the instructions 906 by the hardware processor 902 at least partially represents an electronic design automation tool implementing part or all of the methods described in this specification according to one or more embodiments (hereinafter referred to as processes and / or methods).

[0315] The processor 902 is electrically coupled to the computer readable storage medium 904 via the bus 908. The processor 902 is also electrically coupled to the input / output (I / O) interface 99 via the bus 908. The network interface 912 is also electrically connected to the processor 902 via the bus 908. The network interface 912 is connected to the network 914, so that the processor 902 and the computer readable storage medium 904 can be connected to external components via the network 914. The processor 902 is configured to execute computer program code 906 encoded in the computer readable storage medium 904 so that the electronic design automation system 900 can be used to perform some or all of the operations referred to in the process and / or method. In one or more embodiments, the processor 902 is a central processing unit, a multiprocessor, a distributed processing system (distributed processing system), an application specific integrated circuit (ASIC) and / or a suitable processing unit.

[0316] In some embodiments, the computer-readable storage medium 904 is an electronic, magnetic, optical, electromagnetic, infrared and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 904 includes semiconductor or solid-state memory, magnetic tape, removable computer diskette, random access memory (RAM), read-only memory (ROM), rigid magnetic disk and / or optical disk. In some embodiments using optical disks, the computer-readable storage medium 904 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W) and / or digital video disc (DVD).

[0317] In some embodiments, the storage medium 904 stores computer program code 906 configured to cause the electronic design automation system 900 (where such execution represents (at least in part) an electronic design automation tool) to be used to perform some or all of the described processes and / or methods. In some embodiments, the storage medium 904 also stores information required to facilitate the execution of some or all of the described processes and / or methods. In one or more embodiments, the storage medium 904 stores a library 907 of standard cells, which includes the standard cells described in this specification.

[0318] The electronic design automation system 900 includes an I / O interface 910. The I / O interface 910 is coupled to an external circuit. In one or more embodiments, the I / O interface 910 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, and / or cursor arrow keys for transmitting information and commands to the processor 902.

[0319] The electronic design automation system 900 also includes a network interface 912 coupled to the processor 902. The network interface 912 allows the electronic design automation system 900 to communicate with a network 914, in which one or more other computer systems are connected to the network 914. The network interface 912 includes a wireless network interface or a wired network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA, and a wired network interface such as ETHERNET, USB, or IEEE-1364. In some embodiments, part or all of the described processes and / or methods are performed in two or more electronic design automation systems 900.

[0320] The electronic design automation system 900 is configured to receive information via the I / O interface 910. The information received via the I / O interface 910 includes one or more of instructions, data, design rules, a database of standard cells, and / or other parameters for processing by the processor 902. The information is transmitted to the processor 902 via the bus 908. The electronic design automation system 900 is configured to receive information about a user interface (UI) via the I / O interface 910. The information is stored in the computer readable storage medium 904 as the user interface 942.

[0321] In some embodiments, part or all of the described processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the described processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the described processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the described processes and / or methods is implemented as a software application that is part of an electronic design automation system 900. In some embodiments, part or all of the described processes and / or methods are implemented as a software application used by the electronic design automation system 900. In some embodiments, the described processes and / or methods are implemented as a software application that is part of an electronic design automation system 900. A layout diagram including standard cells is generated by a tool or other suitable layout generation tool.

[0322] In some embodiments, the process is a function of a program stored in a non-transitory computer-readable recording medium. The non-transitory computer-readable recording medium includes, but is not limited to, an external / removable and / or internal / built-in storage or memory unit, for example, one or more of an optical disc (such as a DVD), a magnetic disk (such as a hard disk), a semiconductor memory (such as a read-only memory, a random access memory, a memory card, etc.).

[0323] Fig.10 1 is a block diagram of an integrated circuit manufacturing system 1000 and an integrated circuit manufacturing process associated therewith according to some embodiments. In some embodiments, based on the layout diagram, one or more semiconductor masks, or at least one of at least one component in a layer of a semiconductor integrated circuit, are manufactured using the integrated circuit manufacturing system 1000.

[0324] exist Fig.10 In the present invention, the integrated circuit manufacturing system 1000 includes entities, such as a design house 1020, a mask company 1030, and an integrated circuit manufacturer / fabricator ("fab") 1050, which interact with each other in the design, development, and manufacturing cycle and / or services related to an integrated circuit device 1060. The entities in the integrated circuit manufacturing system 1000 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities or receives services from one or more other entities. In some embodiments, two or more of the design house 1020, the mask company 1030, and the integrated circuit manufacturing plant 1050 are owned by a single larger company. In some embodiments, two or more of the design company 1020, the mask company 1030, and the integrated circuit fabrication plant 1050 are co-located in a common facility and use common resources.

[0325] The design company (or design team) 1020 generates an integrated circuit design layout 1022. The integrated circuit design layout 1022 includes various geometric patterns designed for use in the integrated circuit device 1060. The geometric patterns correspond to the patterns of the metal, oxide, or semiconductor layers of the various components that constitute the integrated circuit device 1060 to be manufactured. Various layers are combined to form various integrated circuit features. For example, a portion of the integrated circuit design layout 1022 includes various integrated circuit features to be formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source electrodes, and drain electrodes, metal lines or vias for interconnecting layers, and openings for bonding pads. The design company 1020 executes an appropriate design program to form the integrated circuit design layout 1022. The design program includes one or more of a logical design, a physical design, or a place-and-route. The integrated circuit design layout 1022 is presented in one or more data files having geometric pattern information. For example, the integrated circuit design layout 1022 may be represented in a GDSⅡ file format or a DFⅡ file format.

[0326] The mask company 1030 includes data preparation 1032 and mask manufacturing 1044. The mask company 1030 uses the integrated circuit design layout drawing 1022 to manufacture one or more masks 1045 for manufacturing various layers of the integrated circuit device 1060 according to the integrated circuit design layout drawing 1022. The mask company 1030 performs mask data preparation 1032, wherein the integrated circuit design layout drawing 1022 is converted into a representative data file (RDF). The mask data preparation 1032 provides the representative data file to the mask manufacturing 1044. The mask manufacturing 1044 includes a mask writer. The mask writer converts the representative data file into an image on a substrate, such as a mask (reticle) 1045 or a semiconductor wafer 1053. The integrated circuit design layout drawing 1022 is manipulated by the mask data preparation 1032 to conform to the specific characteristics of the mask writer and / or the requirements of the integrated circuit manufacturing plant 1050. In Fig.10 1, mask data preparation 1032 and mask manufacturing 1044 are illustrated as separate elements. In some embodiments, mask data preparation 1032 and mask manufacturing 1044 may be collectively referred to as mask data preparation.

[0327] In some embodiments, the mask data preparation 1032 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. Optical proximity correction adjusts the integrated circuit design layout 1022. In some embodiments, the mask data preparation 1032 further includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, etc., or a combination of the foregoing techniques. In some embodiments, inverse lithography technology (ILT) is also used, which treats optical proximity correction as an inverse imaging problem.

[0328] In some embodiments, mask data preparation 1032 includes a mask rule checker (MRC) that checks the integrated circuit design layout that has undergone the optical proximity correction process using a set of mask creation rules, wherein the mask creation rules may include specific geometric and / or connection constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the mask rule checker modifies the integrated circuit design layout 1022 to compensate for the constraints during mask fabrication 1044, which may undo some of the modifications performed by the optical proximity correction to meet the mask creation rules.

[0329] In some embodiments, the mask data preparation 1032 includes a lithography process checking (LPC), which simulates a process to be performed by the integrated circuit manufacturing plant 1050 to manufacture the integrated circuit device 1060. The lithography process checking simulates the process based on the integrated circuit design layout 1022 to create a simulated manufactured device, such as the integrated circuit device 1060. The process parameters in the lithography process checking simulation may include parameters related to various processes of the integrated circuit manufacturing cycle, parameters related to the tools used to manufacture the integrated circuit, and / or other aspects of the manufacturing process. The lithography process checking may consider various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, etc., or a combination of the foregoing factors. In some embodiments, after a simulated fabricated device has been created by lithography process inspection, if the simulated device is not close enough in shape to meet design criteria, optical proximity correction and / or mask criteria checker may be repeated to further improve the integrated circuit design layout 1022.

[0330] It should be understood that the above description of the mask data preparation 1032 has been simplified for the purpose of clarity. In some embodiments, the data preparation 1032 includes additional features such as logic operations (LOPs) to modify the integrated circuit design layout 1022 according to manufacturing criteria. In addition, during the data preparation 1032, the processes applied to the integrated circuit design layout 1022 can be performed in a variety of different orders.

[0331] After the mask data preparation 1032 and during the mask manufacturing 1044, a single mask 1045 or a group of masks 1045 are manufactured based on the modified integrated circuit design layout 1022. In some embodiments, the mask manufacturing 1044 includes performing one or more lithography exposures based on the integrated circuit design layout 1022. In some embodiments, an electron beam (e-beam) or a multiple electron beam mechanism is used to form a pattern on the mask (photomask or mask) 1045 based on the modified integrated circuit design layout 1022. The mask 1045 can be formed using various techniques. In some embodiments, the mask 1045 is formed using a binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose a layer of photosensitive material (e.g., photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In some examples, a binary mask version of the mask 1045 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chrome) coated in the opaque areas of the binary mask. In other examples, the mask 1045 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 1045, various features in a pattern formed on the phase shift mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated phase shift mask or an alternating phase shift mask. The masks produced by the mask manufacturing 1044 are used in various processes. For example, such masks are used in an ion implantation process to form various doped regions in the semiconductor wafer 1053, in an etching process to form various etched regions in the semiconductor wafer 1053, and / or in other suitable processes.

[0332] The integrated circuit manufacturing plant 1050 is an integrated circuit manufacturing entity, which includes one or more manufacturing facilities for manufacturing various integrated circuit products. In some embodiments, the integrated circuit manufacturing plant 1050 is a semiconductor foundry. For example, there may be a first manufacturing facility for front-end manufacturing (front-end-of-line, FEOL) manufacturing) of multiple integrated circuit products, a second manufacturing facility that can provide back-end manufacturing (back-end-of-line, BEOL) manufacturing) for interconnection and packaging of integrated circuit products, and a third manufacturing facility that provides other services for the foundry business.

[0333] The integrated circuit manufacturing plant 1050 includes a manufacturing tool 1052 configured to perform various manufacturing operations on a semiconductor wafer 1053 so that an integrated circuit device 1060 is manufactured according to one or more photomasks (e.g., photomask 1045). In various embodiments, the manufacturing tool 1052 includes one or more wafer steppers, ion implanters, photoresist coaters, process chambers (e.g., chemical vapor deposition (CVD) chambers or low-pressure chemical vapor deposition furnaces), chemical mechanical planarization (CMP) systems, plasma etching systems, wafer cleaning systems, or manufacturing equipment capable of performing one or more suitable manufacturing processes described herein.

[0334] The integrated circuit manufacturing plant 1050 uses the mask 1045 manufactured by the mask company 1030 to manufacture the integrated circuit device 1060. Therefore, the integrated circuit manufacturing plant 1050 at least indirectly uses the integrated circuit design layout 1022 to manufacture the integrated circuit device 1060. In some embodiments, the semiconductor wafer 1053 is manufactured by the integrated circuit manufacturing plant 1050 using the mask 1045 to form the integrated circuit device 1060. In some embodiments, the integrated circuit manufacturing includes performing one or more lithography exposures based at least indirectly on the integrated circuit design layout 1022. The semiconductor wafer 1053 includes a silicon substrate or other suitable substrate having a material layer formed thereon. The semiconductor wafer 1053 further includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent manufacturing operations).

[0335] Some embodiments of the present disclosure provide a semiconductor device, which includes a group of external connectors, which are arranged in multiple rows and columns. This group of external connectors includes multiple receiving connectors and multiple transmitting connectors. The receiving connector and the transmitting connector are correspondingly configured to input information to the semiconductor device and output information from the semiconductor device. The receiving connector includes a first receiving connector group of multiple first continuous receiving connectors in the receiving connector and a second receiving connector group of multiple second continuous receiving connectors in the receiving connector. The transmitting connector includes a first transmitting connector group of multiple first continuous transmitting connectors in the transmitting connector and a second transmitting connector group of multiple second continuous transmitting connectors in the transmitting connector. The first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group are arranged relative to each other in a row direction along multiple rows.

[0336] In some embodiments, the plurality of rows include a first row set having the first serial receiving connector arranged therein, a second row set having the second serial receiving connector arranged therein, a third row set having the first serial transmitting connector arranged therein, and a fourth row set having the second serial transmitting connector arranged therein. Furthermore, the first row set to the fourth row set do not overlap with each other.

[0337] In some embodiments, the first continuous receiving connector corresponds to the first continuous transmitting connector, and the second continuous receiving connector corresponds to the second continuous transmitting connector. In some embodiments, the second transmitting connector group, the first transmitting connector group, the first receiving connector group, and the second receiving connector group are arranged in sequence along the row direction. In some embodiments, the second continuous receiving connector is continuous with the first continuous receiving connector, and the second continuous transmitting connector is continuous with the first continuous transmitting connector.

[0338] In some embodiments, this group of external connectors further includes multiple power external connectors, and the power external connectors include, in multiple rows, at least one row of power external connectors between each pair of adjacent groups among the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group, and two end rows of power external connectors in which the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group are arranged.

[0339] In some embodiments, the set of external connectors further includes a plurality of power supply external connectors and a plurality of ground external connectors. The power supply external connector includes, in a plurality of columns, at least one entire column of power supply external connectors between each pair of adjacent groups among the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group, and two end columns of power supply external connectors with the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group arranged therebetween. The ground external connector includes, in a plurality of columns, at least one entire column of ground external connectors between each pair of adjacent groups, and two end columns of ground external connectors with the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group arranged therebetween.

[0340] In some embodiments, the set of external connectors further includes a plurality of clock external connectors arranged along one or more center rows of the plurality of rows. In some embodiments, the second consecutive receive connector and the second consecutive transmit connector are disabled. In some embodiments, the set of external connectors corresponds to a universal waferlet interconnect express protocol, and each of the first receive connector set, the second receive connector set, the first transmit connector set, and the second transmit connector set includes exactly 32 consecutive primary band data external connectors.

[0341] Some embodiments of the present disclosure provide an integrated circuit device, which includes a first die and a second die. Each of the first die and the second die includes a group of external connectors arranged in multiple rows and multiple columns. This group of external connectors includes multiple receiving connectors, multiple transmitting connectors, and multiple power external connectors. The receiving connector includes a first receiving connector group of multiple first receiving connectors in the receiving connector. The transmitting connector includes a first transmitting connector group of multiple first transmitting connectors in the transmitting connector. The power external connector includes, in multiple columns, a first complete row of power external connectors between the first receiving connector group and the first transmitting connector group. The first receiving connector of the first die is correspondingly coupled to the first transmitting connector of the second die. The first transmitting connector of the first die is correspondingly coupled to the first receiving connector of the second die.

[0342] In some embodiments, in the first die, the receiving connector further includes a second receiving connector group of multiple second receiving connectors in the receiving connector; the transmitting connector further includes a second transmitting connector group of multiple second transmitting connectors in the transmitting connector, the first receiving connector group is arranged between the second receiving connector group and the first transmitting connector group along a row direction of the multiple rows; the first transmitting connector group is arranged between the second transmitting connector group and the first receiving connector group along a row direction. The power external connector further includes a second complete row of power external connectors between the first receiving connector group and the second receiving connector group, a third complete row of power external connectors between the first transmitting connector group and the second transmitting connector group, and two complete end rows of power external connectors with the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group arranged therebetween. In some embodiments, the second receiving connector and the second transmitting connector of the first die are not coupled to the external connector of the second die.

[0343] In some embodiments, in the second die, the receiving connector further includes a second receiving connector group of a plurality of second receiving connectors in the receiving connector; the transmitting connector further includes a second transmitting connector group of a plurality of second transmitting connectors in the transmitting connector, the first receiving connector group is arranged between the second receiving connector group and the first transmitting connector group along a row direction of the plurality of rows; the first transmitting connector group is arranged between the second transmitting connector group and the first receiving connector group along a row direction. The power external connector further includes a second complete row of power external connectors between the first receiving connector group and the second receiving connector group, a third complete row of power external connectors between the first transmitting connector group and the second transmitting connector group, and two complete end rows of power external connectors with the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group arranged therebetween.

[0344] In some embodiments, the second receive connector and the second transmit connector of the first die are not coupled to the external connector of the second die, and the second receive connector and the second transmit connector of the second die are not coupled to the external connector of the first die. In some embodiments, the second receive connector of the first die is correspondingly coupled to the second transmit connector of the second die, and the second transmit connector of the first die is correspondingly coupled to the second receive connector of the second die.

[0345] In some embodiments, in each of the first die and the second die, the set of external connectors corresponds to a Universal Dielet Interconnect Express protocol, and each of the first receive connector set and the first transmit connector set includes exactly 32 consecutive primary band data external connectors.

[0346] Some embodiments of the present disclosure provide a method at least partially performed by at least one processor. The method includes generating a second bump map based on a first bump map and storing the second bump map in a non-transitory computer-readable storage medium. The first bump map includes a bump group arranged in multiple rows and multiple columns. The bump group includes multiple receiving bumps and multiple transmitting bumps. The receiving bumps include a first receiving bump group of multiple first receiving bumps in the receiving bumps and a second receiving bump group of multiple second receiving bumps in the receiving bumps. The transmitting bumps include a first transmitting bump group of multiple first transmitting bumps in the transmitting bumps and a second transmitting bump group of multiple second transmitting bumps in the transmitting bumps. The multiple columns include a first column set in which the first receiving bumps are arranged, a second column set in which the second receiving bumps are arranged, a third column set in which the first transmitting bumps are arranged, and a fourth column set in which the second transmitting bumps are arranged. The first column set to the fourth column set do not overlap with each other. Generating the second bump map includes copying the first column set having the first receiving bumps arranged therein and the third column set having the first transmitting bumps arranged therein into the second bump map, or disabling the second receiving bumps and the second transmitting bumps to obtain the second bump map.

[0347] In some embodiments, the method further includes controlling the manufacture of an integrated circuit device based on the first bump mapping and the second bump mapping. The integrated circuit device includes a first die, a second die, and an interconnect structure. The first die includes a first I / O terminal corresponding to the first bump mapping. The second die includes a second I / O terminal corresponding to the second bump mapping. The first receiving bump in the first I / O terminal of the first die is correspondingly coupled to the first transmitting bump in the second I / O terminal of the second die by the interconnect structure, and the first transmitting bump in the first I / O terminal of the first die is correspondingly coupled to the first receiving bump in the second I / O terminal of the second die by the interconnect structure.

[0348] In some embodiments, the first bump map corresponds to the universal chiplet interconnect express protocol and includes exactly 64 main band data bumps, the main band data bumps corresponding to the first receive bump, the second receive bump, the first transmit bump, and the second transmit bump in the first bump map, and the second bump map corresponds to the universal chiplet interconnect express protocol and includes exactly 32 main band data bumps, the main band data bumps corresponding to the first receive bump and the first transmit bump in the second bump map.

[0349] The features of several embodiments are summarized above so that those with ordinary knowledge in the art can better understand various aspects of the present disclosure. It should be understood by those with ordinary knowledge in the art that the present disclosure can be easily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments introduced herein. It should also be understood by those with ordinary knowledge in the art that such equivalent configurations do not deviate from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device comprising a set of external connectors arranged in a plurality of rows and a plurality of columns, characterized in that: The set of external connectors includes a plurality of receiving connectors and a plurality of transmitting connectors, the receiving connectors and the transmitting connectors being correspondingly configured to input information to the semiconductor device and output information from the semiconductor device; The receiving connector comprises: a first receiving connector group of a plurality of first consecutive receiving connectors in the receiving connector; and a second receiving connector group of a plurality of second consecutive receiving connectors in the receiving connector; The transmitting connector comprises: a first launch connector group of a plurality of first consecutive launch connectors in the launch connector; and a second launch connector group of a plurality of second consecutive launch connectors in the launch connector; The first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group are arranged opposite to each other in a row direction of the plurality of rows.

2. The semiconductor device according to claim 1, wherein: The columns include: a first row set having said first serial receiving connectors arranged therein; a second row set having said second serial receiving connectors arranged therein; a third row set having said first serial transmitting connectors arranged therein; and having a fourth row set in which said second serial transmitting connectors are arranged; and The first to fourth column sets do not overlap with each other.

3. The semiconductor device according to claim 1, wherein: The first serial receive connector corresponds to the first serial transmit connector; and The second serial receive connector corresponds to the second serial transmit connector.

4. The semiconductor device according to claim 1, wherein: The second serial receive connector is continuous with the first serial receive connector; and the second serial transmit connector is continuous with the first serial transmit connector.

5. The semiconductor device according to claim 1, wherein: The set of external connectors further includes a plurality of power external connectors; and The power external connector includes, in the plurality of columns, at least one row of the power external connectors between each adjacent pair of the first receive connector group, the second receive connector group, the first transmit connector group, and the second transmit connector group; as well as There are two end rows of the power external connector in which the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group are arranged.

6. The semiconductor device according to claim 1, wherein: The set of external connectors further comprises: Multiple power supply external connectors; and Multiple grounded external connectors; The power supply external connector includes, in the plurality of columns, at least one entire row of the power supply external connectors between each adjacent pair of the first receive connector set, the second receive connector set, the first transmit connector set, and the second transmit connector set; and The power supply external connector two terminal rows have the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group arranged between them; and The grounded external connector includes, in the plurality of columns, at least one entire row of said grounded external connectors between each pair of adjacent groups; and There are two end rows of the grounded external connector with the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group arranged therebetween.

7. The semiconductor device according to claim 1, wherein The second serial receive connector and the second serial transmit connector are disabled.

8. The semiconductor device according to claim 1, wherein: The set of external connectors corresponds to a universal dielet interconnect express protocol; and Each of the first receive connector set, the second receive connector set, the first transmit connector set, and the second transmit connector set includes exactly 32 consecutive primary band data external connectors.

9. An integrated circuit device, comprising a first die and a second die, characterized in that: Each of the first die and the second die includes a set of external connectors arranged in a plurality of rows and a plurality of columns; The set of external connectors includes a plurality of receiving connectors, a plurality of transmitting connectors, and a plurality of power external connectors; The receiving connector includes a first receiving connector group of a plurality of first receiving connectors in the receiving connector; The transmit connector includes a first transmit connector group of a plurality of first transmit connectors in the transmit connector; and The power external connectors include, in the plurality of columns, a first complete column of the power external connectors between the first receive connector group and the first transmit connector group; The first receiving connector of the first die is correspondingly coupled to the first transmitting connector of the second die; and The first transmitting connector of the first die is correspondingly coupled to the first receiving connector of the second die.

10. The integrated circuit device according to claim 9, wherein: In the first grain, The receiving connector further includes a second receiving connector set of a plurality of second receiving connectors in the receiving connector; The transmitting connector further includes a second transmitting connector set of a plurality of second transmitting connectors in the transmitting connector, The first receiving connector group is arranged along a row direction of the plurality of rows between the second receiving connector group and the first transmitting connector group; The first transmitting connector group is arranged between the second transmitting connector group and the first receiving connector group along the row direction; The power external connector further comprises: a second complete row of said power external connectors between said first receiving connector set and said second receiving connector set; a third complete row of said power external connectors between said first launch connector set and said second launch connector set; and There are two complete terminal rows of the power external connector with the first receiving connector group, the second receiving connector group, the first transmitting connector group, and the second transmitting connector group arranged therebetween.

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