Multi-range self-cleaning flow chip

Abstract

The utility model relates to a multi-range self-cleaning flow chip. The light emitting diode comprises a substrate; a supporting structure layer; a platinum thermal resistance wire layer; a first insulating layer; the lower thermopile and the central heat source are respectively arranged on the first insulating layer; the upper thermopile of the second insulating layer is arranged on the second insulating layer; a third insulating layer; connecting a wire structure; the upstream temperature measuring element thermopile lower-layer thermocouple and the upstream temperature measuring element thermopile upper-layer thermocouple form an upstream temperature measuring element thermopile; the downstream temperature measuring element thermopile lower-layer thermocouple and the downstream temperature measuring element thermopile upper-layer thermocouple form a downstream temperature measuring element thermopile; the plurality of groups of central heat sources are arranged side by side along the longitudinal direction of the chip; isolation through holes are released from the front surfaces between the thermopiles of the adjacent upstream temperature measuring elements and between the thermopiles of the adjacent downstream temperature measuring elements. According to the utility model, the effects of multi-range test, self-cleaning and low power consumption are realized.

Description

Technical Field

[0001] The utility model relates to the technical field of flow sensors, in particular to a multi-range self-cleaning flow chip. Background Art

[0002] Thermal flow sensor is a flow sensor based on thermal sensing, which can be used to measure the flow of gas and liquid. It mainly includes hot wire sensor, compensation circuit, temperature compensation circuit and operational amplifier. Thermal flow sensor has been widely used in many fields due to its advantages of high precision, fast response speed and not easily affected by the medium. The main application areas include industrial automation, air conditioning, automobile industry, medical equipment, robots, etc. Existing flow chips have the following problems:

[0003] After long-term use, the sensitive area of ​​the temperature measuring element of the existing flow chip is prone to moisture and dirt, resulting in reduced measurement accuracy and requiring regular cleaning and maintenance.

[0004] Due to the limitation of the chip end, it is difficult to adjust different ranges through the chip itself. Therefore, the existing flow chip can usually only provide a fixed range, which can only be compensated by external circuit and flow channel structure design, which increases the complexity of design and implementation and is difficult to meet the needs of different application scenarios for multiple ranges.

[0005] There is a situation where the power consumption is relatively high, which not only increases the cost of use, but also limits its application in certain scenarios where power supply is limited or low power consumption is required; there are certain limitations in measurement accuracy and resolution, which affects its use in some high-precision applications. Summary of the invention

[0006] To this end, the utility model provides a multi-range self-cleaning flow chip, which achieves the effects of multi-range testing, self-cleaning and low power consumption.

[0007] In order to solve the above technical problems, the utility model provides a multi-range self-cleaning flow chip, comprising:

[0008] substrate;

[0009] A supporting structure layer is disposed on the substrate;

[0010] A platinum thermal resistance wire layer is arranged on the supporting structure layer;

[0011] A first insulating layer, disposed on the supporting structure layer;

[0012] The lower thermopile and the central heat source are respectively arranged on the first insulating layer; wherein the lower thermopile includes a lower thermocouple of an upstream temperature measuring element thermopile and a lower thermocouple of a downstream temperature measuring element thermopile, and each group of the central heat source includes an upstream heating element heat source thermocouple, a central heating element heat source thermocouple and a downstream heating element heat source thermocouple sequentially arranged in the transverse direction;

[0013] a second insulating layer, covering the lower thermopile and each of the central heat sources;

[0014] An upper thermopile is disposed on the second insulating layer, and the upper thermopile includes an upper thermocouple of an upstream temperature measuring element thermopile and an upper thermocouple of a downstream temperature measuring element thermopile;

[0015] a third insulating layer, covering the upper thermopile;

[0016] A connecting wire structure, penetrating the third insulating layer, to respectively realize the connection between the lower thermopile and the upper thermopile, the connection of the central heat source and the connection of the platinum thermal resistance wire layer;

[0017] The thermocouple of the lower layer of the upstream temperature measuring element thermopile and the thermocouple of the upper layer of the upstream temperature measuring element thermopile constitute the upstream temperature measuring element thermopile; the thermocouple of the lower layer of the downstream temperature measuring element thermopile and the thermocouple of the upper layer of the downstream temperature measuring element thermopile constitute the downstream temperature measuring element thermopile;

[0018] A plurality of groups of central heat sources are arranged side by side along the longitudinal direction of the chip;

[0019] Wherein, a plurality of groups of thermopile temperature measuring elements are provided and symmetrically distributed along the transverse symmetrical section of the chip, and each group of thermopile temperature measuring elements includes a plurality of rows of upstream temperature measuring element thermopiles and a corresponding plurality of rows of downstream temperature measuring element thermopiles;

[0020] Among them, there are front-side release isolation through holes between adjacent upstream temperature measuring element thermoelectric piles and between adjacent downstream temperature measuring element thermoelectric piles.

[0021] In one embodiment of the present invention, a back side release cavity is provided on the back side of the substrate, and the front side release isolation through hole extends to the back side release cavity.

[0022] In one embodiment of the present utility model, the central heat source and the thermopile temperature measuring elements are respectively provided in three groups.

[0023] In one embodiment of the present invention, in each group of the thermopile temperature measuring elements, two adjacent groups of the upstream temperature measuring element thermopile and two adjacent groups of the downstream temperature measuring element thermopile are connected via wires.

[0024] In one embodiment of the utility model, the transverse symmetry axis of the chip passes through the central heat source located in the middle, and the upstream heating element heat source thermocouple, the central heating element heat source thermocouple and the downstream heating element heat source thermocouple in each group of the central heat source are arranged in sequence along the transverse direction, thereby correspondingly constituting an upstream heating resistor R1, an upstream heating resistor R2, an upstream heating resistor R3, a central heating resistor R4, a central heating resistor R5, a central heating resistor R6, a downstream heating resistor R7, a downstream heating resistor R8 and a downstream heating resistor R9, and the upstream heating resistor R1, the upstream heating resistor R2, the upstream heating resistor R3, the central heating resistor R4, the central heating resistor R5, the central heating resistor R6, the downstream heating resistor R7, the downstream heating resistor R8 and the downstream heating resistor R9 are connected in series and / or in parallel.

[0025] In one embodiment of the utility model, all of the thermopile temperature measuring elements include an upstream heating resistor R1 supporting a positive electrode of a thermopile temperature measuring element, an upstream heating resistor R1 supporting a negative electrode of a thermopile temperature measuring element, an upstream heating resistor R2 supporting a positive electrode of a thermopile temperature measuring element, an upstream heating resistor R2 supporting a negative electrode of a thermopile temperature measuring element, an upstream heating resistor R3 supporting a positive electrode of a thermopile temperature measuring element, an upstream heating resistor R3 supporting a negative electrode of a thermopile temperature measuring element, a downstream heating resistor R7 supporting a positive electrode of a thermopile temperature measuring element, a downstream heating resistor R7 supporting a negative electrode of a thermopile temperature measuring element, a downstream heating resistor R8 supporting a positive electrode of a thermopile temperature measuring element, a downstream heating resistor R8 supporting a negative electrode of a thermopile temperature measuring element, a downstream heating resistor R9 supporting a positive electrode of a thermopile temperature measuring element, and a downstream heating resistor R9 supporting a negative electrode of a thermopile temperature measuring element;

[0026] The central heat source includes a central heating element heat source wire symmetrically arranged along the transverse symmetry axis of the chip to heat the positive electrode, and a central heating element heat source wire to heat the negative electrode;

[0027] The platinum thermal resistance wire layer includes an upstream platinum thermal resistance wire positive electrode, an upstream platinum thermal resistance wire negative electrode, a downstream platinum thermal resistance wire positive electrode and a downstream platinum thermal resistance wire negative electrode.

[0028] In one embodiment of the utility model, the connecting wire structure includes an upstream temperature measuring element thermopile cold end connecting wire structure connected to the lower thermocouple of the upstream temperature measuring element thermopile, an upstream temperature measuring element thermopile hot end connecting wire structure connected between the lower thermocouple of the upstream temperature measuring element thermopile and the upper thermocouple of the upstream temperature measuring element thermopile, a downstream temperature measuring element thermopile cold end connecting wire structure connected to the lower thermocouple of the downstream temperature measuring element thermopile, a downstream temperature measuring element thermopile hot end connecting wire structure connected between the lower thermocouple of the downstream temperature measuring element thermopile and the upper thermocouple of the downstream temperature measuring element thermopile, an upstream heating element heat source connecting wire structure connected to the upstream heating element heat source thermocouple, a central heating element heat source connecting wire structure connected to the central heating element heat source thermocouple, a downstream heating element heat source connecting wire structure connected to the downstream heating element heat source thermocouple, and an upstream resistance wire connecting wire structure and a downstream resistance wire connecting wire structure connected to the platinum thermal resistance wire layer.

[0029] In one implementation of the utility model, the platinum thermal resistance wire layer is serpentine, and the front release isolation through hole passes through the serpentine gap formed by the platinum thermal resistance wire layer.

[0030] In one embodiment of the present invention, the support structure layer includes a first silicon oxide support layer, a silicon nitride support layer and a second silicon oxide support layer which are sequentially arranged on the surface of the substrate.

[0031] In one embodiment of the utility model, a passivation layer is provided on the surface of the third insulating layer, and the front release isolation through hole sequentially penetrates the passivation layer, the third insulating layer, the second insulating layer, the first insulating layer, the second silicon oxide support layer, the silicon nitride support layer and the first silicon oxide support layer.

[0032] The above technical solution of the utility model has the following advantages compared with the prior art:

[0033] The multi-range self-cleaning flow chip described in the utility model designs the central heat source into a "non" structure and adopts a combination of thermal resistors of various lengths so that the spacing between the central heating resistor element and the temperature measuring element is different, thereby achieving flow measurement requirements of different ranges. In order to further expand the possibility of range measurement, a cross-series and parallel design of multiple groups of thermal resistors is adopted, and the series-parallel structure is adjusted in combination with laser ablation, thereby realizing multi-range testing of a single chip and meeting measurement requirements of different ranges. At the same time, the multiple groups of thermal resistors working with the central heat source are also used for measurements of different ranges, and the remaining thermal resistors disconnected by laser ablation and their corresponding temperature measuring thermopiles can be used to monitor the ambient temperature and serve as a control group to eliminate background interference factors.

[0034] The insulating layer between the thermocouple pairs of adjacent temperature measuring elements is released by etching on the front and back sides to form an isolation through-hole. Because of the separation of the back heat transfer channel, the temperature measuring element is more sensitive to heat at this time. Therefore, the central heat source only needs a very small voltage to drive the temperature measuring element to sense the heat change, thereby improving the overall resolution of the chip and reducing the chip power consumption.

[0035] By designing a set of "snake-shaped" platinum thermal resistance wire layers under the functional layer of the temperature measuring element, after each use, the platinum thermal resistance wire is powered with high voltage to self-clean the chip of some water vapor and dirt attached to the sensitive area of ​​the temperature measuring element, thereby not affecting the accuracy of the flow chip when used next time. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to make the content of the utility model more clearly understood, the utility model is further described in detail below based on specific embodiments of the utility model in combination with the accompanying drawings.

[0037] Figure 1 It is a schematic structural diagram of a transverse sectional view (XX' axis) of the utility model.

[0038] Figure 2 It is a longitudinal sectional view (YY' axis) structural schematic diagram of the utility model.

[0039] Figure 3 It is a schematic diagram of the chip structure from a top view of the utility model.

[0040] Figure 4 It is a schematic diagram of the chip thermopile temperature measuring element, the "snake-shaped" platinum thermal resistance wire layer and the front release isolation through hole of the utility model.

[0041] Figure 5 It is a schematic diagram of the serpentine platinum thermal resistor wire layer and the front release isolation through hole of the utility model.

[0042] Figure 6 It is a schematic diagram of three groups of thermopile temperature measuring elements and front release isolation through holes of the utility model.

[0043] Figure 7 It is a schematic diagram of a thermopile temperature measuring element of the utility model.

[0044] Figure 8 It is the equivalent original diagram of the range-adjustable circuit of the utility model.

[0045] Description of the Figures in the Specification:

[0046] 1. Substrate;

[0047] 2. A first silicon oxide support layer;

[0048] 3. Silicon nitride support layer;

[0049] 4. A second silicon oxide support layer;

[0050] 5a, the thermocouple of the lower layer of the thermopile of the upstream temperature measuring element; 5b, the thermocouple of the lower layer of the thermopile of the downstream temperature measuring element;

[0051] 6a, upstream heating element heat source thermocouple; 6b, central heating element heat source thermocouple; 6c, downstream heating element heat source thermocouple;

[0052] 7a, a first insulating layer; 7b, a second insulating layer; 7c, a third insulating layer;

[0053] 8a, upper thermocouple of the thermopile of the upstream temperature measuring element; 8b, upper thermocouple of the thermopile of the downstream temperature measuring element;

[0054] 91. The cold end connection wire structure of the thermopile of the upstream temperature measuring element; 92. The hot end connection wire structure of the thermopile of the upstream temperature measuring element; 93. The heat source connection wire structure of the upstream heating element; 94. The heat source connection wire structure of the central heating element; 95. The heat source connection wire structure of the downstream heating element; 96. The cold end connection wire structure of the thermopile of the downstream temperature measuring element; 97. The hot end connection wire structure of the thermopile of the downstream temperature measuring element; 98. The upstream resistance wire connection wire structure; 99. The downstream resistance wire connection wire structure;

[0055] 10. Passivation layer;

[0056] 11. Platinum thermal resistance wire layer;

[0057] 12. Front release isolation through hole;

[0058] 13. Back release cavity;

[0059] 1-1. Upstream heating resistor R1 is equipped with positive electrode of thermopile temperature measuring element; 1-2. Upstream heating resistor R1 is equipped with negative electrode of thermopile temperature measuring element; 1-3. Upstream heating resistor R2 is equipped with positive electrode of thermopile temperature measuring element; 1-4. Upstream heating resistor R2 is equipped with negative electrode of thermopile temperature measuring element; 1-5. Upstream heating resistor R3 is equipped with positive electrode of thermopile temperature measuring element; 1-6. Upstream heating resistor R3 is equipped with negative electrode of thermopile temperature measuring element; 1-7. Downstream heating resistor R7 is equipped with positive electrode of thermopile temperature measuring element; 1-8. Downstream heating resistor R7 is equipped with negative electrode of thermopile temperature measuring element; 1- 9. Downstream heating resistor R8 is equipped with positive electrode of thermopile temperature measuring element; 1-10. Downstream heating resistor R8 is equipped with negative electrode of thermopile temperature measuring element; 1-11. Downstream heating resistor R9 is equipped with positive electrode of thermopile temperature measuring element; 1-12. Downstream heating resistor R9 is equipped with negative electrode of thermopile temperature measuring element; 1-13. Central heating element heat source wire heating positive electrode; 1-14. Central heating element heat source wire heating negative electrode; 1-15. Upstream platinum thermal resistance wire positive electrode; 1-16. Upstream platinum thermal resistance wire negative electrode; 1-17. Downstream platinum thermal resistance wire positive electrode; 1-18. Downstream platinum thermal resistance wire negative electrode. DETAILED DESCRIPTION

[0060] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0061] Reference Figures 1 to 3 As shown, a multi-range self-cleaning flow chip of the utility model comprises:

[0062] Substrate 1;

[0063] A supporting structure layer, disposed on the substrate 1;

[0064] The platinum thermal resistance wire layer 11 is arranged on the supporting structure layer;

[0065] A first insulating layer 7a, disposed on the supporting structure layer;

[0066] The lower thermopile and the central heat source are respectively arranged on the first insulating layer 7a; wherein the lower thermopile includes an upstream temperature measuring element thermopile lower thermocouple 5a and a downstream temperature measuring element thermopile lower thermocouple 5b, and each group of the central heat source includes an upstream heating element heat source thermocouple 6a, a central heating element heat source thermocouple 6b and a downstream heating element heat source thermocouple 6c arranged in sequence along the transverse direction;

[0067] A second insulating layer 7b, covering the lower thermopile and each of the central heat sources;

[0068] An upper thermopile is arranged on the second insulating layer 7b, and the upper thermopile includes an upper thermocouple 8a of an upstream temperature measuring element thermopile and an upper thermocouple 8b of a downstream temperature measuring element thermopile;

[0069] A third insulating layer 7c, covering the upper thermopile;

[0070] A connecting wire structure, penetrating the third insulating layer 7c, to respectively realize the connection between the lower thermopile and the upper thermopile, the connection of the central heat source and the connection of the platinum thermal resistance wire layer 11;

[0071] The lower thermocouple 5a of the upstream temperature measuring element thermopile and the upper thermocouple 8a of the upstream temperature measuring element thermopile constitute the upstream temperature measuring element thermopile; the lower thermocouple 5b of the downstream temperature measuring element thermopile and the upper thermocouple 8b of the downstream temperature measuring element thermopile constitute the downstream temperature measuring element thermopile;

[0072] A plurality of groups of central heat sources are arranged side by side along the longitudinal direction (YY' axis direction) of the chip;

[0073] Wherein, a plurality of groups of thermopile temperature measuring elements are provided and symmetrically distributed along the transverse symmetrical section of the chip, and each group of thermopile temperature measuring elements includes a plurality of rows of upstream temperature measuring element thermopiles and a corresponding plurality of rows of downstream temperature measuring element thermopiles;

[0074] Among them, the front release isolation through holes 12 are provided between the adjacent upstream temperature measuring element thermoelectric piles and between the adjacent downstream temperature measuring element thermoelectric piles.

[0075] Specifically, a back side release cavity 13 is provided on the back side of the substrate 1 , and the front side release isolation through hole 12 extends to the back side release cavity 13 .

[0076] Through bidirectional release etching on the front and back sides, the insulating layer between the adjacent thermocouple pairs of the temperature measuring element is isolated by forming an isolation through hole, thereby isolating the back heat transfer channel and improving the sensitivity of the temperature measuring element to heat. This allows the central heat source to be driven by only a small voltage, and the temperature measuring element can sense the heat change, thereby improving the overall resolution of the chip and reducing the chip power consumption.

[0077] Specifically, the central heat source and the thermopile temperature measuring elements are respectively provided in three groups.

[0078] Specifically, in each group of the thermopile temperature measuring elements, two adjacent groups of the upstream temperature measuring element thermopile and two adjacent groups of the downstream temperature measuring element thermopile are connected via wires.

[0079] Specifically, refer to Figure 3As shown, the transverse symmetry axis (XX' axis) of the chip passes through the central heat source located in the middle, and the upstream heating element heat source thermocouple 6a, the central heating element heat source thermocouple 6b and the downstream heating element heat source thermocouple 6c in each group of the central heat source are arranged in sequence along the transverse direction, thereby correspondingly constituting an upstream heating resistor R1, an upstream heating resistor R2, an upstream heating resistor R3, a central heating resistor R4, a central heating resistor R5, a central heating resistor R6, a downstream heating resistor R7, a downstream heating resistor R8 and a downstream heating resistor R9, and the upstream heating resistor R1, the upstream heating resistor R2, the upstream heating resistor R3, the central heating resistor R4, the central heating resistor R5, the central heating resistor R6, the downstream heating resistor R7, the downstream heating resistor R8 and the downstream heating resistor R9 are connected in series and / or in parallel.

[0080] Specifically, all of the thermopile temperature measuring elements include a positive electrode 1-1 of a thermopile temperature measuring element supporting an upstream heating resistor R1, a negative electrode 1-2 of a thermopile temperature measuring element supporting an upstream heating resistor R1, a positive electrode 1-3 of a thermopile temperature measuring element supporting an upstream heating resistor R2, a negative electrode 1-4 of a thermopile temperature measuring element supporting an upstream heating resistor R2, a positive electrode 1-5 of a thermopile temperature measuring element supporting an upstream heating resistor R3, a negative electrode 1-6 of a thermopile temperature measuring element supporting an upstream heating resistor R3, a positive electrode 1-7 of a thermopile temperature measuring element supporting a downstream heating resistor R7, a negative electrode 1-8 of a thermopile temperature measuring element supporting a downstream heating resistor R7, a positive electrode 1-9 of a thermopile temperature measuring element supporting a downstream heating resistor R8, a negative electrode 1-10 of a thermopile temperature measuring element supporting a downstream heating resistor R8, a positive electrode 1-11 of a thermopile temperature measuring element supporting a downstream heating resistor R9, and a negative electrode 1-12 of a thermopile temperature measuring element supporting a downstream heating resistor R9;

[0081] The central heat source includes a central heating element heat source wire symmetrically arranged along the transverse symmetry axis of the chip to heat the positive electrode 1-13 and a central heating element heat source wire to heat the negative electrode 1-14;

[0082] The platinum thermal resistance wire layer 11 includes an upstream platinum thermal resistance wire positive electrode 1-15, an upstream platinum thermal resistance wire negative electrode 1-16, a downstream platinum thermal resistance wire positive electrode 1-17 and a downstream platinum thermal resistance wire negative electrode 1-18.

[0083] Specifically, the connecting wire structure includes an upstream temperature measuring element thermopile cold end connecting wire structure 91 connected to the upstream temperature measuring element thermopile lower thermocouple 5a, an upstream temperature measuring element thermopile hot end connecting wire structure 92 connected between the upstream temperature measuring element thermopile lower thermocouple 5a and the upstream temperature measuring element thermopile upper thermocouple 8a, a downstream temperature measuring element thermopile cold end connecting wire structure 96 connected to the downstream temperature measuring element thermopile lower thermocouple 5b, and a downstream temperature measuring element thermopile cold end connecting wire structure 97 connected to the downstream temperature measuring element thermopile lower thermocouple 5b and the downstream temperature measuring element thermopile upper thermocouple 8a. The downstream temperature measuring element thermopile hot end connecting wire structure 97 between the upper thermocouple 8b of the temperature measuring element thermopile, the upstream heating element heat source connecting wire structure 93 connected to the upstream heating element heat source thermocouple 6a, the central heating element heat source connecting wire structure 94 connected to the central heating element heat source thermocouple 6b, the downstream heating element heat source connecting wire structure 95 connected to the downstream heating element heat source thermocouple 6c, and the upstream resistance wire connecting wire structure 98 and the downstream resistance wire connecting wire structure 99 connected to the platinum thermal resistance wire layer 11.

[0084] In this embodiment, refer to Figure 5 As shown, the platinum thermal resistance wire layer 11 is in a "snake shape", and the front release isolation through hole 12 passes through the serpentine gap formed by the platinum thermal resistance wire layer 11. The platinum thermal resistance wire layer 115 includes two groups, which are respectively formed under the cold ends of the upstream temperature measuring element thermopile and the downstream temperature measuring element thermopile. A high voltage power supply of 5-10V is supplied to them through (the upstream resistance wire connecting wire structure 98 and the downstream resistance wire connecting wire structure 99) to achieve self-cleaning treatment of water vapor and dirt attached to the sensitive area of ​​the temperature measuring element, thereby ensuring that the accuracy is not affected when used next time.

[0085] Specifically, the support structure layer includes a first silicon oxide support layer 2, a silicon nitride support layer 3 and a second silicon oxide support layer 4 sequentially arranged on the surface of the substrate 1. A passivation layer 10 is arranged on the surface of the third insulating layer 7c, and the front release isolation through hole 12 sequentially penetrates the passivation layer 10, the third insulating layer 7c, the second insulating layer 7b, the first insulating layer 7a, the second silicon oxide support layer 4, the silicon nitride support layer 3 and the first silicon oxide support layer 2.

[0086] Through the above structure, the central heat source is in a "non" shape. The nine groups of resistors (R1-R9) of the central heat source can be connected in series or in parallel through laser ablation. The lengths of resistors R1-R9 can be set to be not completely equal, and the total resistance of the central heat source can be adjusted, so that the heating power and total heat of the central heat source are different. Therefore, when the upstream and downstream temperature measuring elements receive the same flow, they will produce different output sizes to adjust the different ranges of the whole chip. For example, when it is necessary to measure a small range flow, due to the change of the small flow, the chip needs to have higher sensitivity and resolution at the same input voltage. The central heat source can be connected in series and parallel by means of laser ablation to achieve the central heat source connection mode with the largest total resistance and the largest heat generation, so that the temperature measuring element has a larger output voltage and greater sensitivity at a small flow rate, meeting the needs of small range flow measurement.

[0087] When it is necessary to measure a large range of flow, because the range requirement is relatively large, the chip needs to have a change in output under a large range of flow under the same input voltage and is not saturated. Therefore, it is necessary to adjust the series-parallel mode of the central heat source to achieve a central heat source connection mode with the minimum total resistance and the minimum heat generation, so that the temperature measuring element can still have changes and output at a large flow rate to meet the needs of large-range flow measurement. By designing multiple groups of thermal resistors in cross-series and parallel, combined with laser ablation to adjust the series-parallel structure to meet the measurement of different ranges of flow. A single chip can meet the measurement needs of multiple ranges.

[0088] The equivalent original diagram of the adjustable range circuit of the central heat source is as follows Figure 8 As shown, different equivalent circuit diagrams can be formed by different laser ablation methods.

[0089] Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solution of the utility model rather than to limit it. Although the utility model has been described in detail with reference to examples, ordinary technicians in the field should understand that the technical solution of the utility model can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the utility model, which should be included in the scope of the claims of the utility model.

Claims

1. A multi-range self-cleaning flow chip, characterized in that: include: Substrate (1); A supporting structure layer, arranged on the substrate (1); A platinum thermal resistance wire layer (11) is arranged on the supporting structure layer; A first insulating layer (7a) is arranged on the supporting structure layer; The lower thermopile and the central heat source are respectively arranged on the first insulating layer (7a); wherein the lower thermopile comprises an upstream temperature measuring element thermopile lower thermocouple (5a) and a downstream temperature measuring element thermopile lower thermocouple (5b), and each group of the central heat source comprises an upstream heating element heat source thermocouple (6a), a central heating element heat source thermocouple (6b) and a downstream heating element heat source thermocouple (6c) arranged in sequence in the transverse direction; A second insulating layer (7b), covering the lower thermopile and each of the central heat sources; An upper thermopile is arranged on the second insulating layer (7b), the upper thermopile comprising an upper thermocouple (8a) of an upstream temperature measuring element thermopile and an upper thermocouple (8b) of a downstream temperature measuring element thermopile; A third insulating layer (7c), covering the upper thermopile; A connecting wire structure, which penetrates the third insulating layer (7c), so as to respectively realize the connection between the lower thermopile and the upper thermopile, the connection of the central heat source, and the connection of the platinum thermal resistance wire layer (11); The lower thermocouple (5a) of the upstream temperature measuring element thermopile and the upper thermocouple (8a) of the upstream temperature measuring element thermopile constitute the upstream temperature measuring element thermopile; the lower thermocouple (5b) of the downstream temperature measuring element thermopile and the upper thermocouple (8b) of the downstream temperature measuring element thermopile constitute the downstream temperature measuring element thermopile; A plurality of groups of central heat sources are arranged side by side along the longitudinal direction of the chip; Wherein, a plurality of groups of thermopile temperature measuring elements are provided and symmetrically distributed along the transverse symmetrical section of the chip, and each group of thermopile temperature measuring elements includes a plurality of rows of upstream temperature measuring element thermopiles and a corresponding plurality of rows of downstream temperature measuring element thermopiles; Wherein, front-side release isolation through holes (12) are provided between adjacent upstream temperature measuring element thermoelectric piles and between adjacent downstream temperature measuring element thermoelectric piles.

2. A multi-range self-cleaning flow chip according to claim 1, characterized in that: A back release cavity (13) is provided on the back side of the substrate (1), and the front release isolation through hole (12) extends to the back release cavity (13).

3. A multi-range self-cleaning flow chip according to claim 1, characterized in that: The central heat source and the thermopile temperature measuring elements are respectively provided in three groups.

4. A multi-range self-cleaning flow chip according to claim 3, characterized in that: In each group of the thermopile temperature measuring elements, two adjacent groups of the upstream temperature measuring element thermopile and two adjacent groups of the downstream temperature measuring element thermopile are connected via wires.

5. The multi-range self-cleaning flow chip according to claim 3, characterized in that: The transverse symmetry axis of the chip passes through the central heat source located in the middle, and the upstream heating element heat source thermocouple (6a), the central heating element heat source thermocouple (6b) and the downstream heating element heat source thermocouple (6c) in each group of the central heat source are arranged in sequence along the transverse direction, thereby correspondingly forming an upstream heating resistor R1, an upstream heating resistor R2, an upstream heating resistor R3, a central heating resistor R4, a central heating resistor R5, a central heating resistor R6, a downstream heating resistor R7, a downstream heating resistor R8 and a downstream heating resistor R9, and the upstream heating resistor R1, the upstream heating resistor R2, the upstream heating resistor R3, the central heating resistor R4, the central heating resistor R5, the central heating resistor R6, the downstream heating resistor R7, the downstream heating resistor R8 and the downstream heating resistor R9 are connected in series and / or in parallel.

6. A multi-range self-cleaning flow chip according to claim 4, characterized in that: All of the thermopile temperature measuring elements include a positive electrode (1-1) of a thermopile temperature measuring element supporting an upstream heating resistor R1, a negative electrode (1-2) of a thermopile temperature measuring element supporting an upstream heating resistor R1, a positive electrode (1-3) of a thermopile temperature measuring element supporting an upstream heating resistor R2, a negative electrode (1-4) of a thermopile temperature measuring element supporting an upstream heating resistor R2, a positive electrode (1-5) of a thermopile temperature measuring element supporting an upstream heating resistor R3, a negative electrode (1-6) of a thermopile temperature measuring element supporting an upstream heating resistor R3, a positive electrode (1-7) of a thermopile temperature measuring element supporting a downstream heating resistor R7, a negative electrode (1-8) of a thermopile temperature measuring element supporting a downstream heating resistor R7, a positive electrode (1-9) of a thermopile temperature measuring element supporting a downstream heating resistor R8, a negative electrode (1-10) of a thermopile temperature measuring element supporting a downstream heating resistor R8, a positive electrode (1-11) of a thermopile temperature measuring element supporting a downstream heating resistor R9, and a negative electrode (1-12) of a thermopile temperature measuring element supporting a downstream heating resistor R9; The central heat source comprises a central heating element heat source wire symmetrically arranged along the transverse symmetry axis of the chip to heat the positive electrode (1-13) and a central heating element heat source wire to heat the negative electrode (1-14); The platinum thermal resistance wire layer (11) comprises an upstream platinum thermal resistance wire positive electrode (1-15), an upstream platinum thermal resistance wire negative electrode (1-16), a downstream platinum thermal resistance wire positive electrode (1-17) and a downstream platinum thermal resistance wire negative electrode (1-18).

7. The multi-range self-cleaning flow chip according to claim 1, characterized in that: The connecting wire structure comprises an upstream temperature measuring element thermopile cold end connecting wire structure (91) connected to the upstream temperature measuring element thermopile lower layer thermocouple (5a), an upstream temperature measuring element thermopile hot end connecting wire structure (92) connected between the upstream temperature measuring element thermopile lower layer thermocouple (5a) and the upstream temperature measuring element thermopile upper layer thermocouple (8a), a downstream temperature measuring element thermopile cold end connecting wire structure (96) connected to the downstream temperature measuring element thermopile lower layer thermocouple (5b), and a downstream temperature measuring element thermopile cold end connecting wire structure (97) connected to the downstream temperature measuring element thermopile lower layer thermocouple (5b) and the downstream temperature measuring element thermopile. A downstream temperature measuring element thermopile hot end connecting wire structure (97) between the upper thermocouples (8b) of the stack, an upstream heating element heat source connecting wire structure (93) connected to the upstream heating element heat source thermocouple (6a), a central heating element heat source connecting wire structure (94) connected to the central heating element heat source thermocouple (6b), a downstream heating element heat source connecting wire structure (95) connected to the downstream heating element heat source thermocouple (6c), and an upstream resistance wire connecting wire structure (98) and a downstream resistance wire connecting wire structure (99) connected to the platinum thermal resistance wire layer (11).

8. The multi-range self-cleaning flow chip according to claim 1, characterized in that: The platinum thermal resistance wire layer (11) is in a serpentine shape, and the front release isolation through hole (12) passes through a serpentine gap formed by the platinum thermal resistance wire layer (11).

9. The multi-range self-cleaning flow chip according to claim 1, characterized in that: The support structure layer comprises a first silicon oxide support layer (2), a silicon nitride support layer (3) and a second silicon oxide support layer (4) which are sequentially arranged on the surface of the substrate (1).

10. The multi-range self-cleaning flow chip according to claim 9, characterized in that: A passivation layer (10) is provided on the surface of the third insulating layer (7c), and the front release isolation through hole (12) sequentially penetrates the passivation layer (10), the third insulating layer (7c), the second insulating layer (7b), the first insulating layer (7a), the second silicon oxide support layer (4), the silicon nitride support layer (3) and the first silicon oxide support layer (2).

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