Zero line and live line exchange detection circuit and detection device

Abstract

The utility model discloses a null line and live line switching detection circuit and detection device. The detection circuit comprises a main control unit, and a voltage acquisition unit and an adjustment control unit which are connected with the main control unit. The voltage acquisition unit is used for acquiring the current voltage; the adjusting control unit comprises a plurality of adjusting control branches, and each adjusting control branch is provided with an adjusting resistor, a diode group, a field effect transistor and an adjusting capacitor which are sequentially connected in series; the main control unit is provided with an initial capacitor, one end of the initial capacitor is grounded, and the other end of the initial capacitor is connected with the plurality of adjusting capacitors and then is connected to the main control unit. One end of the adjusting capacitor is connected to the main control unit, the other end of the adjusting capacitor is connected with a drain electrode of the field effect transistor, a grid electrode of the field effect transistor is connected with the diode group, the other end of the diode group is connected with the adjusting capacitor, and the detection precision of zero and live wire exchange detection is effectively improved.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic circuits, and in particular relates to a zero-live wire swap detection circuit and a detection device. Background Art

[0002] With the development of electricity meters, the market has higher and higher requirements on the functions, installation, and maintenance of electricity meters. Electricity meters are important metering equipment in the electricity consumption of residential users. During the installation of electricity meters, special attention should be paid to the wiring of the neutral and live wires. If the neutral and live wires are connected reversely, that is, the neutral wire is connected to the live wire terminal on the meter, and the live wire is connected to the neutral wire terminal on the meter, the user's electrical equipment may be energized when it is turned off because the live wire is not disconnected, thereby causing electricity accidents.

[0003] However, the current commonly used neutral-live swap detection function on the market has relatively high requirements for the power grid environment, requiring a small grid voltage fluctuation range. In a grid environment with large grid voltage fluctuations, it is difficult to stably and accurately detect whether the neutral and live wires are swapped using conventional live-neutral swap detection methods. Therefore, how to provide a detection circuit that can accurately detect whether the neutral and live wires are swapped is an urgent problem to be solved. Utility Model Content

[0004] The present application provides a zero-live wire swap detection circuit and a detection device to solve the problem of how to accurately detect whether the zero-live wire is swapped.

[0005] In order to solve the above technical problems, the present application provides a zero-live line exchange detection circuit, the circuit comprising a main control unit, and a voltage acquisition unit and a regulation control unit connected to the main control unit;

[0006] The voltage acquisition unit is used to acquire the current voltage;

[0007] The regulating control unit comprises a plurality of regulating control branches, each of which is provided with a regulating resistor, a diode group, a field effect transistor and a regulating capacitor connected in series in sequence;

[0008] The main control unit is provided with an initial capacitor, one end of the initial capacitor is grounded, and the other end of the initial capacitor is connected to the main control unit after being connected to a plurality of the adjustment capacitors.

[0009] As a further improvement of the present application, one end of the regulating capacitor is connected to the main control unit, the other end of the regulating capacitor is connected to the drain of the field effect transistor, the gate of the field effect transistor is connected to the diode group, the other end of the diode group is connected to the regulating capacitor, and the source of the field effect transistor is grounded.

[0010] As a further improvement of the present application, a preset capacitor is also arranged in parallel at both ends of the initial capacitor, one end of the initial capacitor and the preset capacitor are respectively connected to the main control unit, and the other end of the initial capacitor and the preset capacitor are connected to the ground.

[0011] As a further improvement of the present application, corresponding connection resistors are provided between the voltage acquisition unit and the main control unit, and between the voltage acquisition unit and each of the regulation control branches.

[0012] As a further improvement of the present application, the diode group includes a first diode and a second diode arranged in parallel;

[0013] The anode of the first diode and the cathode of the second diode are connected together and then connected to the regulating capacitor, and the cathode of the first diode and the anode of the second diode are connected together and then connected to the gate of the field effect transistor.

[0014] As a further improvement of the present application, the number of the regulating control branches N≤5;

[0015] Among them, the capacitance value of the initial capacitor is less than the capacitance value of the regulating capacitor corresponding to the first regulating control branch, less than the capacitance value of the regulating capacitor corresponding to the second regulating control branch, less than the capacitance value of the regulating capacitor corresponding to the third regulating control branch, less than the capacitance value of the regulating capacitor corresponding to the fourth regulating control branch, less than the capacitance value of the regulating capacitor corresponding to the fifth regulating control branch.

[0016] As a further improvement of the present application, the field effect transistor is an N-channel enhancement mode MOS transistor, and the parasitic output capacitance of the N-channel enhancement mode MOS transistor is less than 10 pF.

[0017] As a further improvement of the present application, an anti-parallel diode is arranged between the drain and the source of the field effect tube, the cathode of the anti-parallel diode is connected to the drain of the field effect tube, and the anode of the anti-parallel diode is connected to the source of the field effect tube.

[0018] As a further improvement of the present application, the main control unit includes a main control chip, and the voltage acquisition unit is connected to the VCC pin of the main control chip through the connection resistor to transmit the current voltage to the main control chip;

[0019] After the initial capacitor is connected to the plurality of adjustment capacitors, they are connected to the FILT0 pin of the main control chip; one end of the preset capacitor is connected to the FILT1 pin of the main control chip, and the other end of the preset capacitor is connected to the other end of the initial capacitor and the GND pin of the main control chip, and they are grounded together;

[0020] The OUT pin of the main control chip is connected to an output resistor for outputting the detection result.

[0021] The present application also provides a zero-live wire swap detection device, which includes any one of the zero-live wire swap detection circuits described above.

[0022] The present application provides a zero-live line switching detection circuit and detection device, which have the following beneficial effects:

[0023] The present application sets a voltage acquisition unit to collect the current grid voltage, sets a number of adjustment control branches, and sets an initial capacitor different from the adjustment capacitor in the main control unit, so that the main control unit adjusts the detection sensitivity value under the current voltage through a number of adjustment control branches, realizes automatic adjustment of the adaptive sensitivity capacitance value according to the grid environment, improves the applicability of the detection circuit, and effectively expands the grid voltage fluctuation range of the zero-live wire exchange detection; by adding N adjustment control branches, the detection sensitivity value is expanded from the default one sensitivity capacitance value to 2 N The sensitivity capacitance value improves the detection accuracy of the zero-live wire swapping detection, and can stably and accurately detect whether the zero-live wire is swapped even in a power grid environment with large power grid voltage fluctuations. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only part of the embodiments of the present application, rather than all the embodiments. For ordinary technicians in this field, without paying creative work, other drawings obtained based on these drawings all fall within the scope of protection of this application.

[0025] Figure 1 It is a structural schematic diagram of a zero-live line exchange detection circuit provided in an embodiment of the present application;

[0026] Figure 2 This is a specific embodiment diagram of a zero-live wire swap detection circuit provided in an embodiment of the present application;

[0027] Figure 3 It is a module connection diagram of a zero-live wire swap detection circuit provided in an embodiment of the present application;

[0028] Figure 4 It is a detection flow chart of a zero-live line exchange detection circuit provided in an embodiment of the present application;

[0029] Figure 5 It is a detection flow chart corresponding to the specific embodiment diagram in a zero-live wire swap detection circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0031] In order to make the description of the disclosed content more detailed and complete, the following is an illustrative description of the implementation methods and specific examples of the present application; however, this is not the only form of implementing or applying the specific embodiments of the present application. The implementation methods cover the features of multiple specific embodiments and the method steps and their sequences for constructing and operating these specific embodiments. However, other specific embodiments can also be used to achieve the same or equal functions and step sequences. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0033] In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" refers to two or more than two, and other quantifiers are similar. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application, and the embodiments of the present application and the features in the embodiments may be combined with each other without conflict.

[0034] In order to solve the problem of how to improve the voltage detection range of the zero-live wire swap detection and improve the accuracy of the detection results, please refer to Figure 1-Figure 5 , the present application embodiment proposes a zero-live line exchange detection circuit, please refer to Figure 3, which is a module connection diagram of a zero-live wire swapping detection circuit provided in an embodiment of the present application. The detection circuit includes a main control unit, and a voltage acquisition unit and an adjustment control unit connected to the main control unit; wherein the voltage acquisition unit is used to collect the current voltage, and the adjustment control unit includes a plurality of adjustment control branches, each of which is provided with a corresponding impedance element. The impedance element is a device or component used to reflect or detect the impedance of a certain power line in the field of electronic components, and usually refers to components such as resistors, capacitors, and inductors. In the embodiment of the present application, it is preferred to set the impedance element in the form of an adjustment capacitor.

[0035] It should be noted that as long as it can be connected to the main control unit, collect the current circuit voltage, and transmit the collected voltage data to the main control unit by wired or wireless means, any circuit structure of the voltage collection unit or voltage collection device is feasible, and this application does not impose any further restrictions on this.

[0036] Please refer to Figure 1 , which is a structural schematic diagram of a zero-live wire swapping detection circuit provided in an embodiment of the present application. It can be observed that the regulation control branch provided in the present application includes a regulation resistor, a diode group, a field effect transistor and a regulation capacitor connected in series in sequence. The main control unit is provided with an initial impedance element different from the above-mentioned impedance element. The above-mentioned initial impedance element is also set to the form of an initial capacitor. It can be observed that one end of the initial capacitor is connected to the above-mentioned several regulation capacitors and then connected to the main control unit together.

[0037] As an optional implementation, the main control unit provided in the present application is used to compare the current voltage with a preset voltage range to obtain a comparison result, and control the access status of several adjustment control branches according to the comparison result, so as to adjust the detection sensitivity value under the current voltage based on the initial capacitance through the adjustment capacitor corresponding to the adjustment control branch; since the present application sets the above-mentioned impedance element and the initial impedance element in the form of a capacitor, the detection sensitivity value at this time is specifically reflected as the sensitivity capacitance value corresponding to the voltage.

[0038] In a specific embodiment provided in the present application, it is preferred to connect one end of the regulating capacitor set in each regulating control branch to the main control unit, connect the other end of the regulating capacitor to the drain of the above-mentioned field effect transistor, connect the gate of the field effect transistor to the diode group, connect the other end of the diode group to the regulating capacitor, and set the source of the field effect transistor to be grounded.

[0039] Furthermore, the diode group includes a first diode and a second diode arranged in parallel, wherein the anode of the first diode and the cathode of the second diode are connected together and then connected to the adjustment capacitor, and the cathode of the first diode and the anode of the second diode are connected together and then connected to the gate of the field effect transistor; an anti-parallel diode is also arranged between the drain and the source of the field effect transistor, and it can be observed that the cathode of the anti-parallel diode is connected to the drain of the field effect transistor, and the anode of the anti-parallel diode is connected to the source of the field effect transistor.

[0040] As an optional implementation, the main control unit provided in the present application is used to receive the current voltage collected by the voltage collection unit, compare the current voltage with a preset voltage range to obtain a comparison result, and control the access status of several adjustment control branches according to the above comparison result, thereby adjusting the detection sensitivity value under the current voltage through the connected adjustment capacitor.

[0041] The above-mentioned preset voltage range is the range of allowable current voltage fluctuation determined based on the nominal voltage. The nominal voltage Un is the voltage value based on which the relevant performance of the instrument is confirmed. It is used to facilitate identification and selection of components. It is the closest standard voltage value and is different from the rated voltage commonly used in this field.

[0042] Furthermore, a preset capacitor is arranged in parallel at both ends of the initial capacitor, and one end of the preset capacitor and the initial capacitor are respectively connected to different interfaces of the main control unit, and the other ends of the preset capacitor and the initial capacitor are connected to the ground. At the same time, corresponding connection resistors are arranged between the voltage acquisition unit and the main control unit, and between the voltage acquisition unit and each regulation control branch; the output end of the main control unit is used to output the zero and live wire detection results, and an output resistor is arranged between the output end of the main control unit and the output lead LN_CHK.

[0043] It should be understood that the present application names the electronic components as initial capacitors, adjustable capacitors, preset capacitors, adjustable resistors, connection resistors, etc. according to the different functions realized by the components, in order to distinguish the functions that different capacitors and resistors can realize in the circuit. However, this does not mean that the adjustable capacitors, initial capacitors, and preset capacitors provided in the present application must be realized by using different capacitors, nor does it serve as a restriction on the specific models of capacitors and resistors.

[0044] Next, based on the above-mentioned voltage acquisition unit, main control unit and adjustment control unit, it is further described how the main control unit combines the adjustment capacitance of the connected control branch on the basis of the initial capacitance to adjust the detection sensitivity value under the current voltage, that is, the sensitivity capacitance value corresponding to the voltage.

[0045] In an embodiment of the present application, the voltage acquisition unit is used to collect the voltage value of the actual operation of the power grid at the current moment. Before the formal test, each regulation control branch is set to a low level state by default, and the field effect transistors in each regulation control branch are all in a non-conducting state. The main control unit will adjust a default value according to the induced electromotive force of the power grid at the current moment. The default value can be considered to be the capacitance value of the initial capacitor connected to the main control unit.

[0046] During the formal test process, the main control unit will receive the voltage value of the current power grid operation collected by the voltage acquisition unit, and compare the voltage value with the preset voltage range to obtain a comparison result. The preset voltage range applied in this application refers to the range of allowable current voltage fluctuations determined based on the nominal voltage Un.

[0047] Exemplarily, the regulation control unit provided in the present application is provided with N regulation control branches, including a first regulation control branch, a second regulation control branch, ..., and an Nth regulation control branch in sequence. The capacitance value of the initial capacitor is preferably set to be less than the capacitance value of the regulation capacitor corresponding to the first regulation control branch < the capacitance value of the regulation capacitor corresponding to the second regulation control branch < ... < the capacitance value of the regulation capacitor corresponding to the Nth regulation control branch.

[0048] It should be noted that when multiple adjustment control branches are provided, the capacitance value of the adjustment capacitor corresponding to each adjustment control branch increases successively. However, due to the limited capacitance values ​​that can be selected when actually selecting the adjustment capacitor, the multiple adjustment capacitors cannot be increased in a completely certain ratio. There may be a ratio relationship that is approximately equal to , or there may be a situation where the increasing rate becomes smaller and smaller, resulting in a situation where the distribution of each adjustment capacitor value becomes more and more dense. Therefore, the above methods of selecting the capacitance value of the adjustment capacitor are all feasible, and this application does not impose further restrictions on this.

[0049] Corresponding to the above N regulating control branches, there are 2 N The voltage preset ranges are, in sequence, a first preset voltage range, a second preset voltage range, ..., a second preset voltage range, N Preset voltage range, and satisfy 100%Un≥first preset voltage range>second preset voltage range>,......,>second preset voltage range N Preset voltage range, Un is the nominal voltage.

[0050] Please refer to Figure 4 , is a detection flow chart of a zero-live line exchange detection circuit provided in an embodiment of the present application, wherein the present application sequentially determines through the main control unit whether the current voltage is greater than or equal to the first preset voltage range, the second preset voltage range, ..., the second preset voltage range, ..., the second preset voltage range, ..., the second preset voltage range, ..., the second preset voltage range, ..., the first ... NPreset voltage range; when the main control unit determines that the current voltage is greater than or equal to the first preset voltage range, the N regulating control branches are controlled to be in a disconnected state; when the current voltage is determined to be greater than or equal to the second preset voltage range, the first regulating control branch is controlled to be in a connected state, and the remaining regulating control branches are all in a disconnected state; when the current voltage is determined to be greater than or equal to the third preset voltage range, the second regulating control branch is controlled to be in a connected state, and the remaining regulating control branches are all in a disconnected state; the above judgment actions are performed in sequence, and if it is determined that the current voltage is greater than or equal to the second preset voltage range, the second regulating control branch is controlled to be in a connected state, and the remaining regulating control branches are all in a disconnected state. N When the voltage range is preset, the N regulating control branches are all controlled to be in the connected state.

[0051] The present application also provides that when it is determined that the current voltage is less than the lowest value of the preset voltage range, the current voltage is not subjected to zero-live wire exchange detection; wherein the lowest value of the preset voltage range is 40% Un, and the second N The preset voltage range is ≥ the lowest value of the preset voltage range.

[0052] After the main control chip completes the above judgment action, it adjusts the detection sensitivity value under the current voltage based on the initial capacitance and the adjustment capacitance corresponding to the currently connected adjustment control branch; wherein the detection sensitivity value under the current voltage is the sum of the capacitance values ​​of the initial capacitance and several currently connected adjustment capacitors.

[0053] In a specific embodiment provided in this application, please refer to Figure 2 , is a specific embodiment diagram of a zero-live line exchange detection circuit provided in an embodiment of the present application. The present application describes in detail the process of obtaining the comparison result by comparing the above-mentioned circuits under the condition that N=2 is provided with two adjustment control branches.

[0054] It can be observed that in this specific embodiment, the main control unit includes a main control chip, which is provided with VCC, FILT0, GND, FILT1, and OUT pins, that is, the prior art is provided with a power pin, a ground pin, an output pin, and multiple input pins. Chips that can receive voltage data, control the levels of each branch, and perform data transmission are all feasible. Therefore, this application does not impose further restrictions on the specific model of the main control chip.

[0055] Exemplarily, the connecting resistors include resistors R1, R3 and R5, the adjusting resistors include resistors R2 and R4, the adjusting capacitors include capacitors C2 and C3, the field effect transistors include field effect transistors Q1 and Q2, the initial capacitor is C1, and the preset capacitor is C4; wherein, the VCC pin of the main control chip is connected to the resistor R5, and the other end of the resistor R5 is used to access the grid voltage VCC, thereby obtaining the current grid voltage through the VCC pin.

[0056] Specifically, one end of the resistor R2 in the first regulation control branch is connected to a diode group formed by a diode D1 and a diode D2 connected in reverse parallel, the other end of the diode group is connected to the gate of the field effect transistor Q1, the source of the field effect transistor Q1 is grounded, the drain of the field effect transistor Q1 is connected to the capacitor C2, and an anti-parallel diode D11 is arranged between the drain and the source of the field effect transistor Q1, the cathode of the diode D11 is connected to the drain of the field effect transistor Q1, and the anode of the anti-parallel diode D11 is connected to the source of the field effect transistor Q1.

[0057] One end of the resistor R4 in the second regulation control branch is connected to a diode group formed by a diode D3 and a diode D4 connected in reverse parallel, and the other end of the diode group is connected to the gate of the field effect transistor Q2. The source of the field effect transistor Q2 is grounded, and the drain of the field effect transistor Q2 is connected to the capacitor C3. An anti-parallel diode D21 is arranged between the drain and the source of the field effect transistor Q2, and the cathode of the diode D21 is connected to the drain of the field effect transistor Q2, and the anode of the anti-parallel diode D21 is connected to the source of the field effect transistor Q2.

[0058] After one end of capacitor C1 is connected to capacitor C2 and capacitor C3, they are jointly connected to the FILT0 pin of the main control chip. One end of the preset capacitor C4 is connected to the FILT1 pin of the main control chip. The other end of the preset capacitor C4 is connected to the other end of the initial capacitor C1 and the GND pin of the main control chip, and they are jointly grounded. A resistor R6 is set between the OUT pin of the main control chip and the output lead LN_CHK to output the detection result.

[0059] It should be noted that the capacitance values ​​of capacitors C1, C2 and C3 determine the detection sensitivity of the circuit. Therefore, the smaller the capacitance value is set, the higher the detection sensitivity that the circuit can provide. It is preferred to set the capacitance value ratio of capacitors C1, C2 and C3 to 1:2:4.

[0060] Diodes D1, D2, D3 and D4 use diodes with smaller PN junction capacitance, preferably less than 2pf; field effect transistors Q1 and Q2 use N-channel enhancement MOS transistors with smaller parasitic output capacitance, preferably the parasitic output capacitance of the N-channel enhancement MOS transistor is less than 10pF, so the capacitance values ​​of the relative capacitors C1, C2 and C3 can be ignored, thereby improving the circuit measurement accuracy.

[0061] The present application is provided with four voltage preset ranges corresponding to the above-mentioned two regulation control branches, namely the first preset voltage range, the second preset voltage range, the third preset voltage range and the fourth preset voltage range, since the minimum value of the preset voltage range set in the present application is 40%Un, and it is necessary to satisfy the fourth preset voltage range ≥ the minimum value of the preset voltage range.

[0062] Therefore, the above-mentioned first preset voltage range, second preset voltage range, third preset voltage range and fourth preset voltage range need to be within the range of 40% Un-100% Un. The preset voltage range within 40% Un-100% Un can be evenly divided into four preset voltage ranges for the main control chip to compare, namely 100% Un, 80% Un, 60% Un, and 40% Un. At this time, the first preset voltage range is 100% Un, the second preset voltage range is 80% Un, the third preset voltage range is 60% Un, and the fourth preset voltage range is 40% Un.

[0063] It should be noted that the above-mentioned preset voltage range within 40%Un-100%Un is based on 2 2 The preset voltage range is evenly divided into four preset voltage ranges. Of course, the preset voltage range within 40%Un-100%Un can also be allocated by other allocation methods, such as by weighting, the preset voltage range can also be divided into two according to the number of adjustment control branches. N The preset voltage range can be reallocated according to the actual performance of the circuit, as long as the preset voltage range within 40%Un-100%Un can be allocated to 2 N Any allocation method selected for the preset voltage range is feasible, and this application does not impose any further restrictions on this.

[0064] Please refer to Figure 5 , which is a detection flow chart corresponding to the specific embodiment diagram in a zero-live wire exchange detection circuit provided in an embodiment of the present application. When the main control chip determines that the current grid voltage is ≥ the first preset voltage range 100% Un, the first regulation control branch and the second regulation control branch are controlled to be in a disconnected state, that is, at this time, the first regulation control branch and the second regulation control branch are both in a low level, and the capacitor C2 and the capacitor C3 are both in a closed state and do not affect the capacitor C1. Since the impedance element and the initial impedance element are set in the form of a capacitor in the present application, the detection sensitivity value is specifically reflected as the sensitivity capacitance value, that is, when the main control chip determines that the current grid voltage is ≥ the first preset voltage range 100% Un, the detection sensitivity capacitance value provided by the circuit at this time is the capacitance value of the capacitor C1.

[0065] When the main control chip determines that the current grid voltage is ≥ 80% Un of the second preset voltage range, the first regulating control branch is controlled to be in the connected state and the second regulating control branch is in the disconnected state. That is, at this time, the first regulating control branch is in the high level state, the second regulating control branch is in the low level state, the capacitor C2 is in the on state, and the capacitor C3 is in the off state. At this time, the detection sensitivity capacitance value provided by the circuit is the capacitance value of capacitor C1 + capacitor C2.

[0066] When the main control chip determines that the current grid voltage is ≥ 60% Un of the third preset voltage range, the first regulating control branch is controlled to be in a disconnected state and the second regulating control branch is in a connected state, that is, at this time the first regulating control branch is in a low level state, the second regulating control branch is in a high level state, capacitor C2 is in a closed state, and capacitor C3 is in an open state. At this time, the detection sensitivity capacitance value provided by the circuit is the capacitance value of capacitor C1 + capacitor C3.

[0067] When the main control chip determines that the current grid voltage is ≥40%Un of the fourth preset voltage range, the first regulating control branch and the second regulating control branch are both in the connected state, that is, the first regulating control branch is in a high level state, the second regulating control branch is in a high level state, and capacitors C2 and C3 are both in the on state. At this time, the detection sensitivity capacitance value provided by the circuit is the capacitance value of capacitor C1+capacitor C2+capacitor C3.

[0068] When the main control chip determines that the current grid voltage is less than 40% Un, no detection is performed. This is because when the grid voltage is less than 40% Un, it means that the grid environment is in an unstable state and there may be a possibility of missed detection or false detection. Therefore, when the grid voltage is less than 40% Un, the main control chip does not perform exchange detection.

[0069] Taking the connection of two adjustment control branches as an example, a fixed detection sensitivity capacitance value C1 can be expanded to four matching detection sensitivity capacitance values ​​of C1, C1+C2, C1+C3, and C1+C2+C3. Through the relevant knowledge of probability theory, it can be deduced that when N adjustment control branches are connected, a fixed detection sensitivity capacitance value can be expanded to 2 N A matching detection sensitivity capacitance value is achieved, so that even when the grid voltage fluctuates greatly, the detection sensitivity can be accurately adjusted according to the access voltage, which expands the grid voltage fluctuation range of zero-live wire switching detection and achieves higher detection accuracy.

[0070] Since setting too many adjustment control branches will make the circuit cumbersome and redundant, and increase the computational complexity of the main control unit, the present application preferably sets the number of adjustment control branches N≤5, and sets the capacitance value of the initial capacitor to be < the capacitance value of the adjustment capacitor corresponding to the first adjustment control branch < the capacitance value of the adjustment capacitor corresponding to the second adjustment control branch < the capacitance value of the adjustment capacitor corresponding to the third adjustment control branch < the capacitance value of the adjustment capacitor corresponding to the fourth adjustment control branch < the capacitance value of the adjustment capacitor corresponding to the fifth adjustment control branch.

[0071] by Figure 2Taking the two adjustment capacitors C2 and C3 shown as examples, C1 is a fixed capacitance value, C2 is a capacitor that is larger than C1 but smaller than C3, and C3 is a capacitor that is selectively larger than C1 and C2. Since the parallel capacitance value of C1, C2, and C3 determines the sensitivity of the induced potential detection, the smaller the capacitance, the higher the sensitivity. Therefore, the present application preferably sets the ratio range of C1:C2:C3 to be approximately 1:2:4 to increase the sensitivity capacitance value that the circuit can achieve.

[0072] Please continue to refer to Figure 2 When the main control chip outputs a high level, the current detection ground is the live wire, and when the main control chip outputs a low level, the current detection ground is the neutral wire, thereby realizing the zero-live wire exchange detection; the main control chip can also be set to output the current detection ground as the ground wire when the main control chip outputs a high level, and the current detection ground as the live wire when the main control chip outputs a low level; the main control chip can also be set to output in the form of whether the indicator light flashes or the buzzer gives a sound prompt. As long as it can be distinguished from any output method selected by the two different detection circuits of the live wire and the neutral wire, it is feasible, and this application does not impose further restrictions on this.

[0073] Based on the above-mentioned zero-live wire exchange detection circuit, the present application also provides a zero-live wire exchange detection device. For other details about the above-mentioned zero-live wire exchange detection device to implement the above-mentioned technical solution, please refer to the description of the zero-live wire exchange detection circuit provided in the above-mentioned application embodiment, which will not be repeated here.

[0074] The present application provides a zero-live wire exchange detection circuit and detection device, which collect the current grid voltage by setting a voltage acquisition unit, setting a plurality of adjustment control branches, and setting an initial capacitor different from the adjustment capacitor in the main control unit, so that the main control unit adjusts the detection sensitivity value under the current voltage through the plurality of adjustment control branches, thereby realizing automatic adjustment of the adaptive sensitivity capacitance value according to the grid environment, improving the applicability of the detection circuit, and effectively expanding the grid voltage fluctuation range of the zero-live wire exchange detection; by adding N adjustment control branches, the detection sensitivity value is expanded from the default one sensitivity capacitance value to 2 N The sensitivity capacitance value improves the detection accuracy of the zero-live wire swapping detection, and can stably and accurately detect whether the zero-live wire is swapped even in a power grid environment with large power grid voltage fluctuations.

[0075] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A zero-live line exchange detection circuit, characterized in that: It includes a main control unit, and a voltage acquisition unit and a regulation control unit connected to the main control unit; The voltage acquisition unit is used to acquire the current voltage; The regulating control unit comprises a plurality of regulating control branches, each of which is provided with a regulating resistor, a diode group, a field effect transistor and a regulating capacitor connected in series in sequence; The main control unit is provided with an initial capacitor, one end of the initial capacitor is grounded, and the other end of the initial capacitor is connected to the main control unit after being connected to a plurality of the adjustment capacitors.

2. A zero-live line exchange detection circuit as claimed in claim 1, characterized in that: One end of the regulating capacitor is connected to the main control unit, the other end of the regulating capacitor is connected to the drain of the field effect tube, the gate of the field effect tube is connected to the diode group, the other end of the diode group is connected to the regulating capacitor, and the source of the field effect tube is grounded.

3. A zero-live line exchange detection circuit as claimed in claim 1, characterized in that: A preset capacitor is also arranged in parallel at both ends of the initial capacitor, one end of the initial capacitor and the preset capacitor are respectively connected to the main control unit, and the other ends of the initial capacitor and the preset capacitor are connected to the ground.

4. A zero-live line exchange detection circuit as claimed in claim 3, characterized in that: Corresponding connection resistors are arranged between the voltage acquisition unit and the main control unit, and between each of the regulation control branches.

5. A zero-live line swap detection circuit as claimed in claim 1, characterized in that: The diode group includes a first diode and a second diode arranged in parallel; The anode of the first diode and the cathode of the second diode are connected together and then connected to the regulating capacitor, and the cathode of the first diode and the anode of the second diode are connected together and then connected to the gate of the field effect transistor.

6. A zero-live line swap detection circuit as claimed in claim 1, characterized in that: The number of the regulating control branches N≤5; Among them, the capacitance value of the initial capacitor is less than the capacitance value of the regulating capacitor corresponding to the first regulating control branch, less than the capacitance value of the regulating capacitor corresponding to the second regulating control branch, less than the capacitance value of the regulating capacitor corresponding to the third regulating control branch, less than the capacitance value of the regulating capacitor corresponding to the fourth regulating control branch, less than the capacitance value of the regulating capacitor corresponding to the fifth regulating control branch.

7. A zero-live line swap detection circuit as claimed in claim 1, characterized in that: The field effect transistor is an N-channel enhancement mode MOS transistor, and the parasitic output capacitance of the N-channel enhancement mode MOS transistor is less than 10 pF.

8. A zero-live line swap detection circuit as claimed in claim 1, characterized in that: An anti-parallel diode is arranged between the drain and source of the field effect tube, the cathode of the anti-parallel diode is connected to the drain of the field effect tube, and the anode of the anti-parallel diode is connected to the source of the field effect tube.

9. A zero-live line swap detection circuit as claimed in claim 4, characterized in that: The main control unit includes a main control chip, and the voltage acquisition unit is connected to the VCC pin of the main control chip through the connection resistor to transmit the collected voltage value to the main control chip; After the initial capacitor is connected to the plurality of adjustment capacitors, they are connected to the FILT0 pin of the main control chip; one end of the preset capacitor is connected to the FILT1 pin of the main control chip, and the other end of the preset capacitor is connected to the other end of the initial capacitor and the GND pin of the main control chip, and they are grounded together; The OUT pin of the main control chip is connected to an output resistor for outputting the detection result.

10. A zero-live line exchange detection device, characterized in that: It comprises the zero-live line swapping detection circuit as described in any one of claims 1-9.

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