Ethernet transmission circuit based on high-capacity FPGA

Abstract

The utility model discloses an Ethernet transmission circuit based on a high-capacity FPGA (Field Programmable Gate Array), which comprises an FPGA chip D51, a 24-path parallel light emitting module D89, a 24-path parallel light receiving module D90, a 12-path parallel light receiving and transmitting integrated module D91 and a power supply module, and the FPGA chip D51 is electrically connected with the 24-path parallel light emitting module D89, the 24-path parallel light receiving module D90 and the 12-path parallel light receiving and transmitting integrated module D91 through an Ethernet protocol. According to the Ethernet transmission circuit based on the large-capacity FPGA disclosed by the utility model, the number of Ethernet transmission paths between the FPGA chip and the optical fiber links is selected according to requirements, the large-capacity Ethernet transmission rate can be met at the same time, and the modules of the optical fiber links are selected to be started according to requirements, so that the multi-link optical fiber data transmission of the FPGA chip is met, and the data transmission efficiency is improved. Therefore, the method has the advantages of higher transmission rate, more transmission data and the like.

Description

Technical Field

[0001] The utility model belongs to the technical field of FPGA Ethernet transmission, and in particular relates to an Ethernet transmission circuit based on a large-capacity FPGA. Background Art

[0002] Based on the continuous changes in market requirements and design concepts, the capacity requirements for FPGA boards are becoming larger and larger. As a result, the design requirements for various parts of FPGA boards are constantly increasing. The number of Ethernet transmission paths between existing FPGA chips and optical fiber links is small, which cannot meet the large-capacity transmission rate. In addition, many existing optical fiber links only have optical transceiver modules, which have limited links for optical fiber reception and transmission, and cannot meet the multi-link optical fiber data transmission.

[0003] Therefore, further improvements are made to the above problems. Utility Model Content

[0004] The main purpose of the utility model is to provide an Ethernet transmission circuit based on a large-capacity FPGA, which is linked through an FPGA chip D51, a 24-channel parallel optical transmitting module D89, a 24-channel parallel optical receiving module D90, a 12-channel parallel optical transceiver integrated module D91 and a power supply module, so that the number of Ethernet transmission paths between the FPGA chip and the optical fiber link is selected according to demand, and the large-capacity Ethernet transmission rate can be met at the same time, and the activation of the modules of each optical fiber link is selected according to demand, so as to meet the multi-link optical fiber data transmission of the FPGA chip, thereby having the advantages of faster transmission rate, more transmission data, etc.

[0005] To achieve the above purpose, the utility model provides an Ethernet transmission circuit based on a large-capacity FPGA, including an FPGA chip D51, a 24-way parallel optical transmitter module D89, a 24-way parallel optical receiver module D90, a 12-way parallel optical transceiver integrated module D91 and a power supply module, wherein the FPGA chip D51 is electrically connected to the 24-way parallel optical transmitter module D89, the 24-way parallel optical receiver module D90 and the 12-way parallel optical transceiver integrated module D91 through an Ethernet protocol, wherein:

[0006] The 24 transmitting pins (a total of 24 pins, each corresponding to two pins) of the 24-way parallel optical transmitting module D89 are used to convert the high-speed signal of the FPGA chip D51 transmitted through Ethernet into an optical signal and transmit it. The BF42 pin of the FPGA chip D51 is electrically connected to the D14 pin of the 24-way parallel optical transmitting module D89, the BF43 pin of the FPGA chip D51 is electrically connected to the D15 pin of the 24-way parallel optical transmitting module D89, the BD42 pin of the FPGA chip D51 is electrically connected to the C12 pin of the 24-way parallel optical transmitting module D89, and the BD43 pin of the FPGA chip D51 is electrically connected to the C13 pin of the 24-way parallel optical transmitting module D89. The pins are electrically connected, the BB42 pin of the FPGA chip D51 is electrically connected to the B10 pin of the 24-way parallel optical transmission module D89, the BB43 pin of the FPGA chip D51 is electrically connected to the B11 pin of the 24-way parallel optical transmission module D89, the AW40 pin of the FPGA chip D51 is electrically connected to the D10 pin of the 24-way parallel optical transmission module D89, and the AW41 pin of the FPGA chip D51 is electrically connected to the D11 pin of the 24-way parallel optical transmission module D89 (4 paths are selected for description here, a total of 24 paths are connected to D51, each path, for example, for P16 / N16, can provide a transmission rate of 25G, and the number of transmission paths is set according to demand);

[0007] The 24 receiving pins (a total of 24 pins, each corresponding to two pins) of the 24-way parallel optical receiving module D90 are used to receive external optical fiber information and transmit it to the FPGA chip D51 through Ethernet, the BC45 pin of the FPGA chip D51 is electrically connected to the D14 pin of the 24-way parallel optical receiving module D90, the BC46 pin of the FPGA chip D51 is electrically connected to the D15 pin of the 24-way parallel optical receiving module D90, the BA45 pin of the FPGA chip D51 is electrically connected to the C12 pin of the 24-way parallel optical receiving module D90, and the BA46 pin of the FPGA chip D51 is electrically connected to the C13 pin of the 24-way parallel optical receiving module D90. The AW45 pin of the FPGA chip D51 is electrically connected to the B10 pin of the 24-way parallel optical receiving module D90, the AW46 pin of the FPGA chip D51 is electrically connected to the B11 pin of the 24-way parallel optical receiving module D90, the AV43 pin of the FPGA chip D51 is electrically connected to the D10 pin of the 24-way parallel optical receiving module D90, and the AV44 pin of the FPGA chip D51 is electrically connected to the D11 pin of the 24-way parallel optical receiving module D90 (4 paths are selected for description here, a total of 24 paths are connected to D51, each path, for example, for P16 / N16, can provide a transmission rate of 25G, and the number of transmission paths is set according to demand);

[0008] The 12 transmitting pins (a total of 12 pins, each corresponding to two pins) of the 12-way parallel optical transceiver module D91 are used to convert the high-speed signal transmitted by the FPGA chip D51 through Ethernet into an optical signal and transmit it. The 12 receiving pins (a total of 12 pins, each corresponding to two pins) of the 12-way parallel optical transceiver module D91 are used to receive external optical fiber information and transmit it to the FPGA chip D51 through Ethernet. The AN45 pin of the FPGA chip D51 is electrically connected to the B18 pin of the 12-way parallel optical transceiver module D91. The FPGA The AN46 pin of the chip D51 is electrically connected to the B19 pin of the 12-way parallel optical transceiver integrated module D91, the AN40 pin of the FPGA chip D51 is electrically connected to the J18 pin of the 12-way parallel optical transceiver integrated module D91, and the AN41 pin of the FPGA chip D51 is electrically connected to the J19 pin of the 12-way parallel optical transceiver integrated module D91 (here, 1 receiving channel and 1 transmitting channel are selected for description, and a total of 12 channels are connected to D51. Each channel, for example, for P24 / N24, can provide a transmission rate of 25G, and the number of transmission channels is set according to demand);

[0009] The power supply module includes a first power supply unit, a second power supply unit, a third power supply unit and a fourth power supply unit, the first power supply unit is electrically connected to the 24-way parallel optical transmitter module D89, the second power supply unit is electrically connected to the 24-way parallel optical receiver module D90, and the third power supply unit and the fourth power supply unit are electrically connected to the 12-way parallel optical transceiver integrated module D91 respectively. As a further preferred technical solution of the above technical solution, the first power supply unit includes a magnetic bead L2, the first end of the magnetic bead L2 is connected to the input power supply terminal and the second end of the magnetic bead L2 is connected to the first output power supply terminal (F1_VCCT3.3), and the second end of the magnetic bead L2 is grounded through capacitor C1252, capacitor C1256, capacitor C1260, capacitor C1264, capacitor C1268 and capacitor C1272 respectively.

[0010] As a further preferred technical solution of the above technical solution, the second power supply unit includes a magnetic bead L3, the first end of the magnetic bead L3 is connected to the input power supply terminal and the second end of the magnetic bead L3 is connected to the second output power supply terminal (F2_VCCR3.3), and the second end of the magnetic bead L3 is grounded through capacitor C1253, capacitor C1257, capacitor C1261, capacitor C1265, capacitor C1269 and capacitor C1273 respectively.

[0011] As a further preferred technical solution of the above technical solution, the third power supply unit includes a magnetic bead L4, a first end of the magnetic bead L4 is connected to the input power supply terminal and a second end of the magnetic bead L4 is connected to the third output power supply terminal (F3_VCCR3.3), and the second end of the magnetic bead L4 is grounded through capacitor C1254, capacitor C1258, capacitor C1262, capacitor C1266, capacitor C1270 and capacitor C1274 respectively;

[0012] The fourth power supply unit includes a magnetic bead L5, a first end of the magnetic bead L5 is connected to the input power supply terminal and a second end of the magnetic bead L5 is connected to the fourth output power supply terminal (F3_VCCT3.3), and the second end of the magnetic bead L5 is grounded through capacitor C1255, capacitor C1259, capacitor C1263, capacitor C1267, capacitor C1271 and capacitor C1275.

[0013] As a further preferred technical solution of the above technical solution, the first output power supply terminal is electrically connected to the power supply terminal of the 24-way parallel optical transmitting module D89; the second output power supply terminal is electrically connected to the power supply terminal of the 24-way parallel optical receiving module D90; the third output power supply terminal is electrically connected to the receiving power supply terminal of the 12-way parallel optical transceiver module D91; the fourth output power supply terminal is electrically connected to the transmitting power supply terminal of the 12-way parallel optical transceiver module D91.

[0014] As a further preferred technical solution of the above technical solution, the FPGA chip D51 also includes a power supply filter circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The utility model discloses a circuit diagram of a 24-channel parallel optical transmission module of an Ethernet transmission circuit based on a large-capacity FPGA.

[0016] Figure 2 The utility model discloses a circuit diagram of a 24-channel parallel optical receiving module of an Ethernet transmission circuit based on a large-capacity FPGA.

[0017] Figure 3 The utility model discloses a circuit diagram of a 12-channel parallel optical transceiver integrated module of an Ethernet transmission circuit based on a large-capacity FPGA.

[0018] Figure 4 The utility model discloses a circuit diagram of a power supply module of an Ethernet transmission circuit based on a large-capacity FPGA.

[0019] Figure 5 The utility model discloses a circuit diagram of an FPGA chip of an Ethernet transmission circuit based on a large-capacity FPGA.

[0020] Figure 6 The utility model discloses a power supply filter circuit diagram of an Ethernet transmission circuit based on a large-capacity FPGA. DETAILED DESCRIPTION

[0021] The following description is used to disclose the utility model so that those skilled in the art can implement the utility model. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the utility model defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the utility model.

[0022] The utility model discloses an Ethernet transmission circuit based on a large-capacity FPGA. The specific embodiments of the utility model are further described below in conjunction with preferred embodiments.

[0023] In the embodiments of the present invention, those skilled in the art will note that the capacitors and the like involved in the present invention may be regarded as prior art.

[0024] Preferred embodiments.

[0025] like Figure 1-6 As shown, the utility model discloses an Ethernet transmission circuit based on a large-capacity FPGA, including an FPGA chip D51, a 24-way parallel optical transmitting module D89, a 24-way parallel optical receiving module D90, a 12-way parallel optical transceiver integrated module D91 and a power supply module, wherein the FPGA chip D51 is electrically connected to the 24-way parallel optical transmitting module D89, the 24-way parallel optical receiving module D90 and the 12-way parallel optical transceiver integrated module D91 through an Ethernet protocol, wherein:

[0026] The 24 transmitting pins (a total of 24 pins, each corresponding to two pins) of the 24-way parallel optical transmitting module D89 are used to convert the high-speed signal of the FPGA chip D51 transmitted through Ethernet into an optical signal and transmit it. The BF42 pin of the FPGA chip D51 is electrically connected to the D14 pin of the 24-way parallel optical transmitting module D89, the BF43 pin of the FPGA chip D51 is electrically connected to the D15 pin of the 24-way parallel optical transmitting module D89, the BD42 pin of the FPGA chip D51 is electrically connected to the C12 pin of the 24-way parallel optical transmitting module D89, and the BD43 pin of the FPGA chip D51 is electrically connected to the C13 pin of the 24-way parallel optical transmitting module D89. The pins are electrically connected, the BB42 pin of the FPGA chip D51 is electrically connected to the B10 pin of the 24-way parallel optical transmission module D89, the BB43 pin of the FPGA chip D51 is electrically connected to the B11 pin of the 24-way parallel optical transmission module D89, the AW40 pin of the FPGA chip D51 is electrically connected to the D10 pin of the 24-way parallel optical transmission module D89, and the AW41 pin of the FPGA chip D51 is electrically connected to the D11 pin of the 24-way parallel optical transmission module D89 (4 paths are selected for description here, a total of 24 paths are connected to D51, each path, for example, for P16 / N16, can provide a transmission rate of 25G, and the number of transmission paths is set according to demand);

[0027] The 24 receiving pins (a total of 24 pins, each corresponding to two pins) of the 24-way parallel optical receiving module D90 are used to receive external optical fiber information and transmit it to the FPGA chip D51 through Ethernet, the BC45 pin of the FPGA chip D51 is electrically connected to the D14 pin of the 24-way parallel optical receiving module D90, the BC46 pin of the FPGA chip D51 is electrically connected to the D15 pin of the 24-way parallel optical receiving module D90, the BA45 pin of the FPGA chip D51 is electrically connected to the C12 pin of the 24-way parallel optical receiving module D90, and the BA46 pin of the FPGA chip D51 is electrically connected to the C13 pin of the 24-way parallel optical receiving module D90. The AW45 pin of the FPGA chip D51 is electrically connected to the B10 pin of the 24-way parallel optical receiving module D90, the AW46 pin of the FPGA chip D51 is electrically connected to the B11 pin of the 24-way parallel optical receiving module D90, the AV43 pin of the FPGA chip D51 is electrically connected to the D10 pin of the 24-way parallel optical receiving module D90, and the AV44 pin of the FPGA chip D51 is electrically connected to the D11 pin of the 24-way parallel optical receiving module D90 (4 paths are selected for description here, a total of 24 paths are connected to D51, each path, for example, for P16 / N16, can provide a transmission rate of 25G, and the number of transmission paths is set according to demand);

[0028] The 12 transmitting pins (a total of 12 pins, each corresponding to two pins) of the 12-way parallel optical transceiver module D91 are used to convert the high-speed signal transmitted by the FPGA chip D51 through Ethernet into an optical signal and transmit it. The 12 receiving pins (a total of 12 pins, each corresponding to two pins) of the 12-way parallel optical transceiver module D91 are used to receive external optical fiber information and transmit it to the FPGA chip D51 through Ethernet. The AN45 pin of the FPGA chip D51 is electrically connected to the B18 pin of the 12-way parallel optical transceiver module D91. The FPGA The AN46 pin of the chip D51 is electrically connected to the B19 pin of the 12-way parallel optical transceiver integrated module D91, the AN40 pin of the FPGA chip D51 is electrically connected to the J18 pin of the 12-way parallel optical transceiver integrated module D91, and the AN41 pin of the FPGA chip D51 is electrically connected to the J19 pin of the 12-way parallel optical transceiver integrated module D91 (here, 1 receiving channel and 1 transmitting channel are selected for description, and a total of 12 channels are connected to D51. Each channel, for example, for P24 / N24, can provide a transmission rate of 25G, and the number of transmission channels is set according to demand);

[0029] The power supply module includes a first power supply unit, a second power supply unit, a third power supply unit and a fourth power supply unit. The first power supply unit is electrically connected to the 24-way parallel optical transmitting module D89, the second power supply unit is electrically connected to the 24-way parallel optical receiving module D90, and the third power supply unit and the fourth power supply unit are electrically connected to the 12-way parallel optical transceiver module D91 respectively.

[0030] Specifically, the first power supply unit includes a magnetic bead L2, a first end of the magnetic bead L2 is connected to the input power supply end and a second end of the magnetic bead L2 is connected to the first output power supply end (F1_VCCT3.3), and the second end of the magnetic bead L2 is grounded through capacitor C1252, capacitor C1256, capacitor C1260, capacitor C1264, capacitor C1268 and capacitor C1272 (capacitors are used for filtering).

[0031] More specifically, the second power supply unit includes a magnetic bead L3, a first end of the magnetic bead L3 is connected to the input power terminal and a second end of the magnetic bead L3 is connected to the second output power terminal (F2_VCCR3.3), and the second end of the magnetic bead L3 is grounded through capacitor C1253, capacitor C1257, capacitor C1261, capacitor C1265, capacitor C1269 and capacitor C1273 (capacitors for filtering).

[0032] Furthermore, the third power supply unit includes a magnetic bead L4, a first end of the magnetic bead L4 is connected to the input power supply terminal and a second end of the magnetic bead L4 is connected to the third output power supply terminal (F3_VCCR3.3), and the second end of the magnetic bead L4 is grounded through capacitor C1254, capacitor C1258, capacitor C1262, capacitor C1266, capacitor C1270 and capacitor C1274 (capacitors are used for filtering).

[0033] The fourth power supply unit includes a magnetic bead L5, a first end of the magnetic bead L5 is connected to the input power supply terminal and a second end of the magnetic bead L5 is connected to the fourth output power supply terminal (F3_VCCT3.3), and the second end of the magnetic bead L5 is grounded through capacitor C1255, capacitor C1259, capacitor C1263, capacitor C1267, capacitor C1271 and capacitor C1275 (capacitors are used for filtering).

[0034] Furthermore, the first output power terminal is electrically connected to the power supply terminal of the 24-way parallel optical transmitting module D89; the second output power terminal is electrically connected to the power supply terminal of the 24-way parallel optical receiving module D90; the third output power terminal is electrically connected to the receiving power supply terminal of the 12-way parallel optical transceiver module D91; and the fourth output power terminal is electrically connected to the transmitting power supply terminal of the 12-way parallel optical transceiver module D91.

[0035] Preferably, the FPGA chip D51 also includes a power supply filtering circuit.

[0036] For the utility model, the number of Ethernet transmission paths between the FPGA chip and the optical fiber link is selected according to the requirements, and the large-capacity Ethernet transmission rate can be met at the same time;

[0037] Furthermore, if the optical fiber links required by the FPGA chip do not exceed 12, the 12-channel parallel optical transceiver module D91 can be used for operation. If the optical fiber links required by the FPGA chip exceed 12, the 24-channel parallel optical transmitter module D89 and the 24-channel parallel optical receiver module D90 need to be started to work, so as to realize multi-link optical fiber data transmission, which has the advantages of faster transmission rate and more transmission data.

[0038] For D89 HTG8533 24-channel parallel optical transmitter module, it is a high-performance press-fit 24-channel parallel optical transmitter module for very short distance parallel multi-channel optical interconnection data communication. The central wavelength of the module is 850nm, powered by a single 3.30V power supply, and the single-channel transmission rate is 25.78125Gbps;

[0039] For the D90 HTG8534 24-channel parallel optical receiver module, HTG8534A-MH-DA8YY is a high-performance press-fit 24-channel parallel optical receiver module for very short-distance parallel multi-channel optical interconnect data communication. The module has a central wavelength of 850nm, a single 3.30V power supply, and a single-channel transmission rate of 25.78125Gbps;

[0040] For D91 HTG8532 12-channel parallel optical transceiver module, HTG8532A-MD-DA8YY is a high-performance press-fit 12-channel parallel optical transceiver module for very short distance parallel multi-channel optical interconnect data communication. The central wavelength of the module is 850nm, powered by a single 3.30V power supply, and the single-channel transmission rate is 25.78125Gbps.

[0041] It is worth mentioning that the technical features such as capacitors involved in this utility model patent application should be regarded as prior art. The specific structure, working principle and possible control method and spatial layout method of these technical features can be selected by conventional methods in the field and should not be regarded as the invention point of this utility model patent. This utility model patent will not be further elaborated.

[0042] For those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present utility model should be included in the protection scope of the present utility model.

Claims

1. An Ethernet transmission circuit based on a large-capacity FPGA, characterized in that: It includes an FPGA chip D51, a 24-way parallel optical transmitter module D89, a 24-way parallel optical receiver module D90, a 12-way parallel optical transceiver integrated module D91 and a power supply module. The FPGA chip D51 is electrically connected to the 24-way parallel optical transmitter module D89, the 24-way parallel optical receiver module D90 and the 12-way parallel optical transceiver integrated module D91 through an Ethernet protocol, wherein: The 24-way transmitting pins of the 24-way parallel optical transmitting module D89 are used to convert the high-speed signal of the FPGA chip D51 transmitted through Ethernet into an optical signal and transmit it, the BF42 pin of the FPGA chip D51 is electrically connected to the D14 pin of the 24-way parallel optical transmitting module D89, the BF43 pin of the FPGA chip D51 is electrically connected to the D15 pin of the 24-way parallel optical transmitting module D89, the BD42 pin of the FPGA chip D51 is electrically connected to the C12 pin of the 24-way parallel optical transmitting module D89, and the BD The 43 pin of the FPGA chip D51 is electrically connected to the C13 pin of the 24-way parallel optical transmission module D89, the BB42 pin of the FPGA chip D51 is electrically connected to the B10 pin of the 24-way parallel optical transmission module D89, the BB43 pin of the FPGA chip D51 is electrically connected to the B11 pin of the 24-way parallel optical transmission module D89, the AW40 pin of the FPGA chip D51 is electrically connected to the D10 pin of the 24-way parallel optical transmission module D89, and the AW41 pin of the FPGA chip D51 is electrically connected to the D11 pin of the 24-way parallel optical transmission module D89; The 24 receiving pins of the 24-way parallel optical receiving module D90 are used to receive external optical fiber information and transmit it to the FPGA chip D51 through Ethernet, the BC45 pin of the FPGA chip D51 is electrically connected to the D14 pin of the 24-way parallel optical receiving module D90, the BC46 pin of the FPGA chip D51 is electrically connected to the D15 pin of the 24-way parallel optical receiving module D90, the BA45 pin of the FPGA chip D51 is electrically connected to the C12 pin of the 24-way parallel optical receiving module D90, and the BA46 pin of the FPGA chip D51 is electrically connected to the C13 pin of the 24-way parallel optical receiving module D90. The pin is electrically connected to the C13 pin of the 24-way parallel optical receiving module D90, the AW45 pin of the FPGA chip D51 is electrically connected to the B10 pin of the 24-way parallel optical receiving module D90, the AW46 pin of the FPGA chip D51 is electrically connected to the B11 pin of the 24-way parallel optical receiving module D90, the AV43 pin of the FPGA chip D51 is electrically connected to the D10 pin of the 24-way parallel optical receiving module D90, and the AV44 pin of the FPGA chip D51 is electrically connected to the D11 pin of the 24-way parallel optical receiving module D90; The 12-way transmitting pins of the 12-way parallel optical transceiver integrated module D91 are used to convert the high-speed signal transmitted by the FPGA chip D51 through Ethernet into an optical signal and transmit it. The 12-way receiving pins of the 12-way parallel optical transceiver integrated module D91 are used to receive external optical fiber information and transmit it to the FPGA chip D51 through Ethernet. The AN45 pin of the FPGA chip D51 is electrically connected to the B18 pin of the 12-way parallel optical transceiver integrated module D91, the AN46 pin of the FPGA chip D51 is electrically connected to the B19 pin of the 12-way parallel optical transceiver integrated module D91, the AN40 pin of the FPGA chip D51 is electrically connected to the J18 pin of the 12-way parallel optical transceiver integrated module D91, and the AN41 pin of the FPGA chip D51 is electrically connected to the J19 pin of the 12-way parallel optical transceiver integrated module D91; The power supply module includes a first power supply unit, a second power supply unit, a third power supply unit and a fourth power supply unit. The first power supply unit is electrically connected to the 24-way parallel optical transmitting module D89, the second power supply unit is electrically connected to the 24-way parallel optical receiving module D90, and the third power supply unit and the fourth power supply unit are electrically connected to the 12-way parallel optical transceiver module D91 respectively.

2. The Ethernet transmission circuit based on a large-capacity FPGA according to claim 1, characterized in that: The first power supply unit includes a magnetic bead L2, a first end of the magnetic bead L2 is connected to the input power end and a second end of the magnetic bead L2 is connected to the first output power end, and the second end of the magnetic bead L2 is grounded through capacitor C1252, capacitor C1256, capacitor C1260, capacitor C1264, capacitor C1268 and capacitor C1272 respectively.

3. The Ethernet transmission circuit based on a large-capacity FPGA according to claim 2, characterized in that: The second power supply unit includes a magnetic bead L3, a first end of the magnetic bead L3 is connected to the input power supply end and a second end of the magnetic bead L3 is connected to the second output power supply end, and the second end of the magnetic bead L3 is grounded through capacitor C1253, capacitor C1257, capacitor C1261, capacitor C1265, capacitor C1269 and capacitor C1273 respectively.

4. The Ethernet transmission circuit based on a large-capacity FPGA according to claim 3, characterized in that: The third power supply unit includes a magnetic bead L4, a first end of the magnetic bead L4 is connected to the input power supply end and a second end of the magnetic bead L4 is connected to the third output power supply end, and the second end of the magnetic bead L4 is grounded through capacitor C1254, capacitor C1258, capacitor C1262, capacitor C1266, capacitor C1270 and capacitor C1274 respectively; The fourth power supply unit includes a magnetic bead L5, a first end of the magnetic bead L5 is connected to the input power supply terminal and a second end of the magnetic bead L5 is connected to the fourth output power supply terminal, and the second end of the magnetic bead L5 is grounded through capacitor C1255, capacitor C1259, capacitor C1263, capacitor C1267, capacitor C1271 and capacitor C1275 respectively.

5. The Ethernet transmission circuit based on a large-capacity FPGA according to claim 4, characterized in that: The first output power terminal is electrically connected to the power supply terminal of the 24-way parallel optical transmitting module D89; the second output power terminal is electrically connected to the power supply terminal of the 24-way parallel optical receiving module D90; the third output power terminal is electrically connected to the receiving power supply terminal of the 12-way parallel optical transceiver module D91; the fourth output power terminal is electrically connected to the transmitting power supply terminal of the 12-way parallel optical transceiver module D91.

6. The Ethernet transmission circuit based on a large-capacity FPGA according to claim 5, characterized in that: FPGA chip D51 also includes a power supply filtering circuit.

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