Chip packaging structure and electronic equipment
By using a design in which thermal conductive pins are used in the chip packaging structure to extend into the plastic package, the problem of rising chip operating temperature is solved, heat dissipation performance and chip integration are improved, and the reliability of electronic equipment is enhanced.
Patent Information
- Application Number
- CN202323528440.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-22
- Publication Date
- 2025-01-24
- Estimated Expiration
- 2033-12-22
AI Technical Summary
As the number and density of chips increase, the chip operating temperature rises sharply, which may lead to thermal failure. It is necessary to improve the heat dissipation efficiency of electronic devices to avoid temperatures exceeding the normal range.
A chip packaging structure is adopted, which includes a first and a second substrate. The second substrate is provided with thermal conductive pins extending into the plastic package to improve heat dissipation performance.
By stacking settings, increase chip integration, enhance heat dissipation performance, prevent the chip temperature from being too high, and improve the reliability of electronic equipment.
Smart Images
Figure CN222394807U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and electronic equipment. Background Art
[0002] With the promotion of artificial intelligence and autonomous driving technology, electronic devices require higher computing power, which are often designed to include flip chips and upright chips. As the number and density of chips continue to increase, the number of chip transistors is increasing and the density is increasing, the chip operating temperature rises sharply, and thermal failure, temporary failure or permanent damage may occur. Therefore, it is necessary to ensure that electronic devices have good heat dissipation performance to avoid thermal failure caused by exceeding the normal operating temperature range of the chip. Utility Model Content
[0003] The utility model aims to provide a chip packaging structure and electronic equipment, which can improve chip integration and heat dissipation effect.
[0004] The embodiment of the utility model is achieved as follows:
[0005] In a first aspect, the utility model provides a chip packaging structure, comprising:
[0006] a first substrate;
[0007] a first chip, wherein the first chip is disposed on the first substrate and is electrically connected to the first substrate;
[0008] A plastic package, which is disposed on the first substrate and covers the first chip;
[0009] A second substrate, wherein the second substrate is provided with a heat-conducting pin, and an end of the heat-conducting pin away from the second substrate extends into the plastic package;
[0010] a second chip, wherein the second chip is disposed on a side of the second substrate away from the heat-conducting pins, and the second chip is electrically connected to the first substrate or the second substrate;
[0011] A protective layer is disposed on the second substrate, or is disposed on both the first substrate and the second substrate, so as to protect the second chip.
[0012] In an optional embodiment, the thermally conductive pin at least partially extends into the plastic package body, and a side surface of the second substrate on which the thermally conductive pin is provided has a preset height with a side surface of the plastic package body away from the first substrate.
[0013] In an optional embodiment, the second substrate is provided with a plurality of the thermally conductive pins, a portion of the thermally conductive pins extend above the first chip, and a portion of the thermally conductive pins extend between adjacent first chips.
[0014] In an optional embodiment, the first chip includes a flip chip, a first pad is provided on the first substrate, the flip chip is provided with a first bump, and the first bump is welded to the first pad.
[0015] In an optional embodiment, the second chip includes a front-mounted chip, a second pad is provided on the first substrate, the front-mounted chip is provided with a third pad, and the third pad is electrically connected to the second pad via a connecting wire.
[0016] In an optional embodiment, an adhesive is provided between the front-mounted chip and the second substrate.
[0017] In an optional embodiment, the protection layer is disposed along the periphery of the second substrate, covering the second substrate and the bonding structure of the connecting wires.
[0018] In an optional embodiment, the second chip includes a flip chip, a fourth pad is provided on the second substrate, a second bump is provided on the flip chip, and the second bump is welded to the fourth pad; the second substrate is electrically connected to the first substrate.
[0019] In an optional embodiment, the protection layer is provided on the second substrate to cover the second chip.
[0020] In a second aspect, the utility model provides an electronic device, comprising a circuit board and a chip packaging structure as described in any one of the aforementioned embodiments, wherein the chip packaging structure and the circuit board are electrically connected.
[0021] The beneficial effects of the embodiments of the utility model include:
[0022] The chip packaging structure proposed in the present application, the first substrate and the second substrate are stacked, which is conducive to improving the integration of the chip, improving the performance of the product, and enriching the functions. In addition, the second substrate is provided with heat-conducting pins extending into the plastic package, which greatly improves the heat dissipation performance, prevents the chip from overheating, and improves the reliability of product operation.
[0023] The electronic device proposed in the present application includes the above-mentioned chip packaging structure, which has high chip integration, rich functions, and good heat dissipation effect. It can transfer the heat of the chip to the outside, improve the heat dissipation performance, thereby preventing the chip from thermal failure and improving the operating reliability of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the utility model and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying creative work.
[0025] Figure 1 A schematic diagram of a chip packaging structure proposed in the first embodiment of the utility model;
[0026] Figure 2 A schematic diagram of a chip packaging structure proposed in the second embodiment of the utility model;
[0027] Figure 3 A schematic diagram of a process of a chip packaging structure proposed in an embodiment of the utility model.
[0028] Icon: 100-chip packaging structure; 110-first substrate; 111-first solder pad; 113-second solder pad; 120-first chip; 121-first bump; 130-plastic package; 140-second substrate; 141-thermal conductive pin; 150-second chip; 151-third solder pad; 153-fourth solder pad; 155-second bump; 160-protective layer; 161-adhesive; 163-connecting wire; 165-conductive column; 170-solder ball. DETAILED DESCRIPTION
[0029] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Generally, the components of the embodiments of the utility model described and shown in the drawings here can be arranged and designed in various different configurations.
[0030] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the present invention to be protected, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0031] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0032] In the description of the present utility model, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings, or the orientation or position relationship in which the utility model product is usually placed when in use, which is only for the convenience of describing the utility model and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0033] In addition, the terms "horizontal", "vertical" and the like do not mean that the components are required to be absolutely horizontal or suspended, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0034] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0035] First embodiment
[0036] Please refer to Figure 1The present embodiment provides a chip packaging structure 100, comprising a first substrate 110, a first chip 120, a plastic package 130, a second substrate 140, a second chip 150 and a protective layer 160. The first chip 120 is disposed on the first substrate 110 and is electrically connected to the first substrate 110. The plastic package 130 is disposed on the first substrate 110 and covers the first chip 120. The second substrate 140 is provided with a heat-conducting pin 141, and one end of the heat-conducting pin 141 away from the second substrate 140 extends into the plastic package 130. The second chip 150 is disposed on a side of the second substrate 140 away from the heat-conducting pin 141, and the second chip 150 is electrically connected to the first substrate 110 or the second substrate 140. The protective layer 160 is disposed on the second substrate 140, or is disposed on both the first substrate 110 and the second substrate 140 to protect the second chip 150. In the chip packaging structure 100, the first substrate 110 and the second substrate 140 are stacked, which is conducive to improving the integration of the chip, improving the performance of the product, and enriching the functions. In addition, the second substrate 140 is provided with a heat-conducting pin 141 extending into the plastic package 130, which greatly improves the heat dissipation performance, prevents the chip from overheating, and improves the reliability of product operation.
[0037] The second chip 150 may be a flip chip or a face-up chip. This embodiment is described by taking the case where the second chip 150 is a face-up chip as an example.
[0038] Optionally, the first chip 120 includes a flip chip, the first substrate 110 is provided with a first pad 111, the flip chip is provided with a first bump 121, and the first bump 121 is welded to the first pad 111. If the first chip 120 includes a face-up chip, the face-up chip and the first pad 111 on the first substrate 110 are connected by wire bonding.
[0039] On the first substrate 110, the number of the first chips 120 may be one or more. If there are multiple chips, all of them may be upright chips, or all of them may be flip chips. Alternatively, some may be upright chips, and some may be flip chips, which is not specifically limited here. In this embodiment, the first chip 120 uses multiple flip chips.
[0040] The second substrate 140 is stacked on the first substrate 110, and the heat-conducting pins 141 at least partially extend into the plastic package 130, and the heat-conducting pins 141 can transfer the heat in the plastic package 130 to the outside of the plastic package 130. Optionally, a side surface of the second substrate 140 provided with the heat-conducting pins 141 and a side surface of the plastic package 130 away from the first substrate 110 have a preset height H. That is, there is a gap between the second substrate 140 and the plastic package 130, which is more conducive to heat dissipation.
[0041] Optionally, the second substrate 140 is provided with a plurality of heat-conducting pins 141, a portion of the heat-conducting pins 141 extends above the first chip 120, and a portion of the heat-conducting pins 141 extends between adjacent first chips 120. The extension lengths of the plurality of heat-conducting pins 141 in the plastic package 130 can be flexibly set, and can be the same or different. In this embodiment, the extension lengths of the plurality of heat-conducting pins 141 in the plastic package 130 are different. The heat-conducting pins 141 located between adjacent first chips 120 have a longer extension length. The heat-conducting pins 141 located above the first chip 120 have a shorter extension length. It should be noted that there is a certain distance between the upper surface of the first chip 120 and the end face of the heat-conducting pins 141 to prevent the heat-conducting pins 141 from damaging the chip. In this way, the heat above the first chip 120 and the heat around the first chip 120 can be guided out of the plastic package 130, thereby cooling the first chip 120. In addition, the provision of the thermally conductive pins 141 can also alleviate the warping deformation caused by the plastic packaging stress and maintain the flatness of the packaging structure.
[0042] It should be noted that the shape, size, number and distribution position of the heat conductive pins 141 are not limited and can be flexibly set. For example, the cross-sectional shape of the heat conductive pins 141 can be a triangle, rhombus, rectangle, square, circle, ellipse, pentagon, hexagon, octagon or any other shape, which is not specifically limited here.
[0043] In this embodiment, the connection method of the plastic package 130 and the thermal conductive pin 141 is that when the plastic package 130 is formed, the second substrate 140 is first fixed on the first substrate 110, and then the plastic package material is poured so that the plastic package material immerses part of the thermal conductive pin 141, and the plastic package 130 is connected to the thermal conductive pin 141 as a whole after the plastic package 130 is cured. In this way, the bonding of the plastic package 130 and the thermal conductive pin 141 can be improved. Of course, before the plastic package 130 is cured, the second substrate 140 can be pressed onto the plastic package 130 so that part of the thermal conductive pin 141 is inserted into the plastic package 130. Alternatively, other methods can be used to extend the thermal conductive pin 141 into the plastic package 130, which is not specifically limited here.
[0044] Optionally, the second chip 150 includes a front-mounted chip, a second pad 113 is provided on the first substrate 110, and a third pad 151 is provided on the front-mounted chip, and the third pad 151 and the second pad 113 are electrically connected via a connecting wire 163. That is, in this embodiment, the second chip 150 and the first substrate 110 are connected by wire bonding. Optionally, an adhesive 161 is provided between the front-mounted chip and the second substrate 140. The front-mounted chip is fixed to the second substrate 140 via the adhesive 161.
[0045] Optionally, the protective layer 160 is arranged along the periphery of the second substrate 140, covering the second substrate 140 and the wiring structure of the connecting wire 163. In this embodiment, the protective layer 160 is made of colloid, and the colloid is glued along the periphery of the second chip 150, and the third pad 151 and the connecting wire 163 on the second chip 150 are covered to protect the second chip 150, the second substrate 140 and the connecting wire 163. It is easy to understand that the protective layer 160 covers the second chip 150, the second substrate 140, the plastic package 130 and the first substrate 110 at the same time. Among them, other places on the upper surface of the second chip 150 except the third pad 151 can be selectively covered or exposed by the colloid. In this embodiment, the middle area of the upper surface of the second chip 150 is not covered with colloid, which is conducive to heat dissipation.
[0046] The number of the second chips 150 can be one or more, which can be flexibly set according to actual needs and is not specifically limited here.
[0047] Second embodiment
[0048] Combination Figure 2 In this embodiment, the second chip 150 mainly includes a flip chip, a fourth pad 153 is provided on the second substrate 140, and the flip chip is provided with a second bump 155, and the second bump 155 and the fourth pad 153 are welded; the second substrate 140 and the first substrate 110 are electrically connected.
[0049] Optionally, the chip package structure 100 further includes a conductive pillar 165, one end of which is electrically connected to the first substrate 110, and the other end of which is electrically connected to the second substrate 140, so as to achieve electrical connection between the first substrate 110 and the second substrate 140. The conductive pillar 165 plays the role of heat conduction and electrical connection.
[0050] Optionally, the protective layer 160 is disposed on the second substrate 140 to cover the second chip 150. In this embodiment, the protective layer 160 may be a plastic package 130, which covers the second chip 150 and protects the second chip 150. Of course, the protective layer 160 may also be a colloid, which is not specifically limited here.
[0051] Other contents not mentioned in this embodiment are similar to those described in the first embodiment and will not be described in detail here.
[0052] The embodiment of the utility model further provides an electronic device, comprising a circuit board and a chip packaging structure 100 as in any one of the above embodiments, wherein the chip packaging structure 100 is electrically connected to the circuit board. Optionally, a fifth pad is further provided on a side of the first substrate 110 away from the second substrate 140, and a solder ball 170 is provided on the fifth pad, and the first substrate 110 is soldered to the circuit board through the solder ball 170.
[0053] Combination Figure 3 The chip packaging structure 100 provided by the embodiment of the present invention has a manufacturing process as follows:
[0054] Step S1: providing a first substrate 110 , which may be an organic substrate such as a base plate, a silicon-based substrate, or a ceramic substrate.
[0055] Step S2: mounting the first chip 120 on the first substrate 110 . The first chip 120 may be a face-up chip or a flip-chip.
[0056] Step S3: plastic encapsulate the first chip 120 to form a plastic encapsulation body 130. The second substrate 140 is pressed onto the surface of the plastic encapsulation body 130 by a plastic encapsulation process, so that the heat conductive pins 141 are arranged in the plastic encapsulation body 130. There is a gap of a preset height H between the second substrate 140 and the plastic encapsulation body 130. The gap can be used to improve the heat dissipation performance. The heat conductive pins 141 are conducive to heat dissipation and alleviate warping deformation.
[0057] Step S4: Mount the second chip 150 on the second substrate 140. The second chip 150 is fixed on the second substrate 140 by using adhesive 161. The second chip 150 and the first substrate 110 are electrically connected by using the wire bonding process again.
[0058] Step S5 : using the dispensing process again to fill and protect the wire bonding structure on the second chip 150 with colloid to form a protection layer 160 .
[0059] Step S6: Perform a ball planting process on the bottom of the first substrate 110 to form solder balls 170. Finally, perform cutting to separate the package structure into individual products to complete the process.
[0060] In summary, the chip packaging structure 100 and the electronic device provided by the embodiment of the present invention have the following beneficial effects, including:
[0061] The chip packaging structure 100 proposed in the embodiment of the utility model, the first substrate 110 and the second substrate 140 are stacked, which is conducive to improving the integration of the chip, improving the performance of the product, and enriching the functions. In addition, the second substrate 140 is provided with a heat-conducting pin 141 extending into the plastic package 130, which greatly improves the heat dissipation performance, prevents the chip from overheating, and improves the reliability of product operation. At the same time, it is conducive to alleviating the warping deformation of the plastic package 130.
[0062] The electronic device proposed in the embodiment of the utility model includes the above-mentioned chip packaging structure 100, which has high chip integration, rich functions, and good heat dissipation effect. It can transfer the heat of the chip to the outside, improve the heat dissipation performance, thereby preventing the chip from thermal failure and improving the operating reliability of the electronic device.
[0063] The above description is only the preferred embodiment of the utility model, and is not intended to limit the utility model. For those skilled in the art, the utility model can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.
Claims
1. A chip packaging structure, characterized in that: include: a first substrate; a first chip, wherein the first chip is disposed on the first substrate and is electrically connected to the first substrate; A plastic package, which is disposed on the first substrate and covers the first chip; A second substrate, wherein the second substrate is provided with a heat-conducting pin, and an end of the heat-conducting pin away from the second substrate extends into the plastic package; a second chip, wherein the second chip is disposed on a side of the second substrate away from the heat-conducting pins, and the second chip is electrically connected to the first substrate or the second substrate; A protective layer is disposed on the second substrate, or is disposed on both the first substrate and the second substrate, so as to protect the second chip.
2. The chip packaging structure according to claim 1, characterized in that: The heat-conducting pin at least partially extends into the plastic package body, and a side surface of the second substrate on which the heat-conducting pin is provided has a preset height with a side surface of the plastic package body away from the first substrate.
3. The chip packaging structure according to claim 1, characterized in that: The second substrate is provided with a plurality of the thermally conductive pins, a portion of the thermally conductive pins extend above the first chip, and a portion of the thermally conductive pins extend between adjacent first chips.
4. The chip packaging structure according to claim 1, characterized in that: The first chip comprises a flip chip, the first substrate is provided with a first pad, the flip chip is provided with a first bump, and the first bump is welded to the first pad.
5. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The second chip comprises a front-mounted chip, a second pad is disposed on the first substrate, the front-mounted chip is provided with a third pad, and the third pad is electrically connected to the second pad via a connecting wire.
6. The chip packaging structure according to claim 5, characterized in that: Adhesive glue is provided between the front-mounted chip and the second substrate.
7. The chip packaging structure according to claim 5, characterized in that: The protection layer is disposed along the outer periphery of the second substrate, covering the second substrate and the bonding structure of the connecting wire.
8. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The second chip comprises a flip chip, a fourth pad is disposed on the second substrate, a second bump is disposed on the flip chip, and the second bump is welded to the fourth pad; the second substrate is electrically connected to the first substrate.
9. The chip packaging structure according to claim 8, characterized in that: The protection layer is arranged on the second substrate and is used for covering the second chip.
10. An electronic device, characterized in that: The invention comprises a circuit board and a chip packaging structure as claimed in any one of claims 1 to 9, wherein the chip packaging structure is electrically connected to the circuit board.