Adapter card for capacity expansion
Use a transfer card through the design capacity expansion, using the M.2 gold finger module and multiple M.2 port line modules, combined with the control instructions and clock signals of the central processor, to achieve multiple PCIE interface hard disks of small -sized PCB boards The expansion of the capacity solves the problem of high costs and rates in existing technologies, improves the storage capacity and reduces production costs.
Patent Information
- Application Number
- CN202420972790.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-08
- Publication Date
- 2025-01-28
- Estimated Expiration
- 2034-05-08
AI Technical Summary
In the prior art, many small-size PCB boards only support a single PCIE M.2 interface, which cannot meet customers' needs for multiple PCIE interface hard disks. The existing expansion cards are costly and the rate is limited by the chip speed.
Design a capacity expansion card, connect to the motherboard through the M.2 gold finger module, including multiple M.2 port line modules, clock modules, and detection modules. Switch and activate multiple M.2 port modules to achieve capacity expansion.
Through a conversion card and software configuration, multiple M.2 port modules are automatically extended, which increases the storage capacity and reduces production costs without affecting the rate of hard disks.
Smart Images
Figure CN222420946U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of interface expansion, and in particular relates to an adapter card for capacity expansion. Background Art
[0002] With the development of technology, the demand for storage capacity is increasing. The storage capacity of a single hard disk can no longer meet the demand, and many devices have the need to expand capacity.
[0003] Now many PCB boards can connect multiple M.2 hard drives with PCIE interfaces on the board, but for small-sized boards, due to the size limitation of the board, many boards only support a single PICE M.2 interface, but customers need hard drives with multiple PCIE interfaces, so an expansion card is needed for expansion. At present, the expansion card uses chips for conversion, which is relatively expensive, and the speed of the expansion card follows the speed of the chip. The higher the speed, the more expensive the chip.
[0004] Based on the above reasons, there is an urgent need for a capacity expansion adapter card that solves the above problems. Utility Model Content
[0005] The purpose of the utility model is to overcome the shortcomings of the above-mentioned prior art and provide an adapter card for capacity expansion. Multiple M.2 port line modules can be realized through an adapter card and corresponding software configuration, thereby improving capacity and reducing production costs. The central processing unit can automatically switch according to the detection signal without affecting the rate.
[0006] The utility model is implemented as follows: a capacity expansion adapter card is used to cooperate with a central processing unit on a motherboard, the central processing area is used to output multiple PCIE signals and a single clock signal, and is characterized in that the capacity expansion adapter card includes:
[0007] M.2 gold finger module, which is used for detachable electrical connection with the motherboard and communication with the central processing unit on the motherboard;
[0008] M.2 port circuit, with multiple M.2 port line modules;
[0009] A clock module, used for converting the single clock signal into multiple clock signals to distribute to multiple M.2 port line modules, and activating multiple M.2 port line modules;
[0010] A detection module, used to detect the electrical connection status between the mainboard and the adapter card for capacity expansion, and output a detection signal indicating that an expansion card is connected to the M.2 gold finger module after detecting that the mainboard and the adapter card are electrically connected;
[0011] The M.2 gold finger module is further used to feed back the detection signal to the central processor, receive control instructions of multiple PCIE signal channels and a single clock signal from the central processor, establish a signal transmission channel with multiple M.2 port line modules in response to the control instruction, and send the single clock signal to the clock module;
[0012] The clock module is further used to configure the single-channel clock signal into a multi-channel clock signal after receiving the single-channel clock signal and distribute it to multiple M.2 port line modules to synchronize the signal transmission clocks of the multiple M.2 port line modules.
[0013] Preferably, the M.2 gold finger module is used to electrically connect to the M.2 port for expansion on the motherboard, and includes a first channel, a second channel, a third channel and a fourth channel;
[0014] The first channel includes: a PETN0 / SATA_A- pin for outputting a PCIE9_TX_DN signal to the M.2 port, a PETP0 / SATA_A+ pin for outputting a PCIE9_TX_DP signal to the M.2 port; a PERN0 / SATA_B+ pin for receiving a PCIE9_RX_DN signal output by the M.2 port, and a PERP0 / SATA_B- pin for receiving a PCIE9_RX_DP signal output by the M.2 port;
[0015] The second channel includes: a PERN1 pin for outputting a PCIE10_RX_DN signal to the M.2 port, a PERP1 pin for outputting a PCIE10_RX_DP signal to the M.2 port; a PETN1 pin for receiving a PCIE10_TX_DN signal output by the M.2 port, and a PETP1 pin for receiving a PCIE10_TX_DP signal output by the M.2 port;
[0016] The third channel includes: a PERN2 pin for outputting a PCIE11_RX_DN signal to the M.2 port, a PERP2 pin for outputting a PCIE11_RX_DP signal to the M.2 port; a PETN2 pin for receiving a PCIE11_TX_DN signal output by the M.2 port, and a PETP2 pin for receiving a PCIE11_TX_DP signal output by the M.2 port;
[0017] The fourth channel includes: a PERN3 pin for outputting a PCIE12_RX_DN signal to the M.2 port, a PERP3 pin for outputting a PCIE12_RX_DP signal to the M.2 port; a PETN3 pin for receiving a PCIE12_TX_DN signal output by the M.2 port, and a PETT3 pin for receiving a PCIE12_RX_DN signal output by the M.2 port.
[0018] Further, the M.2 gold finger module includes a clock channel, and the clock channel includes a REFCLKN pin receiving a PCIE_REFCLK_SSD_DN signal output by the M.2 port, and a REFCLKP pin receiving a PCIE_REFCLK_SSD_DP signal output by the M.2 port.
[0019] Furthermore, the M.2 gold finger module includes a logic channel, which includes an NC6 pin grounded through a resistor, a PERST / NC21 pin receiving an M.2 port input MUF_PLT_RS signal, and a PEWAKE / NC3 pin outputting a PCIL_WAKI signal to the M.2 port.
[0020] Preferably, the clock module comprises: a clock expansion chip that expands one clock signal into multiple clock signal outputs, which are used to supply the solid-state hard disks with 4 PCIE 1 channels on the expansion board respectively.
[0021] Preferably, the clock expansion chip comprises: an IN+ pin for receiving a PCIE_CLK_DP signal output by the motherboard CLK, and an IN- pin for receiving a PCIE_CLK_DN signal output by the motherboard CLK;
[0022] Furthermore, the clock expansion chip further includes: a first group of clock output channels, a second group of clock output channels, a third group of clock output channels and a fourth group of clock output channels;
[0023] The first group of clock output channels includes: a Q0+ pin for outputting a PCIE_CLK_OUT_D0P signal, and a Q0- pin for outputting a PCIE_CLK_OUT_D0N signal;
[0024] The second group of clock output channels includes: a Q1+ pin for outputting a PCIE_CLK_OUT_D1P signal, and a Q1- pin for outputting a PCIE_CLK_OUT_D1N signal;
[0025] The third group of clock output channels includes: a Q2+ pin for outputting a PCIE_CLK_OUT_D2P signal, and a Q2- pin for outputting a PCIE_CLK_OUT_D2N signal;
[0026] The fourth group of clock output channels includes: a Q3+ pin for outputting a PCIE_CLK_OUT_D3P signal, and a Q3- pin for outputting a PCIE_CLK_OUT_D3N signal.
[0027] Preferably, each of the M.2 port line modules includes: a first PETN0 / SATA_A- pin for receiving the ASM_PCIE_TX1N signal output by the M.2 gold finger module, a first PETP0 / SATA_A+ pin for outputting an ASM_PCIE_TX1P signal, a first PERN0 / SATA_B+ pin for outputting an ASM_PCIE_RX1N signal, and a first PERP0 / SATA_B- pin for outputting an ASM_PCIE_RX1P signal.
[0028] Furthermore, each of the M.2 port line modules includes: a first PERST / NC21 pin for outputting a DWNRST2_L signal and a PCIE_RST# signal to the M.2 gold finger, and a PEWAKE / NC3 pin for outputting a PCIE_WAKE signal.
[0029] Furthermore, each of the M.2 port line modules includes: a REFCLKN pin for receiving an ASM_PCIE_CLK1N signal output by the clock module and a REFCLKP pin for receiving an ASM_PCIE_CLK1P signal output by the clock module.
[0030] The utility model provides an adapter card for capacity expansion, which is used in conjunction with a central processing unit of a mainboard. The central processing area is used to output multiple PCIE signals and a single clock signal. The adapter card includes an M.2 gold finger module connected to the mainboard, an M.2 port circuit having multiple M.2 port line modules, a clock module and a detection module for receiving a control signal output by the M.2 gold finger module to drive multiple M.2 port line modules to conduct. When the mainboard is connected to the adapter card, the detection module outputs a detection signal to the M.2 gold finger module indicating that the adapter card is connected. The M.2 gold finger module feeds back the detection signal to the central processing unit. The central processing unit outputs control instructions of multiple PCIE signals and a single clock signal through the M.2 gold finger module according to the received detection signal. The clock module configures the single clock signal into a multiple clock module signal and distributes it to multiple M.2 modules to expand multiple M.2 port line modules. The central processing unit can automatically switch a single M.2 port line module 210 to multiple M.2 port line modules 210 according to the detection signal, thereby increasing the capacity, reducing the production cost, and not affecting the speed. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the technical solution of the present utility model, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0032] Figure 1 It is a block diagram of an adapter card for capacity expansion provided in an embodiment of the utility model.
[0033] Figure 2 It is a circuit diagram of an M.2 gold finger module in a capacity expansion adapter card provided in an embodiment of the utility model.
[0034] Figure 3 It is a circuit diagram of a single M.2 port line module in a capacity expansion adapter card provided in an embodiment of the utility model.
[0035] Figure 4 It is a circuit diagram of a clock module in a capacity expansion adapter card provided in an embodiment of the utility model.
[0036] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0037] In the present invention, the terms "first", "second", etc. are mainly used to distinguish different devices, elements or components, which may be the same or different in specific types and structures, and are not used to indicate or imply the relative importance and quantity of the indicated devices, elements or components. Unless otherwise specified, "plurality" means two or more.
[0038] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.
[0039] Overview of the riser card for capacity expansion as an example
[0040] like Figure 1 As shown, an adapter card for capacity expansion provided by an embodiment of the utility model is used in conjunction with a central processing unit (not shown) on a motherboard, wherein the central processing area is used to output multiple PCIE signals and a single clock signal, and is characterized in that the adapter card for capacity expansion includes:
[0041] M.2 gold finger module 100, used for detachable electrical connection with the motherboard and communication with the central processing unit on the motherboard;
[0042] The M.2 port circuit 200 has a plurality of M.2 port line modules 210;
[0043] The clock module 300 is used to convert the single clock signal into multiple clock signals to distribute to the multiple M.2 port line modules 210, and activate the multiple M.2 port line modules 210;
[0044] The detection module 400 is used to detect the electrical connection state between the mainboard and the adapter card for capacity expansion, and output a detection signal indicating that an expansion card is connected to the M.2 gold finger module 100 after detecting that the mainboard and the adapter card are electrically connected;
[0045] The M.2 gold finger module 100 is further used to feed back the detection signal to the central processor, receive control instructions of multiple PCIE signal channels and a single clock signal from the central processor, establish a signal transmission channel with multiple M.2 port line modules 210 in response to the control instruction, and send the single clock signal to the clock module 300;
[0046] The clock module 300 is further used to configure the single-channel clock signal into a multi-channel clock signal after receiving the single-channel clock signal and distribute it to the multiple M.2 port line modules 210 to synchronize the signal transmission clocks of the multiple M.2 port line modules 210.
[0047] The utility model can realize multiple M.2 port line modules 210 through an adapter card and corresponding software configuration in the central processor. The central processor can automatically switch a single M.2 port line module 210 to multiple M.2 port line modules 210 according to the detection signal, thereby improving the capacity, reducing the production cost, and not affecting the speed.
[0048] Overview of the M.2 Gold Finger Module as an Example
[0049] like Figure 2 As shown, preferably, the M.2 gold finger module 100 is used to electrically connect to the M.2 port for expansion on the motherboard, and includes a first channel 110, a second channel 120, a third channel 130 and a fourth channel 140;
[0050] The first channel 110 includes: a PETN0 / SATA_A- pin for outputting a PCIE9_TX_DN signal to the M.2 port, a PETP0 / SATA_A+ pin for outputting a PCIE9_TX_DP signal to the M.2 port; a PERN0 / SATA_B+ pin for receiving a PCIE9_RX_DN signal output by the M.2 port, and a PERP0 / SATA_B- pin for receiving a PCIE9_RX_DP signal output by the M.2 port;
[0051] The second channel 120 includes: a PERN1 pin for outputting a PCIE10_RX_DN signal to the M.2 port, a PERP1 pin for outputting a PCIE10_RX_DP signal to the M.2 port; a PETN1 pin for receiving a PCIE10_TX_DN signal output by the M.2 port, and a PETP1 pin for receiving a PCIE10_TX_DP signal output by the M.2 port;
[0052] The third channel 130 includes: a PERN2 pin for outputting a PCIE11_RX_DN signal to the M.2 port, a PERP2 pin for outputting a PCIE11_RX_DP signal to the M.2 port; a PETN2 pin for receiving a PCIE11_TX_DN signal output by the M.2 port, and a PETP2 pin for receiving a PCIE11_TX_DP signal output by the M.2 port;
[0053] The fourth channel 140 includes: a PERN3 pin for outputting a PCIE12_RX_DN signal to the M.2 port, a PERP3 pin for outputting a PCIE12_RX_DP signal to the M.2 port; a PETN3 pin for receiving a PCIE12_TX_DN signal output by the M.2 port, and a PETT3 pin for receiving a PCIE12_RX_DN signal output by the M.2 port.
[0054] Furthermore, the M.2 gold finger module includes a clock channel 150, and the clock channel includes a REFCLKN pin for receiving a PCIE_REFCLK_SSD_DN signal output by the M.2 port, and a REFCLKP pin for receiving a PCIE_REFCLK_SSD_DP signal output by the M.2 port.
[0055] Furthermore, the M.2 gold finger module includes a logic channel 160, which includes an NC6 pin grounded through a resistor, a PERST / NC21 pin receiving an M.2 port input MUF_PLT_RS signal, and a PEWAKE / NC3 pin outputting a PCIL_WAKI signal to the M.2 port.
[0056] Overview of the M.2 line module as an example
[0057] like Figure 3 As shown, preferably, each of the M.2 port line modules 210 includes: a first PETN0 / SATA_ A- pin for receiving the ASM_PCIE_TX1N signal output by the M.2 gold finger module 100, a first PETP0 / SATA_ A+ pin for outputting the ASM_PCIE_TX1P signal, a first PERN0 / SATA_B+ pin for outputting the ASM_PCIE_RX1N signal, and a first PERP0 / SATA_B- pin for outputting the ASM_PCIE_RX1P signal;
[0058] The first PETN0 / SATA_A- of the M.2 port line module 210 is connected to the PETN0 / SATA_A- pin of the M.2 gold finger module 100, and a coupling capacitor C1 is connected between the two.
[0059] The first PETP0 / SATA_A+ pin of the M.2 port line module 210 is connected to the PETP0 / SATA_A+ pin of the M.2 gold finger module 100, and a coupling capacitor C2 is connected between the two;
[0060] The first PERN0 / SATA_B+ of the M.2 port line module 210 is connected to the PERN0 / SATA_B+ pin of the M.2 gold finger module 100, and the two can be directly connected or connected with a 0 ohm resistor;
[0061] The first PERP0 / SATA_B- of the M.2 port line module 210 is connected to the PERP0 / SATA_B- pin of the M.2 gold finger module 100, and the two can be directly connected or connected with a 0 ohm resistor.
[0062] Furthermore, each of the M.2 port line modules 210 also includes: a first PERST / NC21 pin for outputting a DWNRST2_L signal and a PCIE_RST# signal to the M.2 gold finger, and a first PEWAKE / NC3 pin for outputting a PCIE_WAKE signal;
[0063] The first PERST / NC21 of the M.2 port line module 210 is connected to the PERST / NC21 of the M.2 gold finger, and the first PEWAKE / NC3 of the M.2 port line module 210 is connected to the PEWAKE / NC3 of the M.2 gold finger.
[0064] Furthermore, each of the M.2 port line modules 210 further includes: a REFCLKN pin for receiving an ASM_PCIE_CLK1N signal output by the clock module and a REFCLKP pin for receiving an ASM_PCIE_CLK1P signal output by the clock module;
[0065] The REFCLKN pin is connected to the Q0- pin of the clock module, and the REFCLKP pin is connected to the Q0+ pin of the clock module.
[0066] Clock Module Overview as an Example
[0067] like Figure 4 As shown, preferably, the clock module 300 includes: a clock expansion chip that expands one clock signal into multiple clock signal outputs, which is used to supply the solid state drives with 4 PCIE 1 channels on the expansion board. In this example, the clock module 300 is preferably PI6CBE33045, and can also be TI CDCDB400.
[0068] Preferably, the clock expansion chip comprises: an IN+ pin for receiving a PCIE_CLK_DP signal output by the motherboard CLK, and an IN- pin for receiving a PCIE_CLK_DN signal output by the motherboard CLK;
[0069] Furthermore, the clock expansion chip further includes: a first group of clock output channels 310, a second group of clock output channels 320, a third group of clock output channels 330 and a fourth group of clock output channels 340;
[0070] The first group of clock output channels 310 includes: a Q0+ pin for outputting a PCIE_CLK_OUT_D0P signal, and a Q0- pin for outputting a PCIE_CLK_OUT_D0N signal; PCIE_CLK_OUT_D0P is connected to pin 55 of the first M.2 port line module 210, and PCIE_CLK_OUT_D0N is connected to the REFCLKN pin of the first M.2 port line module 210.
[0071] The second group of clock output channels 320 includes: a Q1+ pin for outputting a PCIE_CLK_OUT_D1P signal, and a Q1- pin for outputting a PCIE_CLK_OUT_D1N signal; PCIE_CLK_OUT_D1P is connected to the REFCLKP pin of the second M.2 port line module 210, and PCIE_CLK_OUT_D1N is connected to the REFCLKN pin of the second M.2 port line module 210.
[0072] The third group of clock output channels 330 includes: a Q2+ pin for outputting a PCIE_CLK_OUT_D2P signal, and a Q2- pin for outputting a PCIE_CLK_OUT_D2N signal; PCIE_CLK_OUT_D2P is connected to the REFCLKP pin of the third M.2 port line module 210, and PCIE_CLK_OUT_D2N is connected to the REFCLKN pin of the third M.2 port line module 210.
[0073] The fourth group of clock output channels 340 includes: a Q3+ pin for outputting a PCIE_CLK_OUT_D3P signal, and a Q3- pin for outputting a PCIE_CLK_OUT_D3N signal. PCIE_CLK_OUT_D3P is connected to the REFCLKP pin of the fourth M.2 port circuit module 210, and PCIE_CLK_OUT_D3N is connected to the REFCLKN pin of the fourth M.2 port circuit module 210.
[0074] The first, second, third and fourth M.2 port line modules 210 are described in the specification. Figure 1Arranged from top to bottom.
[0075] In this embodiment, the M.2 port circuit 200 and the clock module 300 are both powered by the power module 500, and the power supply voltage is 3.3V, wherein the 3.3V voltage is used by the motherboard to charge or power the power module through the M.2 gold finger, which saves lines and facilitates power supply.
[0076] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the protection scope of the present invention.
Claims
1. A capacity expansion adapter card, used in conjunction with a central processing unit on a motherboard, the central processing unit is used to output multiple PCIE signals and a single clock signal, characterized in that: The capacity expansion adapter card includes: M.2 gold finger module, which is used for detachable electrical connection with the motherboard and communication with the central processing unit on the motherboard; M.2 port circuit, with multiple M.2 port line modules; A clock module, used for converting the single clock signal into multiple clock signals to distribute to multiple M.2 port line modules, and activating multiple M.2 port line modules; A detection module, used to detect the electrical connection state between the mainboard and the capacity expansion adapter card, and output a detection signal indicating that an expansion card is connected to the M.2 gold finger module after detecting that the mainboard and the capacity expansion adapter card are electrically connected; The M.2 gold finger module is further used to feed back the detection signal to the central processor, receive control instructions of multiple PCIE signal channels and a single clock signal from the central processor, establish a signal transmission channel with multiple M.2 port line modules in response to the control instruction, and send the single clock signal to the clock module; The clock module is further used to configure the single-channel clock signal into a multi-channel clock signal after receiving the single-channel clock signal and distribute it to multiple M.2 port line modules to synchronize the signal transmission clocks of the multiple M.2 port line modules.
2. The capacity expansion adapter card according to claim 1, characterized in that: The M.2 gold finger module is used to electrically connect to the M.2 port for expansion on the motherboard, and includes a first channel, a second channel, a third channel and a fourth channel; The first channel includes: a PETN0 / SATA_A- pin for outputting a PCIE9_TX_DN signal to the M.2 port, a PETP0 / SATA_A+ pin for outputting a PCIE9_TX_DP signal to the M.2 port; a PERN0 / SATA_B+ pin for receiving a PCIE9_RX_DN signal output by the M.2 port, and a PERP0 / SATA_B- pin for receiving a PCIE9_RX_DP signal output by the M.2 port; The second channel includes: a PERN1 pin for outputting a PCIE10_RX_DN signal to the M.2 port, a PERP1 pin for outputting a PCIE10_RX_DP signal to the M.2 port; a PETN1 pin for receiving a PCIE10_TX_DN signal output by the M.2 port, and a PETP1 pin for receiving a PCIE10_TX_DP signal output by the M.2 port; The third channel includes: a PERN2 pin for outputting a PCIE11_RX_DN signal to the M.2 port, a PERP2 pin for outputting a PCIE11_RX_DP signal to the M.2 port; a PETN2 pin for receiving a PCIE11_TX_DN signal output by the M.2 port, and a PETP2 pin for receiving a PCIE11_TX_DP signal output by the M.2 port; The fourth channel includes: a PERN3 pin for outputting a PCIE12_RX_DN signal to the M.2 port, a PERP3 pin for outputting a PCIE12_RX_DP signal to the M.2 port; a PETN3 pin for receiving a PCIE12_TX_DN signal output by the M.2 port, and a PETT3 pin for receiving a PCIE12_RX_DN signal output by the M.2 port.
3. The capacity expansion adapter card according to claim 2, characterized in that: The M.2 gold finger module includes a clock channel, and the clock channel includes a REFCLKN pin receiving a PCIE_REFCLK_SSD_DN signal output by the M.2 port, and a REFCLKP pin receiving a PCIE_REFCLK_SSD_DP signal output by the M.2 port.
4. The capacity expansion adapter card according to claim 3, characterized in that: The M.2 gold finger module includes a logic channel, which includes an NC6 pin grounded through a resistor, a PERST / NC21 pin receiving an M.2 port input MUF_PLT_RS signal, and a PEWAKE / NC3 pin outputting a PCIL_WAKI signal to the M.2 port.
5. The capacity expansion adapter card according to claim 1, characterized in that: The clock module includes: a clock expansion chip that expands one clock signal into multiple clock signal outputs, which are used to supply the solid state hard disks with 4 PCIE 1 channels on the expansion board respectively.
6. The capacity expansion adapter card according to claim 5, characterized in that: The clock expansion chip comprises: an IN+ pin for receiving a PCIE_CLK_DP signal output by a mainboard CLK, and an IN- pin for receiving a PCIE_CLK_DN signal output by a mainboard CLK.
7. The capacity expansion adapter card according to claim 5, characterized in that: The clock expansion chip also includes: a first group of clock output channels, a second group of clock output channels, a third group of clock output channels and a fourth group of clock output channels; The first group of clock output channels includes: a Q0+ pin for outputting a PCIE_CLK_OUT_D0P signal, and a Q0- pin for outputting a PCIE_CLK_OUT_D0N signal; The second group of clock output channels includes: a Q1+ pin for outputting a PCIE_CLK_OUT_D1P signal, and a Q1- pin for outputting a PCIE_CLK_OUT_D1N signal; The third group of clock output channels includes: a Q2+ pin for outputting a PCIE_CLK_OUT_D2P signal, and a Q2- pin for outputting a PCIE_CLK_OUT_D2N signal; The fourth group of clock output channels includes: a Q3+ pin for outputting a PCIE_CLK_OUT_D3P signal, and a Q3- pin for outputting a PCIE_CLK_OUT_D3N signal.
8. The capacity expansion adapter card according to claim 2, characterized in that: Each of the M.2 port circuit modules includes: a first PETN0 / SATA_A- pin for receiving the ASM_PCIE_TX1N signal output by the M.2 gold finger module, a first PETP0 / SATA_A+ pin for outputting the ASM_PCIE_TX1P signal, a first PERN0 / SATA_B+ pin for outputting the ASM_PCIE_RX1N signal, and a first PERP0 / SATA_B- pin for outputting the ASM_PCIE_RX1P signal, wherein the first PETN0 / SATA_A- It is connected to the PETN0 / SATA_A- pin of the M.2 gold finger module, the first PETP0 / SATA_A+ pin of the M.2 port circuit module is connected to the PETP0 / SATA_A+ pin of the M.2 gold finger module, the first PERN0 / SATA_B+ of the M.2 port circuit module is connected to the PERN0 / SATA_B+ pin of the M.2 gold finger module, and the first PERP0 / SATA_B- of the M.2 port circuit module is connected to the PERP0 / SATA_B- pin of the M.2 gold finger module.
9. The capacity expansion adapter card according to claim 1, characterized in that: Each of the M.2 port circuit modules includes: a first PERST / NC21 pin for outputting a DWNRST2_L signal and a PCIE_RST# signal to the M.2 gold finger, and a first PEWAKE / NC3 pin for outputting a PCIE_WAKE signal. The first PERST / NC21 of the M.2 port circuit module is connected to the PERST / NC21 of the M.2 gold finger, and the first PEWAKE / NC3 of the M.2 port circuit module is connected to the PEWAKE / NC3 of the M.2 gold finger.
10. The capacity expansion adapter card according to claim 7, characterized in that: Each of the M.2 port line modules includes: a REFCLKN pin for receiving the ASM_PCIE_CLK1N signal output by the clock module and a REFCLKP pin for receiving the ASM_PCIE_CLK1P signal output by the clock module, the REFCLKN pin is connected to the Q0- pin of the clock module, and the REFCLKP pin is connected to the Q0+ pin of the clock module.