Computing fast interconnection converter chip, memory access processing method and electronic equipment

Abstract

The invention provides a computing fast interconnection converter chip, a memory access processing method and electronic equipment, and relates to the technical field of research and development of basic hardware, design and research and development of chips and the like. According to the specific implementation, the CXL Switch chip comprises at least two CPU uplink port control logic units, at least two CXL downlink port control logic units, an interconnection bus, a consistency cache control logic unit and a cache; the at least two CPU uplink port control logic units, the at least two CXL downlink port control logic units, the consistency cache control logic unit and the cache are respectively connected with the interconnection bus; wherein the consistency cache control logic unit and the cache are used for realizing at least two CPU (Central Processing Unit) chips externally connected with the CXL Switch chip, and at least two CXL memory expansion cards connected through the CXL Switch chip can be shared. According to the technology disclosed by the invention, the pooling function of the CXL can be realized, and the application range of the CXL memory expansion card is effectively enriched.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, specifically to the research and development of basic hardware, and the design and development of chips and other technical fields, and more particularly to a computing fast interconnect converter chip, a memory access processing method and an electronic device. Background Art

[0002] Compute Express Link (CXL) is the core technology for achieving storage and computing separation.

[0003] With the evolution of CXL technology, CXL expansion function has emerged, which can realize memory expansion of a single machine. In specific implementation, a CXL memory expansion card can be set to realize memory expansion. Furthermore, with the evolution of CXL technology, CXL pooling function has emerged, which can realize memory sharing among multiple central processing unit (CPU) chips. Summary of the invention

[0004] The present invention provides a computing fast interconnect converter chip, a memory access processing method and an electronic device.

[0005] According to one aspect of the present disclosure, a computing fast interconnect converter chip is provided, comprising: at least two computing fast interconnect upstream port control logic units, at least two computing fast interconnect downstream port control logic units, an interconnect bus, and a consistent cache control logic unit and a cache; the at least two computing fast interconnect upstream port control logic units, the at least two computing fast interconnect downstream port control logic units, the consistent cache control logic unit and the cache are respectively connected to the interconnect bus;

[0006] Wherein, the at least two computing fast interconnection uplink port control logic units are also connected to at least two central processing unit chips; the at least two computing fast interconnection downlink port control logic units are also connected to at least two computing fast interconnection memory expansion cards;

[0007] The coherent cache control logic unit and the cache are used to enable the at least two central processing unit chips to share the at least two computing fast interconnect memory expansion cards.

[0008] According to another aspect of the present disclosure, a data memory access processing method based on the chip as described in any one of the above aspects is provided, wherein the method comprises:

[0009] For each computing fast interconnect uplink port control logic unit, the computing fast interconnect uplink port control logic unit receives a memory access request sent by a connected central processing unit chip, wherein the memory access request carries a memory access address; the memory access address is an address in any computing fast interconnect memory expansion card of the at least two computing fast interconnect memory expansion cards; and forwards the memory access request to an interconnect bus;

[0010] The interconnect bus forwards the memory access request to a coherent cache control logic unit;

[0011] The coherent cache control logic unit performs data memory access processing based on the memory access request.

[0012] According to yet another aspect of the present disclosure, an electronic device is provided, comprising: a computing fast interconnect converter chip as described in any one of the above aspects.

[0013] According to the technology disclosed in the present invention, a CXL memory expansion card that only supports the CXL expansion function can also realize the CXL pooling function, which can effectively enrich the application scope of the CXL memory expansion card.

[0014] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0016] Figure 1 is a schematic diagram according to a first embodiment of the present disclosure;

[0017] Figure 2 is a schematic diagram according to a second embodiment of the present disclosure;

[0018] Figure 3 This is an application example diagram of a CXL memory card with CXL pooling function provided by the present disclosure;

[0019] Figure 4 is a schematic diagram according to a third embodiment of the present disclosure;

[0020] Figure 5 is a schematic diagram according to a fourth embodiment of the present disclosure;

[0021] Figure 6 is a schematic diagram according to a fifth embodiment of the present disclosure;

[0022] Figure 7 is a schematic diagram according to a sixth embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0024] Obviously, the described embodiments are only part of the embodiments of the present disclosure, but not all of them. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0025] It should be noted that the terminal devices involved in the embodiments of the present disclosure may include but are not limited to mobile phones, personal digital assistants (PDAs), wireless handheld devices, tablet computers and other smart devices; display devices may include but are not limited to personal computers, televisions and other devices with display functions.

[0026] In addition, the term "and / or" in this article is only a description of the association relationship between the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0027] In actual applications, when implementing the extended functions of CXL, the CXL controller only needs to implement the protocol conversion from the CXL protocol to the Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM; DDR for short) controller, without involving issues related to handling cache consistency. When implementing the pooling function of CXL, it is generally necessary to introduce a CXL Switch chip and a CXL controller that supports the CXL pooling function. In order to support the pooling function of CXL, while implementing the protocol conversion function from the CXL protocol to the DDR controller, it is also necessary to add logic for handling cache consistency issues.

[0028] In the prior art, the CXL expansion function appeared first, resulting in a large number of CXL memory expansion cards that only support the CXL expansion function on the market. Later, the CXL pooling function appeared. To implement the CXL pooling function, it is necessary to set up a CXL memory card that supports the pooling function. However, since the CXL memory expansion card that supports the CXL expansion function does not support the pooling function, that is, the CXL memory expansion card cannot handle cache consistency-related issues, the CXL memory expansion card that supports the CXL expansion function cannot implement the CXL pooling function.

[0029] Based on the above technical problems, the present disclosure provides a CXL converter (Switch) chip, which can enable a CXL memory expansion card that only supports CXL expansion functions to also realize the CXL pooling function. When used in CXL memory sharing scenarios, it can effectively enrich the application scope of CXL memory expansion cards.

[0030] Figure 1 is a schematic diagram according to the first embodiment of the present disclosure; Figure 1 As shown, this embodiment provides a CXL switch chip 100, including: at least two CXL upstream port control logic units 101, at least two CXL downstream port control logic units 102, an interconnection bus 103, and a consistent cache control logic unit 104 and a cache 105; the at least two CXL upstream port control logic units 101, at least two CXL downstream port control logic units 102, the consistent cache control logic unit 104 and the cache 105 are respectively connected to the interconnection bus 103.

[0031] like Figure 1 As shown, in this embodiment, the coherent cache control logic unit 104 and the cache 105 are separately configured as an example. In actual applications, the two can also be configured as an integrated structure. In this embodiment, the coherent cache control logic unit 104 is connected to the cache 105.

[0032] The coherent cache control logic unit 104 and the cache 105 are used to enable at least two CPU chips externally connected to the CXL Switch chip 100 to share at least two CXL memory expansion cards connected via the CXL Switch chip 100 .

[0033] That is, in this embodiment, at least two CXL uplink port control logic units 101 are also connected to at least two central processing unit chips; at least two CXL downlink port control logic units 102 are also connected to at least two CXL memory expansion cards.

[0034] For example, in a specific implementation, one end of at least two CXL upstream port control logic units 101 is connected to at least two CPU chips; specifically, one end of each CXL upstream port control logic unit 101 is connected to a CPU chip. One end of at least two CXL downstream port control logic units 102 is connected to at least two CXL memory expansion cards, specifically, one end of each CXL downstream port control logic unit is connected to a CXL memory expansion card; the other end of each CXL upstream port control logic unit 101, the other end of each CXL downstream port control logic unit 102, and the coherent cache control logic unit 104 and the cache 105 are respectively connected to the interconnect bus 103.

[0035] The CXL memory expansion card in this embodiment is a CXL memory expansion card that does not have the CXL pooling capability. The CXL memory expansion card in this embodiment may include a CXL controller and a memory stick. The CXL Switch chip 100 in this embodiment, when applied, can be connected to multiple CPU chips and multiple CXL memory expansion cards at the same time, and multiple CXL memory expansion cards can form a memory pool to realize multiple CPU chips sharing the memory pool. Although the multiple CXL memory expansion cards in this embodiment do not support the pooling function, in this embodiment, by setting a consistent cache control logic unit 104 and a cache 105 in the CXL Switch chip 100, the logic of the cache consistency problem can be processed. In this way, multiple CXL memory expansion cards can realize the function of protocol conversion from CXL protocol to DDR controller, and the consistent cache control logic unit 104 and the cache 105 can process the logic of the cache consistency problem, and then the CXL Switch chip 100 in this embodiment can be used to realize multiple CPU chips sharing multiple CXL memory expansion cards. The CXL Switch chip 100 of this embodiment, by setting a consistent cache control logic unit 104 and a cache 105 in the CXL Switch chip 100, can enable the CXL Switch chip 100 to implement memory sharing based on a CXL memory expansion card that does not have a pooling capability, which can effectively enrich the application scope of the CXL memory expansion card that does not have a pooling capability; and can also make memory sharing no longer dependent on a newly developed CXL memory card that supports a pooling function.

[0036] Figure 2 is a schematic diagram according to the second embodiment of the present disclosure; Figure 2 As shown, the CXL Switch chip 200 provided in this embodiment can be Figure 1 Based on the technical solutions of the illustrated embodiments, the technical solutions of the present disclosure are further described in more detail.

[0037] like Figure 2As shown, the CXL Switch chip 200 provided in this embodiment includes the above Figure 1 The structure of the CXL Switch chip 100 of the embodiment shown.

[0038] Furthermore, in this embodiment, the coherent cache control logic unit 204 and the cache 205 in the CXL Switch chip 200 are described in more detail to implement how at least two CPU chips can share at least two CXL memory expansion cards.

[0039] Specifically, in this embodiment, for each CXL uplink port control logic unit 201, the CXL uplink port control logic unit 201 is used to receive a memory access request sent by a connected CPU chip, and the memory access request carries a memory access address; the memory access address is an address in any CXL memory expansion card of at least two CXL memory expansion cards; the memory access request of this embodiment is an access request or a storage request of the CPU chip to any CXL memory expansion card of at least two CXL memory expansion cards; that is, the memory access address of this embodiment includes an access address or a storage address.

[0040] The interconnect bus 203 is used to forward the memory access request to the coherent cache control logic unit 204;

[0041] The consistent cache control logic unit 204 is used to perform data memory access processing based on the memory access request.

[0042] It should be noted that when the coherent cache control logic unit 204 performs data access processing based on a memory access request, it also needs to refer to the data in the cache when necessary.

[0043] Further optionally, in an embodiment of the present disclosure, the processing of an access request by the CXL Switch chip 200 of this embodiment is first introduced, which may specifically include the following contents.

[0044] For each CXL uplink port control logic unit 201, the CXL uplink port control logic unit 201 is used to receive an access request sent by a connected CPU chip, where the access request carries an access address;

[0045] The interconnect bus 203 is used to forward the access request to the coherent cache control logic unit 204;

[0046] The coherent cache control logic unit 204 is used to obtain the data of the access address based on the recorded memory data status information table; and transmit the data to the CPU chip through the interconnection bus 203 and the CXL uplink port control logic unit 201.

[0047] In this embodiment, the memory data status information table in the coherent cache control logic unit 204 records the cache conditions and cache status of the data of the memory address that it is responsible for managing;

[0048] Specifically, the coherent cache control logic unit 204 is responsible for managing the data of the memory addresses of at least two CXL memory expansion cards connected to the CXL Switch chip 200. When the data of a certain memory address managed by the coherent cache control logic unit 204 is read by one of the at least two CPUs connected to the CXLSwitch chip 200, the memory address of the read data, the identifier of the CPU reading the data, the operation state of the CPU reading the data, and the state of the data in the cache 205 can be recorded in the memory data state information. Among them, the operation state of the CPU reading the data includes reading or reading and modifying. If the operation state is reading, it means that the CPU reading the data has not modified the data of the memory address. At this time, if the data of the memory address is stored in the cache 205, it is still in a valid state; if the data of the memory address is not stored in the cache 205, the data is stored in the CXL memory expansion card to which the corresponding memory address belongs, and the state is also valid. If the operation state is reading and modifying, it means that the CPU reading the data has modified the data of the memory address after reading the data of the memory address. At this time, if the data of the memory address is stored in the local cache 205, it is in an invalid state. Similarly, the data of the memory address in the CXL memory expansion card to which the memory address belongs is also invalid. In this embodiment, the coherent cache control logic unit 204 and the corresponding cache 205 appear in pairs, and both must exist at the same time.

[0049] The coherent cache control logic unit 204 is responsible for managing the data of the memory addresses of at least two CXL memory expansion cards. The data in the recently accessed memory addresses can be stored in the corresponding cache 205 to improve the response speed in subsequent accesses.

[0050] Specifically, in the embodiment of the present disclosure, the coherent cache control logic unit 204 obtains the data of the access address based on the recorded memory data status information table, mainly including the following application scenarios:

[0051] For example, in the first application scenario, data of the access address may be obtained from the cache.

[0052] Specifically, the consistent cache control logic unit 204 can be used to determine that the data of the access address is stored in the cache and the data is valid based on the recorded memory data status information table and the data stored in the cache, and then determine that the data of the access address needs to be obtained from the cache, and the data of the access address is obtained from the cache. For example, the consistent cache control logic unit 204 can detect whether the data of the access address is stored in the cache according to the memory status information table. If it is stored and valid, the data of the access address can be directly obtained from the cache. Correspondingly, the consistent cache control logic unit 204 then transmits the obtained data of the access address to the CPU chip that sends the access request through the interconnect bus 203 and the CXL uplink port control logic unit 201.

[0053] In the second application scenario, data of the access address may be obtained from the first target CXL memory expansion card corresponding to the access address.

[0054] Specifically, the CXL uplink port control logic unit 201 is used to obtain the identifier of the first target CXL downlink port control logic unit connected to the first target CXL memory expansion card corresponding to the access address according to the preset configuration information and the access address; and forward it to the interconnection bus 203 together with the access request; the first target CXL memory expansion card is the CXL memory expansion card corresponding to the access address among the at least two CXL memory expansion cards.

[0055] In this embodiment, the preset configuration information may include the identifier of each CXL downstream port control logic unit and the corresponding relationship between the address segments that the CXL memory expansion card connected to the CXL downstream port control logic unit is responsible for. The corresponding relationship is pre-configured and stored in each CXL upstream port control logic unit 201. Based on this, each time an access request is received, the CXL memory expansion card to which the access address in the access request belongs can be obtained based on the corresponding relationship in the configuration relationship, and then the identifier of the corresponding CXL downstream port control logic unit can be accurately and efficiently obtained.

[0056] The interconnect bus 203 is used to forward the memory access request and the identifier of the first target CXL downstream port control logic unit 202 to the coherent cache control logic unit 204;

[0057] The consistent cache control logic unit 204 is also used to determine that the data of the access address is not stored in the cache based on the recorded memory data status information table and the data stored in the cache. When the data of the access address stored in the first target CXL memory expansion card is valid, it is determined that the data of the access address needs to be obtained from the first target CXL memory expansion card, and an access request is sent to the first target CXL memory expansion card through the interconnection bus and the first target CXL downlink port control logic unit 202, so that the first target CXL memory expansion card can return the data after reading the data from the memory. In this embodiment, the link for returning data is the reverse link of the access request data. Specifically, the first target CXL memory expansion card returns the data to the consistent cache control logic unit 204 through the first target CXL downlink port control logic unit 202 and the interconnection bus 203. The consistent cache control logic unit 204 transmits the data to the CPU chip that sends the access request through the interconnection bus 203 and the CXL uplink port control logic unit 201.

[0058] Further optionally, in this embodiment, it may be configured that after the first target CXL memory expansion card reads data from the memory, the data is directly transmitted to the CPU chip that sends the access request through the interconnection bus 203 and the CXL uplink port control logic unit 201 .

[0059] In the third application scenario, the access address data can be obtained from other CPU chips.

[0060] Specifically, the coherent cache control logic unit 204 is also used to determine that the data corresponding to the access address in the first target CXL memory expansion card corresponding to the cache and the access address is invalid based on the recorded memory data status information table and the data stored in the cache 205; or the data of the access address is not stored in the cache, and the data corresponding to the access address in the first target CXL memory expansion card corresponding to the access address is invalid; and it can also be determined that the valid data of the access address is stored in the memory of other CPUs, at this time, a listening command is sent to other CPU chips through the interconnection bus 203 and other CXL uplink port control logic units 201, and the listening command carries the access address, so that other CPU chips can obtain the data of the access address and return the data. Similarly, the link for returning data is the reverse link for sending the listening command. Specifically, other CPU chips transmit the acquired data to the coherent cache control logic unit 204 through other CXL uplink port control logic units 201 and the interconnection bus 203.

[0061] In this embodiment, the other CPU refers to a CPU other than the CPU that issues the access request. The other CXL uplink port control logic unit 201 refers to a CXL uplink port control logic unit connected to other CPUs.

[0062] In this embodiment, by adopting the above three scenarios, any one of the at least two CPUs can accurately and efficiently access and process the data in any one of the at least two CXL memory expansion cards, thereby effectively enabling at least two CPUs to share the memory of at least two CXL memory expansion cards.

[0063] The processing of the data storage request by the CXL Switch chip 200 of this embodiment is described in detail below, which may specifically include the following two implementations:

[0064] In the first implementation, when writing data, it can be written only in the cache 205 .

[0065] Specifically, for each CXL uplink port control logic unit 201, the CXL uplink port control logic unit 201 is further configured to receive a first storage request sent by a connected CPU chip, where the first storage request carries a first storage address and first data;

[0066] The CXL uplink port control logic unit 201 is further configured to obtain, according to preset configuration information and the first storage address, an identifier of a second target CXL downlink port control logic unit 202 connected to a second target CXL memory expansion card corresponding to the first storage address; and forward the identifier to the interconnection bus 203 together with the first storage request; the second target CXL memory expansion card is a CXL memory expansion card corresponding to the first storage address among the at least two CXL memory expansion cards;

[0067] The interconnect bus 203 is used to forward the first storage request and the identifier of the second target CXL downstream port control logic unit 202 to the coherent cache control logic unit 204;

[0068] The coherent cache control logic unit 204 is configured to store the first storage address, the first data and the identifier of the second target CXL downstream port control logic unit 202 in the cache 205 and update the memory data status information table.

[0069] The data storage mechanism of this implementation is to write all data into the cache first, and then write the data into the corresponding CXL memory expansion card when the data in the cache becomes invalid.

[0070] In this embodiment, while storing data in the cache 205, the identifier of the corresponding second target CXL downstream port control logic unit 202 also needs to be stored. Specifically, a field can be expanded during storage to store the identifier so that when the first data is invalidated later, it can be stored in the corresponding CXL memory expansion card in a timely and accurate manner.

[0071] For example, further optionally, in the data storage process of the implementation, all data are first stored in the cache 205 after being received, so that the data in the cache will be filled up quickly. Specifically, when the data in the cache 205 is full, the data that is about to expire can be re-cached in a CXL memory expansion card.

[0072] Specifically, the cache 205 is also used to determine invalid data when the data is full; wherein the cache 205 may determine the invalid data by selecting the data with the earliest storage time, or by selecting the data with the lowest frequency of use, or by other methods, which are not limited here. Then, the cache 205 is also used to send the invalid data, the corresponding second storage address and the corresponding identifier of the third target CXL downlink port control logic unit 202 to the interconnection bus 203, and the interconnection bus 203 sends the invalid data and the corresponding second storage address to the connected third target CXL memory expansion card through the corresponding third target CXL downlink port control logic unit based on the identifier of the third target CXL downlink port control logic unit, so that the third target CXL memory expansion card writes the invalid data in the cache at the corresponding second storage address.

[0073] The consistent cache control logic unit 204 is used to update the memory data status information table based on the invalid data.

[0074] In a second implementation, when writing data, data may be written to the cache 205 and the corresponding CXL memory expansion card at the same time.

[0075] Specifically, for each CXL uplink port control logic unit 201, the CXL uplink port control logic unit 201 is further configured to receive a second storage request sent by a connected CPU chip, wherein the second storage request carries a third storage address and second data;

[0076] The CXL uplink port control logic unit 201 is further configured to obtain an identifier of a fourth target CXL downlink port control logic unit connected to a fourth target CXL memory expansion card to be stored according to preset configuration information and a third storage address; and forward the identifier to the interconnection bus 203 together with the second storage request; the fourth target CXL memory expansion card is a CXL memory expansion card corresponding to the third storage address among the at least two CXL memory expansion cards;

[0077] The interconnection bus 203 is used to forward the second storage request to the coherent cache control logic unit 204; and also based on the identifier of the fourth target CXL downlink port control logic unit, send the second storage request to the connected fourth target CXL memory expansion card through the corresponding fourth target CXL downlink port control logic unit, so that the fourth target CXL memory expansion card writes the second data on the corresponding third storage address;

[0078] The consistent cache control logic unit 204 is used to store the third storage address and the second data in the cache 205 and update the memory data status information table.

[0079] The CXL Switch chip 200 of this embodiment, by providing a consistent cache control logic unit 204 and a cache 205, adopts the above two data storage processing methods, so that any one of the at least two CPUs can perform accurate and efficient data storage processing in any one of the at least two CXL memory expansion cards, thereby effectively enabling at least two CPUs to share the memory of at least two CXL memory expansion cards.

[0080] like Figure 2 As shown, the CXL Switch chip 200 of this embodiment further includes a fabric manager (FabricManager; FM) management logic unit 206, which is used to configure the corresponding relationship between the storage address fragments corresponding to each CXL memory expansion card and the identifier of the corresponding connected CXL downstream port control logic unit 202, and transmit the corresponding relationship to each CXL upstream port control logic unit 201 through the interconnection bus 203. In this way, the corresponding relationship can be stored in each CXL upstream port control logic unit 201 as preset configuration information, providing effective support for subsequent data access and data storage.

[0081] In this embodiment, a mature and reliable CXL memory expansion card can be used to build a CXL memory pooling system without relying on a newly developed CXL memory card that supports the pooling function. Moreover, in this embodiment, by designing a cache in the CXL Switch chip 200, compared with designing a cache in the CXL memory card, the CPU access delay to the CXL memory pool can be better reduced, thereby effectively improving the access efficiency.

[0082] Figure 3 FIG. 1 is an application example diagram of a CXL memory card with CXL pooling function provided by the present disclosure. Figure 3 As shown above Figure 2The difference between the embodiments shown is that in this embodiment, in order to realize CXL pooling, the memory card used is a memory card that supports the CXL pooling function. At this time, since the memory card supports the pooling function, the CXL Switch chip does not need to be configured Figure 2 The consistent cache control logic unit 204 and cache 205 in.

[0083] like Figure 3 As shown, the CXL Switch chip 300 of this embodiment includes: at least two CXL upstream port control logic units 301, at least two CXL downstream port control logic units 302, and an interconnection bus 303;

[0084] One end of at least two CXL uplink port control logic units 301 is connected to at least two CPU chips; one end of each CXL uplink port control logic unit 301 is connected to one CPU chip;

[0085] One end of at least two CXL downstream port control logic units 302 is connected to at least two CXL memory cards with pooling function, and one end of each CXL downstream port control logic unit 302 is connected to a CXL memory card with pooling function;

[0086] The other end of each CXL upstream port control logic unit 301 and the other end of each CXL downstream port control logic unit 302 are connected to the interconnection bus 303 respectively.

[0087] exist Figure 3 In the architecture shown, the process of the CPU chip accessing the CXL memory pool may include the following steps:

[0088] 1. Taking memory reading as an example, the CPU chip sends a memory read request to the CXL Switch chip 300; the memory read request may carry a request type and a memory address; the request type may identify the request as a read request or a write request;

[0089] 2. The CXL upstream port control logic unit 301 of the CXL Switch chip 300 may determine the identifier of the CXL downstream port control logic unit 302 to be accessed according to the preset configuration information and the memory access address; and send a memory read request and the identifier of the CXL downstream port control logic unit 302 to the interconnection bus 303;

[0090] 3. The interconnect bus 303 sends a memory read request to the corresponding CXL downstream port control logic unit 302 according to the identifier of the CXL downstream port control logic unit 302;

[0091] 4. The CXL downstream port control logic unit 302 sends the memory read request to the CXL memory card with pooling function;

[0092] 5. The CXL memory card determines whether the latest data corresponding to the memory address exists in other CPU chips; if the latest data is in other CPU chips, the CXL memory card sends a listening command to notify other CPU chips to write the latest data back to the CXL memory card. The listening command will be delivered to other CPU chips via the CXL downstream port control logic unit 302 of the CXL Switch chip 300, the interconnection bus 303, and the CXL upstream port control logic unit 301 corresponding to other CPUs. Other CPU chips deliver the latest data corresponding to the memory address to the CXL memory card via the CXL upstream port control logic unit 301 corresponding to other CPUs of the CXL Switch chip 300, the interconnection bus 303, and the CXL downstream port control logic unit 302. Then, the CXL memory card delivers the acquired data to the CPU chip that issued the memory access request through the CXL downstream port control logic unit 302, the interconnection bus 303, and the CXL upstream port control logic unit 301.

[0093] If the CXL memory card determines that the latest data corresponding to the memory address is in the CXL memory card, the CXL memory card directly reads the data at the memory address and sends it to the CPU chip that issued the memory access request via the CXL downstream port control logic unit 302, the interconnection bus 303, and the CXL upstream port control logic unit 301 of the CXL Switch chip 300.

[0094] With the above Figure 3 Compared with the embodiment shown, Figure 1 and Figure 2 In the embodiment shown, the CXL memory expansion card is a memory card that supports memory expansion, but does not support the pooling function. Therefore, this type of CXL memory expansion card does not support the use of Figure 3 The CXLSwitch chip shown in the figure realizes memory sharing. Figure 1 or Figure 2 The architecture shown is used to implement memory sharing.

[0095] With the above Figure 3 Compared with the embodiment shown, Figure 1 and Figure 2 In the embodiment shown, by setting the coherent cache control logic unit and cache in the CXL Switch chip, at least two CPUs can effectively share the memory of at least two memory expansion cards. Figure 1 and Figure 2The technical solution of the embodiment shown can use the mature and reliable CXL memory expansion card to build a CXL memory pooling system without relying on the newly developed CXL memory card that supports the pooling function. Moreover, in the technical solution of this embodiment, by designing a cache in the CXL Switch chip, compared with designing a cache in the CXL memory card, the delay of the CPU accessing the CXL memory pool can be better reduced.

[0096] Figure 4 is a schematic diagram according to the third embodiment of the present disclosure; Figure 5 As shown, this embodiment provides a method based on the above Figure 1 or Figure 2 The data access processing method of the chip in the embodiment shown may specifically include the following steps:

[0097] S401, for each CXL uplink port control logic unit in the CXL Switch chip, the CXL uplink port control logic unit receives a memory access request sent by a connected CPU chip, where the memory access request carries a memory access address; the memory access address is an address in any CXL memory expansion card of at least two CXL memory expansion cards; and forwards the memory access request to an interconnect bus;

[0098] S402, the interconnect bus forwards the memory access request to the coherent cache control logic unit;

[0099] S403: The coherent cache control logic unit performs data memory access processing based on the memory access request.

[0100] The data access processing method of this embodiment is as follows: Figure 1 or Figure 2 The CXL Switch chip of the embodiment shown implements at least two CPUs to access data of at least two CXL memory expansion cards. For the specific implementation principle, please refer to the above Figure 2 The relevant records of the illustrated embodiment will not be repeated here.

[0101] The data access processing method of this embodiment can perform data access processing on the memory access request based on the coherent cache control logic unit in the CXL Switch chip, thereby providing effective support for at least two CPUs to share the memory of at least two CXL memory expansion cards.

[0102] Figure 5 is a schematic diagram according to the fourth embodiment of the present disclosure; the data access processing method of the chip of this embodiment, in the above Figure 4 Based on the technical solution of the embodiment shown, the technical solution of the present disclosure is further described in detail by taking access to data as an example. Figure 5As shown, the data access processing method of the chip in this embodiment may specifically include the following steps:

[0103] S501, the CXL uplink port control logic unit receives an access request sent by a connected CPU chip, the access request carrying an access address; and forwards the access request to an interconnect bus;

[0104] S502, the interconnect bus forwards the access request to the coherent cache control logic unit;

[0105] S503 , the coherent cache control logic unit obtains the data of the access address based on the recorded memory data status information table; and transmits the data to the CPU chip through the interconnect bus and the CXL uplink port control logic unit.

[0106] For example, step S503 may include the following three situations when implemented specifically:

[0107] Scenario 1: When the coherent cache control logic unit determines that the data of the access address needs to be obtained from the cache based on the recorded memory data status information table and the data stored in the cache, the coherent cache control logic unit obtains the data of the access address from the cache.

[0108] Scenario 2: When the consistency cache control logic unit determines that memory data needs to be obtained from the first target CXL memory expansion card based on the recorded memory data status information table and the data stored in the cache, the consistency cache control logic unit sends an access request to the first target CXL memory expansion card through the interconnection bus and the first target CXL downstream port control logic unit based on the identifier of the first target CXL downstream port control logic unit obtained in advance, so that the first target CXL memory expansion card reads data from the memory and returns the data; the first target CXL memory expansion card is a CXL memory expansion card corresponding to the access address of at least two CXL memory expansion cards; the first target CXL downstream port control logic unit is a CXL downstream port control logic unit connected to the first target CXL memory expansion card;

[0109] At this time, correspondingly, when the coherent cache control logic unit determines that memory data needs to be obtained from the first target CXL memory expansion card based on the recorded memory data status information table and the data stored in the cache, based on the pre-acquired identifier of the first target CXL downstream port control logic unit, before sending an access request to the first target CXL memory expansion card through the interconnection bus and the first target CXL downstream port control logic unit, it may also include:

[0110] The CXL uplink port control logic unit obtains the identifier of the first target CXL downlink port control logic unit connected to the first target CXL memory expansion card corresponding to the access address according to the preset configuration information and the access address; and forwards it to the interconnect bus together with the access request;

[0111] The interconnect bus forwards the memory access request and the identifier of the first target CXL downstream port control logic unit to the coherent cache control logic unit.

[0112] Scenario three: When the consistency cache control logic unit determines that the data of the access address is stored in the memory of other CPUs based on the recorded memory data status information table and the data stored in the cache, it sends a listening command to other CPU chips through the interconnection bus and other CXL upstream port control logic units. The listening command carries the access address so that other CPU chips can obtain the data of the access address and return the data.

[0113] The above three situations of this embodiment correspond to the above Figure 2 For details of the three application scenarios in the embodiment shown, please refer to the above Figure 2 The relevant records of the illustrated embodiment will not be repeated here.

[0114] The data memory access processing method of the chip of this embodiment, by adopting the above three situations, can enable any one of the at least two CPUs to accurately and efficiently access and process the data in any one of the at least two CXL memory expansion cards, thereby providing effective support for at least two CPUs to share the memory of at least two CXL memory expansion cards.

[0115] Figure 6 is a schematic diagram according to the fifth embodiment of the present disclosure; Figure 6 As shown, the data access processing method of the chip of this embodiment, in the above Figure 4 Based on the technical solution of the embodiment shown, taking data storage as an example, the following steps may be specifically included:

[0116] S601, a CXL uplink port control logic unit receives a first storage request sent by a connected CPU chip, the first storage request carrying a first storage address and first data; and forwards the first storage request to an interconnection bus;

[0117] S602: The CXL uplink port control logic unit obtains, according to preset configuration information and the first storage address, an identifier of a second target CXL downlink port control logic unit connected to a second target CXL memory expansion card corresponding to the first storage address; and forwards the identifier to the interconnect bus together with the first storage request; the second target CXL memory expansion card is a CXL memory expansion card corresponding to the first storage address among the at least two CXL memory expansion cards;

[0118] S603, the interconnect bus forwards the first storage request to the coherent cache control logic unit, and at the same time forwards the identifier of the second target CXL downstream port control logic unit to the coherent cache control logic unit;

[0119] S604, the coherent cache control logic unit stores the first storage address, the first data, and the acquired identifier of the second target CXL downstream port control logic unit in the cache, and updates the memory data status information table;

[0120] Further optionally, this embodiment may also include the following steps:

[0121] (a) when the cache is full of data, determining the invalid data, and sending the invalid data, the corresponding second storage address and the identifier of the corresponding third target CXL downstream port control logic unit to the interconnection bus, and the interconnection bus sends the invalid data and the corresponding second storage address to the connected third target CXL memory expansion card through the corresponding third target CXL downstream port control logic unit based on the identifier of the third target CXL downstream port control logic unit, so that the third target CXL memory expansion card writes the invalid data in the cache to the corresponding second storage address;

[0122] (b) The coherent cache control logic unit updates the memory data status information table based on the invalidated data.

[0123] Specifically, a field may be extended in the second data to store the identifier of the corresponding second target CXL downstream port control logic unit.

[0124] Figure 6 The data storage mechanism provided by the illustrated embodiment corresponds to the above Figure 2 The data storage method of the first implementation method in the embodiment shown in the figure can be referred to above for details. Figure 2 The relevant records of the illustrated embodiment will not be repeated here.

[0125] The CXL Switch chip 200 of this embodiment, by providing a consistent cache control logic unit 204 and a cache 205, adopts the above data storage processing to enable any one of the at least two CPUs to perform accurate and efficient data storage processing in any one of the at least two CXL memory expansion cards, thereby providing effective support for at least two CPUs to share the memory of at least two CXL memory expansion cards.

[0126] Figure 7 is a schematic diagram according to the sixth embodiment of the present disclosure; Figure 7 As shown, the data access processing method of the chip of this embodiment, in the above Figure 4 Based on the technical solution of the embodiment shown, taking data storage as an example, the following steps may be specifically included:

[0127] S701, the CXL uplink port control logic unit receives a second storage request sent by a connected CPU chip, the second storage request carrying a third storage address and second data; and forwards the second storage request to an interconnection bus;

[0128] S702, the CXL uplink port control logic unit obtains, according to preset configuration information and the third storage address, an identifier of a fourth target CXL downlink port control logic unit connected to a fourth target CXL memory expansion card corresponding to the third storage address; and forwards the identifier to the interconnect bus together with the second storage request; the fourth target CXL memory expansion card is a CXL memory expansion card corresponding to the third storage address among the at least two CXL memory expansion cards;

[0129] S703: the interconnect bus sends a second storage request to the connected fourth target CXL memory expansion card through the corresponding fourth target CXL downstream port control logic unit based on the identifier of the fourth target CXL downstream port control logic unit, so that the fourth target CXL memory expansion card writes the second data on the corresponding third storage address;

[0130] S704, the interconnect bus further forwards the second storage request to the coherent cache control logic unit;

[0131] S705: The coherent cache control logic unit stores the third storage address and the second data in the cache, and updates the memory data status information table.

[0132] There may be no order relationship between steps S704-S705 and step S703.

[0133] Figure 7 For Figure 6 The different data storage mechanisms of the embodiments shown correspond to the above Figure 2 The data storage method of the second implementation method in the embodiment shown in the figure can be referred to above for details. Figure 2 The relevant records of the illustrated embodiment will not be repeated here.

[0134] The CXL Switch chip 200 of this embodiment, by providing a consistent cache control logic unit 204 and a cache 205, adopts the above data storage processing to enable any one of the at least two CPUs to perform accurate and efficient data storage processing in any one of the at least two CXL memory expansion cards, thereby providing effective support for at least two CPUs to share the memory of at least two CXL memory expansion cards.

[0135] Further optionally, in this embodiment, the following steps may also be included:

[0136] (1) configuring a correspondence between the address fragments of each CXL memory expansion card and the identifier of the corresponding connected CXL downstream port control logic unit;

[0137] (2) The configured correspondence is stored in each CXL upstream port control logic unit through the interconnection bus.

[0138] By configuring the correspondence between the address fragments of each CXL memory expansion card and the identifier of the corresponding connected CXL downstream port control logic unit, it is convenient to Figure 5-Figure 7 Used in the scenario of the illustrated embodiment, effective support is provided for data access or data storage.

[0139] Specifically, steps (1) and (2) can be implemented by the FM management logic unit. For details, please refer to the above Figure 2 The relevant records of the illustrated embodiment will not be repeated here.

[0140] This embodiment may also provide an electronic device, which may include the above Figure 1 or Figure 2 The CXL Switch chip of the embodiment shown in the figure can be specifically used as described above. Figure 4-Figure 7 The processing flow of the access request or storage request in the illustrated embodiment performs memory access processing in the shared memory. For details, please refer to the records of the above-mentioned related embodiments, which will not be repeated here.

[0141] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0142] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A computing fast interconnect converter chip, comprising: At least two computing fast interconnection uplink port control logic units, at least two computing fast interconnection downlink port control logic units, an interconnection bus, and a consistent cache control logic unit and a cache; the at least two computing fast interconnection uplink port control logic units, the at least two computing fast interconnection downlink port control logic units, the consistent cache control logic unit and the cache are respectively connected to the interconnection bus; Among them, the consistent cache control logic unit and the cache are used to realize that at least two central processing unit chips external to the computing fast interconnect converter chip can share at least two computing fast interconnect memory expansion cards connected through the computing fast interconnect converter chip.

2. The chip according to claim 1, wherein: For each of the computing fast interconnect uplink port control logic units, the computing fast interconnect uplink port control logic unit is used to receive a memory access request sent by a connected central processing unit chip, and the memory access request carries a memory access address; the memory access address is an address in any of the at least two computing fast interconnect memory expansion cards; the memory access request is an access request or a storage request from the central processing unit chip to any of the at least two computing fast interconnect memory expansion cards; the memory access address includes an access address or a storage address; The interconnect bus is used to forward the memory access request to the coherent cache control logic unit; The coherent cache control logic unit is used to perform data memory access processing based on the memory access request.

3. The chip according to claim 1, wherein: For each of the computing fast interconnection uplink port control logic units, the computing fast interconnection uplink port control logic unit is used to receive an access request sent by a connected central processing unit chip, wherein the access request carries an access address; The interconnect bus is used to forward the access request to the coherent cache control logic unit; The coherent cache control logic unit is used to obtain the data of the access address based on the recorded memory data status information table; and transmit the data to the central processing unit chip through the interconnect bus and the computing fast interconnect uplink port control logic unit.

4. The chip according to claim 3, wherein: The computing fast interconnect uplink port control logic unit is used to obtain the identifier of the first target computing fast interconnect downlink port control logic unit connected to the first target computing fast interconnect memory expansion card corresponding to the access address according to the preset configuration information and the access address; and forward it to the interconnection bus together with the access request; the first target computing fast interconnect memory expansion card is the computing fast interconnect memory expansion card corresponding to the access address among the at least two computing fast interconnect memory expansion cards; The interconnect bus is used to forward the memory access request and the identifier of the first target computing fast interconnect downstream port control logic unit to the coherent cache control logic unit; The consistent cache control logic unit is also used to determine that when it is necessary to obtain memory data from the first target computing fast interconnect memory expansion card based on the recorded memory data status information table and the data stored in the cache, send the access request to the first target computing fast interconnect memory expansion card through the interconnection bus and the first target computing fast interconnect downlink port control logic unit, so that the first target computing fast interconnect memory expansion card returns the data after reading the data from the memory.

5. The chip according to claim 3, wherein: The consistent cache control logic unit is also used to determine that the data of the access address is stored in the memory of other central processing units based on the recorded memory data status information table and the data stored in the cache, and to send a listening command to other central processing unit chips through the interconnection bus and other computing fast interconnection uplink port control logic units. The listening command carries the access address so that the other central processing unit chips can obtain the data of the access address and return the data.

6. The chip according to claim 3, wherein: The coherent cache control logic unit is used to obtain the data of the access address from the cache when it is determined that the data of the access address needs to be obtained from the cache based on the recorded memory data status information table and the data stored in the cache.

7. The chip according to claim 2, wherein: For each of the computing fast interconnection uplink port control logic units, the computing fast interconnection uplink port control logic unit is further used to receive a first storage request sent by a connected central processing unit chip, wherein the first storage request carries a first storage address and first data; The computing fast interconnect uplink port control logic unit is further used to obtain, according to preset configuration information and the first storage address, an identifier of a second target computing fast interconnect downlink port control logic unit connected to a second target computing fast interconnect memory expansion card corresponding to the first storage address; and forward it to the interconnection bus together with the first storage request; the second target computing fast interconnect memory expansion card is a computing fast interconnect memory expansion card corresponding to the first storage address among the at least two computing fast interconnect memory expansion cards; The interconnect bus is used to forward the first storage request and the identifier of the second target computing fast interconnect downstream port control logic unit to the coherent cache control logic unit; The coherent cache control logic unit is used to store the first storage address, the first data and the identifier of the second target computing fast interconnect downlink port control logic unit in the cache, and update the memory data status information table.

8. The chip according to claim 7, wherein: The cache is also used to determine invalid data when the data is full, and send the invalid data, the corresponding second storage address and the corresponding identifier of the third target computing fast interconnection downlink port control logic unit to the interconnection bus, and the interconnection bus sends the invalid data and the corresponding second storage address to the connected third target computing fast interconnection memory expansion card through the corresponding third target computing fast interconnection downlink port control logic unit based on the identifier of the third target computing fast interconnection downlink port control logic unit, so that the third target computing fast interconnection memory expansion card writes the invalid data in the cache at the corresponding second storage address; The coherent cache control logic unit is used to update the memory data status information table based on the invalid data.

9. The chip according to claim 2, wherein: For each of the computing fast interconnection uplink port control logic units, the computing fast interconnection uplink port control logic unit is further used to receive a second storage request sent by a connected central processing unit chip, wherein the second storage request carries a third storage address and second data; The computing fast interconnect uplink port control logic unit is further used to obtain, according to preset configuration information and the third storage address, an identifier of a fourth target computing fast interconnect downlink port control logic unit connected to a fourth target computing fast interconnect memory expansion card corresponding to the third storage address; and forward the identifier to the interconnect bus together with the second storage request; the fourth target computing fast interconnect memory expansion card is a computing fast interconnect memory expansion card corresponding to the third storage address among the at least two computing fast interconnect memory expansion cards; The interconnect bus is used to forward the second storage request to the coherent cache control logic unit; and based on the identifier of the fourth target computing fast interconnect downlink port control logic unit, the second storage request is sent to the connected fourth target computing fast interconnect memory expansion card through the corresponding fourth target computing fast interconnect downlink port control logic unit, so that the fourth target computing fast interconnect memory expansion card writes the second data on the corresponding third storage address; The coherent cache control logic unit is used to store the third storage address and the second data in the cache and update the memory data status information table.

10. The chip according to any one of claims 5 to 9, wherein: The chip also includes a structure manager management logic unit, which is used to configure the correspondence between the address fragments of each of the computing fast interconnect memory expansion cards and the identifiers of the corresponding connected computing fast interconnect downlink port control logic units; and transmit the correspondence to each of the computing fast interconnect uplink port control logic units through the interconnection bus.

11. A data access processing method based on the chip according to any one of claims 1 to 10, wherein: The method comprises: For each computing fast interconnect uplink port control logic unit, the computing fast interconnect uplink port control logic unit receives a memory access request sent by a connected central processing unit chip, wherein the memory access request carries a memory access address; the memory access address is an address in any computing fast interconnect memory expansion card of the at least two computing fast interconnect memory expansion cards; and forwards the memory access request to an interconnect bus; The interconnect bus forwards the memory access request to a coherent cache control logic unit; The coherent cache control logic unit performs data memory access processing based on the memory access request.

12. The method according to claim 11, wherein: The computing fast interconnection uplink port control logic unit receives a memory access request sent by a connected central processing unit chip, including: The computing fast interconnection uplink port control logic unit receives an access request sent by the connected central processing unit chip, wherein the access request carries an access address; The consistent cache control logic unit performs data access processing based on the memory access request, including: The coherent cache control logic unit obtains the data of the access address based on the recorded memory data status information table; and transmits the data to the central processing unit chip through the interconnect bus and the computing fast interconnect uplink port control logic unit.

13. The method according to claim 12, wherein: The consistent cache control logic unit obtains the data of the access address based on the recorded memory data status information table, including: The coherent cache control logic unit obtains the data of the access address from the cache when determining that the data of the access address needs to be obtained from the cache based on the recorded memory data status information table and the data stored in the cache.

14. The method according to claim 12, wherein: The consistent cache control logic unit obtains the data of the access address based on the recorded memory data status information table, including: When the consistent cache control logic unit determines that memory data needs to be obtained from the first target computing fast interconnect memory expansion card based on the recorded memory data status information table and the data stored in the cache, the consistent cache control logic unit sends the access request to the first target computing fast interconnect memory expansion card through the interconnection bus and the first target computing fast interconnect downlink port control logic unit based on the identifier of the first target computing fast interconnect memory expansion card obtained in advance, so that the first target computing fast interconnect memory expansion card reads data from the memory and returns the data; the first target computing fast interconnect memory expansion card is the computing fast interconnect memory expansion card corresponding to the access address among the at least two computing fast interconnect memory expansion cards; the first target computing fast interconnect downlink port control logic unit is the computing fast interconnect downlink port control logic unit connected to the first target computing fast interconnect memory expansion card; When the coherent cache control logic unit determines that memory data needs to be obtained from the first target computing fast interconnect memory expansion card based on the recorded memory data status information table and the data stored in the cache, before sending the access request to the first target computing fast interconnect memory expansion card through the interconnection bus and the first target computing fast interconnect downlink port control logic unit based on the pre-acquired identifier of the first target computing fast interconnect downlink port control logic unit, the method further includes: The computing fast interconnection uplink port control logic unit obtains the identifier of the first target computing fast interconnection downlink port control logic unit connected to the first target computing fast interconnection memory expansion card corresponding to the access address according to the preset configuration information and the access address; and forwards it to the interconnection bus together with the access request; The interconnect bus forwards the memory access request and the identifier of the first target computing fast interconnect downstream port control logic unit to the coherent cache control logic unit.

15. The method according to claim 12, wherein: The consistent cache control logic unit obtains the data of the access address based on the recorded memory data status information table, including: When the consistent cache control logic unit determines that the data of the access address is stored in the memory of other central processing units based on the recorded memory data status information table and the data stored in the cache, it sends a listening command to other central processing unit chips through the interconnection bus and other computing fast interconnection uplink port control logic units. The listening command carries the access address so that the other central processing unit chips can obtain the data of the access address and return the data.

16. The method according to claim 11, wherein: The computing fast interconnection uplink port control logic unit receives a memory access request sent by a connected central processing unit chip, including: The computing fast interconnection uplink port control logic unit receives a first storage request sent by the connected central processing unit chip, wherein the first storage request carries a first storage address and first data; The consistent cache control logic unit performs data access processing based on the memory access request, including: The coherent cache control logic unit stores the first storage address, the first data and the pre-acquired identifier of the second target computing fast interconnection downlink port control logic unit in the cache, and updates the memory data status information table; Before the consistency cache control logic unit stores the first storage address, the first data, and the pre-acquired identifier of the second target computing fast interconnection downlink port control logic unit in the cache and updates the memory data status information table, the method further includes: The computing fast interconnect uplink port control logic unit obtains the identifier of the second target computing fast interconnect downlink port control logic unit connected to the second target computing fast interconnect memory expansion card corresponding to the first storage address according to the preset configuration information and the first storage address; and forwards it to the interconnection bus together with the first storage request; the second target computing fast interconnect memory expansion card is the computing fast interconnect memory expansion card corresponding to the first storage address among the at least two computing fast interconnect memory expansion cards; The interconnect bus forwards the first storage request to the coherent cache control logic unit and at the same time forwards the identifier of the second target computing fast interconnect downstream port control logic unit to the coherent cache control logic unit.

17. The method according to claim 16, wherein: The method further comprises: When the cache is full of data, the cache determines the invalid data, and sends the invalid data, the corresponding second storage address and the identifier of the corresponding third target computing fast interconnection downlink port control logic unit to the interconnection bus, and the interconnection bus sends the invalid data and the corresponding second storage address to the connected third target computing fast interconnection memory expansion card through the corresponding third target computing fast interconnection downlink port control logic unit based on the identifier of the third target computing fast interconnection downlink port control logic unit, so that the third target computing fast interconnection memory expansion card writes the invalid data in the cache at the corresponding second storage address; The coherent cache control logic unit updates the memory data status information table based on the failed data.

18. The method according to claim 11, wherein: The computing fast interconnection uplink port control logic unit receives a memory access request sent by a connected central processing unit chip, including: The computing fast interconnection uplink port control logic unit receives a second storage request sent by a connected central processing unit chip, wherein the second storage request carries a third storage address and second data; The consistent cache control logic unit performs data access processing based on the memory access request, including: The coherent cache control logic unit stores the third storage address and the second data in the cache, and updates the memory data status information table; The method further comprises: The computing fast interconnect uplink port control logic unit obtains the identifier of the fourth target computing fast interconnect downlink port control logic unit connected to the fourth target computing fast interconnect memory expansion card corresponding to the third storage address according to the preset configuration information and the third storage address; and forwards it to the interconnection bus together with the second storage request; the fourth target computing fast interconnect memory expansion card is the computing fast interconnect memory expansion card corresponding to the third storage address among the at least two computing fast interconnect memory expansion cards; The interconnection bus sends the second storage request to the connected fourth target computing fast interconnection memory expansion card through the corresponding fourth target computing fast interconnection downlink port control logic unit based on the identifier of the fourth target computing fast interconnection downlink port control logic unit, so that the fourth target computing fast interconnection memory expansion card writes the second data on the corresponding third storage address.

19. The method according to any one of claims 14 and 16-18, wherein: The method further comprises: Configuring a correspondence between the address fragments of each of the computing fast interconnect memory expansion cards and the identifiers of the correspondingly connected computing fast interconnect downlink port control logic units; The corresponding relationship is stored in each computing fast interconnection uplink port control logic unit through the interconnection bus.

20. An electronic device comprising the computing fast interconnect converter chip as described in any one of claims 1-10.

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