Packaging structure and electronic equipment

Abstract

The utility model provides a packaging structure and electronic equipment, and the packaging structure comprises a carrier plate and at least one chip. The chip is fixedly connected with the carrier plate; the adjacent chips are connected through a connecting piece, the surface of each chip is provided with a retaining wall, the retaining walls are arranged around the connecting piece, the space between the connecting piece and the retaining walls is filled with a plastic packaging layer, and the retaining walls are used for blocking flowing and overflowing of the plastic packaging layer. In the chip packaging structure, the retaining wall structure is arranged to block pollution caused by flowing or overflowing of the plastic packaging layer, and the operability and the reliability of the chip packaging structure are further improved.

Description

Technical Field

[0001] The present application relates to the field of packaging technology, and in particular to a packaging structure and an electronic device. Background Art

[0002] A chip is a way to miniaturize a circuit and is usually manufactured on the surface of a semiconductor wafer. After the chip is prepared, it usually needs to be attached to a packaging substrate, such as a ceramic substrate. Other electrical modules are also provided on the packaging substrate for electrical connection with the chip to form a chip packaging structure.

[0003] In electronic products, the chip is the core component that processes and controls signals and data. However, the surface of the chip is often very fragile and easily damaged by the external environment. Through chip dispensing, a layer of protective glue can be covered on the surface of the chip to form a protective layer, which effectively prevents the chip from being damaged by mechanical shock and other influences, ensuring the normal operation of the chip.

[0004] However, in the existing chip dispensing solutions, the glue can easily contaminate the bonding wires or pads, thus affecting the performance and operability of the chip packaging structure. Utility Model Content

[0005] The purpose of the embodiments of the present application is to provide a packaging structure, which provides a retaining wall structure to prevent contamination caused by the flow or overflow of a plastic packaging layer, thereby further improving the reliability of the chip packaging structure.

[0006] In a first aspect, the present application provides a packaging structure, comprising: a carrier board, at least one chip; the chip is fixedly connected to the carrier board; adjacent chips are connected via connectors, a retaining wall is provided on the surface of the chip, the retaining wall is provided around the connector, a plastic encapsulation layer is filled between the connector and the retaining wall, and the retaining wall is used to block the flow of the plastic encapsulation layer.

[0007] In one embodiment, the retaining wall has an annular structure surrounding the edge of the connecting member and / or the plastic packaging layer, and the annular structure is: a single-layer annular structure or a multi-layer annular structure or a special-shaped annular structure.

[0008] In one embodiment, a filling space is formed between the connecting member and the retaining wall, and the plastic sealing layer is filled in the filling space.

[0009] In one embodiment, the material of the plastic sealing layer is glue or plastic sealing compound.

[0010] In one embodiment, the connecting member includes: a first electrical connecting component and a second electrical connecting component; the chip includes: a first chip and a second chip; wherein the first electrical connecting component is arranged on the first chip, the second electrical connecting component is arranged on the second chip, and the first electrical connecting component and the second electrical connecting component are electrically connected.

[0011] In one embodiment, the barrier wall is a metal redistribution layer, and the metal redistribution layer is located on the surface of the first chip and surrounds the connection element.

[0012] In one embodiment, a bonding area is further connected to the metal redistribution layer, and the bonding area is electrically connected to the carrier through wire bonding.

[0013] In one embodiment, the retaining wall is made of dielectric material.

[0014] In one embodiment, bumps, bonding points or pads are disposed on the metal redistribution layer.

[0015] In a second aspect, the present application provides an electronic device, comprising a packaging structure as described in any one of the first aspects of the present application.

[0016] Compared with the prior art, the technical solution of the present application has at least the following advantages:

[0017] In the present application, a retaining wall structure is provided to prevent contamination caused by the flow or overflow of the plastic packaging layer, thereby further improving the operability and reliability of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of a packaging structure provided in the first embodiment of the present application;

[0020] Figure 2 A top view of the packaging structure provided in the first embodiment of the present application Figure 1 ;

[0021] Figure 3 A top view of the packaging structure provided in the first embodiment of the present application Figure 2 ;

[0022] Figure 4 A top view of the packaging structure provided in the first embodiment of the present application Figure 3 ;

[0023] Figure 5 A schematic diagram of the structure of a metal redistribution layer as a retaining wall provided in the first embodiment of the present application;

[0024] Figure 6 A schematic diagram of a packaging structure provided in accordance with a second embodiment of the present application;

[0025] Figure 7 A schematic diagram of a packaging structure provided in a third embodiment of the present application;

[0026] Figure 8 A schematic diagram of a packaging structure provided in the fourth embodiment of the present application.

[0027] Reference numerals:

[0028] 1- packaging structure; 100- carrier board; 200- chip; 210- first chip; 220- second chip; 300- connector; 400- retaining wall; 410- ring structure; 411- bump; 500- plastic encapsulation layer; 600- metal redistribution layer; 700- bonding area; 800- wire bonding; 900- SMT components. DETAILED DESCRIPTION

[0029] The terms “first”, “second”, “third”, etc. are only used for distinguishing descriptions and do not indicate the order of arrangement, nor can they be understood as indicating or implying relative importance.

[0030] In addition, the terms "horizontal", "vertical", "overhanging" and the like do not mean that the components are required to be absolutely horizontal or overhanging, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0031] In the description of the present application, it should be noted that the terms "inside", "outside", "left", "right", "up", "down", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the products of the present application are usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0032] In the description of this application, unless otherwise clearly specified and limited, the terms "set", "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements.

[0033] The technical solution of the present application will be described below in conjunction with the accompanying drawings.

[0034] Please refer to Figure 1 , which is a schematic diagram of a packaging structure 1 provided in the first embodiment of the present application, the packaging structure 1, comprises: a carrier 100, at least one chip 200; the chip 200 is fixedly connected to the carrier 100; adjacent chips 200 are connected by a connector 300, a retaining wall 400 is arranged on the surface of the chip 200, the retaining wall 400 is arranged around the connector 300, a plastic sealing layer 500 is filled between the connector 300 and the retaining wall 400, and the retaining wall 400 is used to prevent the flow and overflow of the plastic sealing layer 500.

[0035] The carrier 100 is the core material for packaging the chip 200. One side of the carrier 100 is connected to the chip 200 to achieve electrical and physical connection, signal distribution, and communication between the internal and external circuits of the chip 200. In addition, the carrier 100 can also protect, support, fix and assemble the chip 200, enhance the thermal conductivity and heat dissipation performance of the chip 200, and ensure that the chip 200 is not physically damaged. The packaging process of the carrier 100 and the chip 200 can be selected according to the actual packaging requirements.

[0036] In one embodiment, the carrier 100 is a substrate, which can be a multilayer board, usually composed of several layers of materials, including a conductive layer, an insulating layer and a welding pad. The function of the substrate is mainly to provide circuit connection and support components. In the process of electronic product packaging, the substrate is often an important component. Optionally, the substrate can be a hard board, or a FPC (Flexible Printed Circuit, referred to as FPC), or a combination of a hard board and a flexible circuit board.

[0037] In other embodiments, the carrier 100 is directly replaced by a frame, which is designed to support the chip and is usually made of metal or plastic. The function of the frame is mainly to provide support and fixation to ensure that the electronic product will not be physically damaged during operation. In the packaging process of electronic products, the frame is often used to carry chips and other components.

[0038] Optionally, the chip 200 can be provided as one or more chips, and the adjacent chips 200 are electrically connected through the connector 300. The structure of the connector 300 includes but is not limited to a bump, a pad, a solder ball, etc. The retaining wall 400 can be partially or completely disposed on the surface of the chip 200, and partially / semi-enclosed around the connector 300. When the retaining wall 400 is a metal redistribution layer, it is electroplated on the surface of the chip 200; when the retaining wall is a dielectric material, such as polyimide (PI), it is grown on the surface of the chip 200 by spin coating.

[0039] Furthermore, a filling space is formed between the connector 300 and the retaining wall 400, and the plastic encapsulation layer 500 is filled in the filling space. The filling space can be used to accommodate the plastic encapsulation layer 500 and prevent the plastic encapsulation layer 500 from overflowing from the retaining wall 400, thereby preventing the plastic encapsulation layer 500 from contaminating the chip 200 or the bonding wires.

[0040] Optionally, the material of the plastic layer 500 is glue or plastic compound. In one embodiment, when the height of the interconnection solder joint is small and the gap is small, it is necessary to use glue (underfill) with a smaller particle size to fill between the connector 300 and the retaining wall 400. The type or process of glue can be adjusted according to the use environment or the mounting process. In the reflow process or other thermal processes, the stress caused by thermal mismatch at the welding point is prone to fracture. The use of glue can increase the strength of the welding point and enhance the reliability of the chip 200.

[0041] In other embodiments, the plastic encapsulation material may be filled between the connector 300 and the retaining wall 400, and the retaining wall 400 may be used to block the flow of the plastic encapsulation material. The plastic encapsulation material may be an insulating material such as resin, glass fiber, ceramic, etc. After the plastic encapsulation layer 500 is cured, it may also wrap and protect the chip 200 and help the chip 200 dissipate heat.

[0042] In this embodiment, the retaining wall 400 structure is provided to prevent contamination caused by the flow or overflow of the plastic packaging layer 500, thereby further improving the operability and reliability of the chip packaging structure.

[0043] For further information, please refer to Figure 2 , Figure 3 and Figure 4 The retaining wall 400 has an annular structure 410 surrounding the edge of the connecting member 300 and / or the plastic packaging layer 500 .

[0044] Optional, such as Figure 2 As shown, the annular structure 410 is a single-layer annular structure, such as a structure of an annular track. When the annular structure 410 is a single-layer annular structure, the annular structure 410 can be arranged at the edge of the plastic packaging layer 500 .

[0045] like Figure 3 As shown, the annular structure 410 is a multi-layer annular structure, such as a double-layer annular track structure. When the annular structure 410 is a multi-layer annular structure, the inner annular structure 410 can surround the edge of the connector 300, and the outer annular structure 410 can surround the edge of the plastic layer 500.

[0046] like Figure 4 As shown, the annular structure 410 is a special-shaped annular structure, for example, a plurality of protrusions 411 are provided on the outer side of the single-layer annular structure. When the annular structure 410 is a special-shaped annular structure, the annular structure 410 can surround the edge of the plastic encapsulation layer 500.

[0047] Furthermore, the connector 300 includes: a first electrical connection component and a second electrical connection component; the chip 200 includes: a first chip 210 and a second chip 220; wherein, the first electrical connection component is arranged on the first chip 210, the second electrical connection component is arranged on the second chip 220, and the first electrical connection component and the second electrical connection component are electrically connected.

[0048] Optionally, the first electrical connection component may be a bump, a pad or a solder ball, etc., and the second electrical connection component may be a bump, a pad or a solder ball, etc. Taking the first electrical connection component as a bump and the second electrical connection component as a bump as an example, the first chip 210 and the second chip 220 are connected correspondingly through the bumps, so the connector is any combination of the two.

[0049] Exemplarily, the size of the bump can be from a microbump to a conventional bump. The bump size and spacing can be selected according to chip performance requirements and process conditions. The material of the bump can be one of tin material (solder bump), copper material (copper pillar bump) or gold material (Au bump), which can be selected according to design requirements.

[0050] Optional, see Figure 5 The retaining wall 400 is a metal redistribution layer 600 . The metal redistribution layer 600 is located on the surface of the first chip 210 and surrounds the connection member 300 .

[0051] Optionally, the retaining wall 400 in this embodiment may be a semicircular structure, surrounding the connecting member 300 .

[0052] In this embodiment, the wiring of the metal redistribution layer 600 is located on the first chip 210 and the second chip 220 to achieve electrical connection between the two chips.

[0053] If it is necessary to realize the electrical connection of a third chip other than the two chips, or to realize the electrical connection with the substrate or the frame, further, a wire bonding area 700 is connected to the metal redistribution layer 600, and the wire bonding area 700 is electrically connected to the carrier 100 through wire bonding 800. In this embodiment, by setting the wire bonding area 700 on the metal redistribution layer 600, the wire bonding area 700 is further connected to the third chip or the substrate or the frame through wire bonding. The wire used for the wire bonding 800 can be a gold wire, a copper wire, etc., which can be selected according to the use environment and requirements.

[0054] Optionally, the metal redistribution layer 600 is made of copper, and the metal redistribution layer 600 is provided with bumps, bonding points or pads.

[0055] Optionally, the retaining wall 400 is a dielectric material, for example, polyimide (PI). In one embodiment, the first chip 210 and the second chip 220 are directly connected through bumps, and then the polyimide PI is surrounded outside the connector 300. The polyimide PI can be arranged at the edge of the connector 300 in a partially / half-enclosed / fully-enclosed manner.

[0056] Optional, see Figure 6 , a silicon capacitor or SMT component 900 is used to replace the structure of the second chip 220, the SMT component 900 is connected to the second chip 220 through a connector 300, wherein the structure of the connector 300, the retaining wall 400, the plastic sealing layer 500 and the connection relationship between the components are similar to Figure 1 The structures in are the same or similar and can be referenced to each other.

[0057] Optional, see Figure 7 The first chip 210 is flip-chip mounted on the bottom of the carrier 100, the carrier 100 may be a substrate, the first chip 210 and the substrate are connected via a connector 300, wherein the structures of the connector 300, the retaining wall 400, and the plastic encapsulation layer 500 and the connection relationship between the components are similar to Figure 1 The structures in are the same or similar and can be referenced to each other.

[0058] Optional, see Figure 8 The first chip 210 may be two, each of which is connected to the second chip 220 through a connector 300. The structures of the connector 300, the retaining wall 400, and the plastic layer 500 and the connection relationship between the components are similar to Figure 1 The structures in are the same or similar and can be referenced to each other.

[0059] In the above embodiment, multiple chips 200 can be flexibly interconnected.

[0060] The present application also provides an electronic device, comprising at least one Figure 1-Figure 8The packaging structure 1. The electronic device may include a terminal device such as a smart phone, or a tablet computer, a smart wearable device, a smart door lock or other types of electronic devices using the packaging structure 1.

[0061] It should be noted that, in the absence of conflict, the features in the embodiments of this application may be combined with each other.

[0062] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A packaging structure, characterized in that: include: A carrier board and at least one chip; the chip is fixedly connected to the carrier board; adjacent chips are connected via connectors, a retaining wall is arranged on the surface of the chip, the retaining wall is arranged around the connector, a plastic sealing layer is filled between the connector and the retaining wall, and the retaining wall is used to prevent the flow and overflow of the plastic sealing layer.

2. The packaging structure according to claim 1, characterized in that: The retaining wall has an annular structure surrounding the edge of the connecting piece and / or the plastic sealing layer, and the annular structure is: a single-layer annular structure or a multi-layer annular structure or an irregular annular structure, wherein the irregular annular structure is a structure in which a plurality of protrusions are protruding outward from the outer side of the single-layer annular structure.

3. The packaging structure according to claim 1, characterized in that: A filling space is formed between the connecting piece and the retaining wall, and the plastic sealing layer is filled in the filling space.

4. The packaging structure according to any one of claims 1 to 3, characterized in that: The material of the plastic sealing layer is dispensing glue or plastic sealing compound.

5. The packaging structure according to claim 1, characterized in that: The connecting member includes: a first electrical connecting member and a second electrical connecting member; the chip includes: a first chip and a second chip; The first electrical connection component is disposed on the first chip, the second electrical connection component is disposed on the second chip, and the first electrical connection component and the second electrical connection component are electrically connected.

6. The packaging structure according to claim 5, characterized in that: The retaining wall is a metal redistribution layer, which is located on the surface of the first chip and surrounds the connecting member.

7. The packaging structure according to claim 6, characterized in that: The metal redistribution layer is also connected to a wiring area, and the wiring area is electrically connected to the carrier through wire bonding.

8. The packaging structure according to claim 5, characterized in that: The retaining wall is made of dielectric material.

9. The packaging structure according to claim 6, characterized in that: The metal redistribution layer is provided with bumps, bonding points or pads.

10. An electronic device, characterized in that: Comprising the packaging structure as claimed in any one of claims 1 to 9.

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