Chip packaging structure

Abstract

The chip packaging structure provided by the utility model comprises the components of a first lead frame which comprises a plurality of groups of first and second pins which are arranged in a surrounding manner; the first chip is inversely arranged on the first pin, and the lower surface of the first chip faces the upper surface of the first pin; the second lead frame comprises a main base island and a plurality of auxiliary base islands on the periphery of the main base island, the main base island and the auxiliary base islands are connected through connecting rods, the main base island and the first lead frame are in the same layer and are surrounded by the first pin and the second pin, the auxiliary base islands are arranged above the first chip, and the lower surfaces of the auxiliary base islands are attached to the upper surface of the first chip; the second chip is positively arranged on the main base island, and the lower surface of the second chip is attached to the upper surface of the main base island; the bonding wire is connected with the upper surface of the second chip and the upper surface of the second pin; the cooling fin is arranged on the second lead frame, the lower surface of the cooling fin is attached to the upper surface of the auxiliary base island, and the edge of the cooling fin is clamped. According to the technical scheme, heat of the first chip and heat of the second chip are dissipated from the front face and the back face of the packaging structure at the same time through combination of the second lead frame and the cooling fins.

Description

Technical Field

[0001] The utility model relates to the field of chip packaging, in particular to a chip packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, a new design method of chiplet technology has emerged, which packages small chips with different functions together to form a heterogeneous integrated chip packaging structure. As the input and output density of chips increases, the number of chips integrated in a single package increases significantly. The existing 2.5D packaging technology is to package multiple small chips into one package as a multi-chip packaging solution to connect adjacent chip pads in a single package to improve its packaging integration.

[0003] However, the existing 2.5D packaging is mainly based on the packaging on the substrate, and the lead frame is less used in the 2.5D packaging due to its low interconnection density. In addition, the multi-chip based on the lead frame has a relatively single heat dissipation channel.

[0004] Therefore, how to improve the integration of lead frame-based packaging and the heat dissipation performance of the packaging structure is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The technical problem to be solved by the utility model is how to improve the integration of packaging based on a lead frame and the heat dissipation performance of a packaging structure, and to provide a chip packaging structure.

[0006] In order to solve the above problems, the utility model provides a chip packaging structure, comprising: a first lead frame, comprising a plurality of groups of first pins and second pins arranged in a surrounding manner; at least one first chip, flipped on the first pin, and the lower surface of the first chip faces the upper surface of the first pin; a second lead frame, comprising a main base island and a plurality of sub-base islands arranged on the periphery of the main base island, the main base island and the sub-base islands are connected by a connecting rod, the main base island is in the same layer as the first lead frame and is surrounded by the first pin and the second pin, the sub-base islands are arranged above the first chip, and the lower surface of each of the sub-base islands is bonded to the upper surface of the first chip; a second chip, mounted upright on the main base island, and the lower surface of the second chip is bonded to the upper surface of the main base island; a welding wire connecting the upper surface of the second chip and the upper surface of the second pin; a heat sink, arranged on the second lead frame, the lower surface of the heat sink is bonded to the upper surface of the sub-base island, and the edge of the heat sink is clamped to the edge of the sub-base island.

[0007] The above technical solution arranges a plurality of flip-mounted first chips between the first lead frame and the second lead frame, and then uses the second lead frame as a base island to mount the second chip. The second lead frame can realize the interconnection of the non-functional surfaces of the first chip and the second chip, meeting more packaging unit integration requirements and the expansion of application scenarios. The second lead frame is directly combined with the heat sink by snap-fitting, which simplifies the process and reduces costs. The combination of the second lead frame and the heat sink can dissipate the heat of the first chip and the second chip from the front and back of the packaging structure at the same time, thereby improving the heat dissipation capacity of the entire package.

[0008] It should be understood that the above general description and the detailed description below are only exemplary and explanatory and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but in appropriate cases, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the specific implementation of the utility model, the following is a brief introduction to the drawings required for the description of the specific implementation. Obviously, the drawings described below are only some specific implementations of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0010] Figure 1A It is a structural schematic diagram of the first embodiment of the chip packaging structure of the utility model;

[0011] Figure 1B for Figure 1A A top view of

[0012] Figure 1C A schematic top view of the first lead frame of the first embodiment of the chip packaging structure of the utility model;

[0013] Figure 1D A schematic top view of the positional relationship between a first lead frame and a first chip of a first embodiment of the chip packaging structure of the utility model;

[0014] Figure 1E It is a schematic diagram of a top view of the second lead frame of the first embodiment of the chip packaging structure of the utility model;

[0015] Figure 1F A schematic top view of the connection relationship of the second chip of the first embodiment of the chip packaging structure of the utility model;

[0016] Figure 2AIt is a structural schematic diagram of a second embodiment of the chip packaging structure of the utility model;

[0017] Figure 2B for Figure 2A A top view of

[0018] Figure 2C A top view of a second embodiment of the chip packaging structure of the present invention;

[0019] Figure 3A It is a structural schematic diagram of a third embodiment of the chip packaging structure of the utility model;

[0020] Figure 3B A schematic structural diagram of a second lead frame of a third embodiment of the chip packaging structure of the utility model;

[0021] Figure 4 It is a structural schematic diagram of a fourth embodiment of the chip packaging structure of the present invention. DETAILED DESCRIPTION

[0022] The technical scheme in the embodiment of the utility model will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.

[0023] Please also read Figure 1A to Figure 1F ,in, Figure 1A It is a structural schematic diagram of the first embodiment of the chip packaging structure of the utility model; Figure 1B for Figure 1A A top view of Figure 1C A schematic top view of the first lead frame of the first embodiment of the chip packaging structure of the utility model; Figure 1D A schematic top view of the positional relationship between a first lead frame and a first chip of a first embodiment of the chip packaging structure of the utility model; Figure 1E It is a schematic diagram of a top view of the second lead frame of the first embodiment of the chip packaging structure of the utility model; Figure 1F It is a top view structural diagram of the connection relationship of the second chip of the first embodiment of the chip packaging structure of the utility model.

[0024] like Figure 1A to Figure 1FAs shown, the chip packaging structure includes: a first lead frame 11, a second lead frame 12, at least one first chip 13, a second chip 14, a bonding wire 15, and a heat sink 16. The first lead frame 11 includes a plurality of first pins 111 and second pins 112 arranged around. The first chip 13 is flipped on the first pin 111, and the lower surface S1 of the first chip 13 faces the upper surface S0 of the first pin 111. The second lead frame 12 includes a main base island 121 and a plurality of sub-base islands 122 arranged around the main base island 121, the main base island 121 and the sub-base island 122 are connected by a connecting rod 123, the main base island 121 is in the same layer as the first lead frame 11 and is surrounded by the first pin 111 and the second pin 112, the sub-base island 122 is arranged above the first chip 13, and the lower surface S3 of each of the sub-base islands 122 is in contact with the upper surface S2 of the first chip 13. The second chip 14 is mounted on the main base island 121, and the lower surface S5 of the second chip 14 is attached to the upper surface S4 of the main base island 121. The bonding wire 15 connects the upper surface S6 of the second chip 14 and the upper surface S0 of the second lead 112. The heat sink 16 is disposed on the second lead frame 12, and the lower surface S7 of the heat sink 16 is attached to the upper surface S4 of the auxiliary base island 122, and the edge of the heat sink 16 is clamped with the edge of the auxiliary base island 122.

[0025] The above technical solution arranges a plurality of flip-mounted first chips between the first lead frame and the second lead frame, and then uses the second lead frame as a base island to mount the second chip. The second lead frame can realize the interconnection of the non-functional surfaces of the first chip and the second chip, meeting more packaging unit integration requirements and the expansion of application scenarios. The second lead frame is directly combined with the heat sink by snap-fitting, which simplifies the process and reduces costs. The combination of the second lead frame and the heat sink can dissipate the heat of the first chip and the second chip from the front and back of the packaging structure at the same time, thereby improving the heat dissipation capacity of the entire package.

[0026] In this embodiment, the upper surface S0 and the lower surface S9 of the first lead frame 11, the upper surface S4 and the lower surface S3 of the second lead frame 12, the upper surface S2 and the lower surface S1 of the first chip 13, the upper surface S6 and the lower surface S5 of the second chip 14, and the upper surface S8 and the lower surface S7 of the heat sink 16 are two surfaces arranged in a direction perpendicular to the first lead frame 11. The lower surface S1 of the first chip 13 is a functional surface, and the upper surface S2 is a non-functional surface; the upper surface S6 of the second chip 14 is a functional surface, and the lower surface S5 is a non-functional surface.

[0027] In some embodiments, the first chip 13 and the second chip 14 may be memory chips, wherein the memory integrated circuits may be such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, magnetic random access memory (MRAM) devices, resistive random access memory (ReRAM) devices, ferroelectric random access memory (FeRAM) devices, or phase change random access memory (PcRAM) devices.

[0028] like Figure 1A As shown, in some embodiments, the chip packaging structure also includes a packaging body 17, covering the first lead frame 11, the second lead frame 12, the first chip 13, the second chip 14, the welding wire 15 and the heat sink 16, and the lower surface S9 and side surface S11 of the first lead frame 11, the lower surface S3 of the main base island 121, and the upper surface S8 of the heat sink 16 are exposed to the packaging body 17.

[0029] Combined with reference Figure 1A as well as Figure 1E In some embodiments, the edge of the auxiliary base island 122 away from the main base island 121 has a first side wall 18 folded toward the upper surface S4 of the auxiliary base island 122 for clamping the edge of the heat sink 16 .

[0030] In some embodiments, a side surface S180 of the first side wall 18 is exposed to the package body 17 , further increasing a heat dissipation channel of the second lead frame 12 .

[0031] In this embodiment, the upper surface S182 of the first side wall 18 is flush with the upper surface S8 of the heat sink 16 and is also exposed to the package body 17 .

[0032] In some embodiments, the projection of the heat sink 16 on the surface of the first lead frame 11 completely or partially overlaps with the projections of the first chip 13 and the second chip 14 on the surface of the first lead frame 11, and a heat sink 16 with a larger surface area is provided to ensure the heat dissipation effect of the packaging structure.

[0033] In some embodiments, a gap is formed between the lower surface S3 of the sub-base island 122 and the upper surface S0 of the first lead frame 11 in a direction perpendicular to the first lead frame 11 , so as to provide packaging space for the second chip 14 and the bonding wires 15 .

[0034] In some embodiments, the first chip 13 is flip-mounted on the first pin 111 through the solder bump 101; the second chip 14 is mounted on the main base island 121 through the adhesive 102. In this embodiment, the adhesive 102 is a conductive adhesive. In other embodiments, the adhesive 102 can also be a non-conductive adhesive.

[0035] like Figure 1C As shown, in some embodiments, the first lead frame 11 has four groups of pin arrays 110 distributed on four relative sides, and two adjacent groups of the pin arrays are perpendicular to each other. Each of the pin arrays 110 includes a plurality of second pins 112 and a plurality of first pins 111 located on both sides of the plurality of second pins 112; the first chip 13 is disposed at the intersection 1103 of the pin arrays 110.

[0036] In some embodiments, the length of the first pin 111 is less than or equal to the length of the second pin 112, and the length of the first pin 111 decreases in a direction approaching the intersection 1103 of the pin array 110. Figure 1A as well as Figure 1F , a longer second pin 112 is provided to facilitate connecting the second chip 14 and the second pin 112 through a bonding wire. The length of the first pin 111 is arranged to decrease in a direction close to the intersection 1103 of the pin array 110 to meet the space limitation of the intersection 1103 of the pin array 110.

[0037] In other embodiments, the pin array 110 may also be composed of a plurality of first pins 111 and a plurality of second pins 112 located on both sides of the plurality of first pins 111; the length of the second pins 112 is less than or equal to the length of the first pins 111, and the length of the second pins 112 decreases in a direction approaching the intersection of the pin array 110. Accordingly, the first chip 13 is disposed on the first pins 111, that is, at the center of the pin array 110.

[0038] like Figure 1E As shown, in this embodiment, the second lead frame 12 includes a main base island 121 and four auxiliary base islands 122. The main base island 121 and the auxiliary base islands 122 are both rectangular base islands. The four corners of the main base island 121 are connected to the four auxiliary base islands 122 through the connecting rods 123 respectively.

[0039] like Figure 1FAs shown, the sub-base island 122 is located at the intersection 1103 of the pin array 110 of the first lead frame 11, and while the sub-base island 122 is connected to the first chip 13, it does not affect the connection between the bonding wire 15 and the second pin 112, thereby achieving a reasonable layout of the packaging space and improving the utilization of the packaging space. In this embodiment, the size of the second lead frame 12 is the same as that of the first lead frame 11.

[0040] In this embodiment, the connecting rod 123 is a straight rod extending from the main base island 121 to the auxiliary base island 122, as shown in Figure 1. In other embodiments, the connecting rod 123 can also be in an arc shape, a step shape, an "L" shape or a "C" shape.

[0041] like Figure 1F As shown, in some embodiments, the projection of the sub-base island 122 on the surface of the first lead frame 11 completely or partially overlaps with the projection of the first chip 13 on the surface of the first lead frame 11, so that the first chip 13 is connected to the main base island 121 through the sub-base island 122, and then the non-functional surface of the first chip 13 is connected to the non-functional surface of the second chip 14, and at the same time, the heat of the first chip 13 and the second chip 14 is dissipated from the non-functional surface of the packaging structure at the same time, thereby improving the heat dissipation capacity of the entire package.

[0042] Combined with reference Figure 1A as well as Figure 1F In some embodiments, the upper surface S6 of the second chip 14 includes a plurality of conductive pads 141, each of which is connected to a second pin 112 via a bonding wire 15. In this embodiment, the conductive pad 141 is located at the edge of the second chip 14 to be close to the second pin 112, thereby saving the length of the bonding wire 15 and the packaging space.

[0043] Please also read Figure 2A to Figure 2C ,in, Figure 2A It is a structural schematic diagram of a second embodiment of the chip packaging structure of the utility model; Figure 2B for Figure 2A A top view of Figure 2C It is a top view of the second embodiment of the chip packaging structure of the present invention. Figure 2A to Figure 2C The embodiment shown is Figure 1A to Figure 1F The difference of the embodiment shown is that the side surface S280 of the first side wall 28 is covered in the packaging body 27. In order to clearly show the chip packaging structure of the present invention, Figure 2C The package body 27 is not shown.

[0044] like Figure 2CAs shown, in this embodiment, the size of the second lead frame 22 is smaller than the size of the first lead frame 21 .

[0045] Please also read Figure 3A to Figure 3B ,in, Figure 3A It is a structural schematic diagram of a third embodiment of the chip packaging structure of the utility model; Figure 3B It is a structural schematic diagram of a second lead frame of the third embodiment of the chip packaging structure of the utility model. Figure 3A to Figure 3B The embodiment shown is Figure 1A to Figure 1F The difference from the illustrated embodiment is that the edge of the heat sink 36 has a second side wall 39 folded toward the lower surface S7 of the heat sink 36 for clamping the edge of the sub-base island 322 of the second lead frame 32 .

[0046] In some implementations, a side surface S390 of the second sidewall 39 is exposed to the package body 37 .

[0047] In this embodiment, the size of the heat sink 36 is the same as the size of the first lead frame 31 .

[0048] like Figure 3B As shown, the second lead frame 32 in this embodiment is different from the second lead frame in the first embodiment in that the sub-base island 322 in this embodiment does not have a folded side wall at the edge of the second lead frame 32 .

[0049] See also Figure 4 , which is a structural diagram of the fourth embodiment of the chip packaging structure of the present invention. Figure 4 The embodiment shown is Figure 3A to Figure 3B What is different from the illustrated embodiment is that, in this embodiment, a side surface S490 of the second side wall 49 is covered on the packaging body 47 .

[0050] In this embodiment, the size of the second lead frame 42 is smaller than the size of the first lead frame 41 .

[0051] The above technical solution arranges a plurality of flip-mounted first chips between the first lead frame and the second lead frame, and then uses the second lead frame as a base island to mount the second chip. The second lead frame can realize the interconnection of the non-functional surfaces of the first chip and the second chip, meeting more packaging unit integration requirements and the expansion of application scenarios. The second lead frame is directly combined with the heat sink by snap-fitting, which simplifies the process and reduces costs. The combination of the second lead frame and the heat sink can dissipate the heat of the first chip and the second chip from the front and back of the packaging structure at the same time, thereby improving the heat dissipation capacity of the entire package.

[0052] It should be noted that references in the specification to "an embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0053] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. Similarly, terms such as "one", "a" or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected / coupled" refers not only to the direct coupling of one component to another component, but also to the indirect coupling of one component to another component through an intermediate component.

[0054] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present utility model are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments of the present utility model and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concepts of the present utility model. In the above-mentioned embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0055] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: A first lead frame includes a plurality of groups of first pins and second pins arranged in a surrounding manner; At least one first chip is flipped on the first lead, and the lower surface of the first chip faces the upper surface of the first lead; A second lead frame, comprising a main base island and a plurality of sub-base islands arranged outside the main base island, wherein the main base island and the sub-base islands are connected by a connecting rod, the main base island is in the same layer as the first lead frame and is surrounded by the first pin and the second pin, the sub-base islands are arranged above the first chip, and the lower surface of each of the sub-base islands is in contact with the upper surface of the first chip; A second chip is mounted on the main base island, and a lower surface of the second chip is in contact with an upper surface of the main base island; A bonding wire connecting the upper surface of the second chip and the upper surface of the second pin; A heat sink is arranged on the second lead frame, wherein the lower surface of the heat sink is in contact with the upper surface of the auxiliary base island, and the edge of the heat sink is clamped with the edge of the auxiliary base island.

2. The chip packaging structure according to claim 1, characterized in that: It also includes a package body, covering the first lead frame, the second lead frame, the first chip, the second chip, the welding wire and the heat sink, the lower surface and side surface of the first lead frame, the lower surface of the main base island, and the upper surface of the heat sink are exposed to the package body.

3. The chip packaging structure according to claim 2, characterized in that: The edge of the auxiliary base island away from the main base island has a first side wall folded toward the upper surface of the auxiliary base island for clamping the edge of the heat sink.

4. The chip packaging structure according to claim 3, characterized in that: A side surface of the first side wall is exposed to the package body.

5. The chip packaging structure according to claim 2, characterized in that: The edge of the heat sink has a second side wall folded toward the lower surface of the heat sink, and is used for clamping the edge of the auxiliary base island of the second lead frame.

6. The chip packaging structure according to claim 5, characterized in that: A side surface of the second side wall is exposed to the package body.

7. The chip packaging structure according to claim 1, characterized in that: The projection of the heat sink on the surface of the first lead frame completely or partially overlaps with the projections of the first chip and the second chip on the surface of the first lead frame.

8. The chip packaging structure according to claim 1, characterized in that: A gap is formed between a lower surface of the sub-base island and an upper surface of the first lead frame in a direction perpendicular to the first lead frame.

9. The chip packaging structure according to claim 1, characterized in that: The first lead frame has four groups of pin arrays distributed on four opposite sides, two adjacent groups of the pin arrays are perpendicular to each other, each of the pin arrays includes a plurality of the second pins and a plurality of the first pins located on both sides of the plurality of the second pins; the first chip is arranged at the intersection of the pin arrays.

10. The chip packaging structure according to claim 1, characterized in that: The first chip is flip-mounted on the first pin via solder bumps; and the second chip is face-mounted on the main base island via adhesive.

11. The chip packaging structure according to claim 1, characterized in that: A projection of the sub-base island on the surface of the first lead frame completely or partially overlaps with a projection of the first chip on the surface of the first lead frame.

12. The chip packaging structure according to claim 1, characterized in that: The upper surface of the second chip includes a plurality of conductive pads, each of which is connected to a second pin through a bonding wire.

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