Chip packaging structure
By using the combination of the second -lead framework and the transit structure in the chip packaging structure, the stacking and interconnection of multiple chips is realized, and the problem of insufficient packaging integration and heat dissipation performance in existing technology has improved. Heading ability.
Patent Information
- Application Number
- CN202421106551.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-20
- Publication Date
- 2025-01-28
- Estimated Expiration
- 2034-05-20
AI Technical Summary
The existing 2.5D packaging technology has shortcomings in terms of integration and heat dissipation performance, especially the lead frame-based packaging structure, which has low interconnect density and single heat dissipation channels.
A chip packaging structure is adopted to achieve the stacking and interconnection of multiple inverted chips through the combination of the second -lead framework and the transit structure. This structure includes the first lead framework, the second lead framework, the rotor structure, and the chip of multiple inverted chips.
It improved the integration and heat dissipation performance based on the lead framework, simplified the process, improved the quality of the packaging, and improved the heat dissipation capacity of the entire packaging through the back heat dissipation.
Smart Images
Figure CN222421970U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of chip packaging structures, in particular to a chip packaging structure. Background Art
[0002] With the rapid development of the semiconductor industry, a new design method of chiplet technology has emerged, which packages small chips with different functions together to form a heterogeneous integrated chip packaging structure. As the input and output density of chips increases, the number of chips integrated in a single package increases significantly. The existing 2.5D packaging technology is to package multiple small chips into one package as a multi-chip packaging solution to connect adjacent chip pads in a single package to improve its packaging integration.
[0003] However, the existing 2.5D packaging is mainly based on the packaging on the substrate, and the lead frame is less used in the 2.5D packaging due to its low interconnection density. In addition, the multi-chip based on the lead frame has a relatively single heat dissipation channel.
[0004] Therefore, how to improve the integration of lead frame-based packaging and the heat dissipation performance of the packaging structure is a technical problem that needs to be solved urgently. Summary of the invention
[0005] The technical problem to be solved by the utility model is how to improve the integration of packaging based on a lead frame and the heat dissipation performance of a packaging structure, and to provide a chip packaging structure.
[0006] In order to solve the above problems, the utility model provides a chip packaging structure, comprising: a first lead frame, comprising a plurality of first pins and a plurality of second pins alternately arranged around, the upper surface portion of the second pin protruding to form a conductive column; at least one first chip, flipped on the first pin, and the lower surface of the first chip facing the upper surface of the first pin; a second lead frame, comprising a main base island and a plurality of sub-base islands arranged around the main base island, the main base island and the sub-base islands are connected by a connecting rod, the main base island is in the same layer as the first lead frame and is surrounded by the first pin and the second pin, the sub-base island is arranged above the first chip, and The lower surface of each of the sub-base islands is bonded to the upper surface of the first chip; a transfer structure is arranged above the first lead frame and the second lead frame, the lower surface of the transfer structure faces the first lead frame, and the top of the conductive column is connected to the lower surface of the transfer structure; a second chip is flipped on the transfer structure, the upper surface of the second chip faces the lower surface of the transfer structure, and the lower surface of the second chip is bonded to the upper surface of the main base island; at least one third chip is flipped on the transfer structure, the upper surface of the third chip faces the lower surface of the transfer structure, and the lower surface of the third chip is bonded to the upper surface of the sub-base island.
[0007] The above technical solution realizes the stacking and interconnection of multiple flip chips through the second lead frame and the transfer structure, meeting more packaging unit integration requirements and the expansion of application scenarios. Multiple chips are pre-flipped on the transfer structure, and the transfer structure is then combined with the first lead frame and the second lead frame, which simplifies the process and improves the packaging yield. The combination of the second lead frame and the transfer structure can dissipate the heat of multiple chips on the upper and lower surfaces of the second lead frame structure from the back of the package at the same time, thereby improving the heat dissipation capacity of the entire package.
[0008] It should be understood that the above general description and the detailed description below are only exemplary and explanatory and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but in appropriate cases, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] In order to more clearly illustrate the technical solutions in the specific implementation of the utility model, the following is a brief introduction to the drawings required for the description of the specific implementation. Obviously, the drawings described below are only some specific implementations of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0010] Figure 1It is a structural schematic diagram of an embodiment of the chip packaging structure of the utility model;
[0011] Figure 2 A schematic top view of a first lead frame of an embodiment of the chip packaging structure of the utility model;
[0012] Figure 3 A diagram showing the position relationship between a first lead frame and a first chip of an embodiment of the chip packaging structure of the utility model;
[0013] Figure 4 A schematic top view of the second lead frame of an embodiment of the chip packaging structure of the utility model;
[0014] Figure 5 This is a diagram showing the positional relationship between the transfer structure, the second chip and the third chip of an embodiment of the chip packaging structure of the present invention. DETAILED DESCRIPTION
[0015] The technical scheme in the embodiment of the utility model will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.
[0016] Please also read Figure 1 to Figure 5 ,in, Figure 1 It is a structural schematic diagram of an embodiment of the chip packaging structure of the utility model; Figure 2 A schematic top view of a first lead frame of an embodiment of the chip packaging structure of the utility model; Figure 3 A diagram showing the position relationship between a first lead frame and a first chip of an embodiment of the chip packaging structure of the utility model; Figure 4 A schematic top view of the second lead frame of an embodiment of the chip packaging structure of the utility model; Figure 5 This is a diagram showing the positional relationship between the transfer structure, the second chip and the third chip of an embodiment of the chip packaging structure of the present invention.
[0017] like Figure 1 to Figure 5As shown, the chip packaging structure of the utility model includes: a first lead frame 11, a second lead frame 12, at least one first chip 13, a second chip 14, at least one third chip 15, and a transfer structure 16. The first lead frame 11 includes a plurality of first pins 111 and a plurality of second pins 112 arranged alternately and circumferentially, and the upper surface S0 of the second pin 112 partially protrudes to form a conductive column 113. The first chip 13 is flipped on the first pin 111, and the lower surface S1 of the first chip 13 faces the upper surface S0 of the first pin 111. The second lead frame 12 includes a main base island 121 and a plurality of sub-base islands 122 disposed on the periphery of the main base island 121. The main base island 121 and the sub-base islands 122 are connected by connecting rods 123. The main base island 121 is in the same layer as the first lead frame 11 and is surrounded by the first pin 111 and the second pin 112. The sub-base islands 122 are disposed above the first chip 13, and the lower surface S3 of each of the sub-base islands 122 is in contact with the upper surface S2 of the first chip 13. The transfer structure 16 is disposed above the first lead frame 11 and the second lead frame 12. The lower surface S5 of the transfer structure 16 faces the first lead frame 11, and the top of the conductive column 113 is connected to the lower surface S5 of the transfer structure 16. The second chip 14 is flip-mounted on the transfer structure 16, and the upper surface S8 of the second chip 14 faces the lower surface S5 of the transfer structure 16, and the lower surface S7 of the second chip 14 is attached to the upper surface S4 of the main base island 121. The third chip 15 is flip-mounted on the transfer structure 16, and the upper surface S12 of the third chip 15 faces the lower surface S5 of the transfer structure 16, and the lower surface S11 of the third chip 15 is attached to the upper surface S4 of the auxiliary base island 122.
[0018] The above technical solution realizes the stacking and interconnection of multiple flip chips through the second lead frame, meeting more packaging unit integration requirements and the expansion of application scenarios. Multiple chips are pre-flipped on the transfer structure, and the transfer structure is then combined with the first lead frame and the second lead frame, which simplifies the process and improves the packaging yield. The combination of the second lead frame and the transfer structure can dissipate the heat of multiple chips on the upper and lower surfaces of the second lead frame structure from the back of the package at the same time, thereby improving the heat dissipation capacity of the entire package.
[0019] In some embodiments, the first chip 13, the second chip 14 and the third chip 15 may be memory chips, wherein the memory integrated circuits may be such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, magnetic random access memory (MRAM) devices, resistive random access memory (ReRAM) devices, ferroelectric random access memory (FeRAM) devices or phase change random access memory (PcRAM) devices.
[0020] like Figure 2 As shown, in some embodiments, the first lead frame 11 has four groups of pin arrays 110 distributed on four opposite sides, two adjacent groups of the pin arrays 110 are perpendicular to each other, and each pin array 110 includes a plurality of second pins 112 and a plurality of first pins 111 located on both sides of the plurality of second pins 112. The length of the first pin 111 is less than or equal to the length of the second pin 112, and the length of the first pin 111 decreases in sequence along the direction close to the intersection 303 of the pin array 110.
[0021] like Figure 3 As shown, in some embodiments, the first chip 13 is disposed at the intersection 303 of the pin array 110 .
[0022] In other embodiments, the pin array 110 may also be composed of a plurality of first pins 111 and a plurality of second pins 112 located on both sides of the plurality of first pins 111; the length of the second pins 112 is less than or equal to the length of the first pins 111, and the length of the second pins 112 decreases in a direction approaching the intersection of the pin array 110. Accordingly, the first chip 13 is disposed on the first pins 111, that is, at the center of the pin array 110.
[0023] like Figure 4 As shown, in this embodiment, the second lead frame 12 includes a main base island 121 and four auxiliary base islands 122. The main base island 121 and the auxiliary base island 122 are both rectangular base islands. The four corners of the main base island 121 are connected to the four auxiliary base islands 122 through the connecting rods 123 respectively. The auxiliary base island 122 is located at the intersection of the pin array 110. While realizing the connection between the auxiliary base island 122 and the first chip 13, it does not interfere with the connection between the conductive column 113 and the transfer structure 16, realizing a reasonable layout of the packaging space, thereby improving the utilization rate of the packaging space.
[0024] In this embodiment, the connecting rod 123 is a straight rod extending from the main base island 121 to the auxiliary base island 122. In other embodiments, the connecting rod 123 may also be in an arc shape, a step shape, an "L" shape or a "C" shape.
[0025] In some embodiments, the projection of the sub-base island 122 on the surface of the first lead frame 11 completely or partially overlaps with the projections of the first chip 13 and the third chip 15 on the surface of the first lead frame 11, so that the first chip 13 and the third chip 15 are connected to the main base island 121 through the sub-base island 122, and then the upper surface S2 of the first chip 13 and the lower surface S11 of the third chip 15 are connected to the upper surface S8 of the second chip 14, and at the same time, the heat of the first chip 13, the second chip 14 and the third chip 15 is dissipated from the back side of the packaging structure at the same time, thereby improving the heat dissipation capacity of the entire package.
[0026] In some embodiments, the bonding method of the lower surface S3 of the auxiliary base island 122 and the upper surface S2 of the first chip 13 includes direct contact or connection through an adhesive layer 102; similarly, the bonding method of the lower surface S7 of the second chip 14 and the upper surface S4 of the main base island 121 and the bonding method of the lower surface S11 of the third chip 15 and the upper surface S4 of the auxiliary base island 122 also includes direct contact or connection through an adhesive layer 102.
[0027] In some embodiments, the adapter structure 16 is an adapter board or a chip. The adapter board is usually arranged between the chip and other components (such as a circuit board), and a redistribution layer is distributed on the upper and lower surfaces. The chip is generally interconnected with the adapter board by flip-chip welding. As an intermediary bridge between the chip and other components, the adapter board can realize the interconnection between the chip and the circuit board, and can also realize the interconnection between multiple chips through the redistribution layer. The adapter board can be an organic adapter board, and can also be an inorganic adapter board such as a silicon adapter board, a ceramic adapter board, and a glass adapter board. The adapter structure 16 can also be a chip to further increase the packaging density.
[0028] In some embodiments, the projection of the transfer structure 16 on the surface of the first lead frame 11 covers the projections of the first chip 13 , the second chip 14 , and the third chip 15 on the surface of the first lead frame 11 .
[0029] like Figure 1 as well as Figure 5As shown, in some embodiments, a plurality of solder bumps 101 are provided at the edge of the lower surface S5 of the transfer structure 16, and the lower surface S5 of the transfer structure 16 is connected to the top of the conductive column 113 through the solder bumps 101 to achieve electrical connection between the transfer structure 16 and the first lead frame 11.
[0030] Please continue to refer to Figure 1 In some embodiments, the first chip 13 is flipped on the surface of the first lead frame 11 through the solder bump 101; the second chip 14 is flipped on the center position of the transfer structure 16 through the solder bump 101; the third chip 15 is flipped on the edge position of the transfer structure 16 through the solder bump 101.
[0031] In some embodiments, a package body 17 is also included, covering the first lead frame 11, the first chip 13, the second chip 14, the second lead frame 12 and the welding wire, and the lower surface S9 of the first lead frame 11 and the lower surface S3 of the main base island 121 are exposed to the package body 17.
[0032] The above technical solution realizes the stacking and interconnection of multiple flip chips through the second lead frame, meeting more packaging unit integration requirements and the expansion of application scenarios. Multiple chips are pre-flipped on the transfer structure, and the transfer structure is then combined with the first lead frame and the second lead frame, which simplifies the process and improves the packaging yield. The combination of the second lead frame and the transfer structure can dissipate the heat of multiple chips on the upper and lower surfaces of the second lead frame structure from the back of the package at the same time, thereby improving the heat dissipation capacity of the entire package.
[0033] It should be noted that references in the specification to "an embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.
[0034] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. Similarly, terms such as "one", "a" or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected / coupled" refers not only to the direct coupling of one component to another component, but also to the indirect coupling of one component to another component through an intermediate component.
[0035] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present utility model are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments of the present utility model and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concepts of the present utility model. In the above-mentioned embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.
[0036] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.
Claims
1. A chip packaging structure, characterized in that: include: The first lead frame includes a plurality of first pins and a plurality of second pins alternately arranged around each other, wherein upper surfaces of the second pins partially protrude to form conductive columns; At least one first chip is flipped on the first lead, and the lower surface of the first chip faces the upper surface of the first lead; A second lead frame, comprising a main base island and a plurality of sub-base islands arranged outside the main base island, wherein the main base island and the sub-base islands are connected by a connecting rod, the main base island is in the same layer as the first lead frame and is surrounded by the first pin and the second pin, the sub-base islands are arranged above the first chip, and the lower surface of each of the sub-base islands is in contact with the upper surface of the first chip; A transfer structure is arranged above the first lead frame and the second lead frame, the lower surface of the transfer structure faces the first lead frame, and the top of the conductive column is connected to the lower surface of the transfer structure; A second chip is flipped on the transfer structure, with the upper surface of the second chip facing the lower surface of the transfer structure, and the lower surface of the second chip is attached to the upper surface of the main base island; At least one third chip is flipped on the transfer structure, with the upper surface of the third chip facing the lower surface of the transfer structure, and the lower surface of the third chip is in contact with the upper surface of the auxiliary base island.
2. The chip packaging structure according to claim 1, characterized in that: The transfer structure is a transfer board or a chip.
3. The chip packaging structure according to claim 1, characterized in that: The projection of the transfer structure on the surface of the first lead frame covers the projections of the first chip, the second chip, and the third chip on the surface of the first lead frame.
4. The chip packaging structure according to claim 1, characterized in that: A plurality of solder bumps are arranged at the edge of the lower surface of the transfer structure, and the lower surface of the transfer structure is connected to the top of the conductive column through the solder bumps.
5. The chip packaging structure according to claim 1, characterized in that: The first lead frame has four groups of pin arrays distributed on four opposite sides, two adjacent groups of the pin arrays are perpendicular to each other, and each pin array includes a plurality of the second pins and a plurality of the first pins located on both sides of the plurality of the second pins.
6. The chip packaging structure according to claim 5, characterized in that: The first chip is arranged at the intersection of the pin arrays.
7. The chip packaging structure according to claim 1, characterized in that: The first chip is flip-mounted on the surface of the first lead frame via solder bumps; The second chip is flip-mounted at the center of the transfer structure via solder bumps; The third chip is flip-mounted on the edge of the transfer structure through solder bumps.
8. The chip packaging structure according to claim 1, characterized in that: A projection of the sub-base island on the surface of the first lead frame completely or partially overlaps with projections of the first chip and the third chip on the surface of the first lead frame.
9. The chip packaging structure according to claim 1, characterized in that: The invention also includes a package body, which covers the first lead frame, the first chip, the second chip and the second lead frame, and the lower surface of the first lead frame and the lower surface of the main base island are exposed to the package body.