Chip packaging structure and packaging body

Abstract

The utility model provides a chip packaging structure and a packaging body, the chip comprises a welding zone, the welding zone comprises a plurality of sub welding zones, the sub welding zones are arranged around the central point of the welding zone and intersect at the central point, each sub welding zone is provided with at least one welding spot, and the welding spots are arranged in the welding zone. The distance between the welding spot and the central point is 1 / 6 to 1 / 2 of the length or width value of the welding area; and the first bonding wire is connected in series with the plurality of welding spots. According to the invention, the plurality of sub-welding areas are arranged around the central point of the welding area, so that the plurality of welding spots are annularly arranged around the central point of the welding area, the uniform distribution of the plurality of welding spots in the welding area is realized, the effect of uniformly dispersing surge current is achieved, and the welding spots are arranged close to the edge of the welding area, so that the welding spots are conveniently added, and the welding efficiency is improved. And the contact area of the welding spots is increased, so that the surge capacity and the VF of the chip are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device technology, and in particular to a chip packaging structure and a packaging body. Background Art

[0002] When electronic components are working, they often generate instantaneous current surges due to input switch switching, instantaneous start-up or other voltage / current induction sources. The maximum value IFSM that electronic components can withstand this instantaneous current surge is a parameter related to whether the device can be used safely. The forward conduction voltage drop VF is the voltage drop across the ends of the electronic component when it is forward-conducted. It is an important parameter to measure the forward conduction performance of the electronic component. Under general application conditions, the smaller the forward voltage drop, the better. With the continuous development of electronic products, the requirements for chip working safety and reliability are getting higher and higher, and improving the chip's surge current capability and forward conduction performance is an important link. Utility Model Content

[0003] The purpose of this application is to improve the surge current capability of the chip and reduce the forward conduction voltage drop.

[0004] An embodiment of the present application provides a chip packaging structure, including: a chip, the chip including a welding area, the welding area including a plurality of sub-welding areas, the sub-welding areas are arranged around a center point of the welding area and intersect at the center point, each of the sub-welding areas is provided with at least one welding point, the distance between the welding point and the center point is 1 / 6 to 1 / 2 of the length or width value of the welding area; a first bonding wire, the first bonding wire connects a plurality of the welding points in series.

[0005] In some embodiments of the present application, the distance between the welding spot and the edge of the welding area is equal to the difference between the length or width of the welding area and 1 to 5 times the diameter of the first bonding wire.

[0006] In some embodiments of the present application, the welding points are symmetrical with respect to the center point of the welding area.

[0007] In some embodiments of the present application, the distances between the welding points and the edges of the welding areas are equal.

[0008] In some embodiments of the present application, the distance between the welding point and the center point is equal.

[0009] In some embodiments of the present application, some or all of the plurality of welding points are overlapped with each other in pairs.

[0010] In some embodiments of the present application, it is characterized in that the cross-section of the solder joint is a regular shape, the length dimension of the cross-section is 1 to 5 times the cross-section dimension of the first bonding wire, and the width dimension of the cross-section is 1 to 3 times the cross-section dimension of the first bonding wire.

[0011] In some embodiments of the present application, at least one second bonding wire is further included, wherein a first end of the second bonding wire is connected to the first bonding wire, and a second end of the second bonding wire is connected to the concentrated welding end.

[0012] In some embodiments of the present application, connection points between the second bonding wire and the first bonding wire are respectively the welding points.

[0013] An embodiment of the present application further provides a package body, which includes a connection carrier and one or more chip packaging structures, wherein the connection carrier is used to connect electronic components, and the chip packaging structure is electrically connected to the connection carrier.

[0014] In some embodiments of the present application, the connection carrier is a terminal, a base or a lead frame.

[0015] The beneficial effects of the chip packaging structure provided by the present application include but are not limited to the following:

[0016] 1. A chip packaging structure provided in the present application is characterized in that a plurality of sub-welding areas are arranged around a center point in a welding area, and welding points are arranged in the sub-welding areas so that the plurality of welding points are arranged in a ring around the center point of the welding area, thereby achieving uniform distribution of the plurality of welding points in the welding area, and a distance between the welding point and the center point of the welding area is set to 1 / 6 to 1 / 2 of the length or width of the welding area so that the position of the welding point is close to the edge of the welding area, so that the number of welding points can be increased, thereby increasing the contact area of ​​the welding points, improving the surge capacity of the chip, and reducing the forward conduction voltage drop VF of the chip.

[0017] 2. By providing multiple second bonding wires connected to the first bonding wires, the current passing through the chip is conducted to the first bonding wires through the multiple second bonding wires, which effectively shunts the surge current, thereby increasing the surge current threshold and improving the VF of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The following figures describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale.

[0019] in:

[0020] Figure 1a A schematic diagram of a square welding area including four sub-welding areas in a chip packaging structure according to an embodiment of the present application;

[0021] Figure 1b A schematic diagram of a chip packaging structure in an embodiment of the present application in which a square welding area includes 8 sub-welding areas;

[0022] Figure 2a It is a schematic diagram of a plurality of solder joints distributed on a square outline in a chip packaging structure according to an embodiment of the present application;

[0023] Figure 2b It is a schematic diagram of a plurality of solder joints distributed on a circular contour line in a chip packaging structure according to an embodiment of the present application;

[0024] Figure 3a It is a schematic diagram of a chip packaging structure according to an embodiment of the present application, in which a plurality of solder joints are distributed on a circular contour line and are led out by a second bonding wire;

[0025] Figure 3b It is a schematic diagram of a chip packaging structure in an embodiment of the present application in which a plurality of solder joints are distributed on a square outline and are led out by a second bonding wire;

[0026] Figure 3c This is a schematic diagram of a chip packaging structure according to an embodiment of the present application, in which a plurality of solder joints are distributed on a rectangular outline and are led out by a second bonding wire. DETAILED DESCRIPTION

[0027] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0028] The present application provides a chip packaging structure, comprising: a chip, wherein the chip comprises a welding area, wherein the welding area comprises a plurality of sub-welding areas, wherein the sub-welding areas are arranged around a center point of the welding area and intersect at the center point, wherein each of the sub-welding areas is provided with at least one welding point, and a distance between the welding point and the center point is 1 / 6 to 1 / 2 of a length or width value of the welding area; and a first bonding wire, wherein the first bonding wire connects a plurality of the welding points in series.

[0029] The chip packaging structure provided in the present application achieves uniform distribution of multiple solder joints in the soldering area by arranging multiple solder joints in a ring around the center point of the soldering area, and at the same time sets solder joints near the edge of the soldering area, thereby increasing the number of solder joints and the contact area of ​​the solder joints, which is beneficial to improving the surge capability of the chip and reducing the forward conduction voltage drop VF of the chip.

[0030] The chip can be various silicon-based chips or wide bandgap chips on a SiC substrate. Active devices, interlayer dielectric layers and interconnect structures on the SiC substrate can be formed in the SiC substrate. The interconnect structure includes a first interlayer metal layer, a second interlayer metal layer, an insulating layer and a top metal layer. The top metal layer is a conductor layer electrically connected to the bonding wire in the chip and can be made of metal materials such as aluminum and copper. The first bonding wire is electrically connected to the top metal layer of the chip through the multiple solder joints.

[0031] The welding area is an effective welding area on the chip for connecting to the package carrier, and its position needs to accurately correspond to the position of the corresponding electrical connection area on the package carrier. The shape of the welding area can be square, circular, or designed to any shape as needed. According to the circuit layout design, the chip can be provided with one or more welding areas, and each welding area can be provided with one or more welding points. The welding points of the chip are electrically connected to the package carrier through bonding wires, and the chip is electrically interconnected with other electronic components through the package carrier.

[0032] The welding area needs to be separated from the edge of the chip and the non-welding area by a certain distance to meet the welding and packaging requirements. The distance between the welding point and the edge of the welding area should generally be larger than the diameter of the bonding wire to facilitate welding operations. The distance between the welding point and the edge of the welding area can be set to 1 to 5 times the diameter of the bonding wire.

[0033] The chip packaging structure provided in the present application will be described in detail below in conjunction with the embodiments and drawings.

[0034] refer to Figure 1a An embodiment of the present application provides a chip packaging structure, including a chip 1, wherein the chip 1 includes a welding area 2, wherein the welding area 2 includes a plurality of sub-welding areas 21, wherein the plurality of sub-welding areas 21 are arranged around a center point of the welding area and intersect at the center point, and each sub-welding area 21 is provided with at least one welding point 3; a first bonding wire 4, wherein the first bonding wire 4 connects the plurality of welding points 3 in series.

[0035] Figure 1aThe welding area 2 in the figure is a square, and the two diagonals of the square divide the welding area 2 into four sub-welding areas 21 of equal area. Each sub-welding area 21 is provided with a welding spot 3, and a total of four welding spots are provided, wherein two welding spots 3 are provided on the horizontal center line of the welding area 2, and the other two welding spots 3 are provided on the vertical center line of the welding area 2. The four welding spots 3 are at equal distances from the edge of the welding area 2, so as to achieve uniform distribution of the four welding spots 3 in the welding area 2. The four welding spots 3 can also be provided at the center positions of the four sub-welding areas respectively. The distance between the welding spot 3 and the edge of the welding area 2 can be 1 / 6 to 1 / 2 of the side length of the square. In some embodiments, the distance between the welding spot 3 and the edge of the welding area 2 is 1 / 4 to 1 / 2 of the side length of the square, so as to facilitate the addition of welding spots along the edge of the welding area 2 and improve the utilization rate of the area of ​​the welding area 2. The number of welding spots added can be determined according to the area size of the welding area 2 and the flow capacity required by the chip. Of course, the welding spots 3 can also be provided at other positions or diagonals in the sub-welding area 21.

[0036] refer to Figure 1a The first bonding wire 4 starts from the solder joint 3 at the bottom of the soldering area 2 and connects four solder joints 3 in series clockwise, and is led out from the solder joint 3 at the rightmost end of the soldering area 2. The lead-out end of the first bonding wire 4 can be connected to the pin of the lead frame, and connected to other electronic components through the pin, or directly connected to the terminal or the base.

[0037] It should be noted that the starting solder joint and the serial connection direction of the first bonding wire 4 in series with multiple solder joints 3 are not limited, and any solder joint 3 can be used as the starting end, and the serial connection direction can be clockwise or counterclockwise. The position and number of the lead-out ends of the first bonding wire 4 are also not limited, for example, they can be led out from one or more solder joints 3, or from other positions of the first bonding wire 4, and connected to the lead frame, terminal or base through the lead wire.

[0038] refer to Figure 1b , the square welding area 2 is equally divided into eight sub-welding areas 21 along the circumferential direction, and a welding spot 3 is set in each sub-welding area 21. The increase of sub-welding areas 21 can increase the number of welding spots 3, and at the same time ensure that the distribution of multiple welding spots 3 along the circumferential direction in the welding area 2 is more uniform. In some embodiments, the welding spot 3 is set at the center of the sub-welding area 21, so that the position of the welding spot 3 in each sub-welding area 21 can be the same, and the distribution consistency of the multiple welding spots 3 relative to the center point of the welding area 2 is improved.

[0039] Understandably, Figure 1a and Figure 1bThe welding area 2 in the circuit can also be other regular shapes such as a circle, a rectangle, a regular polygon, etc. The regular welding area 2 can be divided into a number of sub-welding areas 21 of equal area from the center along the circumferential direction. A welding spot 3 is set in each sub-welding area 21, so that multiple welding spots 3 can be evenly distributed along the circumferential direction in the welding area 2, effectively dispersing the surge current and improving the current stability of the chip, thereby improving the surge performance and VF of the chip.

[0040] When the welding area 2 is an irregular shape, the welding area 2 can be divided into a plurality of sub-welding areas 21 with approximately equal areas along the circumferential direction, and the welding point 3 is set at the center of the sub-welding area 21. In order to make the areas of the plurality of sub-welding areas 21 approximately equal, the welding area 2 can be divided by a plurality of curves, and the plurality of curves intersect at the center point of the welding area 2.

[0041] In some embodiments, multiple weld spots 3 are symmetrically distributed relative to the center point of the welding area 2, so that multiple weld spots 3 are evenly distributed circumferentially in the welding area 2. At the same time, when the size and shape of the welding area 2 are constant, the area utilization rate of the welding area 2 is effectively improved.

[0042] like Figure 2a , multiple solder joints 3 are distributed on a square contour line set at the same center as the soldering area 2, and different solder joints 3 are symmetrical relative to the center point of the soldering area 2. For example, solder joints 3 can be set at the intersection of the square contour line and the diagonal line of the soldering area 2, and multiple solder joints 3 are evenly distributed in the soldering area 2 along the annular direction, and the distances between multiple solder joints 3 and the edge of the soldering area 2 are consistent, which has the effect of evenly dispersing the surge current. The distance between the side length of the square contour line and the center point of the soldering area 2 can be 1 / 6 to 1 / 2 of the side length of the soldering area 2, so that multiple solder joints 3 are close to the edge of the soldering area 2 respectively. When the shape and area size of the soldering area 2 are certain, the number of solder joints 3 can be increased to increase the contact area of ​​the solder joints and improve the impact resistance of the chip to surge current.

[0043] refer to Figure 2b , multiple welding spots 3 are evenly distributed on a circular contour line, so that each welding spot 3 is at the same distance from the center point of the welding area 2, which improves the consistency of the radial distribution of the welding spots 3 along the welding area 2, and can also make different welding spots 3 symmetrically distributed relative to the center of the welding area 2, thereby improving the balance of the welding spot distribution in the areas on both sides of the center point of the welding area 2. Figure 2b In the embodiment, welding spots 3 are arranged at the intersections of the circular contour line and the diagonal line and the center line of the square welding area 2, so that the multiple welding spots 3 are distributed at equal distances along the circular contour line, and the distances between the welding spots 3 and the center point of the welding area 2 are consistent, thereby improving the uniformity of the distribution of the multiple welding spots 3 in the welding area 2. The radius of the circular contour line can be 1 / 6 to 1 / 2 of the side length of the welding area 2. To facilitate welding operations, the minimum spacing between the circular contour line and the edge of the welding area 2 can be 1 to 5 times the diameter of the first bonding wire 4.

[0044] It is understandable that the plurality of solder joints 3 may also be distributed on an elliptical, polygonal or other arbitrary shaped contour line. In some embodiments, the soldering area 2 is an irregular shape, and the plurality of solder joints 3 are distributed on an elliptical or contour line close to the shape of the soldering area 2.

[0045] The inventors also noticed that in addition to increasing the number of solder joints 3 to increase the contact area of ​​the solder joints, the contact area between the solder joints and the chip can also be increased by increasing the cross-sectional dimensions of a single solder joint. The cross-sectional dimensions of the solder joint 3 are related to the diameter of the first bonding wire 4. In some embodiments, the shape of the solder joint 3 is a regular shape such as a rectangle, square, circle, ellipse, etc. The length dimension of the cross-sectional dimension of the solder joint 3 is 1 to 5 times the diameter of the first bonding wire 4, and the width dimension is 1 to 3 times the diameter of the first bonding wire 4. For example, when a 15 mil diameter aluminum wire is used for welding, the solder joint 3 can be a regular rectangle, and the dimensions of the rectangle are generally: 15 to 45 mil in length and 15 to 30 mil in width. When the number of solder joints is constant, by increasing the contact area of ​​a single solder joint, the chip's current carrying capacity can also be improved, so that the chip's surge performance and VF are greatly improved.

[0046] In addition, the welding quality of solder joint 3 will also directly affect the surge capacity of the chip. Compared with solder joints with random shapes, solder joints with regular shapes, uniform solder, and smooth surfaces can make the electrical contact of the chip packaging structure better and the mechanical contact more secure, effectively avoiding loose soldering, cold soldering, and looseness during use, and maintaining a stable resistance value at the solder joint, thereby improving the surge capacity and reliability of the chip.

[0047] The material of the first bonding wire 4 includes but is not limited to aluminum, copper, silver and gold, and alloy materials can also be used. Among them, aluminum wire is used for welding through cold welding process, which can easily ensure welding quality and reduce welding costs.

[0048] In some embodiments, some or all of the multiple solder joints 3 overlap each other to form a continuous contact surface between the solder joints 3 and the chip, which can greatly increase the contact area of ​​the solder joints, thereby improving the chip's current carrying capacity and its ability to resist impacts of spike currents.

[0049] In some embodiments, the first bonding wire 4 forms a closed loop, and the chip packaging structure further includes at least one second bonding wire 5, the first end of the second bonding wire 5 is connected to the first bonding wire 4, and the second end is welded together. The current passing through the chip is diverted to different positions of the first bonding wire 4 through multiple second bonding wires 5 and then conducted along multiple welding points 3, thereby improving the chip's ability to resist surge current.

[0050] Among them, the second bonding wire 5 can be a gold wire, a copper wire, or an aluminum wire. The position of the connection point between the second bonding wire 5 and the first bonding wire 4 is not limited, and can be located at the soldering point 3 or at other positions on the first bonding wire 4. When there are multiple connection points between the second bonding wire 5 and the first bonding wire 4, the multiple connection points can be dispersedly arranged on the first bonding wire 4, so that the multiple soldering points 3 are evenly dispersed and arranged in the welding area 2, so that the surge current is evenly shunted in the welding area 2. The shape of the closed loop formed by the second bonding wire 4 can be a rectangle, a square, an ellipse, a circular polygon, or other arbitrary shapes.

[0051] When the shape of the closed loop is a rectangle, square, ellipse, circle or regular polygon, the multiple connection points of the multiple second bonding wires 5 and the first bonding wire 4 can be arranged symmetrically relative to the symmetry axis of the above figure, which plays a role in uniformly dispersing the surge current. At the same time, the multiple second bonding wires 5 can also increase the connection strength between the first bonding wire 4 and the external connection point, and improve the structural stability of the chip packaging structure. It can be understood that the multiple second bonding wires 5 can all be welded together, or some of them can be welded together.

[0052] refer to Figure 3a , the first bonding wire 4 is in a ring shape, and there are 5 second bonding wires 5, one end of the 5 second bonding wires 5 is respectively connected to the first bonding wire 4, and the other end is respectively connected to the centralized welding end 6. The centralized welding end 6 can be made by combining multiple welding wires, or it can be made by welding rods, which is convenient for centralized welding of multiple second bonding wires 5. The material of the welding wire or welding rod is metal welding material such as gold, copper, aluminum, alloy, etc. The centralized welding end 6 can also be replaced by a welding point or a pin. When the centralized welding end 6 is a centralized welding point, the cross-sectional size of the centralized welding point can be slightly larger than that of the welding point 3, which is convenient for centralized welding of the second bonding wires 4.

[0053] refer to Figure 3b and Figure 3c The closed loops are square and rectangle respectively, and the connection points of the plurality of second bonding wires 5 and the first bonding wire 4 are symmetrically distributed relative to the vertical symmetry axis of the square or rectangle, so that the force on the first bonding wire 4 is more balanced, thereby increasing the connection strength and structural stability of the chip packaging structure.

[0054] Similarly, the closed loop formed by the first bonding wire 4 can be arranged close to the edge of the welding area 2 to facilitate the addition of welding points. For example, when the welding area 2 is a square, the first bonding wire 4 forms a circular closed loop, and the radius of the circular closed loop is set to 1 / 6 to 1 / 2 of the side length of the welding area 2. To facilitate the welding operation, the minimum distance between the circular closed loop and the edge of the welding area 2 can be 1 to 5 times the diameter of the first bonding wire 4.

[0055] In some embodiments, the plurality of solder joints on the closed loop are overlapped in pairs to form a continuous solder joint contact surface, so that the solder joint contact area is increased, thereby improving the current flow capacity of the chip and improving the surge capacity and VF of the chip.

[0056] An embodiment of the present application further provides a package body, which includes a connection carrier and one or more chip packaging structures described in the present application, wherein the connection carrier is used to connect electronic components, and the chip packaging structure is electrically connected to the connection carrier.

[0057] Wherein, the connection carrier can be a terminal, a base or a lead frame. The base is such as a PCB board, and the PCB board can be a single-sided board, a double-sided board, a multi-layer board or an HDI board (high-density interconnect board). The bonding wire of the chip packaging structure is connected to the conductive layer of the PCB board. The lead frame includes a pad and a pin, and the first bonding wire 4 or the second bonding wire 5 of the chip packaging structure is electrically connected to the lead frame through the pin, or the first bonding wire 4 or the second bonding wire 5 can be directly connected to the pad.

[0058] In some embodiments, the first bonding wire 4 or the second bonding wire 5 of the chip packaging structure is connected to a lead frame or a terminal or a base or other board and then connected as a whole to other substrate baseplates. The other board and substrate baseplates may be ceramic boards. Ceramic boards have excellent thermal stability and high thermal conductivity, and their types include DBC substrates, AMB substrates, PBC substrates, DPC substrates, and the like.

[0059] The electronic components may be resistors, capacitors, inductors, etc.

[0060] The beneficial effects of the chip packaging structure provided by the present application include but are not limited to the following:

[0061] By setting a plurality of sub-welding areas in the welding area, and setting the plurality of sub-welding areas around the center point of the welding area, a plurality of welding points are arranged in a ring, thereby achieving uniform distribution of the plurality of welding points in the welding area, dispersing surge current, and improving the surge capacity of the chip. By positioning the welding points close to the edge of the welding area, when the shape and area of ​​the welding area are constant, the number of welding points can be increased, thereby increasing the total contact area of ​​the welding points, improving the current flow capacity of the chip, and reducing the forward conduction voltage drop VF of the chip, thereby improving the safety and reliability of the chip.

[0062] The welding methods are Normal bond (1*bond) and multi-solder point bonding. After IFSM surge capacity test, the surge is improved by about 10% and the VF (under 30A conditions) is reduced by about 2%.

[0063] It should be noted that different embodiments may produce different beneficial effects. In different embodiments, the beneficial effects that may be produced may be any one or a combination of the above, or any other beneficial effects that may be obtained.

[0064] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of this specification. Although not explicitly stated here, those skilled in the art may make various modifications, improvements and corrections to this application. Such modifications, improvements and corrections are suggested in this specification, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of this application.

[0065] It should be noted that in the description of this application, unless otherwise clearly specified and limited, the terms "install", "connect", "connect", and "fix" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a rotating connection or a sliding connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood in combination with specific circumstances.

[0066] In addition, when terms such as "first", "second", and "third" are used in the specification of this application to describe various features, these terms are only used to distinguish these features and cannot be understood as indicating or implying the relationship between the features, the relative importance, or implicitly indicating the number of features indicated.

[0067] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device nor to limit the scope of the exemplary embodiments.

[0068] At the same time, the present application uses specific words to describe the embodiments of this specification. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in the present application does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0069] Similarly, it should be noted that in order to simplify the description disclosed in this application and thus help understand one or more embodiments, in the above description of the embodiments of this application, multiple features are sometimes combined into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0070] Finally, it should be understood that the embodiments described in this application are only used to illustrate the principles of the embodiments of the present application. Other variations may also fall within the scope of the present application. Therefore, as an example and not a limitation, the alternative configurations of the embodiments of the present application may be considered to be consistent with the teachings of the present application. Accordingly, the embodiments of the present application are not limited to the embodiments explicitly introduced and described in the present application.

Claims

1. A chip packaging structure, characterized in that: include: A chip, wherein the chip comprises a welding area, wherein the welding area comprises a plurality of sub-welding areas, wherein the sub-welding areas are arranged around a center point of the welding area and intersect at the center point, wherein each of the sub-welding areas is provided with at least one welding point, and a distance between the welding point and the center point is 1 / 6 to 1 / 2 of a length or width value of the welding area; A first bonding wire is provided, wherein the first bonding wire connects a plurality of the solder joints in series.

2. The chip packaging structure according to claim 1, characterized in that: The distance between the welding spot and the edge of the welding area is equal to the difference between the length or width of the welding area and 1 to 5 times the diameter of the first bonding wire.

3. The chip packaging structure according to claim 2, characterized in that: The welding points are symmetrical with respect to the center point of the welding area.

4. The chip packaging structure according to claim 3, characterized in that: The welding points are equidistant from the edges of the welding area.

5. The chip packaging structure according to claim 3, characterized in that: The distances between the welding points and the center point are equal.

6. The chip packaging structure according to claim 3, characterized in that: Some or all of the plurality of welding points are overlapped with each other in pairs.

7. The chip packaging structure according to any one of claims 1 to 6, characterized in that: The cross section of the solder joint is a regular shape, the length dimension of the cross section is 1 to 5 times the cross section dimension of the first bonding wire, and the width dimension of the cross section is 1 to 3 times the cross section dimension of the first bonding wire.

8. The chip packaging structure according to any one of claims 1 to 6, characterized in that: It also includes at least one second bonding wire, wherein a first end of the second bonding wire is connected to the first bonding wire, and a second end of the second bonding wire is connected to the concentrated welding end.

9. The chip packaging structure according to claim 8, characterized in that: The connection points of the second bonding wire and the first bonding wire are respectively the welding points.

10. A package, characterized in that: The package body comprises a connection carrier and one or more chip packaging structures according to any one of claims 1 to 9, wherein the connection carrier is used to connect electronic components, and the chip packaging structure is electrically connected to the connection carrier.

11. The package according to claim 10, characterized in that: The connection carrier is a terminal, a base or a lead frame.

Images