Discharge current-limiting control circuit
Through the design of rapid leaking circuits in the BMS circuit, using components such as triode and diode to form a fast leakage circuit, the problem that the MOS tube cannot quickly disconnect during the discharge process is solved, and the reliability of the circuit is improved.
Patent Information
- Application Number
- CN202420255395.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-02
- Publication Date
- 2025-01-28
- Estimated Expiration
- 2034-02-02
AI Technical Summary
During the discharge process of existing BMS circuits, due to the PN capacitance-saving characteristics of the MOS tube, the MOS tube cannot be disconnected quickly when the output becomes low, which is easy to be damaged, affecting the normal operation of the circuit.
A type of discharge -limiting control circuit is designed. Through fast release circuit, the NPN and PNP triode and diode are used to form a fast leakage circuit to achieve rapid disconnection of the MOS tube.
It effectively solves the problem that MOS tubes cannot be quickly disconnected during the discharge process, improved the reliability of the circuit, avoids damage to the MOS tube, and ensure the normal work of the circuit.
Smart Images
Figure CN222423263U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of BMS circuits, in particular to a discharge current limiting control circuit. Background Art
[0002] BMS stands for Battery Management System. It is a device that monitors the status of energy storage batteries. It is mainly used for intelligent management and maintenance of each battery unit, preventing overcharging and over-discharging of the battery, extending the battery life, and monitoring the battery status. The current discharge circuit uses multiple MOS tubes to achieve high current discharge and current sampling at the same time, and controls the current target value based on the feedback of the sampled value. However, due to the PN node capacitance characteristics of the MOS tube, the MOS tube cannot be disconnected quickly when the output becomes low, and the stored charge inside it is easy to cause damage to the MOS tube, thereby affecting the normal operation of the circuit. Utility Model Content
[0003] The purpose of the utility model is to provide a discharge current limiting control circuit. The utility model can quickly discharge the MOS tube in the circuit, so as to facilitate its rapid disconnection and have good reliability.
[0004] The technical scheme of the utility model: a discharge current limiting control circuit comprises a discharge control circuit, and a fast discharge circuit is connected to the discharge control circuit; the discharge control circuit comprises a PMOS tube Q1, an NMOS tube Q2, an NMOS tube Q3, a resistor R1, a pull-down resistor R8, a diode D1, and a resistor R2, the source of the PMOS tube Q1 is connected to a discharge control signal output port, the gate of the PMOS tube Q1 is connected to the drain of the NMOS tube Q2 via the resistor R1, the drain of the PMOS tube Q1 is connected to the positive electrode of the diode D1, and the negative electrode of the diode D1 is connected to the gate of the NMOS tube Q3 via the resistor R2; the source of the NMOS tube Q2 is grounded, the gate of the NMOS tube Q2 is connected to a PWM waveform control port and one end of the pull-down resistor R8, and the other end of the pull-down resistor R8 is grounded; the source of the NMOS tube Q3 is connected to an output circuit, and the drain of the NMOS tube Q3 is connected to a charging circuit The fast discharge circuit includes an NPN transistor Q4, a PNP transistor Q5, a PNP transistor Q6, a resistor R4, a resistor R5, a resistor R6 and a resistor R7; the base of the NPN transistor Q4 is connected to the resistor R1 and the drain of the NMOS transistor Q2, the emitter of the NPN transistor Q4 is grounded, the collector of the NPN transistor Q4 is connected to the positive electrode of the diode D1, the base of the PNP transistor Q5, one end of the resistor R5 and the drain of the PMOS transistor Q1 through the resistor R4, and the other end of the resistor R5 is connected to the collector of the PNP transistor Q5 and the output circuit; the emitter of the PNP transistor Q5 is connected to the base of the PNP transistor Q6, the emitter of the PNP transistor Q6 is connected to the negative electrode of the diode D1, the resistor R2 and one end of the resistor R6, the collector of the PNP transistor Q6 is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to the other end of the resistor R6 and the output circuit.
[0005] In the above-mentioned discharge current limiting control circuit, a current sampling resistor R9 is provided on the output circuit, and two ends of the current sampling resistor R9 are respectively connected to a current collection positive end and a current collection negative end.
[0006] In the aforementioned discharge current limiting control circuit, the discharge control circuit is connected to a first voltage stabilizing circuit and a second voltage stabilizing circuit; the first voltage stabilizing circuit includes a voltage stabilizing tube D3 and a resistor R10; the source of the PMOS tube Q1 is connected to the cathode of the voltage stabilizing tube D3 and one end of the resistor R10, and the other end of the resistor R10 is connected to the anode of the voltage stabilizing tube D3, the resistor R1 and the gate of the PMOS tube Q1; the second voltage stabilizing circuit includes a TVS tube D4 and a voltage stabilizing tube D5, one end of the TVS tube D4 is connected to the cathode of the voltage stabilizing tube D5, the resistor R2, the cathode of the diode D1, the resistor R6 and the emitter of the PNP transistor Q6, and the other end of the TVS tube D4 is connected to the output circuit and the anode of the voltage stabilizing tube D5.
[0007] The aforementioned discharge current limiting control circuit also includes a resistor R11 and a fast discharge diode D6, one end of the resistor R11 is connected to the resistor R1, the drain of the NMOS tube Q2 and the cathode of the fast discharge diode D6, and the other end of the resistor R11 is connected to the anode of the fast discharge diode D6 and the base of the NPN transistor Q4.
[0008] The aforementioned discharge current limiting control circuit also includes a current limiting resistor R12 and a fast discharge diode D7, one end of the current limiting resistor R12 is connected to the PWM waveform control port and the cathode of the fast discharge diode D7, and the other end of the current limiting resistor R12 is connected to the anode of the fast discharge diode D7, the pull-down resistor R8 and the gate of the NMOS tube Q2.
[0009] Compared with the prior art, when the discharge control signal output port outputs a low level, the PNP transistor Q5 and the PNP transistor Q6 are turned on in sequence, and the junction capacitance voltage on the gate of the NMOS tube Q3 can enter the output circuit through the resistor R2, the PNP transistor Q6, and the resistor R7 in sequence to form a fast discharge loop; when the PWM waveform control port outputs a low level, the NPN transistor Q4 is turned on, and the junction capacitance voltage on the PMOS tube Q1 is derived through the resistor R4 and the NPN transistor Q4 in sequence to form a fast discharge loop, thereby realizing the fast disconnection of the MOS tube in the circuit and having good reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 It is a structural schematic diagram of the utility model.
[0011] The markings in the attached drawings are: 1-discharge control circuit; 2-fast discharge circuit; 3-output power; 4-charging circuit; 5-first voltage stabilizing circuit; 6-second voltage stabilizing circuit. DETAILED DESCRIPTION
[0012] The present invention is further described below in conjunction with the accompanying drawings and embodiments, but they are not intended to limit the present invention.
[0013] Embodiment: A discharge current limiting control circuit, as shown in the attached Figure 1As shown, it includes a discharge control circuit 1, and a fast discharge circuit 2 is connected to the discharge control circuit 1; the discharge control circuit 1 includes a PMOS tube Q1, an NMOS tube Q2, an NMOS tube Q3, a resistor R1, a pull-down resistor R8, a diode D1, and a resistor R2. The source of the PMOS tube Q1 is connected to the discharge control signal output port and the DSG control port of the AEF front-end control chip. The high level of the discharge control signal output port controls the NMOS tube Q3 to be turned on, and the low level controls the NMOS tube Q3 to be turned off. The gate of the PMOS tube Q1 is connected to the drain of the NMOS tube Q2 through the resistor R1, the drain of the PMOS tube Q1 is connected to the positive electrode of the diode D1, and the negative electrode of the diode D1 is connected to the negative electrode of the NMOS tube Q3 through the resistor R2. The gate is connected; the source of the NMOS tube Q2 is grounded, the gate of the NMOS tube Q2 is connected to the PWM waveform control port and one end of the pull-down resistor R8, the PWM waveform control port is connected to the MCU single-chip I / O port for PWM waveform control, and the other end of the pull-down resistor R8 is grounded; the source of the NMOS tube Q3 is connected to the output circuit 3, the output circuit is connected to the total negative of the battery, and the drain of the NMOS tube Q3 is connected to the charging circuit 4, which is connected to the charger; the fast discharge circuit 2 includes an NPN transistor Q4, a PNP transistor Q5, a PNP transistor Q6, a resistor R4, a resistor R5, a resistor R6 and a resistor R7; the base of the NPN transistor Q4 is connected to the resistor R1 and the drain of the NMOS tube Q2, the NP The emitter of the N transistor Q4 is grounded, the collector of the NPN transistor Q4 is connected to the positive electrode of the diode D1, the base of the PNP transistor Q5, one end of the resistor R5 and the drain of the PMOS transistor Q1 through the resistor R4, and the other end of the resistor R5 is connected to the collector of the PNP transistor Q5 and the output circuit 3; the emitter of the PNP transistor Q5 is connected to the base of the PNP transistor Q6, the emitter of the PNP transistor Q6 is connected to the negative electrode of the diode D1, the resistor R2 and one end of the resistor R6, the collector of the PNP transistor Q6 is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to the other end of the resistor R6 and the output circuit 3; the output circuit 3 is provided with a current sampling resistor R9, and both ends of the current sampling resistor R9 are connected. The positive terminal and the negative terminal of current collection are respectively connected, and both are connected to the front-end control chip AFE. When current passes through the current sampling resistor R9, a voltage difference is generated at both ends. The positive voltage difference is discharge, and the reverse voltage difference is charge. At the same time, the current value flowing through is collected. The software adjusts the PWM duty cycle through the PWM waveform control port according to the collected current value to achieve control of the current range; the discharge control circuit 1 is connected to the first voltage stabilizing circuit 5 and the second voltage stabilizing circuit 6; the first voltage stabilizing circuit 5 includes a voltage stabilizing tube D3 and a resistor R10; the source of the PMOS tube Q1 is connected to the negative electrode of the voltage stabilizing tube D3 and one end of the resistor R10, and the other end of the resistor R10 is connected to the positive electrode of the voltage stabilizing tube D3, the resistor R1 and the gate of the PMOS tube Q1;The second voltage stabilizing circuit 6 includes a TVS tube D4 and a voltage stabilizing tube D5, one end of the TVS tube D4 is connected to the cathode of the voltage stabilizing tube D5, the resistor R2, the cathode of the diode D1, the resistor R6 and the emitter of the PNP transistor Q6, and the other end of the TVS tube D4 is connected to the output circuit 3 and the anode of the voltage stabilizing tube D5; it also includes a resistor R11 and a fast discharge diode D6, one end of the resistor R11 is connected to the resistor R1, the drain of the NMOS tube Q2 and the cathode of the fast discharge diode D6, and the other end of the resistor R11 is connected to the anode of the fast discharge diode D6 and the base of the NPN transistor Q4; it also includes a current limiting resistor R12 and a fast discharge diode D7, one end of the current limiting resistor R12 is connected to the PWM waveform control port and the cathode of the fast discharge diode D7, and the other end of the current limiting resistor R12 is connected to the anode of the fast discharge diode D7, the pull-down resistor R8 and the gate of the NMOS tube Q2. ;
[0014] Working principle: The discharge control signal output port outputs a high level (+10V-11V), the PWM waveform control port outputs a high level (+3V), the drain and source of the NMOS tube Q2 are turned on, the gate of the PMOS tube Q1 is pulled down, the drain and source are turned on, and the voltage is raised to 9.7V-10V through the diode D1 and the resistor R2. The drain and source are turned on, the charging circuit and the output circuit are turned on, and a large current discharge is achieved; when the discharge control signal output port outputs a low level , PNP transistor Q5 and PNP transistor Q6 are turned on in sequence, and the junction capacitance voltage on the gate of NMOS tube Q3 can enter the output circuit through resistor R2, PNP transistor Q6, and resistor R7 in sequence to form a fast discharge loop; when the PWM waveform control port outputs a low level, NPN transistor Q4 is turned on, and the junction capacitance voltage on PMOS tube Q1 is derived through resistor R4 and NPN transistor Q4 in sequence to form a fast discharge loop, realizing the fast disconnection of the MOS tube in the circuit, and having good reliability.
[0015] The above embodiments only express the implementation methods of the utility model, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the utility model patent. In this embodiment, up, down, left, right, front, and back only represent their relative positions and do not represent their absolute positions. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, which all belong to the protection scope of the utility model. Therefore, the protection scope of the utility model patent shall be based on the attached claims.
Claims
1. A discharge current limiting control circuit, characterized in that: The invention comprises a discharge control circuit (1), and a fast discharge circuit (2) is connected to the discharge control circuit (1); the discharge control circuit (1) comprises a PMOS tube Q1, an NMOS tube Q2, an NMOS tube Q3, a resistor R1, a pull-down resistor R8, a diode D1, and a resistor R2; the source of the PMOS tube Q1 is connected to a discharge control signal output port, the gate of the PMOS tube Q1 is connected to the drain of the NMOS tube Q2 via the resistor R1, the drain of the PMOS tube Q1 is connected to the positive electrode of the diode D1, and the negative electrode of the diode D1 is connected to the gate of the NMOS tube Q3 via the resistor R2; the source of the NMOS tube Q2 is grounded, the gate of the NMOS tube Q2 is connected to a PWM waveform control port and one end of the pull-down resistor R8, and the other end of the pull-down resistor R8 is grounded; the source of the NMOS tube Q3 is connected to an output circuit (3), and the drain of the NMOS tube Q3 is connected to a charging circuit (4); the fast discharge circuit (2) is connected to the discharge control signal output port, and the gate of the NMOS tube Q2 is connected to the positive electrode of the diode D1, and the negative electrode of the diode D1 is connected to the gate of the NMOS tube Q3 via the resistor R2; the source of the NMOS tube Q2 is grounded, the gate of the NMOS tube Q2 is connected to a PWM waveform control port and one end of the pull-down resistor R8, and the other end of the pull-down resistor R8 is grounded; the source of the NMOS tube Q3 is connected to an output circuit (3), and the drain of the NMOS tube Q3 is connected to a charging circuit (4); The output circuit (2) comprises an NPN transistor Q4, a PNP transistor Q5, a PNP transistor Q6, a resistor R4, a resistor R5, a resistor R6 and a resistor R7; the base of the NPN transistor Q4 is connected to the resistor R1 and the drain of the NMOS transistor Q2, the emitter of the NPN transistor Q4 is grounded, the collector of the NPN transistor Q4 is connected to the positive electrode of the diode D1, the base of the PNP transistor Q5, one end of the resistor R5 and the drain of the PMOS transistor Q1 via the resistor R4, and the other end of the resistor R5 is connected to the collector of the PNP transistor Q5 and the output circuit (3); the emitter of the PNP transistor Q5 is connected to the base of the PNP transistor Q6, the emitter of the PNP transistor Q6 is connected to the negative electrode of the diode D1, the resistor R2 and one end of the resistor R6, the collector of the PNP transistor Q6 is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to the other end of the resistor R6 and the output circuit (3).
2. The discharge current limiting control circuit according to claim 1, characterized in that: The output circuit (3) is provided with a current sampling resistor R9, and two ends of the current sampling resistor R9 are respectively connected to a current collection positive end and a current collection negative end.
3. The discharge current limiting control circuit according to claim 1, characterized in that: The discharge control circuit (1) is connected to a first voltage stabilizing circuit (5) and a second voltage stabilizing circuit (6); the first voltage stabilizing circuit (5) comprises a voltage stabilizing tube D3 and a resistor R10; the source of the PMOS tube Q1 is connected to the cathode of the voltage stabilizing tube D3 and one end of the resistor R10, and the other end of the resistor R10 is connected to the anode of the voltage stabilizing tube D3, the resistor R1 and the gate of the PMOS tube Q1; the second voltage stabilizing circuit (6) comprises a TVS tube D4 and a voltage stabilizing tube D5, one end of the TVS tube D4 is connected to the cathode of the voltage stabilizing tube D5, the resistor R2, the cathode of the diode D1, the resistor R6 and the emitter of the PNP transistor Q6, and the other end of the TVS tube D4 is connected to the output circuit (3) and the anode of the voltage stabilizing tube D5.
4. The discharge current limiting control circuit according to claim 1, characterized in that: It also includes a resistor R11 and a fast discharge diode D6, one end of the resistor R11 is connected to the resistor R1, the drain of the NMOS tube Q2 and the cathode of the fast discharge diode D6, and the other end of the resistor R11 is connected to the anode of the fast discharge diode D6 and the base of the NPN transistor Q4.
5. The discharge current limiting control circuit according to claim 4, characterized in that: It also includes a current limiting resistor R12 and a fast discharge diode D7. One end of the current limiting resistor R12 is connected to the PWM waveform control port and the cathode of the fast discharge diode D7. The other end of the current limiting resistor R12 is connected to the anode of the fast discharge diode D7, the pull-down resistor R8 and the gate of the NMOS tube Q2.