TR assembly pulse delay control circuit

Abstract

The utility model relates to the technical field of pulse modulation circuits, in particular to a TR component pulse delay control circuit, which comprises a drain modulation circuit, and the drain modulation circuit comprises a first transistor Q1, a second transistor Q2, a first capacitor C1, a second capacitor C2 and a third capacitor C3. According to the utility model, the rising edge and the falling edge of a radio frequency output waveform can be adjusted by changing a resistance value, and a relatively good frequency spectrum occupied bandwidth is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of pulse modulation circuits, in particular to a TR component pulse delay control circuit. Background Art

[0002] For traditional PMOS pulse modulation circuits, the modulated rising edge is faster and the falling edge is slower; for high-power final amplifiers, high voltage pulse modulation of DC power poses risks; low-voltage DC pulse modulation can avoid damage. Traditional TR components use high-voltage, high-power power pulse modulation, which has a complex structure, high cost, and is not convenient for pulse delay control of components. Utility Model Content

[0003] The utility model provides a TR component pulse delay control circuit, which can realize better spectrum occupation bandwidth.

[0004] In order to achieve the purpose of the utility model, the technical solution adopted is: a TR component pulse delay control circuit, including a drain modulation circuit, the drain modulation circuit includes a first transistor Q1, a second transistor Q2, a first capacitor C1, a second capacitor C2 and a third capacitor C3;

[0005] The source of the first transistor Q1 is connected to the input voltage VCC, the gate of the first transistor Q1 is connected to the diode D1 and the diode D2, and the drain of the first transistor Q1 is the pulse output voltage; the TTL signal is connected to the base of the second transistor Q2 through the resistor R6, the resistor R7 is connected between the base of the second transistor Q2 and the emitter of the second transistor Q2, and the collector of the second transistor Q2 is connected to the input voltage VCC through the series-connected resistor R5 and the resistor R1; the first capacitor C1, the second capacitor C2 and the third capacitor C3 are filter capacitors connected to the source of the first transistor Q1.

[0006] As an optimization solution of the present invention, the TR component pulse delay control circuit also includes resistor R2 and resistor R4. Resistor R2 and resistor R5 are connected in series between the cathode of diode D1 and the collector of the second transistor Q2. Resistor R1, resistor R2 and resistor R4 form a discharge circuit to modulate the falling edge of the pulse output voltage.

[0007] As an optimization solution of the present invention, the TR component pulse delay control circuit also includes a resistor R3. The resistor R3 and the resistor R5 are connected in series between the positive electrode of the diode D2 and the collector of the second transistor Q2. The resistor R3, the resistor R5 and the resistor R1 form a voltage divider circuit to modulate the rising edge of the pulse output voltage.

[0008] As an optimization scheme of the utility model, the TR component includes a transmitting channel, which includes a first-stage power amplifier unit, a second-stage power amplifier unit, a third-stage power amplifier unit and a fourth-stage power amplifier unit. The input end of the first-stage power amplifier unit inputs a radio frequency pulse input signal, the drain +5V of the first-stage power amplifier unit is powered by a drain modulation circuit, the input end of the second-stage power amplifier unit is connected to the output end of the first-stage power amplifier unit, the drain +12V of the second-stage power amplifier unit is powered by a drain modulation circuit, the input end of the third-stage power amplifier unit is connected to the output end of the second-stage power amplifier unit, the input end of the fourth-stage power amplifier unit is connected to the output end of the third-stage power amplifier unit, and the fourth-stage power amplifier unit is synthesized by four-power division of a bridge, four-synthesis of a bridge and four power amplifier modules.

[0009] The utility model has positive effects: 1) the utility model can adjust the rising edge and falling edge of the RF output waveform by changing the resistance value, so as to achieve a better spectrum occupied bandwidth;

[0010] 2) The utility model modulates the +5V and +12V voltages, thereby greatly improving the reliability of the circuit.

[0011] 3) The utility model can effectively improve the flexibility of pulse delay debugging of the component by adjusting the rising edge and falling edge of the RF output signal of the component by adjusting TTL, hardware resistance and RF signal.

[0012] 4) The utility model adopts a four-stage power amplifier, which can better realize pulse delay control through two-stage pulse delay control, effectively simplify the complexity of the modulation circuit, and is conducive to the miniaturization design of the component. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The utility model is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0014] Figure 1 It is a circuit schematic diagram of the utility model;

[0015] Figure 2 It is the principle block diagram of the transmitting channel of the utility model;

[0016] Figure 3 It is a waveform diagram of each node of the utility model. DETAILED DESCRIPTION

[0017] like Figure 1As shown, the utility model discloses a TR component pulse delay control circuit, which can effectively adjust the rising edge and falling edge of the TR component output pulse signal. The biggest feature of radar is pulse operation. For the component output is a pulse signal, the biggest characteristic of the pulse signal is the discontinuity in the time domain. The burst characteristic of the timing is the basic requirement for the pulse to be used in radar applications, so the pulse signal parameters are also the main indicators for radar signal quality evaluation; the main parameters of the pulse signal are the rising edge and the falling edge.

[0018] A TR component pulse delay control circuit includes a drain modulation circuit for power amplifier drain modulation, the drain modulation circuit includes a first transistor Q1, a second transistor Q2, a first capacitor C1, a second capacitor C2 and a third capacitor C3;

[0019] The source of the first transistor Q1 is connected to the input voltage VCC, the gate of the first transistor Q1 is connected to the diode D1 and the diode D2, the source of the first transistor Q1 is a pulse output voltage, and supplies power to the drain of the power amplifier; the TTL signal is connected to the base of the second transistor Q2 through the resistor R6 to achieve current limiting; the resistor R7 is connected between the base of the second transistor Q2 and the ground, and the TTL signal turns on and off the Q2 transistor through R6 and R7; the collector of the second transistor Q2 is connected to the input voltage VCC through the series-connected resistors R5 and R1, and the voltage division of R5 and R1 and the turning on and off of Q2 realize the turning on and off of Q1; the first capacitor C1, the second capacitor C2 and the third capacitor C3 are filter capacitors and are all connected to the drain of the first transistor Q1.

[0020] The TR component pulse delay control circuit also includes a resistor R3. The resistor R3 and the resistor R5 are connected in series between the positive electrode of the diode D2 and the collector of the second transistor Q2. The resistor R3, the resistor R5 and the resistor R1 form a voltage divider circuit to modulate the rising edge of the pulse output voltage.

[0021] The TR component pulse delay control circuit also includes resistor R2 and resistor R4. Resistor R2 and resistor R5 are connected in series between the cathode of diode D1 and the collector of the second transistor Q2. Resistor R1, resistor R2 and resistor R4 form a discharge circuit to modulate the falling edge of the pulse output voltage.

[0022] When TTL is at a high level, the second transistor Q2 is turned on and the resistor R5 is at a low level; VCC divides the voltage through resistors R1, R5 and R3 to turn on the first transistor Q1. By adjusting the resistance values ​​of resistors R1 and R5, the rising and falling edges of the output pulse voltage will change. The rising edge can be effectively controlled by adjusting the resistance value of resistor R3.

[0023] When TTL is at a low level, the second transistor Q2 is turned off and the internal capacitor of the PMOS transistor is discharged, which affects the falling edge of the output voltage. By adjusting the resistance values ​​of resistors R1 and R5, the rising and falling edges of the output pulse voltage will change. The falling edge can be effectively controlled by adjusting the resistance value of resistor R2.

[0024] like Figure 2 As shown, the TR component includes a transmitting channel, which includes a first-stage power amplifier unit, a second-stage power amplifier unit, a third-stage power amplifier unit and a fourth-stage power amplifier unit. The input end of the first-stage power amplifier unit inputs a radio frequency pulse input signal, and the drain +5V of the first-stage power amplifier unit is powered by a drain modulation circuit, which can effectively control the opening and closing of the power amplifier tube. The input end of the second-stage power amplifier unit is connected to the output end of the first-stage power amplifier unit, and the drain +12V of the second-stage power amplifier unit is powered by a drain modulation circuit, which can effectively control the opening and closing of the power amplifier. The input end of the third-stage power amplifier unit is connected to the output end of the second-stage power amplifier unit, and the input end of the fourth-stage power amplifier unit is connected to the output end of the third-stage power amplifier unit. The fourth-stage power amplifier unit is composed of a four-power division of a bridge, a four-power synthesis of a bridge and four power amplifier modules, and the pulse output power is higher than 2KW.

[0025] like Figure 3 As shown, the TR component pulse delay control method is suitable for the TR component output spectrum control and output waveform control, the RF pulse input signal waveform is a periodic signal with a duty cycle of 10%.

[0026] The drain power supply of the first-stage power amplifier unit is modulated, and the rising edge of the DC +5V modulation input voltage is controlled within 100ns-200ns, and the falling edge is greater than 200ns; the drain power supply of the second-stage power amplifier unit is modulated, and the rising edge of the DC +12V modulation input voltage is greater than 200ns, and the falling edge is less than 50ns; the RF pulse output signal waveform has a rising edge between 100ns and 200ns, and a falling edge less than 50ns; the timing relationship at this time is that the rising edge of the RF output signal is controlled by the first-stage power amplifier unit, and the falling edge of the output signal is controlled by the second-stage power amplifier unit, and the third-stage power amplifier unit and the fourth-stage power amplifier unit are completely released, and a better spectrum occupancy bandwidth can be achieved at this time.

[0027] The resistor R1, the resistor R3 and the resistor R5 of the utility model form a voltage divider circuit, which can control the conduction time of the first transistor Q1 (PMOS), that is, the rising edge of the modulated output voltage; the resistor R4, the resistor R1 and the resistor R2 form a discharge loop, which can control the turn-off time of the first transistor Q1, that is, the falling edge of the modulated output voltage;

[0028] The utility model is suitable for drain DC pulse modulation of the internal power amplifier of the TR component in the pulse radar. It is mainly used for the first power amplifier unit and the second power amplifier unit. The pulse delay control of the TR component is realized by controlling the timing of the radio frequency excitation signal, the first power amplifier unit and the second power amplifier unit.

[0029] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A TR component pulse delay control circuit, characterized in that: The drain modulation circuit includes a first transistor Q1, a second transistor Q2, a first capacitor C1, a second capacitor C2 and a third capacitor C3; The source of the first transistor Q1 is connected to the input voltage VCC, the gate of the first transistor Q1 is connected to the diode D1 and the diode D2, and the drain of the first transistor Q1 is the pulse output voltage; the TTL signal is connected to the base of the second transistor Q2 through the resistor R6, the resistor R7 is connected between the base of the second transistor Q2 and the emitter of the second transistor Q2, and the collector of the second transistor Q2 is connected to the input voltage VCC through the series-connected resistor R5 and the resistor R1; the first capacitor C1, the second capacitor C2 and the third capacitor C3 are filter capacitors and are all connected to the source of the first transistor Q1.

2. A TR component pulse delay control circuit according to claim 1, characterized in that: The TR component pulse delay control circuit also includes a resistor R3. The resistor R3 and the resistor R5 are connected in series between the positive electrode of the diode D2 and the collector of the second transistor Q2. The resistor R3, the resistor R5 and the resistor R1 form a voltage divider circuit to modulate the rising edge of the pulse output voltage.

3. A TR component pulse delay control circuit according to claim 2, characterized in that: The TR component pulse delay control circuit also includes resistor R2 and resistor R4. Resistor R2 and resistor R5 are connected in series between the cathode of diode D1 and the collector of the second transistor Q2. Resistor R1, resistor R2 and resistor R4 form a discharge circuit to modulate the falling edge of the pulse output voltage.

4. A TR component pulse delay control circuit according to claim 3, characterized in that: The TR component includes a transmitting channel, which includes a first-stage power amplifier unit, a second-stage power amplifier unit, a third-stage power amplifier unit and a fourth-stage power amplifier unit. The input end of the first-stage power amplifier unit inputs a radio frequency pulse input signal, the drain +5V of the first-stage power amplifier unit is powered by a drain modulation circuit, the input end of the second-stage power amplifier unit is connected to the output end of the first-stage power amplifier unit, the drain +12V of the second-stage power amplifier unit is powered by a drain modulation circuit, the input end of the third-stage power amplifier unit is connected to the output end of the second-stage power amplifier unit, the input end of the fourth-stage power amplifier unit is connected to the output end of the third-stage power amplifier unit, and the fourth-stage power amplifier unit is synthesized by a four-power division of a bridge, a four-synthesis of a bridge and four power amplifier modules.

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