Sound equipment with video output function

Abstract

The utility model provides sound equipment with a video output function, which relates to the technical field of karaoke sound equipment, and adopts the main technical scheme that an input / output module, a decoding processing module, a power amplification module, an audio module, a high-frequency receiving module, a video amplification module and a power supply module are included, and the input end of the decoding processing module is connected with the output end of the input / output module; the input end of the power amplification module is connected with the output end of the decoding processing module; the input end of the audio module is connected with the output end of the power amplification module; the input end of the video amplification module is connected with the output end of the high-frequency receiving module and the output end of the decoding processing module; and the output end of the video amplification module is connected with the input end of the input and output module. Performance and processing capability are improved through the decoding processing module and the power amplification module, and the purpose of improving the tone quality of karaoke is further achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of karaoke speakers, and more specifically, to a speaker with a video output function. Background Art

[0002] With the improvement of people's living standards, karaoke has become one of the ways of life for people to meet, make friends and have fun, and the demand for singing, practicing and listening to songs is gradually becoming a common demand of families. However, the existing karaoke equipment, such as the karaoke system equipped in KTV, usually includes independent speakers, song selection machines, wireless microphone receivers, effects, audio power amplifiers, displays and various wires. It is complicated and has high requirements for installation space and environment. Generally, users do not have the conditions to "move the above set of equipment home".

[0003] Based on the emergence of the above problems, karaoke speakers are born, but the audio processing circuits and power amplifier circuits of existing karaoke speakers have poor performance and weak audio processing capabilities, resulting in poor sound quality when singing karaoke. Utility Model Content

[0004] The utility model aims to provide a speaker with video output function, which solves the problem that the audio processing circuit and power amplifier circuit of the existing karaoke speakers have poor performance and weak audio processing ability, resulting in poor sound quality during karaoke.

[0005] The utility model is realized by the following technical solutions:

[0006] A sound system with a video output function comprises: an input / output module, a decoding processing module, a power amplifying module, an audio module, a high-frequency receiving module, a video amplifying module and a power supply module, wherein the input / output module is used to receive audio signals and output video signals; the input end of the decoding processing module is connected to the output end of the input / output module; the input end of the power amplifying module is connected to the output end of the decoding processing module; the input end of the audio module is connected to the output end of the power amplifying module; the high-frequency receiving module is used to receive video signals; the input end of the video amplifying module is connected to the output end of the high-frequency receiving module and the output end of the decoding processing module; the output end of the video amplifying module is connected to the input end of the input / output module; and the power supply module is used to supply power to each module.

[0007] Optionally, the high-frequency receiving module includes an input unit and a processing unit; the input unit includes a ground isolation circuit, a bipolar power supply PBZ1, an MCX connector, a low-frequency EOC filter circuit, a WiFi filter circuit and a conduction suppression and anti-winding circuit; one end of the ground isolation circuit is used to connect to EGND; the other end of the ground isolation circuit is used to connect to DGND; pins 0, 1, 2, 3, 4 and 5 of the bipolar power supply PBZ1 are all used to connect to DGND; pins 1, 2, 3 and 4 of the MCX connector are all used to connect to EGND; pin 5 of the MCX connector is connected to the input end of the low-frequency EOC filter circuit; the output end of the low-frequency EOC filter circuit is connected to the input end of the WiFi filter circuit; the output end of the WiFi filter circuit is connected to the input end of the conduction suppression and anti-winding circuit; the output end of the conduction suppression and anti-winding circuit is connected to the input end of the processing unit.

[0008] Optionally, the processing unit includes a voltage regulating circuit, a first filtering circuit, a second filtering circuit, a comparison circuit, a first crystal oscillator circuit, a chip U7, a magnetic bead FB5, a magnetic bead FB6, a resistor R27, a resistor R28, a resistor R29, a resistor R30, a resistor R33, a resistor R34, a resistor R35, a resistor R36, a current transformer CT2, a capacitor C61, a capacitor C62, a capacitor C64, a capacitor C65, a capacitor C66, a capacitor C70, a capacitor C72, a capacitor C73, a capacitor C78, ​​a capacitor C81, a capacitor C82, a capacitor C86, a capacitor C87, a capacitor C88, a capacitor C145 and a capacitor C146; the input end of the voltage regulating circuit, the input end of the first filtering circuit, and the input end of the comparison circuit The ends are connected to the output end of the power module; the output end of the voltage regulating circuit is connected to the input end of the second filtering circuit; the input end of the comparison circuit is connected to the voltage regulated power supply; the output end of the comparison circuit is connected to the No. 6 pin of the chip U7 and the No. 7 pin of the chip U7; the input end of the first crystal oscillator circuit is connected to the No. 11 pin of the chip U7 and the No. 12 pin of the chip U7; the output end of the first crystal oscillator circuit is connected to DGND; the No. 51 pin of the chip U7 and one end of the capacitor C61 are connected to one end of the magnetic bead FB5; the other end of the magnetic bead FB5 is connected to the output end of the second filtering circuit; the No. 52 pin of the chip U7, one end of the capacitor C65, and one end of the capacitor C66 are connected to one end of the magnetic bead FB6 The other end of the magnetic bead FB6 is connected to the output end of the first filtering circuit; the other end of the capacitor C61, the other end of the capacitor C65, and the other end of the capacitor C66 are all connected to DGND; the 55th and 56th pins of the chip U7 are both used to connect to the output end of the conduction suppression anti-winding circuit; the 41st pin of the chip U7 is connected to one end of the resistor R27; the 39th pin of the chip U7 is connected to one end of the resistor R28; the 38th pin of the chip U7 is connected to one end of the resistor R29; the 36th pin of the chip U7 is connected to one end of the resistor R30; the 24th pin of the chip U7 is connected to one end of the resistor R33, one end of the resistor R35, and one end of the capacitor C87; the 23rd pin of the chip U7 is connected to One end of the resistor R34, one end of the resistor R36, and one end of the capacitor C88 are all connected; the other end of the resistor R27, the other end of the resistor R28, the other end of the resistor R29, the other end of the resistor R30, the other end of the resistor R35, the other end of the resistor R36, and one end of the capacitor C64 are all connected to the video amplification module; the other end of the capacitor C64, the other end of the capacitor C87, and the other end of the capacitor C88 are all connected to DGND; the other end of the resistor R33 and the other end of the resistor R34 are all connected to the output end of the first filter circuit; pins 27, 35, and 45 of the chip U7, as well as one end of the capacitor C62, one end of the capacitor C70, and one end of the capacitor C82 are all connected to the output end of the first filter circuit;The other end of capacitor C62, the other end of capacitor C70, and the other end of capacitor C82 are all connected to DGND; pins 3, 4, 5, 8, 9, 18, 19, 53, and 54 of the chip U7, as well as one end of current transformer CT2, one end of capacitor C73, one end of capacitor C78, ​​one end of capacitor C81, one end of capacitor C145, and one end of capacitor C146 are all connected to the regulated power supply; the other end of current transformer CT2, the other end of capacitor C73 The other end of capacitor C78, ​​the other end of capacitor C81, the other end of capacitor C145, and the other end of capacitor C146 are all connected to DGND; pins 20 and 34 of the chip U7, as well as one end of capacitor C72 and one end of capacitor C86 are all connected to the output end of the second filter circuit; the other end of capacitor C72 and the other end of capacitor C86 are all connected to DGND; pins 25, 31, 33, 40, 48, and 57 of the chip U7 are all connected to DGND. ;

[0009] Optionally, the comparison circuit includes a magnetic bead FB7, a magnetic bead FB8, a magnetic bead FB13, a transistor Q1, a capacitor C63, a capacitor C67, a capacitor C68, a capacitor C69 and a capacitor C71; one end of the magnetic bead FB13 is connected to the output end of the power module; the other end of the magnetic bead FB13, one end of the magnetic bead FB7, and one end of the capacitor C63 are all connected to the emitter of the transistor Q1; the other end of the capacitor C63 is connected to DGND; the other end of the magnetic bead FB7, the magnetic bead FB7, and the capacitor C69 are ... magnetic bead FB7, One end of bead FB8, one end of capacitor C67, and one end of capacitor C68 are all connected to the regulated power supply; the other end of capacitor C67 and the other end of capacitor C68 are all connected to DGND; the other end of magnetic bead FB8, one end of capacitor C69, one end of capacitor C71, and the collector of transistor Q1 are all connected to pin 6 of chip U7; the other end of capacitor C69 and the other end of capacitor C71 are all connected to DGND; the base of transistor Q1 is connected to pin 7 of chip U7.

[0010] Optionally, the video amplification module includes a chip U1, a third filtering circuit, a fourth filtering circuit, a download serial port circuit, a debugging serial port circuit, a USB differential circuit, an SPI_FLASH interface circuit, a detection circuit, a second crystal oscillator circuit, a resistor R3, and a resistor R4; the input end of the third filtering circuit and the input end of the fourth filtering circuit are both connected to the power module; the output end of the third filtering circuit is connected to A1, A2, B1, B2, C1, C2, D1, and D2 of the chip U1; the output end of the fourth filtering circuit is connected to The output end is connected to G1, G2, H1, and H2 of chip U1; the download serial port circuit is connected to B5 and C5 of the power module and chip U1; the debug serial port circuit is connected to B3 and B4 of the power module and chip U1; the USB differential circuit is connected to L3 and L4 of chip U1; the input end of the SPI_FLASH interface circuit is connected to K1, K2, J1, and J2 of the power module and chip U1; the output end of the SPI_FLASH interface circuit is connected to L1 and L2 are connected; the detection circuit is connected to the power module and L5 of chip U1; the input end of the second crystal oscillator circuit is connected to A5 of chip U1; the output end of the second crystal oscillator circuit is connected to A4 of chip U1; one end of resistor R3 is connected to the power module; the other end of resistor R3 is connected to E8 of chip U1; one end of resistor R4 is connected to the output end of the third filter circuit; the other end of resistor R4 is connected to E1 of chip U1; H8 of chip U1 is connected to the other end of resistor R27; G9 of the chip U1 is connected to the other end of the resistor R28; C9 of the chip U1 is connected to the other end of the resistor R29; C10 of the chip U1 is connected to the other end of the resistor R30; C4 of the chip U1 is connected to the other end of the resistor R35; C3 of the chip U1 is connected to the other end of the resistor R36; B3 and B4 of the chip U1 are both connected to the decoding processing module; D4, E3, E4, F2, F3, F4, G3, G4, H3, and H4 of the chip U1 are all connected to DGND.

[0011] Optionally, the decoding processing module includes an audio input adjustment circuit, a third crystal oscillator circuit, a storage circuit, a DCDC circuit, an antenna element ANT1, a magnetic bead FB12, a chip U10, a resistor R124, a capacitor C89, a capacitor C93, a capacitor C103, a capacitor C106, a capacitor C107, a capacitor C110, a capacitor C114, a capacitor C116, a capacitor C125, a capacitor C126, a capacitor C127, a capacitor C128, a capacitor C129, a capacitor C130, a capacitor C131, a capacitor C132, an electrolytic capacitor C109, and a diode D2; pin 1 of the chip U10, one end of the capacitor C103, and one end of the capacitor C106 are all connected to the analog voltage; the other end of the capacitor C103, the capacitor C131, the capacitor C132, the electrolytic capacitor C109, and the diode D2; pin 1 of the chip U10, one end of the capacitor C103, and one end of the capacitor C106 are all connected to the analog voltage; the other end of the capacitor C103, the capacitor C131, the capacitor C132, the electrolytic capacitor C109, and the diode D2 The other end of capacitor C106 is connected to AGND; pin 2 of the chip U10, one end of capacitor C110, and the positive electrode of electrolytic capacitor C109 are all connected to the negative electrode of diode D2; the positive electrode of diode D2 is used to connect to the first input power supply; pin 3 of the chip U10 is connected to one end of capacitor C114; pin 4 of the chip U10, the other end of capacitor C114, the other end of capacitor C110, and the negative electrode of electrolytic capacitor C109 are all connected to DGND; pin 5 of the chip U10 is connected to the output end of the audio input adjustment circuit; the input end of the audio input adjustment circuit is used to connect to the second input power supply; pin 8 of the chip U10 is connected to B3 of chip U1; pin 9 of the chip U10 is connected to One end of the resistor R124 is connected; the other end of the resistor R124 is connected to B4 of the chip U1; pin 10 of the chip U10, one end of the capacitor C125, and one end of the capacitor C126 are all used for connecting to the second input power supply; the other end of the capacitor C125 and the other end of the capacitor C126 are all connected to DGND; pin 11 of the chip U10 and one end of the capacitor C127 are all connected to one end of the capacitor C129; the other end of the capacitor C129 and one end of the capacitor C128 are all connected to pin 2 of the antenna element ANT1; pin 1 of the antenna element ANT1 is connected to DGND; pin 12 of the chip U10 is connected to DGND; pin 13 of the chip U10 is connected to one end of the capacitor C131, capacitor C13 2 and one end of the magnetic bead FB12 are connected; the other end of the magnetic bead FB12 is used for connecting to the second input power supply; pin 14 of the chip U10 is connected to one end of the capacitor C130; the other end of the capacitor C130 is connected to DGND; pins 15 and 16 of the chip U10 are connected to the third crystal oscillator circuit; pins 17 and 30 of the chip U10 are connected to the input end of the storage circuit; the input end of the storage circuit is used to connect to the second input power supply; pins 28 and 29 of the chip U10 are connected to the output end of the storage circuit; pin 22 of the chip U10 is connected to DGND; pins 25, 46 and 47 of the chip U10 are connected to the input end of the power amplifier module;Pin 33 of the chip U10 is connected to one end of capacitor C116; the other end of capacitor C116 is connected to DGND; pin 34 of the chip U10 is connected to the output end of the audio input adjustment circuit; pin 35 of the chip U10 is connected to one end of capacitor C106; the other end of capacitor C106 is connected to DGND; pin 43 of the chip U10 is connected to one end of capacitor C89 and one end of capacitor C93; pin 44 of the chip U10, the other end of capacitor C89, and the other end of capacitor C93 are all connected to AGND; the input end of the DCDC circuit is used to be connected to the first input power supply; the output end of the DCDC circuit is connected to the input end of the power amplifier module. ;

[0012] Optionally, the audio input adjustment circuit includes a switch S1, a switch S2, a switch S3, a switch S4, a capacitor C133, a capacitor C139, a resistor R48, a resistor R49, a resistor R52, a resistor R54 and a resistor R122; one end of the resistor R122 is used to connect to the second input power supply; the other end of the resistor R122 is connected to pin 34 of the chip U10, one end of the capacitor C133, one end of the resistor R48, one end of the resistor R49, and one end of the resistor R52; the other end of the resistor R48 is connected to pin 2 of the switch S1; the other end of the resistor R49 is connected to pin 2 of the switch S2; the resistor R The other end of 52 is connected to pin 2 of switch S3; the other end of capacitor C133, one end of capacitor C139, pin 1 of switch S1, pin 3 of switch S1, pin 4 of switch S1, pin 1 of switch S2, pin 3 of switch S2, pin 4 of switch S2, pin 1 of switch S3, pin 3 of switch S3, pin 4 of switch S3, pin 1 of switch S4, pin 3 of switch S4, and pin 4 of switch S4 are all connected to DGND; pin 2 of switch S4 is connected to one end of resistor R54; the other end of capacitor C139 and the other end of resistor R54 are all connected to pin 5 of chip U10.

[0013] Optionally, the power amplifier module includes a chip U9, an electrolytic capacitor C90, an electrolytic capacitor C123, a capacitor C91, a capacitor C92, a capacitor C94, a capacitor C95, a capacitor C96, a capacitor C97, a capacitor C98, a capacitor C99, a capacitor C100, a capacitor C101, a capacitor C102, a capacitor C105, a capacitor C104, a capacitor C108, a capacitor C111, a capacitor C112, a capacitor C113, a capacitor C115, a capacitor C117, a capacitor C118, a capacitor C119, a capacitor C120, a capacitor C121, a capacitor C122, a capacitor C124, a resistor R37, a resistor R38, a resistor R39, a resistor R40, a resistor R41, a resistor R42, a resistor R44, a resistor R 45, inductor L15, inductor L16, inductor L17 and inductor L18; pin 1 of chip U9, pin 8 of chip U9, the positive electrode of electrolytic capacitor C90, the positive electrode of electrolytic capacitor C123, one end of capacitor C124, one end of capacitor C122, one end of capacitor C91 and one end of capacitor C92 are all connected to the output end of the DCDC circuit; the negative electrode of electrolytic capacitor C90, the negative electrode of electrolytic capacitor C123, the other end of capacitor C124, the other end of capacitor C122, the other end of capacitor C91 and the other end of capacitor C92 are all connected to GND; pin 2 of chip U9 is connected to one end of resistor R37 and one end of resistor R38; the other end of resistor R37 is connected to DGND; the other end of resistor R38 is connected to GND. One end is connected to pin 25 of chip U10; pin 3 of chip U9 is connected to one end of capacitor C100; the other end of capacitor C100 is connected to one end of capacitor C104, one end of resistor R39, and one end of resistor R41; the other end of resistor R39 is connected to one end of capacitor C98; the other end of capacitor C98 is connected to pin 47 of chip U10; the other end of resistor R41 and the other end of capacitor C104 are both connected to AGND; pin 4 of chip U9 is connected to one end of capacitor C102; pin 5 of chip U9 is connected to one end of capacitor C105; pin 6 of chip U9 is connected to one end of capacitor C111; the other end of capacitor C102, the other end of capacitor C105, and the other end of capacitor C111 are all connected to AGND. Connected to GND; Pin 7 of chip U9 is connected to one end of capacitor C117; the other end of capacitor C117 is connected to one end of capacitor C119, one end of resistor R42, and one end of resistor R44; the other end of resistor R42 is connected to one end of capacitor C105; the other end of capacitor C105 is connected to pin 46 of chip U10; the other end of capacitor C119 and the other end of resistor R44 are both connected to AGND; Pin 9 of chip U9 is connected to one end of capacitor C120; Pin 10 of chip U9 is connected to the other end of capacitor C120 and one end of inductor L18; the other end of inductor L18, one end of resistor R45, one end of capacitor C121, and one end of capacitor C188 are all connected to the audio module;The other end of the resistor R45 is connected to one end of the capacitor C115; the other end of the capacitor C121 and one end of the capacitor C113 are both connected to GND; the pin 11 of the chip U9 is connected to one end of the capacitor C112; the pin 12 of the chip U9 is connected to the other end of the capacitor C112 and one end of the inductor L17; the other end of the inductor L17, the other end of the capacitor C113, the other end of the capacitor C115, and the other end of the capacitor C118 are all connected to the audio module; the pin 14 of the chip U9 is connected to one end of the capacitor C101; the pin 13 of the chip U9 is connected to the other end of the capacitor C101 and the inductor L1 6; the other end of inductor L18, one end of resistor R40, one end of capacitor C99, and one end of capacitor C97 are all connected to the audio module; the other end of resistor R40 is connected to one end of capacitor C95; the other end of capacitor C99 and one end of capacitor C96 are all connected to GND; pin 16 of chip U9 is connected to one end of capacitor C94; pin 15 of chip U9 is connected to the other end of capacitor C94 and one end of inductor L15; the other end of inductor L15, the other end of capacitor C95, the other end of capacitor C96, and the other end of capacitor C97 are all connected to the audio module. ;

[0014] Optionally, the power supply module includes a first power supply circuit, a second power supply circuit and a third power supply circuit; the input end of the first power supply circuit, the input end of the second power supply circuit and the input end of the third power supply circuit are all used to connect to the first input power supply; the output end of the first power supply circuit is connected to the input end of the third power supply circuit and the input end of the video amplification module; the output end of the second power supply circuit is connected to the input end of the video amplification module; the output end of the third power supply circuit is connected to the input end of the high-frequency receiving module.

[0015] Optionally, the input and output module includes a coaxial input circuit, an optical fiber input circuit, a TYPE-C input circuit, a high-frequency HDMI output circuit, an analog audio signal 3.5 jacket input circuit and an analog audio output circuit; the output end of the coaxial input circuit, the output end of the optical fiber input circuit, the output end of the TYPE-C input circuit, the input end of the analog audio signal 3.5 jacket input circuit and the output end of the analog audio output circuit are all connected to the decoding processing module; the input end of the high-frequency HDMI output circuit is connected to the video amplification module.

[0016] Compared with the prior art, the utility model has the following advantages and beneficial effects:

[0017] Input-output module, decoding processing module, power amplifier module, audio module, high-frequency receiving module, video amplifier module and power supply module, the input end of the decoding processing module is connected to the output end of the input-output module; the input end of the power amplifier module is connected to the output end of the decoding processing module; the input end of the audio module is connected to the output end of the power amplifier module; the input end of the video amplifier module is connected to the output end of the high-frequency receiving module and the output end of the decoding processing module; and the output end of the video amplifier module is connected to the input end of the input-output module. The purpose of improving the performance and processing capability through the decoding processing module and the power amplifier module, and then improving the sound quality of karaoke is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present utility model, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present utility model, and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work. In the drawings:

[0019] Figure 1 It is a schematic diagram of an electrical block diagram of a sound system with a video output function in an embodiment;

[0020] Figure 2 It is a structural schematic diagram of an audio isolation circuit with a video output function in an embodiment;

[0021] Figure 3 A schematic diagram of the structure of an audio bipolar power supply with a video output function in an embodiment;

[0022] Figure 4 It is a schematic diagram of the structure of an audio MCX connector with video output function, a low-frequency EOC filter circuit, a WiFi filter circuit and a conduction suppression anti-winding circuit in an embodiment;

[0023] Figure 5 It is a structural schematic diagram of an audio voltage regulating circuit with a video output function in an embodiment;

[0024] Figure 6 A schematic diagram of a first filter circuit and a second filter circuit of an audio system with a video output function in an embodiment;

[0025] Figure 7 It is a structural schematic diagram of an audio chip U7 with a video output function, a comparison circuit and a first crystal oscillator circuit in an embodiment;

[0026] Figure 8 It is a structural schematic diagram of an audio coaxial input circuit with a video output function in an embodiment;

[0027] Fig. 9 It is a structural schematic diagram of an audio optical fiber input circuit with a video output function in an embodiment;

[0028] Fig.10 A schematic diagram of a stereo TYPE-C input circuit with a video output function in an embodiment;

[0029] Fig.11 A schematic diagram of an audio analog audio output circuit with a video output function in an embodiment;

[0030] Fig.12 This is a structural schematic diagram of a high-frequency HDMI output circuit for audio with video output function in an embodiment;

[0031] Fig.13 It is a structural schematic diagram of a 3.5 jacket input circuit for an audio analog audio signal with a video output function in an embodiment;

[0032] Fig.14 It is a structural schematic diagram of a third filter circuit and a fourth filter circuit of an audio system with a video output function in an embodiment;

[0033] Fig.15 This is a schematic diagram of the structure of an audio chip U1 with a video output function in an embodiment;

[0034] Fig.16 It is a structural schematic diagram of a sound download serial port circuit with video output function in an embodiment;

[0035] Fig.17 It is a structural schematic diagram of an audio debugging serial port circuit with a video output function in an embodiment;

[0036] Fig.18 It is a structural schematic diagram of an audio USB differential circuit with video output function in an embodiment;

[0037] Fig.19 It is a structural schematic diagram of an audio SPI_FLASH interface circuit with a video output function in an embodiment;

[0038] Fig. 20 It is a structural schematic diagram of an audio detection circuit with a video output function in an embodiment;

[0039] Fig.21 It is a structural schematic diagram of a second crystal oscillator circuit of an audio system with a video output function in an embodiment;

[0040] Fig. 22A schematic diagram of the structure of an audio power amplifier module with a video output function in an embodiment;

[0041] Fig.23 It is a schematic diagram of the structure of an audio chip U10 with a video output function and a third crystal oscillator circuit in an embodiment;

[0042] Fig.24 A schematic diagram of the structure of an audio storage circuit with a video output function in an embodiment;

[0043] Fig.25 It is a structural schematic diagram of an audio DCDC circuit with video output function in an embodiment;

[0044] Fig.26 It is a structural schematic diagram of an audio input adjustment circuit with a video output function in an embodiment;

[0045] Fig. 27 It is a structural schematic diagram of a first power supply circuit of an audio system with a video output function in an embodiment;

[0046] Fig.28 It is a structural schematic diagram of a second power supply circuit of an audio system with a video output function in an embodiment;

[0047] Fig.29 It is a structural schematic diagram of a third power supply circuit of an audio system with a video output function in an embodiment.

[0048] Marks and corresponding parts names in the attached drawings:

[0049] 100-input and output module; 200-decoding processing module; 300-power amplification module; 400-audio module; 500-high frequency receiving module; 600-video amplification module; 700-power supply module. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the utility model more clearly understood, the utility model is further described in detail below in conjunction with embodiments and drawings. The schematic implementation manner of the utility model and its description are only used to explain the utility model and are not intended to limit the utility model.

[0051] Embodiment: A sound system with video output function, such as Figure 1-Figure 29As shown, it includes: an input and output module 100, a decoding processing module 200, a power amplifier module 300, an audio module 400, a high-frequency receiving module 500, a video amplifier module 600 and a power module 700, wherein the input and output module 100 is used to receive audio signals and output video signals; the input end of the decoding processing module 200 is connected to the output end of the input and output module; the input end of the power amplifier module 300 is connected to the output end of the decoding processing module 200; the input end of the audio module 400 is connected to the output end of the power amplifier module 300; the high-frequency receiving module 500 is used to receive video signals; the input end of the video amplifier module 600 is connected to the output end of the high-frequency receiving module 500 and the output end of the decoding processing module 200; the output end of the video amplifier module 600 is connected to the input end of the input and output module 100; and the power module 700 is used to supply power to each module. Among them, the audio module 400 can be a speaker or a speaker unit composed of multiple speakers.

[0052] In this embodiment, the high frequency receiving module 500 includes an input unit and a processing unit; the input unit includes Figure 2 The ground isolation circuit shown in Figure 3 The bipolar power supply PBZ1 shown, and Figure 4 The MCX connector, low-frequency EOC filter circuit, WiFi filter circuit and conduction suppression anti-winding circuit shown in the figure; one end of the ground isolation circuit is used to connect to EGND; the other end of the ground isolation circuit is used to connect to DGND; pins 0, 1, 2, 3, 4 and 5 of the bipolar power supply PBZ1 are all used to connect to DGND; pins 1, 2, 3 and 4 of the MCX connector are all used to connect to EGND; pin 5 of the MCX connector is connected to the input end of the low-frequency EOC filter circuit; the output end of the low-frequency EOC filter circuit is connected to the input end of the WiFi filter circuit; the output end of the WiFi filter circuit is connected to the input end of the conduction suppression anti-winding circuit; the output end of the conduction suppression anti-winding circuit is connected to the input end of the processing unit.

[0053] In this embodiment, the processing unit includes: Figure 5 The voltage regulation circuit shown in Figure 6 The first filter circuit and the second filter circuit shown in FIG. Figure 7The comparison circuit, the first crystal oscillator circuit and the chip U7 shown in the figure; also include magnetic beads FB5, magnetic beads FB6, resistors R27, R28, R29, R30, R33, R34, R35, R36, current transformer CT2, capacitor C61, capacitor C62, capacitor C64, capacitor C65, capacitor C66, capacitor C70, capacitor C72, capacitor C73, capacitor C78, ​​capacitor C81, capacitor C82, capacitor C86, capacitor C87, capacitor C88, capacitor C145 and capacitor C146; the input end of the voltage regulation circuit, the input end of the first filter circuit, and the input end of the comparison circuit are all connected to the output end of the power module 700; the The output end of the voltage regulating circuit is connected to the input end of the second filtering circuit; the input end of the comparison circuit is connected to the voltage-stabilized power supply; the output end of the comparison circuit is connected to pin 6 of chip U7 and pin 7 of chip U7; the input end of the first crystal oscillator circuit is connected to pin 11 of chip U7 and pin 12 of chip U7; the output end of the first crystal oscillator circuit is connected to DGND; pin 51 of chip U7 and one end of capacitor C61 are connected to one end of magnetic bead FB5; the other end of magnetic bead FB5 is connected to the output end of the second filtering circuit; pin 52 of chip U7, one end of capacitor C65, and one end of capacitor C66 are connected to one end of magnetic bead FB6; the other end of magnetic bead FB6 Connected to the output end of the first filtering circuit; the other end of the capacitor C61, the other end of the capacitor C65, and the other end of the capacitor C66 are all connected to DGND; pins 55 and 56 of the chip U7 are both used to connect to the output end of the conduction suppression anti-winding circuit; pin 41 of the chip U7 is connected to one end of the resistor R27; pin 39 of the chip U7 is connected to one end of the resistor R28; pin 38 of the chip U7 is connected to one end of the resistor R29; pin 36 of the chip U7 is connected to one end of the resistor R30; pin 24 of the chip U7 is connected to one end of the resistor R33, one end of the resistor R35, and one end of the capacitor C87; pin 23 of the chip U7 is connected to one end of the resistor R34 , one end of the resistor R36, and one end of the capacitor C88 are all connected; the other end of the resistor R27, the other end of the resistor R28, the other end of the resistor R29, the other end of the resistor R30, the other end of the resistor R35, the other end of the resistor R36, and one end of the capacitor C64 are all connected to the video amplification module 600; the other end of the capacitor C64, the other end of the capacitor C87, and the other end of the capacitor C88 are all connected to DGND; the other end of the resistor R33 and the other end of the resistor R34 are all connected to the output end of the first filter circuit; pins 27, 35, and 45 of the chip U7, as well as one end of the capacitor C62, one end of the capacitor C70, and one end of the capacitor C82 are all connected to the output end of the first filter circuit;The other end of capacitor C62, the other end of capacitor C70, and the other end of capacitor C82 are all connected to DGND; pins 3, 4, 5, 8, 9, 18, 19, 53, and 54 of the chip U7, as well as one end of current transformer CT2, one end of capacitor C73, one end of capacitor C78, ​​one end of capacitor C81, one end of capacitor C145, and one end of capacitor C146 are all connected to the regulated power supply; the other end of current transformer CT2, the other end of capacitor C73 The other end of capacitor C78, ​​the other end of capacitor C81, the other end of capacitor C145, and the other end of capacitor C146 are all connected to DGND; pins 20 and 34 of the chip U7, as well as one end of capacitor C72 and one end of capacitor C86 are all connected to the output end of the second filter circuit; the other end of capacitor C72 and the other end of capacitor C86 are all connected to DGND; pins 25, 31, 33, 40, 48, and 57 of the chip U7 are all connected to DGND. ;

[0054] In this embodiment, the comparison circuit includes a magnetic bead FB7, a magnetic bead FB8, a magnetic bead FB13, a transistor Q1, a capacitor C63, a capacitor C67, a capacitor C68, a capacitor C69 and a capacitor C71; one end of the magnetic bead FB13 is connected to the output end of the power module 700; the other end of the magnetic bead FB13, one end of the magnetic bead FB7, and one end of the capacitor C63 are all connected to the emitter of the transistor Q1; the other end of the capacitor C63 is connected to DGND; the other end of the magnetic bead FB7 is connected to DGND; One end of the magnetic bead FB8, one end of the capacitor C67, and one end of the capacitor C68 are all connected to the regulated power supply; the other end of the capacitor C67 and the other end of the capacitor C68 are all connected to DGND; the other end of the magnetic bead FB8, one end of the capacitor C69, one end of the capacitor C71, and the collector of the transistor Q1 are all connected to pin 6 of the chip U7; the other end of the capacitor C69 and the other end of the capacitor C71 are all connected to DGND; the base of the transistor Q1 is connected to pin 7 of the chip U7.

[0055] In this embodiment, the video magnification module 600 includes: Fig.15 The chip U1 shown in Fig.14 The third filter circuit and the fourth filter circuit shown in FIG. Fig.16 The download serial port circuit shown in Fig.17 The debugging serial port circuit shown in Fig.18 The USB differential circuit shown in Fig.19 The SPI_FLASH interface circuit shown in Fig. 20 The detection circuit shown in Fig.21The second crystal oscillator circuit, resistor R3, and resistor R4 shown in the figure; the input end of the third filter circuit and the input end of the fourth filter circuit are both connected to the power module 700; the output end of the third filter circuit is connected to A1, A2, B1, B2, C1, C2, D1, and D2 of chip U1; the output end of the fourth filter circuit is connected to G1, G2, H1, and H2 of chip U1; the download serial port circuit is connected to B5 and C5 of the power module 700 and chip U1; the debug serial port circuit is connected to B3 and B4 of the power module 700 and chip U1; the USB differential circuit is connected to L3 and L4 of chip U1; the input end of the SPI_FLASH interface circuit is connected to K1, K2, J1, and J2 of the power module 700 and chip U1; the output end of the SPI_FLASH interface circuit is connected to L1 and L2 of chip U1; the detection circuit is connected to L5 of the power module 700 and chip U1 The input end of the second crystal oscillator circuit is connected to A5 of chip U1; the output end of the second crystal oscillator circuit is connected to A4 of chip U1; one end of resistor R3 is connected to the power module 700; the other end of resistor R3 is connected to E8 of chip U1; one end of resistor R4 is connected to the output end of the third filter circuit; the other end of resistor R4 is connected to E1 of chip U1; H8 of chip U1 is connected to the other end of resistor R27; G9 of chip U1 is connected to the other end of resistor R28 one end is connected; C9 of the chip U1 is connected to the other end of the resistor R29; C10 of the chip U1 is connected to the other end of the resistor R30; C4 of the chip U1 is connected to the other end of the resistor R35; C3 of the chip U1 is connected to the other end of the resistor R36; B3 and B4 of the chip U1 are both connected to the decoding processing module 200; D4, E3, E4, F2, F3, F4, G3, G4, H3, and H4 of the chip U1 are all connected to DGND.

[0056] In this embodiment, the decoding processing module 200 includes: Fig.26 The audio input adjustment circuit shown in Fig.23 The third crystal oscillator circuit shown in Fig.24 The storage circuit shown in Fig.25The DCDC circuit shown, antenna element ANT1, magnetic bead FB12, chip U10, resistor R124, capacitor C89, capacitor C93, capacitor C103, capacitor C106, capacitor C107, capacitor C110, capacitor C114, capacitor C116, capacitor C125, capacitor C126, capacitor C127, capacitor C128, capacitor C129, capacitor C130, capacitor C131, capacitor C132, electrolytic capacitor C109, diode D2; pin 1 of the chip U10, one end of capacitor C103, and one end of capacitor C106 are all connected to the analog voltage; the other end of capacitor C103 and the other end of capacitor C106 are all connected to the analog voltage. AGND connection; Pin 2 of the chip U10, one end of the capacitor C110, and the positive electrode of the electrolytic capacitor C109 are all connected to the negative electrode of the diode D2; the positive electrode of the diode D2 is used to connect to the first input power supply (VDD5V); Pin 3 of the chip U10 is connected to one end of the capacitor C114; Pin 4 of the chip U10, the other end of the capacitor C114, the other end of the capacitor C110, and the negative electrode of the electrolytic capacitor C109 are all connected to DGND; Pin 5 of the chip U10 is connected to the output end of the audio input adjustment circuit; the input end of the audio input adjustment circuit is used to connect to the second input power supply (VDD3.3V); Pin 8 is connected to B3 of chip U1; Pin 9 of the chip U10 is connected to one end of resistor R124; the other end of resistor R124 is connected to B4 of chip U1; Pin 10 of the chip U10, one end of capacitor C125, and one end of capacitor C126 are all connected to the second input power supply (VDD3.3V); the other end of capacitor C125 and the other end of capacitor C126 are both connected to DGND; Pin 11 of the chip U10 and one end of capacitor C127 are both connected to one end of capacitor C129; the other end of capacitor C129 and one end of capacitor C128 are both connected to pin 2 of antenna element ANT1; pin 1 of antenna element ANT1 The first pin of the chip U10 is connected to DGND; the first pin of the chip U10 is connected to one end of the capacitor C131, one end of the capacitor C132, and one end of the magnetic bead FB12; the other end of the magnetic bead FB12 is used to connect to the second input power supply (VDD3.3V); the first pin of the chip U10 is connected to one end of the capacitor C130; the other end of the capacitor C130 is connected to DGND; the first pins 15 and 16 of the chip U10 are connected to the third crystal oscillator circuit; the first pins 17 and 30 of the chip U10 are connected to the input end of the storage circuit; the input end of the storage circuit is used to connect to the second input power supply (VDD3.3V).3V); Pin 28 and Pin 29 of the chip U10 are connected to the output end of the storage circuit; Pin 22 of the chip U10 is connected to DGND; Pin 25, Pin 46 and Pin 47 of the chip U10 are connected to the input end of the power amplifier module 300; Pin 33 of the chip U10 is connected to one end of the capacitor C116; The other end of the capacitor C116 is connected to DGND; Pin 34 of the chip U10 is connected to the output end of the audio input adjustment circuit; Pin 35 of chip U10 is connected to one end of capacitor C106; the other end of capacitor C106 is connected to DGND; pin 43 of chip U10 is connected to one end of capacitor C89 and one end of capacitor C93; pin 44 of chip U10, the other end of capacitor C89 and the other end of capacitor C93 are connected to AGND; the input end of the DCDC circuit is used to connect to the first input power supply (VDD5V); the output end of the DCDC circuit is connected to the input end of the power amplifier module 300. .

[0057] In this embodiment, the audio input adjustment circuit includes a switch S1, a switch S2, a switch S3, a switch S4, a capacitor C133, a capacitor C139, a resistor R48, a resistor R49, a resistor R52, a resistor R54 and a resistor R122; one end of the resistor R122 is used to connect to the second input power supply (VDD3.3V); the other end of the resistor R122 is connected to pin 34 of the chip U10, one end of the capacitor C133, one end of the resistor R48, one end of the resistor R49, and one end of the resistor R52; the other end of the resistor R48 is connected to pin 2 of the switch S1; the other end of the resistor R49 is connected to pin 2 of the switch S2. connection; the other end of resistor R52 is connected to pin 2 of switch S3; the other end of capacitor C133, one end of capacitor C139, pin 1 of switch S1, pin 3 of switch S1, pin 4 of switch S1, pin 1 of switch S2, pin 3 of switch S2, pin 4 of switch S2, pin 1 of switch S3, pin 3 of switch S3, pin 4 of switch S3, pin 1 of switch S4, pin 3 of switch S4, and pin 4 of switch S4 are all connected to DGND; pin 2 of switch S4 is connected to one end of resistor R54; the other end of capacitor C139 and the other end of resistor R54 are both connected to pin 5 of chip U10.

[0058] In this embodiment, if Fig. 22As shown, the power amplifier module 300 includes a chip U9, an electrolytic capacitor C90, an electrolytic capacitor C123, a capacitor C91, a capacitor C92, a capacitor C94, a capacitor C95, a capacitor C96, a capacitor C97, a capacitor C98, a capacitor C99, a capacitor C100, a capacitor C101, a capacitor C102, a capacitor C105, a capacitor C104, a capacitor C108, a capacitor C111, a capacitor C112, a capacitor C113, a capacitor C115, a capacitor C117, a capacitor C118, a capacitor C119, a capacitor C120, a capacitor C121, a capacitor C122, a capacitor C124, a resistor R37, a resistor R38, a resistor R39, a resistor R40, a resistor R41, a resistor R42, a resistor R44, a resistor R45, inductor L15, inductor L16, inductor L17 and inductor L18; pin 1 of chip U9, pin 8 of chip U9, the positive electrode of electrolytic capacitor C90, the positive electrode of electrolytic capacitor C123, one end of capacitor C124, one end of capacitor C122, one end of capacitor C91 and one end of capacitor C92 are all connected to the output end of the DCDC circuit; the negative electrode of electrolytic capacitor C90, the negative electrode of electrolytic capacitor C123, the other end of capacitor C124, the other end of capacitor C122, the other end of capacitor C91 and the other end of capacitor C92 are all connected to GND; pin 2 of chip U9 is connected to one end of resistor R37 and one end of resistor R38; the other end of resistor R37 is connected to DGND; the other end of resistor R38 is connected to GND. One end is connected to pin 25 of chip U10; pin 3 of chip U9 is connected to one end of capacitor C100; the other end of capacitor C100 is connected to one end of capacitor C104, one end of resistor R39, and one end of resistor R41; the other end of resistor R39 is connected to one end of capacitor C98; the other end of capacitor C98 is connected to pin 47 of chip U10; the other end of resistor R41 and the other end of capacitor C104 are both connected to AGND; pin 4 of chip U9 is connected to one end of capacitor C102; pin 5 of chip U9 is connected to one end of capacitor C105; pin 6 of chip U9 is connected to one end of capacitor C111; the other end of capacitor C102, the other end of capacitor C105, and the other end of capacitor C111 are all connected GND connected; pin 7 of chip U9 is connected to one end of capacitor C117; the other end of capacitor C117 is connected to one end of capacitor C119, one end of resistor R42, and one end of resistor R44; the other end of resistor R42 is connected to one end of capacitor C105; the other end of capacitor C105 is connected to pin 46 of chip U10; the other end of capacitor C119 and the other end of resistor R44 are both connected to AGND; pin 9 of chip U9 is connected to one end of capacitor C120; pin 10 of chip U9 is connected to the other end of capacitor C120 and one end of inductor L18; the other end of inductor L18, one end of resistor R45, one end of capacitor C121, and one end of capacitor C188 are all connected to the audio module 400;The other end of the resistor R45 is connected to one end of the capacitor C115; the other end of the capacitor C121 and one end of the capacitor C113 are both connected to GND; the pin 11 of the chip U9 is connected to one end of the capacitor C112; the pin 12 of the chip U9 is connected to the other end of the capacitor C112 and one end of the inductor L17; the other end of the inductor L17, the other end of the capacitor C113, the other end of the capacitor C115, and the other end of the capacitor C118 are all connected to the audio module 400; the pin 14 of the chip U9 is connected to one end of the capacitor C101; the pin 13 of the chip U9 is connected to the other end of the capacitor C101 and the inductor L16 The other end of the inductor L18, one end of the resistor R40, one end of the capacitor C99, and one end of the capacitor C97 are all connected to the audio module 400; the other end of the resistor R40 is connected to one end of the capacitor C95; the other end of the capacitor C99 and one end of the capacitor C96 are all connected to GND; the pin 16 of the chip U9 is connected to one end of the capacitor C94; the pin 15 of the chip U9 is connected to the other end of the capacitor C94 and one end of the inductor L15; the other end of the inductor L15, the other end of the capacitor C95, the other end of the capacitor C96, and the other end of the capacitor C97 are all connected to the audio module 400. ;

[0059] In this embodiment, the power module 700 includes: Fig. 27 The first power supply circuit shown in Fig.28 The second power supply circuit shown and Fig.29 The third power supply circuit shown; the input end of the first power supply circuit, the input end of the second power supply circuit, and the input end of the third power supply circuit are all used to connect to the first input power supply (VDD5V); the output end of the first power supply circuit is connected to the input end of the third power supply circuit and the input end of the video amplification module 600; the output end of the second power supply circuit is connected to the input end of the video amplification module 600; the output end of the third power supply circuit is connected to the input end of the high-frequency receiving module 500.

[0060] In this embodiment, the input-output module 100 includes: Figure 8 The coaxial input circuit shown in Fig. 9 The optical fiber input circuit shown in Fig.10 The TYPE-C input circuit shown in Fig.12 The high-frequency HDMI output circuit shown in Fig.13 The analog audio signal 3.5 jacket input circuit shown and as Fig.11The analog audio output circuit shown; the output end of the coaxial input circuit, the output end of the optical fiber input circuit, the output end of the TYPE-C input circuit, the input end of the analog audio signal 3.5 jacket input circuit, and the output end of the analog audio output circuit are all connected to the decoding processing module 200; the input end of the high-frequency HDMI output circuit is connected to the video amplification module 600.

[0061] In this embodiment, a speaker with a video output function works as follows:

[0062] When singing karaoke at home, connecting a wireless microphone, and connecting to a TV to watch movies, satellite channels, entertainment channels, KTV or music channels. The power module 700 supplies power to each module. This circuit uses a multi-channel input interface, a coaxial input circuit, an optical fiber input circuit, a TYPE-C input circuit, and an analog audio signal 3.5 jacket input circuit, which are transmitted to the decoding processing module 200. The audio signal of the decoding processing module 200 is transmitted to the power amplifier module 300 to drive the audio module 400 to pronounce. In addition, the TV signal is transmitted to the video amplifier module 600 through the high-frequency receiving module 500, and the audio is transmitted to the decoding processing module 200, and flows to the power amplifier module 300 to drive the audio module 400. The video signal amplified by the video amplifier module 600 is connected to the TV broadcast image signal by the high-frequency HDMI output circuit.

[0063] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the utility model in detail. It should be understood that the above description is only the specific implementation method of the utility model and is not used to limit the protection scope of the utility model. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the utility model should be included in the protection scope of the utility model.

Claims

1. A speaker with video output function, characterized in that: include: An input-output module (100), the input-output module (100) being used to receive an audio signal and output a video signal; A decoding processing module (200), the input end of the decoding processing module (200) being connected to the output end of the input-output module; A power amplification module (300), the input end of the power amplification module (300) being connected to the output end of the decoding processing module (200); An audio module (400), the input end of the audio module (400) being connected to the output end of the power amplification module (300); A high-frequency receiving module (500), the high-frequency receiving module (500) being used to receive a video signal; A video amplification module (600), wherein the input end of the video amplification module (600) is connected to the output end of the high-frequency receiving module (500) and the output end of the decoding processing module (200); the output end of the video amplification module (600) is connected to the input end of the input-output module (100); A power supply module (700), wherein the power supply module (700) is used to supply power to each module.

2. The speaker with video output function according to claim 1, characterized in that: The high-frequency receiving module (500) comprises an input unit and a processing unit; The input unit includes a ground isolation circuit, a bipolar power supply PBZ1, an MCX connector, a low-frequency EOC filter circuit, a WiFi filter circuit and a conduction suppression anti-winding circuit; One end of the ground isolation circuit is used to connect to EGND; The other end of the ground isolation circuit is used to connect to DGND; Pins 0, 1, 2, 3, 4 and 5 of the bipolar power supply PBZ1 are all used to connect to DGND; Pins 1, 2, 3 and 4 of the MCX connector are all used to connect to EGND; Pin 5 of the MCX connector is connected to the input end of the low-frequency EOC filter circuit; The output end of the low-frequency EOC filter circuit is connected to the input end of the WiFi filter circuit; The output end of the WiFi filter circuit is connected to the input end of the conduction suppression anti-winding circuit; The output end of the conduction suppression circuit is connected to the input end of the processing unit.

3. The speaker with video output function according to claim 2, characterized in that: The processing unit includes a voltage regulating circuit, a first filtering circuit, a second filtering circuit, a comparison circuit, a first crystal oscillator circuit, a chip U7, a magnetic bead FB5, a magnetic bead FB6, a resistor R27, a resistor R28, a resistor R29, a resistor R30, a resistor R33, a resistor R34, a resistor R35, a resistor R36, a current transformer CT2, a capacitor C61, a capacitor C62, a capacitor C64, a capacitor C65, a capacitor C66, a capacitor C70, a capacitor C72, a capacitor C73, a capacitor C78, ​​a capacitor C81, a capacitor C82, a capacitor C86, a capacitor C87, a capacitor C88, a capacitor C145 and a capacitor C146; The input end of the voltage regulating circuit, the input end of the first filtering circuit, and the input end of the comparison circuit are all connected to the output end of the power module (700); The output end of the voltage regulating circuit is connected to the input end of the second filtering circuit; The input end of the comparison circuit is connected to a regulated power supply; The output end of the comparison circuit is connected to both pin 6 of chip U7 and pin 7 of chip U7; The input end of the first crystal oscillator circuit is connected to both pin 11 of chip U7 and pin 12 of chip U7; The output end of the first crystal oscillator circuit is connected to DGND; Pin 51 of the chip U7 and one end of the capacitor C61 are connected to one end of the magnetic bead FB5; The other end of the magnetic bead FB5 is connected to the output end of the second filter circuit; Pin 52 of the chip U7, one end of the capacitor C65, and one end of the capacitor C66 are all connected to one end of the magnetic bead FB6; The other end of the magnetic bead FB6 is connected to the output end of the first filter circuit; The other end of capacitor C61, the other end of capacitor C65, and the other end of capacitor C66 are all connected to DGND; Pins 55 and 56 of the chip U7 are used to connect to the output end of the conduction suppression anti-winding circuit; Pin 41 of the chip U7 is connected to one end of the resistor R27; Pin 39 of the chip U7 is connected to one end of the resistor R28; Pin 38 of the chip U7 is connected to one end of the resistor R29; Pin 36 of the chip U7 is connected to one end of the resistor R30; Pin 24 of the chip U7 is connected to one end of the resistor R33, one end of the resistor R35, and one end of the capacitor C87; Pin 23 of the chip U7 is connected to one end of the resistor R34, one end of the resistor R36, and one end of the capacitor C88; The other end of the resistor R27, the other end of the resistor R28, the other end of the resistor R29, the other end of the resistor R30, the other end of the resistor R35, the other end of the resistor R36, and one end of the capacitor C64 are all connected to the video amplification module (600); The other end of capacitor C64, the other end of capacitor C87, and the other end of capacitor C88 are all connected to DGND; The other end of the resistor R33 and the other end of the resistor R34 are both connected to the output end of the first filter circuit; Pins 27, 35 and 45 of the chip U7, as well as one end of capacitor C62, one end of capacitor C70 and one end of capacitor C82 are all connected to the output end of the first filter circuit; The other end of capacitor C62, the other end of capacitor C70, and the other end of capacitor C82 are all connected to DGND; Pins 3, 4, 5, 8, 9, 18, 19, 53 and 54 of the chip U7, as well as one end of the current transformer CT2, one end of the capacitor C73, one end of the capacitor C78, ​​one end of the capacitor C81, one end of the capacitor C145 and one end of the capacitor C146 are all connected to the voltage-stabilized power supply; The other end of the current transformer CT2, the other end of the capacitor C73, the other end of the capacitor C78, ​​the other end of the capacitor C81, the other end of the capacitor C145, and the other end of the capacitor C146 are all connected to DGND; Pin 20 and pin 34 of the chip U7, as well as one end of the capacitor C72 and one end of the capacitor C86 are connected to the output end of the second filter circuit; The other end of capacitor C72 and the other end of capacitor C86 are both connected to DGND; Pins 25, 31, 33, 40, 48 and 57 of the chip U7 are all connected to DGND.

4. The speaker with video output function according to claim 3, characterized in that: The comparison circuit includes magnetic beads FB7, FB8, FB13, transistor Q1, capacitor C63, capacitor C67, capacitor C68, capacitor C69 and capacitor C71; One end of the magnetic bead FB13 is connected to the output end of the power module (700); The other end of the magnetic bead FB13, one end of the magnetic bead FB7, and one end of the capacitor C63 are all connected to the emitter of the transistor Q1; The other end of capacitor C63 is connected to DGND; The other end of the magnetic bead FB7, one end of the magnetic bead FB8, one end of the capacitor C67, and one end of the capacitor C68 are all connected to the voltage-stabilized power supply; The other end of capacitor C67 and the other end of capacitor C68 are both connected to DGND; The other end of the magnetic bead FB8, one end of the capacitor C69, one end of the capacitor C71, and the collector of the transistor Q1 are all connected to pin 6 of the chip U7; The other end of capacitor C69 and the other end of capacitor C71 are both connected to DGND; The base of transistor Q1 is connected to pin 7 of chip U7.

5. The speaker with video output function according to claim 3, characterized in that: The video amplification module (600) comprises a chip U1, a third filtering circuit, a fourth filtering circuit, a download serial port circuit, a debugging serial port circuit, a USB differential circuit, an SPI_FLASH interface circuit, a detection circuit, a second crystal oscillator circuit, a resistor R3, and a resistor R4; The input end of the third filter circuit and the input end of the fourth filter circuit are both connected to the power module (700); The output end of the third filter circuit is connected to A1, A2, B1, B2, C1, C2, D1, and D2 of chip U1; The output end of the fourth filter circuit is connected to G1, G2, H1, and H2 of chip U1; The download serial port circuit is connected to the power module (700) and B5 and C5 of the chip U1; The debugging serial port circuit is connected to the power module (700) and B3 and B4 of the chip U1; The USB differential circuit is connected to both L3 and L4 of chip U1; The input end of the SPI_FLASH interface circuit is connected to the power module (700) and K1, K2, J1 and J2 of the chip U1; The output end of the SPI_FLASH interface circuit is connected to both L1 and L2 of the chip U1; The detection circuit is connected to the power module (700) and L5 of the chip U1; The input end of the second crystal oscillator circuit is connected to A5 of chip U1; The output end of the second crystal oscillator circuit is connected to A4 of chip U1; One end of the resistor R3 is connected to the power module (700); The other end of the resistor R3 is connected to E8 of the chip U1; One end of the resistor R4 is connected to the output end of the third filter circuit; The other end of the resistor R4 is connected to E1 of the chip U1; H8 of the chip U1 is connected to the other end of the resistor R27; G9 of the chip U1 is connected to the other end of the resistor R28; C9 of the chip U1 is connected to the other end of the resistor R29; C10 of the chip U1 is connected to the other end of the resistor R30; C4 of the chip U1 is connected to the other end of the resistor R35; C3 of the chip U1 is connected to the other end of the resistor R36; B3 and B4 of the chip U1 are both connected to the decoding processing module (200); D4, E3, E4, F2, F3, F4, G3, G4, H3, and H4 of the chip U1 are all connected to DGND.

6. The speaker with video output function according to claim 5, characterized in that: The decoding processing module (200) comprises an audio input adjustment circuit, a third crystal oscillator circuit, a storage circuit, a DCDC circuit, an antenna element ANT1, a magnetic bead FB12, a chip U10, a resistor R124, a capacitor C89, a capacitor C93, a capacitor C103, a capacitor C106, a capacitor C107, a capacitor C110, a capacitor C114, a capacitor C116, a capacitor C125, a capacitor C126, a capacitor C127, a capacitor C128, a capacitor C129, a capacitor C130, a capacitor C131, a capacitor C132, an electrolytic capacitor C109, and a diode D2; Pin 1 of the chip U10, one end of the capacitor C103, and one end of the capacitor C106 are all connected to the analog voltage; The other end of the capacitor C103 and the other end of the capacitor C106 are both connected to AGND; Pin 2 of the chip U10, one end of the capacitor C110, and the positive electrode of the electrolytic capacitor C109 are all connected to the negative electrode of the diode D2; The anode of the diode D2 is used to be connected to the first input power supply; Pin 3 of the chip U10 is connected to one end of the capacitor C114; Pin 4 of the chip U10, the other end of the capacitor C114, the other end of the capacitor C110, and the negative electrode of the electrolytic capacitor C109 are all connected to DGND; Pin 5 of the chip U10 is connected to the output end of the audio input adjustment circuit; The input end of the audio input adjustment circuit is used to be connected to a second input power supply; Pin 8 of the chip U10 is connected to B3 of the chip U1; Pin 9 of the chip U10 is connected to one end of the resistor R124; The other end of the resistor R124 is connected to B4 of the chip U1; Pin 10 of the chip U10, one end of the capacitor C125, and one end of the capacitor C126 are all used for connecting to a second input power supply; The other end of the capacitor C125 and the other end of the capacitor C126 are both connected to DGND; Pin 11 of the chip U10 and one end of the capacitor C127 are connected to one end of the capacitor C129; The other end of capacitor C129 and one end of capacitor C128 are both connected to pin 2 of antenna element ANT1; Pin 1 of the antenna element ANT1 is connected to DGND; Pin 12 of the chip U10 is connected to DGND; Pin 13 of the chip U10 is connected to one end of the capacitor C131, one end of the capacitor C132, and one end of the magnetic bead FB12; The other end of the magnetic bead FB12 is used for connecting the second input power supply; Pin 14 of the chip U10 is connected to one end of the capacitor C130; The other end of capacitor C130 is connected to DGND; Pins 15 and 16 of the chip U10 are both connected to the third crystal oscillator circuit; Pins 17 and 30 of the chip U10 are connected to the input end of the storage circuit; The input terminal of the storage circuit is used to be connected to a second input power source; Pins 28 and 29 of the chip U10 are connected to the output end of the storage circuit; Pin 22 of the chip U10 is connected to DGND; Pins 25, 46 and 47 of the chip U10 are all connected to the input end of the power amplifier module (300); Pin 33 of the chip U10 is connected to one end of the capacitor C116; The other end of capacitor C116 is connected to DGND; Pin 34 of the chip U10 is connected to the output end of the audio input adjustment circuit; Pin 35 of the chip U10 is connected to one end of the capacitor C106; The other end of capacitor C106 is connected to DGND; Pin 43 of the chip U10 is connected to one end of capacitor C89 and one end of capacitor C93; Pin 44 of the chip U10, the other end of the capacitor C89, and the other end of the capacitor C93 are all connected to AGND; The input end of the DCDC circuit is used to be connected to a first input power source; The output end of the DCDC circuit is connected to the input end of the power amplification module (300).

7. The speaker with video output function according to claim 6, characterized in that: The audio input adjustment circuit includes a switch S1, a switch S2, a switch S3, a switch S4, a capacitor C133, a capacitor C139, a resistor R48, a resistor R49, a resistor R52, a resistor R54 and a resistor R122; One end of the resistor R122 is used to be connected to the second input power source; The other end of the resistor R122 is connected to the pin 34 of the chip U10, one end of the capacitor C133, one end of the resistor R48, one end of the resistor R49, and one end of the resistor R52; The other end of the resistor R48 is connected to pin 2 of the switch S1; The other end of the resistor R49 is connected to pin 2 of the switch S2; The other end of the resistor R52 is connected to the pin 2 of the switch S3; The other end of capacitor C133, one end of capacitor C139, pin 1 of switch S1, pin 3 of switch S1, pin 4 of switch S1, pin 1 of switch S2, pin 3 of switch S2, pin 4 of switch S2, pin 1 of switch S3, pin 3 of switch S3, pin 4 of switch S3, pin 1 of switch S4, pin 3 of switch S4, and pin 4 of switch S4 are all connected to DGND; Pin 2 of switch S4 is connected to one end of resistor R54; The other end of the capacitor C139 and the other end of the resistor R54 are both connected to pin 5 of the chip U10.

8. The speaker with video output function according to claim 6, characterized in that: The power amplifier module (300) comprises a chip U9, an electrolytic capacitor C90, an electrolytic capacitor C123, a capacitor C91, a capacitor C92, a capacitor C94, a capacitor C95, a capacitor C96, a capacitor C97, a capacitor C98, a capacitor C99, a capacitor C100, a capacitor C101, a capacitor C102, a capacitor C105, a capacitor C104, a capacitor C108, a capacitor C111, a capacitor C112, a capacitor C113, a capacitor C115, a capacitor C117, a capacitor C118, a capacitor C119, a capacitor C120, a capacitor C121, a capacitor C122, a capacitor C124, a resistor R37, a resistor R38, a resistor R39, a resistor R40, a resistor R41, a resistor R42, a resistor R44, a resistor R45, an inductor L15, an inductor L16, an inductor L17 and an inductor L18; Pin 1 of chip U9, pin 8 of chip U9, the positive electrode of electrolytic capacitor C90, the positive electrode of electrolytic capacitor C123, one end of capacitor C124, one end of capacitor C122, one end of capacitor C91, and one end of capacitor C92 are all connected to the output end of the DCDC circuit; The negative electrode of the electrolytic capacitor C90, the negative electrode of the electrolytic capacitor C123, the other end of the capacitor C124, the other end of the capacitor C122, the other end of the capacitor C91, and the other end of the capacitor C92 are all connected to GND; Pin 2 of chip U9 is connected to one end of resistor R37 and one end of resistor R38; The other end of resistor R37 is connected to DGND; The other end of resistor R38 is connected to pin 25 of chip U10; Pin 3 of chip U9 is connected to one end of capacitor C100; The other end of the capacitor C100 is connected to one end of the capacitor C104, one end of the resistor R39, and one end of the resistor R41; The other end of the resistor R39 is connected to one end of the capacitor C98; The other end of capacitor C98 is connected to pin 47 of chip U10; The other end of the resistor R41 and the other end of the capacitor C104 are both connected to AGND; Pin 4 of chip U9 is connected to one end of capacitor C102; Pin 5 of chip U9 is connected to one end of capacitor C105; Pin 6 of chip U9 is connected to one end of capacitor C111; The other end of the capacitor C102, the other end of the capacitor C105, and the other end of the capacitor C111 are all connected to GND; Pin 7 of chip U9 is connected to one end of capacitor C117; The other end of the capacitor C117 is connected to one end of the capacitor C119, one end of the resistor R42, and one end of the resistor R44; The other end of the resistor R42 is connected to one end of the capacitor C105; The other end of capacitor C105 is connected to pin 46 of chip U10; The other end of the capacitor C119 and the other end of the resistor R44 are both connected to AGND; Pin 9 of chip U9 is connected to one end of capacitor C120; Pin 10 of chip U9 is connected to the other end of capacitor C120 and one end of inductor L18; The other end of the inductor L18, one end of the resistor R45, one end of the capacitor C121, and one end of the capacitor C188 are all connected to the audio module (400); The other end of the resistor R45 is connected to one end of the capacitor C115; The other end of the capacitor C121 and one end of the capacitor C113 are both connected to GND; Pin 11 of chip U9 is connected to one end of capacitor C112; Pin 12 of chip U9 is connected to the other end of capacitor C112 and one end of inductor L17; The other end of the inductor L17, the other end of the capacitor C113, the other end of the capacitor C115, and the other end of the capacitor C118 are all connected to the audio module (400); Pin 14 of chip U9 is connected to one end of capacitor C101; Pin 13 of chip U9 is connected to the other end of capacitor C101 and one end of inductor L16; The other end of the inductor L18, one end of the resistor R40, one end of the capacitor C99, and one end of the capacitor C97 are all connected to the audio module (400); The other end of the resistor R40 is connected to one end of the capacitor C95; The other end of capacitor C99 and one end of capacitor C96 are both connected to GND; Pin 16 of chip U9 is connected to one end of capacitor C94; Pin 15 of chip U9 is connected to the other end of capacitor C94 and one end of inductor L15; The other end of the inductor L15, the other end of the capacitor C95, the other end of the capacitor C96, and the other end of the capacitor C97 are all connected to the audio module (400).

9. The speaker with video output function according to claim 1, characterized in that: The power module (700) comprises a first power circuit, a second power circuit and a third power circuit; The input end of the first power supply circuit, the input end of the second power supply circuit, and the input end of the third power supply circuit are all used to connect to the first input power supply; The output end of the first power supply circuit is connected to the input end of the third power supply circuit and the input end of the video amplification module (600); The output end of the second power supply circuit is connected to the input end of the video amplification module (600); The output end of the third power supply circuit is connected to the input end of the high-frequency receiving module (500).

10. The speaker with video output function according to claim 1, characterized in that: The input and output module (100) comprises a coaxial input circuit, an optical fiber input circuit, a TYPE-C input circuit, a high-frequency HDMI output circuit, an analog audio signal 3.5 jacket input circuit and an analog audio output circuit; The output end of the coaxial input circuit, the output end of the optical fiber input circuit, the output end of the TYPE-C input circuit, the input end of the analog audio signal 3.5 jacket input circuit, and the output end of the analog audio output circuit are all connected to the decoding processing module (200); The input end of the high-frequency HDMI output circuit is connected to the video amplification module (600).

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