Semiconductor device structure and semiconductor device

Abstract

Various embodiments of the utility model relate to a semiconductor device structure providing a NOT gate logic function, comprising a layer stack which comprises a pair of semiconductor layers with opposite conduction types and a dielectric isolation layer arranged between the semiconductor layers. A first electrode and a second electrode are on a first side of the layer stack, where the first electrode contacts a first side surface of the first semiconductor layer and the second electrode contacts a first side surface of the second semiconductor layer. A third electrode on a second side of the layer stack is in contact with a second side surface of the first semiconductor layer and a second side surface of the second semiconductor layer. A gate dielectric layer is over both side surfaces of the layer stack. A pair of gate electrodes on both sides of the layer stack contacts the gate dielectric layer. A semiconductor device structure may be fabricated using a back-end process using a metal oxide semiconductor material.

Description

Technical Field

[0001] The embodiments of the utility model relate to a semiconductor device structure and a semiconductor device. Background Art

[0002] The semiconductor industry has grown due to continued improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, inductors, capacitors, etc.). In large part, these improvements in integration density have come from repeated reductions in minimum feature size, which has enabled more components to be integrated into a given area. In this regard, individual transistors, interconnects, and related structures have become increasingly smaller, and there is a continuing need to develop new materials, processes, and designs for semiconductor devices and interconnects to enable further advancements.

[0003] Transistors made from oxide semiconductors are an attractive option for back-end-of-line (BEOL) integration because they can be processed at low temperatures and thus may not damage previously fabricated devices. For example, fabrication conditions and techniques may not damage previously fabricated front-end-of-line (FEOL) and middle end-of-line (MEOL) devices. Circuits based on oxide semiconductor-based transistor devices may further include other components that may be fabricated in BEOL processes, such as capacitors, inductors, resistors, and integrated passive devices. Utility Model Content

[0004] One aspect of the utility model provides a semiconductor device structure. The semiconductor device structure includes: a layer stack, a first electrode, a second electrode, a third electrode, a gate dielectric layer, and a pair of gate electrodes. The layer stack includes: a first conductive type semiconductor layer; a dielectric isolation layer located on the first conductive type semiconductor layer; and a second conductive type semiconductor layer located on the dielectric isolation layer. The first electrode is adjacent to the first end of the layer stack and contacts the first side surface of the first conductive type semiconductor layer. The second electrode is adjacent to the first end of the layer stack and contacts the first side surface of the second conductive type semiconductor layer. The third electrode is adjacent to the second end of the layer stack opposite to the first end of the layer stack, and contacts the second side surface of the first conductive type semiconductor layer, the side surface of the dielectric isolation layer, and the second side surface of the second conductive type semiconductor layer. The gate dielectric layer contacts the opposite side surface of the layer stack over at least a portion of the length of the layer stack between the first end and the second end of the layer stack. A pair of gate electrodes contact the gate dielectric layer over at least a portion of the length of the layer stack between the first end and the second end of the layer stack and extend over the opposite side surface of the layer stack.

[0005] Another aspect of the utility model provides a semiconductor device. The semiconductor device includes: a substrate, a plurality of device structures, at least one interconnection level dielectric layer and a NOT gate logic circuit. The substrate includes a semiconductor material layer. A plurality of device structures are formed on or in the semiconductor material layer. At least one interconnection level dielectric layer is located on the substrate and the plurality of device structures and includes a conductive interconnection structure. The NOT gate logic circuit is located on at least one interconnection level dielectric layer. The NOT gate logic circuit includes: a first conductive type semiconductor layer, a second conductive type semiconductor layer, a first electrode, a second electrode, a dielectric isolation layer, a third electrode, a gate dielectric layer and a gate electrode. The first electrode contacts a first side surface of the first conductive type semiconductor layer. The second electrode contacts a first side surface of the second conductive type semiconductor layer. The dielectric isolation layer extends between the first conductive type semiconductor layer and the second conductive type semiconductor layer and between the first electrode and the second electrode. The third electrode contacts a second side surface of the first conductive type semiconductor layer, a second side surface of the second conductive type semiconductor layer and a side surface of the dielectric isolation layer. The gate dielectric layer contacts the first conductive type semiconductor layer and the second conductive type semiconductor layer. The gate electrode contacts the gate dielectric layer.

[0006] Another aspect of the utility model provides a method for manufacturing a semiconductor device structure. The method includes: forming a first conductive type semiconductor layer; forming a first electrode in contact with a first side surface of the first conductive type semiconductor layer; forming a dielectric isolation layer on the first conductive type semiconductor layer and the first electrode; forming a second conductive type semiconductor layer on the dielectric isolation layer; forming a second electrode in contact with the first side surface of the second conductive type semiconductor layer; forming a third electrode in contact with the second side surface of the first conductive type semiconductor layer, the side surface of the dielectric isolation layer, and the second side surface of the second conductive type semiconductor layer; forming a gate dielectric layer on the relative third and fourth side surfaces of the second conductive type semiconductor layer, the relative side surface of the dielectric isolation layer, and the relative third and fourth side surfaces of the first conductive type semiconductor layer; and forming a first gate electrode in contact with the gate dielectric layer on the third side surface of the first conductive type semiconductor layer and the third side surface of the second conductive type semiconductor layer, and forming a second gate electrode in contact with the gate dielectric layer on the fourth side surface of the first conductive type semiconductor layer and the fourth side surface of the second conductive type semiconductor layer.

[0007] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 14 is a vertical cross-sectional view of a first structure before forming a semiconductor device structure providing a NOT gate logic function according to various embodiments of the present invention.

[0009] Figure 2A It is a three-dimensional stereogram of a semiconductor device structure according to various embodiments of the present invention.

[0010] Figure 2B yes Figure 2A Another three-dimensional stereogram of a semiconductor device structure.

[0011] Figure 2C The invention is described in accordance with various embodiments of the present invention. Figure 2A A schematic equivalent circuit diagram illustrating the operation of the semiconductor device structure is shown.

[0012] Figure 2D yes Figure 2A Another three-dimensional perspective view of a semiconductor device structure is shown, illustrating various sizes of components of the semiconductor device structure according to various embodiments of the present invention.

[0013] Figure 3A According to various embodiments of the present invention, Figure 2A and Figure 2B A top view of an intermediate structure during processing of a semiconductor device structure is shown.

[0014] Figure 3B It is along Figure 3A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0015] Figure 4A is a top view of an intermediate structure, which shows a continuous first conductivity type semiconductor layer formed on the first dielectric material layer according to various embodiments of the present invention.

[0016] Figure 4B It is along Figure 4B A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0017] Figure 5A is a top view of an intermediate structure, which shows a patterned mask formed on a continuous first conductivity type semiconductor layer according to various embodiments of the present invention.

[0018] Figure 5B It is along Figure 5A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0019] Fig. 6A is a top view of an intermediate structure showing a discrete first conductivity type semiconductor layer located above a first dielectric material layer according to various embodiments of the present invention.

[0020] Figure 6B It is along Fig. 6A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0021] Fig. 7A is a top view of an intermediate structure, which shows a second dielectric material layer formed on the first dielectric material layer and laterally surrounding the first conductive type semiconductor layer according to various embodiments of the present invention.

[0022] Figure 7B It is along Fig. 7A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0023] Fig. 8A is a top view of an intermediate structure, which shows a patterned mask formed on the second dielectric material layer and the first conductive type semiconductor layer according to various embodiments of the present invention.

[0024] Figure 8B It is along Fig. 8A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0025] Fig.9A is a top view of the intermediate structure, showing an opening formed through the second dielectric material layer and exposing the upper surface of the first dielectric material layer and the upper surface of the via according to various embodiments of the present invention.

[0026] Fig. 9B It is along Fig.9A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0027] Fig. 10A is a top view of an intermediate structure showing a first electrode formed within an opening in a second dielectric material layer according to various embodiments of the present invention.

[0028] Fig. 10B It is along Fig. 10A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0029] Fig.11A is a top view of an intermediate structure, which shows a dielectric isolation layer formed on the first conductive type semiconductor layer, the first electrode and the second dielectric material layer according to various embodiments of the present invention.

[0030] Fig. 11B It is along Fig.11A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0031] Fig. 12Ais a top view of an intermediate structure, which shows a continuous second conductivity type semiconductor layer formed on the dielectric isolation layer according to various embodiments of the present invention.

[0032] Fig. 12B It is along Fig. 12B A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0033] Fig.13A is a top view of an intermediate structure, which shows a patterned mask formed on a continuous second conductivity type semiconductor layer according to various embodiments of the present invention.

[0034] Fig. 13B It is along Fig.13A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0035] Fig.14A is a top view of an intermediate structure showing a discrete second conductivity type semiconductor layer located above a dielectric isolation layer according to various embodiments of the present invention.

[0036] Fig. 14B It is along Fig.14A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0037] Fig.15A is a top view of the intermediate structure, which shows a third dielectric material layer formed on the second dielectric material layer and laterally surrounding the second conductive type semiconductor layer according to various embodiments of the present invention.

[0038] Fig. 15B It is along Fig.15A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0039] Fig.16A is a top view of the intermediate structure, which shows a patterned mask formed on the third dielectric material layer and the second conductivity type semiconductor layer according to various embodiments of the present invention.

[0040] Fig. 16B It is along Fig.16A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0041] Fig.17A is a top view of the intermediate structure showing an opening formed through the third dielectric material layer and exposing the upper surface of the dielectric isolation layer according to various embodiments of the present invention.

[0042] Fig. 17B It is along Fig.17A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0043] Fig.18A is a top view of an intermediate structure showing a second electrode formed within an opening in a third dielectric material layer according to various embodiments of the present invention.

[0044] Fig.18B It is along Fig.18A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0045] Fig.19A is a top view of the intermediate structure, which shows a patterned mask formed on the third dielectric material layer, the second conductivity type semiconductor layer and the second electrode according to various embodiments of the present invention.

[0046] Fig.19B It is along Fig.19A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0047] Fig. 20A is a top view of the intermediate structure, which shows an opening formed through the third dielectric material layer, the dielectric isolation layer, and the second dielectric material layer and exposing the upper surface of the first dielectric material layer according to various embodiments of the present invention.

[0048] Fig. 20B It is along Fig. 20A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0049] Fig.21A is a top view of an intermediate structure showing a third electrode formed within an opening in a third dielectric material layer, a dielectric isolation layer, and a second dielectric material layer according to various embodiments of the present invention.

[0050] Fig. 21B It is along Fig. 21B A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0051] Fig.22A is a top view of the intermediate structure, which shows a patterned mask formed on the third dielectric material layer, the second conductivity type semiconductor layer, the second electrode and the third electrode according to various embodiments of the present invention.

[0052] Fig. 22B It is along Fig.22A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0053] Fig. 22C It is along Fig.22A A vertical cross-sectional view of the intermediate structure taken along line BB' in FIG.

[0054] Fig.23Ais a top view of the intermediate structure, showing a pair of trench openings formed through the third dielectric material layer, the dielectric isolation layer, and the second dielectric material layer and exposing the upper surface of the first dielectric material layer according to various embodiments of the present invention.

[0055] Fig. 23B It is along Fig.23A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0056] Fig.23C It is along Fig.23A A vertical cross-sectional view of an exemplary intermediate structure taken along line BB′ in FIG.

[0057] Fig.24A is a top view of the intermediate structure, showing a gate dielectric layer formed on the third dielectric material layer, the second conductivity type semiconductor layer, the second electrode and the third electrode, and on the sidewalls and bottom surface of the trench opening according to various embodiments of the present invention.

[0058] Fig. 24B It is along Fig.24A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0059] Fig.24C It is along Fig.24A A vertical cross-sectional view of the intermediate structure taken along line BB' in FIG.

[0060] Fig.25A is a top view of an intermediate structure, showing a dielectric filling layer formed over the gate dielectric layer and filling the remaining volume of the trench opening and a patterned mask formed over the dielectric filling layer according to various embodiments of the present invention.

[0061] Fig.25B It is along Fig.25A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0062] Fig.25C It is along Fig.25A A vertical cross-sectional view of the intermediate structure taken along line BB' in FIG.

[0063] Fig.26A is a top view of an intermediate structure showing a pair of trench openings formed through portions of the dielectric fill layer and the gate dielectric layer and exposing an upper surface of the first dielectric layer according to various embodiments of the present invention.

[0064] Fig.26B It is along Fig.26A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0065] Fig.26C It is along Fig.26AA vertical cross-sectional view of the intermediate structure taken along line BB' in FIG.

[0066] Fig.27A is a top view of a semiconductor device structure including a pair of gate electrodes extending on opposite sides of a layer stack according to various embodiments of the present invention.

[0067] Fig.27B It is along Fig.27A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG.

[0068] Fig.27C It is along Fig.27A A vertical cross-sectional view of the intermediate structure taken along line BB' in FIG.

[0069] Fig.27D It is along Fig.27A A vertical cross-sectional view of the intermediate structure taken along line CC' in FIG.

[0070] Fig.27E It is along Fig.27A A vertical cross-sectional view of the intermediate structure taken along line D-D' in FIG.

[0071] Fig.28A It is a top view of a semiconductor device structure according to various embodiments of the present invention, wherein the semiconductor device structure includes a fourth dielectric material layer formed on a gate dielectric layer and a gate electrode, and a plurality of vias located in the fourth dielectric material layer.

[0072] Fig.28B It is along Fig.28A 1 is a vertical cross-sectional view of the semiconductor device structure 100 taken along line AA′ in FIG.

[0073] Fig.28C It is along Fig.28A 8 is a vertical cross-sectional view of the semiconductor device structure 100 taken along line BB′ in FIG.

[0074] Fig.29 is a flow chart illustrating a method for fabricating a semiconductor device structure according to various embodiments of the present invention. DETAILED DESCRIPTION

[0075] The present invention provides many different embodiments or examples for implementing the different features of the provided target. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on a second feature or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not indicate the relationship between the various embodiments and / or configurations discussed by itself.

[0076] Additionally, for ease of description, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one component or feature shown in a figure to another component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Unless expressly stated otherwise, each component having the same reference number is assumed to be of the same material composition and having a thickness within the same thickness range.

[0077] Various embodiments of the present invention provide semiconductor device structures and methods that may be advantageous in terms of manufacturing flexibility, improved integration density, and increased computing power of semiconductor integrated circuit (IC) dies. In this regard, an embodiment semiconductor device structure is provided that may be formed in a BEOL process and may be combined with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices. As such, the disclosed semiconductor device structure may include materials that may be processed at low temperatures and, therefore, may not damage previously fabricated devices (e.g., FEOL devices and MEOL devices).

[0078] In various embodiments, the semiconductor device structure may be configured as a logic NOT gate or inverter circuit such that applying an input signal to a semiconductor device structure having a first logic state will generate an output signal from a semiconductor device structure having a complementary logic state. In this regard, providing a high voltage input signal to the semiconductor device structure may generate a low voltage output signal from the semiconductor device structure, and providing a low voltage input signal to the semiconductor device structure may generate a high voltage output signal from the semiconductor device structure.

[0079] In various embodiments, the semiconductor device structure may include a layer stack, the layer stack including a first conductivity type semiconductor layer, a dielectric isolation layer located on the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer located on the dielectric isolation layer. In various embodiments, the first conductivity type semiconductor layer and / or the second conductivity type semiconductor layer may include a metal oxide semiconductor material. The first electrode and the second electrode may be located on a first side of the layer stack, wherein the first electrode may contact a first side surface of the first conductivity type semiconductor layer, and the second electrode may contact a first side surface of the second conductivity type semiconductor layer. The dielectric isolation layer may extend between the first electrode and the second electrode. The third electrode may be located on a second side of the layer stack opposite to the first side, and may contact a second side surface of the first conductivity type semiconductor layer, a side surface of the dielectric isolation layer, and a second side surface of the second conductivity type semiconductor layer. The gate dielectric layer may surround the layer stack between the first electrode and the second electrode at one end of the layer stack and the third electrode at the other end of the layer stack over at least a portion of the length of the layer stack on both side surfaces and the upper surface of the layer stack. A pair of gate electrodes may be located on both sides of the layer stack, wherein the gate dielectric layer may be located between a first electrode and a second electrode on one end of the layer stack and a third electrode at the other end of the layer stack over at least a portion of the length of the layer stack and between each of the gate electrodes and a corresponding opposite side surface of the layer stack.

[0080] In various embodiments, semiconductor device structures providing NOT gate logic functions may be fabricated using thin film metal oxide semiconductor materials using BEOL processes. Thus, this may enable computing operations to be performed at least partially within one or more interconnect levels of a semiconductor integrated circuit (IC) die, which may enable increased integration density of the semiconductor IC die and / or increased processing power of the semiconductor IC die.

[0081] Figure 11 is a vertical cross-sectional view of a first structure before forming a semiconductor device structure providing a NOT gate logic function according to various embodiments of the present invention. The first structure includes a substrate 8, which may be a semiconductor substrate (e.g., a silicon substrate available on the market). The substrate 8 may include a semiconductor material layer 9 at least at its upper portion. The semiconductor material layer 9 may be a surface portion of a bulk semiconductor substrate, or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 includes a single crystal semiconductor material (e.g., single crystal silicon). In one embodiment, the substrate 8 may include a single crystal silicon substrate including a single crystal silicon material.

[0082] A shallow trench isolation structure 720 including a dielectric material such as silicon oxide may be formed in an upper portion of the semiconductor material layer 9. A suitable doped semiconductor well such as a p-type well and an n-type well may be formed in each region laterally enclosed by a portion of the shallow trench isolation structure 720. A field effect transistor 701 may be formed above the top surface of the semiconductor material layer 9. For example, each field effect transistor 701 may include a source electrode 732, a drain electrode 738, a semiconductor channel 735 including a surface portion of the substrate 8 extending between the source electrode 732 and the drain electrode 738, and a gate structure 750. The semiconductor channel 735 may include a single crystalline semiconductor material. Each gate structure 750 may include a gate dielectric layer 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal semiconductor alloy region 742 may be formed on each source electrode 732, and a drain-side metal semiconductor alloy region 748 may be formed on each drain electrode 738. The devices formed on the top surface of the semiconductor material layer 9 may include complementary metal-oxide-semiconductor (CMOS) transistors and optional additional semiconductor devices (such as resistors, diodes, capacitor structures, etc.), and are collectively referred to as CMOS circuit system 700.

[0083] One or more of the field effect transistors 701 in the CMOS circuit system 700 may include a semiconductor channel 735, which includes a portion of the semiconductor material layer 9 in the substrate 8. If the semiconductor material layer 9 includes a single crystalline semiconductor material such as single crystalline silicon, the semiconductor channel 735 of each field effect transistor 701 in the CMOS circuit system 700 may include a single crystalline semiconductor channel, for example, a single crystalline silicon channel. In one embodiment, a subset of the field effect transistors 701 in the CMOS circuit system 700 may include corresponding nodes, which are then electrically connected to nodes of a subsequently formed non-gate semiconductor device structure.

[0084] In one embodiment, the substrate 8 may include a single crystal silicon substrate, and the field effect transistor 701 may include a corresponding portion of the single crystal silicon substrate as a semiconducting channel. As used herein, a "semiconducting" device refers to a device with a conductivity of 1.0×10 -6 Siemens / cm (S / cm) to 1.0×10 5 Siemens / cm range. As used herein, "semiconductor material" refers to a semiconductor material having an electrical conductivity in the range of 1.0×10 -6 Siemens / cm to 1.0×10 5 Siemens / cm range and can produce conductivity in the range of 1.0 Siemens / cm to 1.0×10 5 Doped materials in the Siemens / cm range.

[0085] Various metal interconnect structures formed in the dielectric material layer may then be formed over the substrate 8 and the semiconductor device 701 thereon (e.g., a field effect transistor). In an illustrative example, the dielectric material layer may include, for example, a first dielectric material layer 601 (sometimes referred to as a contact level dielectric material layer 601), which may be a layer surrounding contact structures connected to the source and drain, a first interconnect level dielectric material layer 610, a second interconnect level dielectric material layer 620, a third interconnect level dielectric material layer 630, and a fourth interconnect level dielectric material layer 640. The metal interconnect structure may include a device contact via structure 612 formed in the first dielectric material layer 601 and contacting corresponding components of the CMOS circuit system 700, a first metal line structure 618 formed in the first interconnect level dielectric material layer 610, a first metal via structure 622 formed in the lower portion of the second interconnect level dielectric material layer 620, a second metal line structure 628 formed in the upper portion of the second interconnect level dielectric material layer 620, a second metal via structure 632 formed in the lower portion of the third interconnect level dielectric material layer 630, a third metal line structure 638 formed in the upper portion of the third interconnect level dielectric material layer 630, a third metal via structure 642 formed in the lower portion of the fourth interconnect level dielectric material layer 640, and a fourth metal line structure 648 formed in the upper portion of the fourth interconnect level dielectric material layer 640. Although the present invention is described using an embodiment in which a metal line structure having four levels is formed in a dielectric material layer, embodiments in which a metal line structure having a fewer number or a greater number of levels is formed in a dielectric material layer are expressly contemplated herein.

[0086] Each of the dielectric material layers (601, 610, 620, 630, 640) may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) may include at least one conductive material, which may be a combination of a metal liner (e.g., a metal nitride or a metal carbide) and a metal filler material. Each metal liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liners and metal filler materials within the scope of the present invention may also be used. In one embodiment, the first metal via structure 622 and the second metal line structure 628 may be formed as an integrated line and via structure by a dual damascene process. In general, any connected set of metal line structures (628, 638, 648) and at least one underlying metal via structure (622, 632, 642) may be formed as an integrated line and via structure.

[0087] Generally speaking, a semiconductor device 701 may be formed on a substrate 8, and metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) and dielectric material layers (601, 610, 620, 630, 640) may be formed on the semiconductor device 701. The metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) may be formed in the dielectric material layers (601, 610, 620, 630, 640) and may be electrically connected to the semiconductor device.

[0088] Refer again Figure 1A first dielectric material layer 102 may be formed on the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) and the dielectric material layers (601, 610, 620, 630, 640). The first dielectric material layer 102 may include a suitable dielectric material, such as silicon oxide, undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Other suitable dielectric materials are also within the scope of the present invention. The first dielectric material layer 102 may be deposited using any suitable deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metalorganic CVD (MOCVD), plasma enhanced CVD (PECVD), sputtering, laser ablation, or the like). In some embodiments, one or more of the above-mentioned metal interconnect structures (e.g., integrated line and via structures) may be formed in the first dielectric material layer 102, and the one or more of the above-mentioned metal interconnect structures may be coupled to the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) in the underlying dielectric material layer (601, 610, 620, 630, 640). The first dielectric material layer 102 may include a planar upper surface 122 .

[0089] Figure 2A is a three-dimensional diagram of the semiconductor device structure 100, and Figure 2B According to various embodiments, Figure 2A Another three-dimensional perspective view of the semiconductor device structure 100 is shown in which the semiconductor device structure 100 has been rotated. Figure 2C The invention is to describe the invention according to various embodiments Figure 2A and Figure 2B A schematic equivalent circuit diagram 100c is shown for illustrating the operation of the semiconductor device structure 100. Figure 2A and Figure 2B The semiconductor device structure 100 shown may be formed by a BEOL process. In some embodiments, the semiconductor device structure 100 may be formed on a dielectric material layer (eg, as described above with reference to FIG. Figure 1 The semiconductor device structure 100 may be embedded in an insulating matrix, which may include one or more dielectric material layers (for clarity, the dielectric material layers 102 are shown in FIG. 1 ). Figure 2A and Figure 2B not shown).

[0090] Reference Figure 2A and Figure 2B , the semiconductor device structure 100 may include a first end 101 and a second end 104 opposite to the first end 101 along a first horizontal direction hd1. A first electrode 113 and a second electrode 115 may be located at the first end 101 of the semiconductor device structure 100. The second electrode 115 may be located above the first electrode 113 in a vertical direction. A dielectric material layer 111 (also referred to as a dielectric isolation layer 111) may be located between the first electrode 113 and the second electrode 115. A third electrode 117 may be located at the second end 104 of the semiconductor device structure 100.

[0091] The layer stack 170 may extend along a first horizontal direction hd1 between a first electrode 113 and a second electrode 115 on one end (e.g., 101) of the layer stack 170 and a third electrode 117 on an opposite end (e.g., 104) of the layer stack 170. The layer stack 170 may include a first conductivity type semiconductor layer 107, a dielectric isolation layer 111 located on the first conductivity type semiconductor layer 107, and a second conductivity type semiconductor layer 109 located on the dielectric isolation layer 111. For example, when the first conductivity type semiconductor layer 107 may be p-type, the second conductivity type semiconductor layer 109 may be n-type, and vice versa. In a non-limiting embodiment, the first conductivity type semiconductor layer 107 may be composed of a p-type semiconductor material, and the second conductivity type semiconductor layer 109 may be composed of an n-type semiconductor material. In some embodiments, the first conductivity type semiconductor layer 107 and the second conductivity type semiconductor layer 109 may be composed of an oxide semiconductor material (as described in further detail below).

[0092] The layer stack 170 may include a gate dielectric layer 103, which may surround the layer stack 170 over at least a portion of the layer stack 170, over both side surfaces and an upper surface of the layer stack 170, between a third electrode 117 on one end (e.g., 104) of the layer stack 170 and a first electrode 113 and a second electrode 115 on the other end (e.g., 101) of the layer stack 170. In other words, the gate dielectric layer 103 may extend over and contact an upper surface and two opposite side surfaces of the second conductive type semiconductor layer 109, two opposite side surfaces of the dielectric isolation layer 111, and two opposite side surfaces of the first conductive type semiconductor layer 107. In some embodiments, the gate dielectric layer 103 may also contact a bottom surface of the first conductive type semiconductor layer 107. A pair of gate electrodes 105a and 105b may be located on both sides of the layer stack 170, wherein the gate dielectric layer 103 may be located between each of the gate electrodes 105a and 105b and respective opposing side surfaces of the layer stack 170 over at least a portion of the length of the layer stack 170. Figure 2A and Figure 2B The gate dielectric layer 103 and gate electrodes 105a and 105b are shown extending along a portion of the length of the layer stack 170, but it should be understood that in other embodiments, the gate dielectric layer 103 and gate electrodes 105a and 105b may extend over the entire or substantially the entire length of the layer stack 170.

[0093] A first end of the first conductive type semiconductor layer 107 may contact a side surface of the first electrode 113, and a second end of the first conductive type semiconductor layer 107 may contact a side surface of the third electrode 117. A first end of the second conductive type semiconductor layer 109 may contact a side surface of the second electrode 115, and a second end of the second conductive type semiconductor layer 109 may contact a side surface of the third electrode 117. Figure 2B and Figure 2C As shown schematically, the first electrode 113 can be electrically connected to a voltage source (e.g., can be maintained at a source voltage VDD). The second electrode 115 can be electrically connected to a ground voltage terminal (e.g., can be maintained at a ground (GND) voltage). The pair of gate electrodes 105a and 105b can be electrically connected to a shared input voltage terminal (e.g., V in The third electrode 117 may be electrically connected to an output signal terminal (eg, V out ).

[0094] like Figure 2A and Figure 2BThe semiconductor device structure 100 shown can be configured as a NOT gate circuit (also called an inverter circuit). A NOT gate circuit is a logic gate circuit that inverts a given input signal (i.e., outputs a complementary logic state). For example, when the input terminal (V in ) provides a low voltage signal (e.g., representing a logic state "0" or "1"), the output signal terminal (V out ) outputs a high voltage signal (e.g., representing the complementary logic state of the input signal, such that when the input low voltage signal represents the logic state "0", the output high voltage signal represents the logic state "1", and vice versa). Similarly, when the input terminal (V in ) provides a high voltage signal at the output signal terminal (V out ) outputs a low voltage signal.

[0095] Figure 2C It is described as Figure 2A and Figure 2B Schematic equivalent circuit diagram 100c of the operation of the semiconductor device structure 100 is shown. Specifically, the first conductive type semiconductor layer 107 can be configured as a channel layer of the first transistor 201, and the first transistor 201 can be a p-channel metal oxide semiconductor field effect transistor (MOSFET). Therefore, the first transistor 201 may include the first conductive type semiconductor layer 107 (which can serve as a p-channel layer), the first electrode 113 (which can serve as a source electrode), the third electrode 117 (which can serve as a drain electrode), the gate dielectric layer 103, and the pair of gate electrodes 105a and 105b located on both sides of the p-channel layer 107. Similarly, the second conductive type semiconductor layer 109 can be configured as a channel layer of the second transistor 203, and the second transistor 203 can be an n-channel metal oxide semiconductor field effect transistor (MOSFET). Therefore, the second transistor 203 may include a second conductivity type semiconductor layer 109 (which may serve as an n-channel layer), a second electrode 115 (which may serve as a source electrode), a third electrode 117 (which may serve as a drain electrode), a gate dielectric layer 103, and the pair of gate electrodes 105a and 105b located on both sides of the n-channel layer 109. It should be understood that the source / drain electrodes 113, 115, and 117 may refer to source electrodes or drain electrodes individually or collectively, depending on the context.

[0096] Refer again Figure 2C , placed at the input signal terminal V inThe low voltage on turns on the first transistor 201 and turns off the second transistor 203. Since the source of the first transistor 201 (ie, the first electrode 113) is connected to a voltage source (VDD) having a high voltage, the output voltage V out (ie, the voltage at the third electrode 117) will have a high voltage. Similarly, the voltage at the input signal terminal V in The high voltage on the second transistor 203 turns on the second transistor 203 and turns off the first transistor 201. Since the source of the second transistor 203 (ie, the second electrode 115) is connected to the ground voltage terminal, the output voltage V out (ie, the voltage at the third electrode 117) will have a low voltage. In this way, a high input signal is converted into a low output signal, and a low input signal is converted into a high input signal. Thus, the semiconductor device structure 100 is configured as a NOT gate or an inverter circuit.

[0097] In some embodiments, Figure 2A and Figure 2B The semiconductor device structure 100 may be formed on an interconnect level dielectric layer having a flat horizontal surface. For example, a first dielectric material layer 102 (eg, see Figure 1 ) Figure 1 The semiconductor device structure 100 is formed on any of the layers 601, 610, 620, 630 and 640 in the embodiment of the present invention, or on one or more additional interconnect level dielectric layers formed on the first dielectric material layer 102. Figure 2A and Figure 2B As shown, the layer stack 170 including the first conductivity type semiconductor layer 107, the dielectric isolation layer 111 and the second conductivity type semiconductor layer 109 can have a horizontal orientation, so that the interface surface of the first conductivity type semiconductor layer 107, the interface surface of the dielectric isolation layer 111 and the interface surface of the second conductivity type semiconductor layer 109 can be substantially parallel to the flat horizontal surface of the interconnect level dielectric layer (for example, see the first dielectric material layer 102 having a horizontal upper surface 122). Figure 1 ). However, it should be understood that other orientations of the semiconductor device structure 100 are also within the scope of the present invention. For example, the semiconductor device structure 100 can be oriented so that the interface surfaces of the gate electrodes 105a, 105b, the interface surface of the gate dielectric layer 103, and the interface surfaces of the corresponding opposite side surfaces of the layer stack 170 can be substantially parallel to the flat horizontal surface of the interconnect level dielectric layer.

[0098] As described above, the interconnect level dielectric layer on which the semiconductor device structure 100 is formed may include one or more electrical interconnect structures. In this regard, one or more of the first electrode 113, the second electrode 115, the third electrode 117, and the gate electrodes 105a and 105b may be electrically connected to the one or more electrical interconnect structures (e.g., 612, 618, 622, 628, 632, 638, 642, 648) formed in one or more dielectric material layers (601, 610, 620, 630, 640) located below the semiconductor device structure 100. In other embodiments, one or more of the first electrode 113, the second electrode 115, the third electrode 117, and the gate electrodes 105a and 105b may be electrically connected to one or more electrical interconnect structures that will be subsequently formed on the semiconductor device structure 100.

[0099] In one or more embodiments, one or both of the first conductive type semiconductor layer 107 and the second conductive type semiconductor layer 109 may include a metal oxide semiconductor. For example, suitable metal oxide semiconductor materials for the p-type semiconductor layer 107 or 109 may include one or more of NiO, SnO and Cu2O. Other suitable p-type semiconductor materials are also within the scope of the present invention. Suitable metal oxide semiconductor materials for the n-type semiconductor layer 109 or 107 may include one or more of the following: InZnO (IZO), InSnO (indium tin oxide (ITO)), In2O3, Ga2O3, InGaZnO (IGZO), Al2O5Zn2, ZnO, InGaO, InWO, ZnO, TiO x , aluminum-doped zinc oxide (AZO), including various combinations and alloys thereof. Other suitable n-type semiconductor materials (e.g., amorphous silicon, III-V materials, and similar materials, including combinations (e.g., stacked layers) and / or alloys thereof) may also be utilized. In some embodiments, the n-type semiconductor layer 109 or 107 may have a structure composed of In x Ga y Zn z MO, wherein 0<x<1; 0≤y≤1; 0≤z≤1; and M is one of Ti, Al, Ag, Ce and Sn. In other embodiments, the n-type semiconductor layer 109 may include an alloy of oxygen, a group III element and a group V element. In other embodiments, one or more of the n-type semiconductor layer 109 or 107 and the p-type semiconductor layer 107 or 109 may be formed of a metal oxide semiconductor having a multilayer structure.

[0100] In some embodiments, the dielectric isolation layer 111 may include AlO x 、SiO2、SiN xOr one or more of other interconnect level dielectric materials, as described above. The gate dielectric layer 103 may include one or more of silicon oxide, aluminum oxide, hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, hafnium dioxide-alumina, etc. In some embodiments, the gate dielectric layer 103 may include a high-k dielectric material. Other suitable materials for the dielectric isolation layer 111 and / or the gate dielectric layer 103 are also within the scope of the present invention.

[0101] As described in more detail below, one or more of the first electrode 113, the second electrode 115, the third electrode 117, and the gate electrodes 105a and 105b may include one or more of TiN, W, WN, WCN, Co, PdCo, ​​Mo, Cu, TaN, Ti, Al, etc. Other suitable conductor materials may also be within the scope of the present invention.

[0102] Figure 2D is a diagram showing various embodiments Figure 2A and Figure 2B Another three-dimensional perspective view of various sizes of components of the semiconductor device structure 100 is shown. As described above, the first conductivity type semiconductor layer 107 can be configured as a p-channel layer of the first transistor 201, and the second conductivity type semiconductor layer 109 can be configured as an n-channel layer of the second transistor 203 (see, for example, Figure 2C Thus, when the corresponding transistors (201, 203) are enabled, the current can be Figure 2D 220a, 220b. In this regard, when the first transistor 201 is enabled (e.g., by applying a low bias or zero bias to the gate electrodes 105a and 105b), positive charge carriers (i.e., "holes") may flow from the first electrode 113 to the third electrode 117, generating a first current 220a. Similarly, when the second transistor 203 is enabled (e.g., by applying a high bias to the gate electrodes 105a and 105b), negative charge carriers (i.e., electrons) may flow from the third electrode 117 to the second electrode 115, but since the current carried by the negative charges is opposite to their movement, the movement of charges in the n-channel 109 generates a second current 220b in the same direction as the first current 220a flowing in the p-channel 107.

[0103] Each of the p-type semiconductor layer 107 and the n-type semiconductor layer 109 may have a corresponding channel length 222 (i.e., along a first horizontal direction hd1) and a corresponding channel width 224 (i.e., along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1). In various embodiments, the channel length 222 may have a value greater than 15 nanometers. An increased value of the channel length 222 may mitigate short channel effects. However, increasing the channel length 222 may result in a reduction in drive current and an increase in the size of the semiconductor device structure 100. Therefore, the channel length 222 may be optimized to determine a sufficiently large value to avoid the short channel effect while also keeping the size of the semiconductor device structure 100 as small as possible. According to various embodiments, the channel width 224 may have a value greater than 5 nanometers and less than 500 nanometers.

[0104] Each of the first electrode 113, the second electrode 115, and the third electrode 117 can have a width along the second horizontal direction hd2 that is approximately equal to the channel width 224. Each of the first electrode 113, the second electrode 115, and the third electrode 117 can also have a length dimension 226 (along hd1) that is greater than 5 nanometers. The first electrode 113 and the second electrode 115 can have thickness dimensions 228 and 229 (along the vertical direction) that are between about 2 nanometers and about 50 nanometers. Figure 2D As shown, the thickness dimension 231 of the third electrode 117 may be greater than the combined thickness dimensions 228 and 229 of the first electrode 113 and the second electrode 115. The thickness dimension 231 of the third electrode 117 may be approximately equal to the total thickness of the layer stack 170 including the first conductivity type semiconductor layer 107, the dielectric isolation layer 111, and the second conductivity type semiconductor layer 109. The dielectric isolation layer 111 may have a thickness 230 greater than 5 nanometers and less than 500 nanometers. In some embodiments, the gate electrodes 105a and 105b may each have a gate length 232 that may be comparable to the channel length 222. For example, in some embodiments, the gate length 232 may be greater than about 10 nanometers. The gate electrodes 105a and 105b may each have a gate width 234 of at least about 10 nanometers. The gate dielectric layer may have a thickness 238 greater than about 2 nanometers and less than about 20 nanometers. The first conductivity type semiconductor layer 107 may have a thickness 240 between about 2 nanometers and about 50 nanometers. The second conductivity type semiconductor layer 109 may have a thickness 241 between about 2 nanometers and about 50 nanometers. In some embodiments, the thickness 240 of the first conductivity type semiconductor layer 107 may be approximately equal to the thickness 228 of the first electrode 113, and the thickness 241 of the second conductivity type semiconductor layer 109 may be approximately equal to the thickness 229 of the second electrode 115.

[0105] Figure 3AAccording to various embodiments of the present invention, Figure 2A and Figure 2B A top view of an intermediate structure of the semiconductor device structure 100 during processing is shown. Figure 3B It is along Figure 3A A vertical cross-sectional view of an exemplary intermediate structure taken along line AA' in FIG. Figure 3A and Figure 3B , an exemplary intermediate structure may include a first dielectric material layer 102 having a flat upper surface 122. The first dielectric material layer 102 may be as described above with reference to Figure 1 Therefore, the first dielectric material layer 102 can be formed on the substrate 8 including the semiconductor material layer 9, the semiconductor device 701, the metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648) and the dielectric material layer (601, 610, 620, 630, 640), as described above with reference to Figure 1 described.

[0106] The first dielectric material layer 102 may be composed of a suitable dielectric material, such as undoped silicate glass, doped silicate glass (e.g., deposited by decomposing tetraethylorthosilicate (TEOS)), organic silicate glass, silicon oxynitride, or silicon carbide nitride. Other suitable dielectric materials are also within the scope of the present invention. The first dielectric material layer 102 may be deposited by a conformal deposition process (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), etc.) or by a self-planarizing deposition process (e.g., spin coating). The thickness of the first dielectric material layer 102 may be in the range of approximately 15 nanometers to approximately 60 nanometers (e.g., approximately 20 nanometers to approximately 40 nanometers), although smaller and larger thicknesses may also be used.

[0107] Refer again Figure 3A and Figure 3B Metal interconnect features (such as metal lines 120 and vias 121 structures) may be formed within the first dielectric material layer 102 (e.g., via a single damascene process or a dual damascene process). The upper surface 123 of each of the vias 121 may be coplanar with the upper surface 122 of the first dielectric material layer 102.

[0108] Figure 4A is a top view of an intermediate structure, which shows a continuous first conductivity type semiconductor layer 107L formed on the first dielectric material layer 102 according to various embodiments of the present invention. Figure 4BIt is along Figure 4B A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Figure 4A and Figure 4B , a continuous first conductive type semiconductor layer 107L may be deposited on the upper surface 122 of the first dielectric material layer 102 and the upper surface 123 of each of the vias 121 via a suitable deposition process (e.g., ALD, CVD, PECVD, PVD, etc.). The thickness of the continuous first conductive type semiconductor layer 107L may be in the range of approximately 2 nanometers to approximately 50 nanometers, although other embodiments may include smaller and larger thicknesses. The continuous first conductive type semiconductor layer 107L may be composed of a suitable semiconductor material (e.g., a metal oxide semiconductor material). In some embodiments, the continuous first conductive type semiconductor layer 107L may be a p-type semiconductor material, including but not limited to one or more of NiO, SnO, and Cu2O. Other suitable p-type semiconductor materials are also within the scope of the present invention. In some embodiments, after the continuous first conductive type semiconductor layer 107L is deposited, the intermediate structure may be optionally annealed. The optional annealing process may be performed using a rapid thermal annealing or a furnace annealing process at a temperature ranging from 200° C. to 400° C. The annealing may be performed in an environment of nitrogen, oxygen, or a mixture thereof.

[0109] Figure 5A is a top view of an intermediate structure, which shows a patterned mask 125 formed on the continuous first conductivity type semiconductor layer 107L according to various embodiments of the present invention. Figure 5B It is along Figure 5A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Figure 5A and Figure 5B The patterned mask 125 can be formed by depositing a layer of photoresist material on the upper surface 124 of the continuous first conductive type semiconductor layer 107L, and patterning the photoresist material using a photolithography technique to form a patterned mask 125 as shown in FIG. Figure 5A and Figure 5B The patterned photoresist mask 125 shown in FIG. 1 may include a stripe portion having a length of at least about 15 nanometers along the first horizontal direction hd1 and a width of at least about 5 nanometers along the second horizontal direction hd2. The patterned mask 125 may then be used as a mask to pattern the continuous first conductive type semiconductor layer 107L, as described below with reference to FIG. Fig. 6A and Figure 6B More details.

[0110] Fig. 6Ais a top view of an intermediate structure showing a discrete first conductivity type semiconductor layer 107 located above the first dielectric material layer 102 according to various embodiments of the present invention. Figure 6B It is along Fig. 6A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig. 6A and Figure 6B , an anisotropic etching process may be performed to remove portions of the continuous first conductive type semiconductor layer 107L that are not masked by the patterned mask 125. The patterned mask 125 may then be removed by ashing or by dissolving with a solvent. The remaining portion of the continuous first conductive type semiconductor layer 107L may include a discrete first conductive type semiconductor layer 107 located above the upper surface 122 of the first dielectric material layer 102. In some embodiments, the first conductive type semiconductor layer 107 may have a length of at least about 15 nanometers along the first horizontal direction hd1 and a width of at least about 5 nanometers along the second horizontal direction hd2.

[0111] Fig. 7A is a top view of an intermediate structure, which shows a second dielectric material layer 126 formed on the first dielectric material layer 102 and laterally surrounding the first conductive type semiconductor layer 107 according to various embodiments of the present invention. Figure 7B It is along Fig. 7A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig. 7A and Figure 7B , a second dielectric material layer 126 may be deposited on the upper surface 122 of the first dielectric material layer 102, the upper surface 123 of the via 121, and the upper surface 110 and side surface of the first conductive type semiconductor layer 107 via a suitable deposition method (e.g., CVD, ALD, PVD, PECVD, spin coating, etc.). The second dielectric material layer 126 may be composed of a suitable dielectric material as described above (e.g., undoped silicate glass, doped silicate glass, organic silicate glass, silicon oxynitride, silicon carbide nitride, etc.). An optional planarization process (e.g., a chemical mechanical planarization (CMP) process) may be performed to remove excess portions of the second dielectric material layer 126 from the upper surface 110 of the first conductive type semiconductor layer 107 and provide a flat upper surface 127 of the second dielectric material layer 126. Fig. 7A and Figure 7B In the embodiment of the present invention, the planar upper surface 127 of the second dielectric material layer 126 is substantially coplanar with the upper surface 110 of the first conductive type semiconductor layer 107. In other embodiments, the planar upper surface 127 of the second dielectric material layer 126 may extend above the upper surface 110 of the first conductive type semiconductor layer 107.

[0112] Fig. 8A is a top view of the intermediate structure, which shows a patterned mask 128 formed on the second dielectric material layer 126 and the first conductive type semiconductor layer 107 according to various embodiments of the present invention. Figure 8B It is along Fig. 8A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig. 8A and Figure 8B The patterned mask 128 can be formed by depositing a layer of photoresist material on the upper surface 127 of the second dielectric material layer 126 and the upper surface 110 of the first conductive type semiconductor layer 107, and patterning the photoresist material using photolithography technology to form a patterned mask 128 as shown in FIG. Fig. 8A and Figure 8B The patterned photoresist mask 128 is shown. The patterned mask 128 may include a stripe-shaped opening 129 passing through the patterned mask 128, wherein a portion of the second dielectric material layer 126 may be exposed at the bottom of the opening 129 in the patterned mask 128. In some embodiments, the opening 129 may have a dimension of at least about 5 nanometers along the second horizontal direction hd2, and may be substantially equal to the width dimension of the first conductive type semiconductor layer 107 along the second horizontal direction hd2. The opening 129 may have a dimension of at least about 5 nanometers along the first horizontal direction hd1.

[0113] Fig.9A 1 is a top view of the intermediate structure, showing the opening 130 formed through the second dielectric material layer 126 and exposing the upper surface 122 of the first dielectric material layer 102 and the upper surface 123 of the via 121 according to various embodiments of the present invention. Fig. 9B It is along Fig.9A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig.9A and Fig. 9B , an anisotropic etching process may be performed to remove portions of the second dielectric material layer 126 that are not masked by the patterned mask 128 and form an opening 130 extending through the second dielectric material layer 126. The patterned mask 128 may then be removed by ashing or by dissolving with a solvent. After the etching process, the upper surface 122 of the first dielectric material layer 102 and the upper surface 123 of the via 121 may be exposed at the bottom of the opening 130. The side surface 133 of the first conductive type semiconductor layer 107 may be exposed along one side of the opening 130. In some embodiments, the opening 130 in the second dielectric material layer 126 may have a dimension of at least about 5 nanometers along the second horizontal direction hd2, and may be substantially equal to the width dimension of the first conductive type semiconductor layer 107 along the second horizontal direction hd2. The opening 130 may have a dimension of at least about 5 nanometers along the first horizontal direction hd1.

[0114] Fig. 10A is a top view of an intermediate structure showing a first electrode 113 formed within an opening 130 in a second dielectric material layer 126 according to various embodiments of the present invention. Fig. 10B It is along Fig. 10A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig. 10A and Fig. 10B , a conductive material may be deposited in the opening 130 in the second dielectric material layer 126 and on the upper surface 110 of the first conductive type semiconductor layer 107 and the upper surface 127 of the second dielectric material layer 126. In some embodiments, the conductive material may include a metal liner material and a metal filling material. The metal liner material may include a conductive metal nitride or a conductive metal carbide, such as Ti, Al, TiN, TiN / W, Ti / Al / Ti, TaN, W, Cu, WN, WCN, PdCo, ​​TiC, TaC and / or WC. The metal filling material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, TiN, TaN, alloys thereof and / or combinations thereof. Other suitable metal liner materials and metal filling materials within the scope covered by the utility model may also be used. The conductive material may be formed by a suitable deposition process, which may include one or more of a CVD process, a PVD process, an ALD process, an electroplating process, etc. Other suitable deposition processes are also within the scope covered by the utility model. Excess portions of the conductive material may be removed from above a horizontal plane including the upper surface 110 of the first conductive type semiconductor layer 107 and the upper surface 127 of the second dielectric material layer 126 by a planarization process such as CMP, although other suitable planarization processes may be used. The remaining portion of the conductive material may form a first electrode 113. The first electrode 113 may contact the via 121 on the bottom surface of the first electrode 113, and may contact the side surface 133 of the first conductive type semiconductor layer 107 on the side surface 133 of the first electrode 113. The width dimension of the first electrode 113 along the second horizontal direction hd2 may be substantially equal to the corresponding width dimension of the first conductive type semiconductor layer 107. The height dimension of the first electrode 113 (along the vertical direction) may be substantially equal to the corresponding thickness dimension of the first conductive type semiconductor layer 107 (i.e., the upper surface 131 of the first electrode 113 may be substantially coplanar with the upper surface 110 of the first conductive type semiconductor layer 107). In various embodiments, the length dimension of the first electrode 113 along the first horizontal direction hd1 may be at least about 5 nanometers.

[0115] Fig.11A is a top view of the intermediate structure, which shows the dielectric isolation layer 111 formed on the first conductive type semiconductor layer 107 , the first electrode 113 , and the second dielectric material layer 126 according to various embodiments of the present invention. Fig. 11B It is along Fig.11AA vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig.11A and Fig. 11B , a dielectric isolation layer 111 may be formed on the upper surface 110 of the first conductive type semiconductor layer 107, the upper surface 131 of the first electrode 113, and the upper surface 127 of the second dielectric material layer 126. The dielectric isolation layer 111 may include, but is not limited to, aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, hafnium dioxide-alumina, or various other insulating structures (e.g., a multilayer stack structure including alternating insulating layers). The dielectric isolation layer may be deposited by a suitable deposition process as described above (e.g., CVD, ALD, PVD, PECVD, spin coating, etc.). In some embodiments, the thickness of the dielectric isolation layer 111 may be at least about 5 nanometers (e.g., between about 5 nanometers and about 500 nanometers), although greater and lesser thicknesses may also be utilized.

[0116] Fig. 12A is a top view of an exemplary structure showing a continuous second conductivity type semiconductor layer 109L formed on a dielectric isolation layer 111 according to various embodiments of the present invention. Fig. 12B It is along Fig. 12B A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig. 12A and Fig. 12B A continuous second conductivity type semiconductor layer 109L may be deposited on the upper surface 132 of the dielectric isolation layer 111 via a suitable deposition process (e.g., ALD, CVD, PECVD, PVD, etc.). The thickness of the continuous second conductivity type semiconductor layer 109L may be in the range of approximately 2 nanometers to approximately 50 nanometers, although other embodiments may include smaller and larger thicknesses. The continuous second conductivity type semiconductor layer 109L may be composed of a suitable semiconductor material (e.g., a metal oxide semiconductor material).

[0117] In some embodiments, the continuous second conductive type semiconductor layer 109L may be an n-type semiconductor material, including but not limited to InZnO (IZO), InSnO (indium tin oxide (ITO)), In2O3, Ga2O3, InGaZnO (IGZO), Al2O5Zn2, ZnO, InGaO, InWO, ZnO, TiO x , aluminum-doped zinc oxide (AZO) (including various combinations and alloys thereof). Other suitable n-type semiconductor materials (such as amorphous silicon, III-V materials, and similar materials, including combinations (e.g., stacked layers) and / or alloys thereof) may also be used. In some embodiments, the continuous second conductivity type semiconductor layer 109L may have a thickness of In. x Gay Zn z The composition given by MO, wherein 0<x<1; 0≤y≤1; 0≤z≤1; and M is one of Ti, Al, Ag, Ce and Sn. In other embodiments, the continuous second conductivity type semiconductor layer 109L may include an alloy of oxygen, group III elements and group V elements. After depositing the continuous second conductivity type semiconductor layer 109L, the exemplary intermediate structure may be optionally annealed. The optional annealing process may be performed at a temperature in the range of 200°C to 400°C using a rapid thermal annealing or furnace annealing process. Annealing may be performed in an environment of nitrogen, oxygen or a mixture thereof.

[0118] The continuous second conductive type semiconductor layer 109L may have a conductive type opposite to the first conductive type semiconductor layer 107 described above. Therefore, in an embodiment where the first conductive type semiconductor layer 107 is composed of a p-type semiconductor material, the continuous second conductive type semiconductor layer 109L may be composed of an n-type semiconductor material. Alternatively, the first conductive type semiconductor layer 107 may be composed of an n-type semiconductor material as described above, in which case the continuous second conductive type semiconductor layer 109L may be composed of an n-type semiconductor material as described above. Figure 4A and Figure 4B The suitable p-type semiconductor material is described.

[0119] Fig.13A is a top view of an intermediate structure, which shows a patterned mask 135 formed on the continuous second conductivity type semiconductor layer 109L according to various embodiments of the present invention. Fig. 13B It is along Fig.13A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig.13A and Fig. 13B The patterned mask 135 can be formed by depositing a layer of photoresist material on the upper surface 134 of the continuous second conductive type semiconductor layer 109L, and patterning the photoresist material using a photolithography technique to form a patterned mask 135 as shown in FIG. Fig.13A and Fig. 13B The patterned photoresist mask 135 shown. In some embodiments, the patterned mask 135 may include stripe portions having a length of at least about 15 nanometers along the first horizontal direction hd1 and a width of at least about 5 nanometers along the second horizontal direction hd2. In some embodiments, the patterned mask 135 may have substantially the same length and width dimensions as the underlying first conductive type semiconductor layer 107 and may be vertically aligned above the first conductive type semiconductor layer 107. The patterned mask 135 may then be used as a mask to pattern the continuous second conductive type semiconductor layer 109L, as described below with reference to Fig.14A and Fig. 14B More details.

[0120] Fig.14A is a top view of the intermediate structure, which shows a discrete second conductivity type semiconductor layer 109 located on the dielectric isolation layer 111 according to various embodiments of the present invention. Fig. 14B It is along Fig.14A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig.14A and Fig. 14B , an anisotropic etching process may be performed to remove portions of the continuous second conductivity type semiconductor layer 109L that are not masked by the patterned mask 135. The patterned mask 135 may then be removed by ashing or by dissolving with a solvent. The remaining portion of the continuous second conductivity type semiconductor layer 109L may include a discrete second conductivity type semiconductor layer 109 located above the upper surface 132 of the dielectric isolation layer 111. In some embodiments, the second conductivity type semiconductor layer 109 may have a length of at least about 15 nanometers along the first horizontal direction hd1 and a width of at least about 5 nanometers along the second horizontal direction hd2. In some embodiments, the second conductivity type semiconductor layer 109 may have substantially the same length and width dimensions as the underlying first conductivity type semiconductor layer 107, and may be vertically aligned above the first conductivity type semiconductor layer 107. In this regard, the side surface of the second conductivity type semiconductor layer 109 may be substantially aligned with the corresponding side surface of the underlying first conductivity type semiconductor layer 107.

[0121] Fig.15A is a top view of the intermediate structure, which shows the third dielectric material layer 136 formed on the second dielectric material layer 126 and laterally surrounding the second conductive type semiconductor layer 109 according to various embodiments of the present invention. Fig. 15B It is along Fig.15A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig.15A and Fig. 15B , a third dielectric material layer 136 may be deposited on the upper surface 127 of the second dielectric material layer 126 and the upper surface 134 and side surfaces of the second conductive type semiconductor layer 109 via a suitable deposition method (e.g., CVD, ALD, PVD, PECVD, spin coating, etc.). The third dielectric material layer 136 may be composed of a suitable dielectric material as described above (e.g., undoped silicate glass, doped silicate glass, organic silicate glass, silicon oxynitride, silicon carbide nitride, etc.). An optional planarization process (e.g., a chemical mechanical planarization (CMP) process) may be performed to remove excess portions of the third dielectric material layer 136 from above the upper surface 134 of the second conductive type semiconductor layer 109 and provide a planar upper surface 137 of the third dielectric material layer 136. Fig.15A and Fig. 15BIn the embodiment of the present invention, the planar upper surface 137 of the third dielectric material layer 136 is substantially coplanar with the upper surface 134 of the second conductive type semiconductor layer 109. In other embodiments, the planar upper surface 137 of the third dielectric material layer 136 may extend above the upper surface 134 of the second conductive type semiconductor layer 109.

[0122] Fig.16A 1 is a top view of the intermediate structure, which shows a patterned mask 138 formed on the third dielectric material layer 136 and the second conductivity type semiconductor layer 109 according to various embodiments of the present invention. Fig. 16B It is along Fig.16A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig.16A and Fig. 16B The patterned mask 138 can be formed by depositing a layer of photoresist material on the upper surface 137 of the third dielectric material layer 136 and the upper surface 134 of the second conductive type semiconductor layer 109, and patterning the photoresist material using photolithography technology to form a Fig.16A and Fig. 16B The patterned photoresist mask 138 shown. The patterned mask 138 may include a stripe-shaped opening 139 passing through the patterned mask 138, wherein a portion of the third dielectric material layer 136 may be exposed at the bottom of the opening 139 in the patterned mask 138. In some embodiments, the opening 139 may have a dimension of at least about 5 nanometers along the second horizontal direction hd2, and may be substantially equal to the width dimension of the second conductive type semiconductor layer 109 along the second horizontal direction hd2. The opening 139 may have a dimension of at least about 5 nanometers along the first horizontal direction hd1. In some embodiments, the dimensions of the opening 139 along the first horizontal direction hd1 and the second horizontal direction hd2 may be substantially the same as the corresponding dimensions of the underlying first electrode 113, and the opening 139 may be vertically aligned above the first electrode 113.

[0123] Fig.17A 1 is a top view of the intermediate structure, showing the opening 140 formed through the third dielectric material layer 136 and exposing the upper surface 132 of the dielectric isolation layer 111 according to various embodiments of the present invention. Fig. 17B It is along Fig.17A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig.17A and Fig. 17B, an anisotropic etching process may be performed to remove portions of the third dielectric material layer 136 that are not masked by the patterned mask 138 and form an opening 140 extending through the third dielectric material layer 136. The patterned mask 138 may then be removed by ashing or by dissolving with a solvent. After the etching process, the upper surface 132 of the dielectric isolation layer 111 may be exposed at the bottom of the opening 140. The side surface 143 of the second conductive type semiconductor layer 109 may be exposed along one side of the opening 140. In some embodiments, the opening 140 in the third dielectric material layer 136 may have a dimension of at least about 5 nanometers along the second horizontal direction hd2, and may be substantially equal to the width dimension of the second conductive type semiconductor layer 109 along the second horizontal direction hd2. The opening 140 may have a dimension of at least about 5 nanometers along the first horizontal direction hd1. In some embodiments, the dimensions of the opening 140 along the first horizontal direction hd1 and the second horizontal direction hd2 may be substantially the same as corresponding dimensions of the underlying first electrode 113 , and the opening 140 may be vertically aligned above the first electrode 113 .

[0124] Fig.18A is a top view of an intermediate structure showing a second electrode 115 formed within an opening 140 in a third dielectric material layer 136 according to various embodiments of the present invention. Fig.18B It is along Fig.18A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig.18A and Fig.18B, a conductive material may be deposited in the opening 140 in the third dielectric material layer 136 and on the upper surface 134 of the second conductive type semiconductor layer 109 and the upper surface 137 of the third dielectric material layer 136. The conductive material may be composed of one or more suitable conductive materials (e.g., the metal liner material and the metal filling material as described above with reference to the first electrode 113). The conductive material may be formed by a suitable deposition process (e.g., one or more of a CVD process, a PVD process, an ALD process, an electroplating process, etc.). Other suitable deposition processes are also within the scope of the present invention. Excess portions of the conductive material may be removed from above the horizontal plane including the upper surface 134 of the second conductive type semiconductor layer 109 and the upper surface 137 of the third dielectric material layer 136 by a planarization process such as CMP, although other suitable planarization processes may be used. The remaining portion of the conductive material may form the second electrode 115. The second electrode 115 may contact the side surface 143 of the second conductive type semiconductor layer 109 on the side surface of the second electrode 115. The width dimension of the second electrode 115 along the second horizontal direction hd2 may be substantially equal to the corresponding width dimension of the second conductive type semiconductor layer 109. The height dimension of the second electrode 115 (along the vertical direction) may be substantially equal to the corresponding height dimension of the second conductive type semiconductor layer 109 (i.e., the upper surface 141 of the second electrode 115 may be substantially coplanar with the upper surface 134 of the second conductive type semiconductor layer 109). In various embodiments, the length dimension of the second electrode 115 along the first horizontal direction hd1 may be at least about 5 nanometers. In some embodiments, the dimensions of the second electrode 115 along the first horizontal direction hd1 and the second horizontal direction hd2 may be substantially the same as the corresponding dimensions of the underlying first electrode 113, and the second electrode 115 may be vertically aligned above the first electrode 113. In this regard, the side surface of the second electrode 115 may be substantially aligned with the corresponding side surface of the underlying first electrode 113. The dielectric isolation layer 111 may be located between the second electrode 115 and the first electrode 113.

[0125] Fig.19A is a top view of the intermediate structure, which shows a patterned mask 144 formed on the third dielectric material layer 136 , the second conductivity type semiconductor layer 109 , and the second electrode 115 according to various embodiments of the present invention. Fig.19B It is along Fig.19A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig.19A and Fig.19B The patterned mask 144 can be formed by depositing a layer of photoresist material on the upper surface 137 of the third dielectric material layer 136, the upper surface 134 of the second conductive type semiconductor layer 109, and the upper surface 141 of the second electrode 115, and patterning the photoresist material using photolithography technology to form a Fig.19A and Fig.19B The patterned photoresist mask 144 shown. The patterned mask 144 may include a stripe-shaped opening 142 passing through the patterned mask 144, wherein a portion of the third dielectric material layer 136 may be exposed at the bottom of the opening 142 in the patterned mask 144. In some embodiments, the opening 142 may have a dimension of at least about 5 nanometers along the second horizontal direction hd2, and may be substantially equal to the width dimension of the second conductive type semiconductor layer 109 and / or the second electrode 115 along the second horizontal direction hd2. The opening 142 may have a dimension of at least about 5 nanometers along the first horizontal direction hd1. The opening 142 may be positioned adjacent to a side surface of the second conductive type semiconductor layer 109, the side surface being opposite to a side surface 143 of the second conductive type semiconductor layer 109 contacting the second electrode 115.

[0126] Fig. 20A 1 is a top view of the intermediate structure, showing the opening 148 formed through the third dielectric material layer 136 , the dielectric isolation layer 111 , and the second dielectric material layer 126 and exposing the upper surface 122 of the first dielectric layer 102 according to various embodiments of the present invention. Fig. 20B It is along Fig. 20A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig. 20A and Fig. 20B , an anisotropic etching process may be performed to remove portions of the third dielectric material layer 136, the dielectric isolation layer 111, and the second dielectric material layer 126 that are not masked by the patterned mask 144, and to form an opening 148 extending through the third dielectric material layer 136, the dielectric isolation layer 111, and the second dielectric material layer 126. The patterned mask 144 may then be removed by ashing or by dissolving with a solvent. After the etching process, the upper surface 122 of the first dielectric material layer 102 and the upper surface 123 of the via 121 may be exposed at the bottom of the opening 148. A side surface 146 of the second conductive type semiconductor layer 109 opposite to the side surface 143 of the second conductive type semiconductor layer 109 contacting the second electrode 115 may be exposed along one side of the opening 148. In addition, a side surface 147 of the first conductive type semiconductor layer 107 opposite to the side surface 133 of the first conductive type semiconductor layer 107 contacting the first electrode 113 may also be exposed along one side of the opening 148. In some embodiments, the opening 148 may have a dimension of at least about 5 nanometers along the second horizontal direction hd2, and may be substantially equal to a width dimension of the second conductive type semiconductor layer 109 and / or the first conductive type semiconductor layer 107 along the second horizontal direction hd2. The opening 148 may have a dimension of at least about 5 nanometers along the first horizontal direction hd1.

[0127] Fig.21Ais a top view of an intermediate structure showing a third electrode 117 formed within an opening 148 in the third dielectric material layer 136 , the dielectric isolation layer 111 , and the second dielectric material layer 126 according to various embodiments of the present invention. Fig. 21B It is along Fig. 21B A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig.21A and Fig. 21B , a conductive material may be deposited in the opening 148 in the third dielectric material layer 136, the dielectric isolation layer 111, and the second dielectric material layer 126 and on the upper surface 134 of the second conductive type semiconductor layer 109, the upper surface 137 of the third dielectric material layer 136, and the upper surface 141 of the second electrode 115. The conductive material may be composed of one or more suitable conductive materials (e.g., the metal liner material and the metal filling material as described above with reference to the first electrode 113). The conductive material may be formed by a suitable deposition process (e.g., one or more of a CVD process, a PVD process, an ALD process, an electroplating process, etc.). Other suitable deposition processes are also within the scope of the present invention. By a planarization process such as CMP, excess portions of the conductive material may be removed from above the horizontal plane including the upper surface 134 of the second conductive type semiconductor layer 109, the upper surface 137 of the third dielectric material layer 136, and the upper surface 141 of the second electrode 115, although other suitable planarization processes may be used. The remaining portion of the conductive material may form a third electrode 117. The third electrode 117 may contact the via 121 on the bottom surface of the third electrode 117. A side surface of the third electrode 117 may also contact a side surface 146 of the second conductive type semiconductor layer 109 and a side surface 147 of the first conductive type semiconductor layer 107, the side surface 146 being opposite to the side surface 143 of the second conductive type semiconductor layer 109 contacting the second electrode 115, and the side surface 147 being opposite to the side surface 133 of the first conductive type semiconductor layer 107 contacting the first electrode 113. In some embodiments, the third electrode 117 may have a dimension of at least about 5 nanometers along the second horizontal direction hd2, and may be substantially equal to a width dimension of the second conductive type semiconductor layer 109 and / or the first conductive type semiconductor layer 107 along the second horizontal direction hd2. The third electrode 117 may have a dimension of at least about 5 nanometers along the first horizontal direction hd1. The third electrode 117 may have a height dimension equal to the combined height dimension of the first conductive type semiconductor layer 107, the dielectric isolation layer 111 and the second conductive type semiconductor layer 109 (i.e., the upper surface 145 of the third electrode 117 may be substantially coplanar with the upper surface 134 of the second conductive type semiconductor layer 109 and the upper surface 141 of the second electrode 115).

[0128] Fig.22Ais a top view of the intermediate structure, which shows a patterned mask 149 formed on the third dielectric material layer 136 , the second conductive type semiconductor layer 109 , the second electrode 115 , and the third electrode 117 according to various embodiments of the present invention. Fig. 22B It is along Fig.22A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig. 22C It is along Fig.22A A vertical cross-sectional view of an exemplary intermediate structure taken along line BB' in FIG. FIG. 22A to FIG. 22C The patterned mask 149 can be formed by depositing a layer of photoresist material on the upper surface 137 of the third dielectric material layer 136, the upper surface 134 of the second conductive type semiconductor layer 109, the upper surface 141 of the second electrode 115, and the upper surface 145 of the third electrode 117, and patterning the photoresist material using photolithography technology to form a Fig.22A and Fig. 22B The patterned photoresist mask 149 is shown. The patterned mask 149 may include a pair of stripe-shaped openings 150 passing through the patterned mask 149, wherein a portion of the third dielectric material layer 136 may be exposed at the bottom of each of the openings 150 in the patterned mask 149. The openings 150 may extend parallel to each other along the first horizontal direction hd1. Each of the openings 150 may be positioned adjacent to a side surface of the second conductive type semiconductor layer 109, such as Fig. 22C shown.

[0129] Fig.23A is a top view of the intermediate structure, showing a pair of trench openings 151 formed through the third dielectric material layer 136 , the dielectric isolation layer 111 , and the second dielectric material layer 126 and exposing the upper surface 122 of the first dielectric layer 102 according to various embodiments of the present invention. Fig. 23B It is along Fig.23A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig.23C It is along Fig.23A A vertical cross-sectional view of the intermediate structure taken along line BB' in FIG. FIG. 23A to FIG. 23C , an anisotropic etching process may be performed to remove portions of the third dielectric material layer 136, the dielectric isolation layer 111, and the second dielectric material layer 126 that are not masked by the patterned mask 149, and form a pair of trench openings 151 extending through the third dielectric material layer 136, the dielectric isolation layer 111, and the second dielectric material layer 126. The patterned mask 149 may then be removed by ashing or by dissolving with a solvent. After the etching process, the upper surface 122 of the first dielectric material layer 102 may be exposed at the bottom of each of the trench openings 151. The trench openings 151 may extend parallel to each other along the first horizontal direction hd1. Referring to FIG. Fig.23CThe remaining portions of the first conductive type semiconductor layer 107, the dielectric isolation layer 111, and the second conductive type semiconductor layer 109 located between the pair of trench openings 151 may form a layer stack 170 having continuous side surfaces on opposite sides of the layer stack 170 forming the outer sidewalls of each of the trench openings 151. Opposite side surfaces 152a and 152b of the second conductive type semiconductor layer 109 and opposite side surfaces 153a and 153b of the first conductive type semiconductor layer 107 may be exposed along the outer sidewalls of the trench openings 151.

[0130] Fig.24A is a top view of the intermediate structure, showing the gate dielectric layer 103 formed on the third dielectric material layer 136 , the second conductivity type semiconductor layer 109 , the second electrode 115 and the third electrode 117 , and on the sidewalls and bottom surface of the trench opening 151 according to various embodiments of the present invention. Fig. 24B It is along Fig.24A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig.24C It is along Fig.24A A vertical cross-sectional view of the intermediate structure taken along line BB' in FIG. FIG. 24A to FIG. 24C , a gate dielectric layer 103 may be deposited on the upper surface 137 of the third dielectric material layer 136, the upper surface 134 of the second conductive type semiconductor layer 109, the upper surface 141 of the second electrode 115, and the upper surface 145 of the third electrode 117, and along the sidewalls and bottom surfaces of each of the trench openings 151. The gate dielectric layer 103 may include a suitable dielectric material (such as, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, tantalum oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina) or various other insulating structures (such as a multilayer stack structure including alternating insulating layers). Other suitable dielectric materials are also within the scope of the present invention. In various embodiments, the gate dielectric layer 103 may be formed by a suitable conformal deposition process (such as ALD, CVD, PECVD, PVD, etc.). The thickness of the gate dielectric layer 103 may range from approximately 2 nanometers to approximately 20 nanometers, although other embodiments may include lesser and greater thicknesses. After depositing the gate dielectric layer 103, the intermediate structure may optionally be annealed. The optional annealing process may be performed using a rapid thermal annealing or furnace annealing process at a temperature in the range of 200° C. to 400° C. The annealing may be performed in an environment of nitrogen, oxygen, or a mixture thereof.

[0131] Fig.25Ais a top view of an intermediate structure, showing a dielectric filling layer 154 formed on the gate dielectric layer 103 and filling the remaining volume of the trench opening 151 and a patterned mask 155 formed on the dielectric filling layer 154 according to various embodiments of the present invention. Fig.25B It is along Fig.25A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig.25C It is along Fig.25A A vertical cross-sectional view of an exemplary intermediate structure taken along line BB' in FIG. FIG. 25A to FIG. 25C A dielectric filling layer 154 may be deposited on the upper surface of the gate dielectric layer 103 via a suitable deposition method (e.g., CVD, ALD, PVD, PECVD, spin coating, etc.). The dielectric filling layer 154 may fill the remaining volume of the pair of trench openings 151. The dielectric filling layer 154 may be composed of a suitable dielectric material as described above. An optional planarization process (e.g., a chemical mechanical planarization (CMP) process) may be performed to provide a planar upper surface of the dielectric filling layer 154.

[0132] like FIG. 25A to FIG. 25C As shown, a patterned mask 155 can be formed on the dielectric filling layer 154 in the following manner: a layer of photoresist material is deposited on the upper surface of the dielectric filling layer 154, and the photoresist material is patterned using a photolithography technique to form a patterned photoresist mask 155. The patterned mask 155 can be similar to the above reference FIG. 22A to FIG. 22C The patterned mask 149 described above may include a pair of strip-shaped openings 156 extending parallel to each other along a first horizontal direction hd1. The dielectric filling layer 154 may be exposed at the bottom of each of the openings 156 in the patterned mask 155. In some embodiments, the length dimension of each of the openings 156 along the first horizontal direction hd1 may be at least about 10 nanometers. In some embodiments, the length dimension of the openings 156 may be substantially equivalent to the distance between the third electrode 117 and the second electrode 115 along the first horizontal direction hd1. In various embodiments, the width dimension of each of the openings 156 along the second horizontal direction hd2 may be at least about 10 nanometers. Fig.25C As shown, the patterned mask 155 may cover the horizontal extension portion 103c of the gate dielectric layer 103 located above the upper surface 134 of the second conductive type semiconductor layer 109 and the vertical extension portions 103a and 103b of the gate dielectric layer 103, and the vertical extension portions 103a and 103b are in contact with the side surfaces 152a and 152b of the second conductive type semiconductor layer 109 and the side surfaces 153a and 153b of the first conductive type semiconductor layer 107.

[0133] Fig.26Ais a top view of an intermediate structure showing a pair of trench openings 157 formed through the dielectric fill layer 154 and portions of the gate dielectric layer 103 and exposing the upper surface 122 of the first dielectric layer 102 according to various embodiments of the present invention. Fig.26B It is along Fig.26A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig.26C It is along Fig.26A A vertical cross-sectional view of the intermediate structure taken along line BB' in FIG. FIG. 26A to FIG. 26C , an anisotropic etching process may be performed to remove portions of the dielectric filling layer 154 and portions of the gate dielectric layer 103 and optionally portions of the third dielectric layer 136, portions of the dielectric isolation layer 111, and portions of the second dielectric layer 126 to provide a pair of trench openings 157 extending parallel to each other along the first horizontal direction hd1. The patterned mask 155 may then be removed by ashing or by dissolving with a solvent. After the etching process, the upper surface 122 of the first dielectric layer 102 may be exposed at the bottom of each of the trench openings 157. Fig.26C As shown, a portion of the gate dielectric layer 103 may surround the layer stack 170 over both side surfaces and the upper surface of the layer stack 170. That is, the first vertically extending portion 103a of the gate dielectric layer 103 may extend over and contact the first side surface 153a of the first conductive type semiconductor layer 107, the first side surface of the dielectric isolation layer 111, and the first side surface 152a of the second conductive type semiconductor layer 109. The second vertically extending portion 103b of the gate dielectric layer 103 may extend over and contact the second side surface 153b of the first conductive type semiconductor layer 107, the second side surface of the dielectric isolation layer 111, and the second side surface 152b of the second conductive type semiconductor layer 109. The horizontal extension portion 103c of the gate dielectric layer 103 may extend above and contact the upper surface 134 of the second conductive type semiconductor layer 109 between the first vertical extension portion 103a and the second vertical extension portion 103b of the dielectric layer 103. The first vertical extension portion 103a and the second vertical extension portion 103b of the gate dielectric layer 103 may each form an outer sidewall of a corresponding trench opening 157.

[0134] Fig.27Ais a top view of a semiconductor device structure 100 including a pair of gate electrodes 105 a and 105 b extending on opposite sides of a layer stack 170 according to various embodiments of the present invention. Fig.27B It is along Fig.27A A vertical cross-sectional view of the intermediate structure taken along line AA' in FIG. Fig.28C It is along Fig.27A A vertical cross-sectional view of the intermediate structure taken along line BB' in FIG. Fig.27D It is along Fig.27A A vertical cross-sectional view of the intermediate structure taken along line CC' in FIG. Fig.27E It is along Fig.27A A vertical cross-sectional view of the intermediate structure taken along line D-D' in FIG. FIG. 27A to FIG. 27E , a conductive material may be deposited within the trench opening 157 and over the upper surface of the dielectric fill layer 154. The conductive material may fill the trench opening 157 to a level that includes at least a horizontal plane of the upper surface of the horizontally extending portion 103c of the gate dielectric layer 103. A planarization process such as a CMP process and / or an etching process may be used to remove a portion of the conductive material and a portion of the dielectric fill layer 154 from above a horizontal plane including the upper surface of the horizontally extending portion 103c of the gate dielectric layer 103, and provide discrete gate electrodes 105a and 105b located within each of the trench openings 157. The first gate electrode 105a may contact the first vertically extending portion 103a of the gate dielectric layer 103 over a first side surface of the layer stack 170, and the second gate electrode 105b may contact the second vertically extending portion 103b of the gate dielectric layer 103 over a second side surface of the layer stack 170.

[0135] The first gate electrode 105a and the second gate electrode 105b may be composed of suitable conductive materials as described above (e.g., TiN, W, WN, WCN, Co, PdCo, ​​Mo, Cu, TaN, Ti, Al, etc., including combinations and alloys thereof). Other suitable conductive materials are also within the scope of the present invention. In some embodiments, the first gate electrode 105a and the second gate electrode 105b may include a metal liner material and a metal filling material as described above. The first gate electrode 105a and the second gate electrode 105b may be formed by a suitable deposition process, which may include one or more of a CVD process, a PVD process, an ALD process, an electroplating process, etc. Other suitable deposition processes are also within the scope of the present invention. In various embodiments, each of the gate electrodes 105a and 105b may have a length dimension of at least about 10 nanometers along the first horizontal direction hd1 and a width dimension of at least about 10 nanometers along the second horizontal direction hd2. The upper surface 158 of each of the gate electrodes 105 a and 105 b may be substantially coplanar with the upper surface of the gate dielectric layer 103 .

[0136] Reference FIG. 27A to FIG. 27E , showing a semiconductor device structure 100 according to an embodiment of the present invention. The semiconductor device structure includes a layer stack 170, the layer stack 170 including a first conductivity type semiconductor layer 107, a dielectric isolation layer 111 located on the first conductivity type semiconductor layer 107, and a second conductivity type semiconductor layer 109 located on the dielectric isolation layer 111. The first electrode 113 may be located on the first end 101 of the semiconductor device structure 100 and may contact the first side surface 133 of the first conductivity type semiconductor layer 107. The second electrode 115 may be located on the first end 101 of the semiconductor device structure 100 and may contact the first side surface 143 of the second conductivity type semiconductor layer 109. The dielectric isolation layer 111 may extend between the first electrode 113 and the second electrode 115. The third electrode 117 may be located on the second end 104 of the semiconductor device structure 100 opposite to the first end 101, and may contact the second side surface 147 of the first conductive type semiconductor layer 107, the side surface of the dielectric isolation layer 111, and the second side surface 146 of the second conductive type semiconductor layer 109. A pair of gate electrodes 105a may extend along opposite side surfaces of the layer stack 170, and the gate dielectric layer 103 may extend between each of the gate electrodes 105a and 105b and each of the corresponding side surfaces of the layer stack 170.

[0137] In various embodiments, the semiconductor device structure 100 may be configured as a NOT gate or inverter circuit such that a given input signal having a first logic state applied at the first gate electrode 105a and the second gate electrode 105b will generate an output signal from the third electrode 117 having a complementary logic state. In this regard, a high voltage input signal at the first gate electrode 105a and the second gate electrode 105b generates a low voltage output signal at the third electrode 117, and a low voltage input signal at the first gate electrode 105a and the second gate electrode 105b generates a high voltage output signal at the third electrode 117. In various embodiments, the semiconductor device structure 100 may be fabricated using a BEOL process using thin film metal oxide semiconductor materials. Thus, this may enable computing operations to be performed at least partially within one or more interconnect levels of a semiconductor integrated circuit (IC) die, which may enable an increase in the integration density of a semiconductor IC die and / or an increase in the processing power of a semiconductor IC die.

[0138] Fig.28A It is a top view of a semiconductor device structure 100 according to various embodiments of the present invention, wherein the semiconductor device structure 100 includes a fourth dielectric material layer 159 formed on a gate dielectric layer 103 and gate electrodes 105a and 105b, and a plurality of vias 160a and 160b located in the fourth dielectric material layer 159. Fig.28B It is along Fig.28A 1 is a vertical cross-sectional view of the semiconductor device structure 100 taken along line AA′ in FIG. Fig.28C It is along Fig.28A A vertical cross-sectional view of the semiconductor device structure 100 taken along line BB' in FIG. FIG. 28A to FIG. 28C , a fourth dielectric material layer 159 may be deposited on the upper surface of the gate dielectric layer 103 and the upper surfaces 158 of the first gate electrode 105a and the second gate electrode 105b by a suitable deposition method (e.g., CVD, ALD, PVD, PECVD, spin coating, etc.). The fourth dielectric material layer 159 may be composed of a suitable dielectric material as described above (e.g., undoped silicate glass, doped silicate glass, organic silicate glass, silicon oxynitride, silicon carbide nitride, etc.). Metal interconnect features including metal lines 161, 163 and vias 160a, 160b, 162 may be formed in the first dielectric material layer 102 (e.g., by a single damascene process or a dual damascene process). (For clarity, Fig.28A The metal lines 161 and 163 are not shown. Fig.28B As shown, the through hole 162 can electrically connect the metal line 163 to the second electrode 115. Fig.28C As shown, a pair of vias 160a and 160b may electrically connect a metal line 161 to each of the gate electrodes 105a and 105b.

[0139] Fig.29 is a flow chart showing a method 300 for fabricating a semiconductor device structure 100 according to various embodiments of the present invention. 4A to 6B and Fig.29 In step 301 of the embodiment method 300, a first conductive type semiconductor layer 107 may be formed. 7A to 10B and Fig.29 In step 303 of the embodiment method 300, a first electrode 113 in contact with the first side surface 133 of the first conductive type semiconductor layer 107 may be formed. FIG. 11A to FIG. 11B and Fig.29 In step 305 of the embodiment method 300, a dielectric isolation layer 111 may be formed on the first conductive type semiconductor layer 107 and the first electrode 113. FIG. 12A to FIG. 14B and Fig.29 In step 307 of the embodiment method 300, a second conductivity type semiconductor layer 109 may be formed on the dielectric isolation layer 111. FIG. 15A to FIG. 18B and Fig.29 In step 309 of the embodiment method 300, a second electrode 115 in contact with the first side surface 143 of the second conductive type semiconductor layer 109 may be formed. FIG. 19A to FIG. 21B and Fig.29 In step 311 of the embodiment method 300, a third electrode 117 may be formed to contact the second side surface 147 of the first conductive type semiconductor layer 107, the side surface of the dielectric isolation layer 111, and the second side surface 146 of the second conductive type semiconductor layer 109. FIG. 22A to FIG. 26C and Fig.29 In step 313 of the embodiment method 300, a gate dielectric layer 103 may be formed on the opposite third side surface 153a and fourth side surface 153b of the first conductive type semiconductor layer 107, the opposite side surface of the dielectric isolation layer 111, and the opposite third side surface 152a and fourth side surface 152b of the second conductive type semiconductor layer 109. FIG. 27A to FIG. 27E and Fig.29 In step 315 of the embodiment method 300, a first gate electrode 105a in contact with the gate dielectric layer 103 may be formed on the third side surface 153a of the first conductive type semiconductor layer 107 and the third side surface 152a of the second conductive type semiconductor layer 109, and a second gate electrode 105b in contact with the gate dielectric layer 103 may be formed on the fourth side surface 153b of the first conductive type semiconductor layer 107 and the fourth side surface 152b of the second conductive type semiconductor layer 109.

[0140] With reference to all the drawings and in accordance with various embodiments of the present invention, a semiconductor device structure 100 is provided. The semiconductor device structure 100 may include a layer stack 170 having a first conductivity type semiconductor layer 107, a dielectric isolation layer 111 located on the first conductivity type semiconductor layer 107, and a second conductivity type semiconductor layer 109 located on the dielectric isolation layer 111. A first electrode 113 may be adjacent to a first end 101 of the layer stack 170 and may contact a first side surface 133 of the first conductivity type semiconductor layer 107. A second electrode 115 may be adjacent to a first end 101 of the layer stack and may contact a first side surface 143 of the second conductivity type semiconductor layer 109. A third electrode 117 may be adjacent to a second end 104 of the layer stack 170 opposite to the first end 101 of the layer stack 170 and may contact a second side surface 147 of the first conductivity type semiconductor layer 107, a side surface of the dielectric isolation layer 111, and a second side surface 146 of the second conductivity type semiconductor layer 109. The gate dielectric layer 103 may contact the opposite side surfaces of the layer stack 170 over at least a portion of the length of the layer stack 170 between the first end and the second end of the layer stack 170. A pair of gate electrodes 105a and 105b may contact the gate dielectric layer 103 and extend over the opposite side surfaces of the layer stack 170 between the first end and the second end of the layer stack 170 over at least a portion of the length of the layer stack 170.

[0141] In an embodiment, at least one of the first conductive type semiconductor layer 107 or the second conductive type semiconductor layer 109 includes a metal oxide semiconductor.

[0142] In another embodiment, the first conductive type semiconductor layer 107 includes a p-type semiconductor layer, and the second conductive type semiconductor layer 109 includes an n-type semiconductor layer.

[0143] In another embodiment, the p-type semiconductor layer includes one or more of NiO, SnO, and Cu2O.

[0144] In another embodiment, the n-type semiconductor layer includes amorphous silicon, Al2O5Zn2-doped ZnO, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, InO, In2O3, InZnO, ZnO, TiO x and one or more of Group III-V semiconductor materials.

[0145] In another embodiment, a length of the layer stack 170 along the first horizontal direction hd1 between the first end 101 and the second end 104 of the layer stack 170 is 15 nanometers or greater.

[0146] In another embodiment, the width of each of the first electrode 113 , the second electrode 115 , and the third electrode 117 along the second horizontal direction hd2 perpendicular to the first horizontal direction hd1 is equal to the width of the layer stack 170 between opposite side surfaces of the layer stack 170 .

[0147] In another embodiment, the thickness of the first conductivity type semiconductor layer 107 and the second conductivity type semiconductor layer 109 is between 2 nanometers and 50 nanometers, the thickness of the dielectric isolation layer 111 is at least 5 nanometers, and the thickness of the gate dielectric layer 103 is between 2 nanometers and 20 nanometers.

[0148] In another embodiment, the gate dielectric layer 103 includes a first portion 103a extending above a first side surface of the layer stack 170, a second portion 103b extending above a second side surface of the layer stack 170, and a third portion 103c extending above an upper surface 134 of the second conductive type semiconductor layer 109 between the first portion 103a and the second portion 103b of the gate dielectric layer 103.

[0149] In another embodiment, the first conductive type semiconductor layer 107 is formed on an interconnect level dielectric layer 102 having a horizontal surface 122, and wherein the interface surface of the first conductive type semiconductor layer 107, the interface surface of the dielectric isolation layer 111, and the interface surface of the second conductive type semiconductor layer 109 are substantially parallel to the horizontal surface 122 of the interconnect level dielectric layer 102.

[0150] In another embodiment, the interconnect level dielectric layer 102 further includes one or more electrical interconnect structures ( 120 , 121 ), and wherein the first electrode 113 and the third electrode 117 are electrically connected to the one or more electrical interconnect structures ( 120 , 121 ).

[0151] In another embodiment, the dielectric material matrix (126, 111, 136, 103, 159) is located above the semiconductor device structure 100 and laterally surrounds the semiconductor device structure 100, the dielectric material matrix (126, 111, 136, 103, 159) includes one or more electrical interconnect structures (160a, 160b, 161, 162, 163), and the second electrode 115 and the pair of gate electrodes 105a and 105b are electrically connected to the one or more electrical interconnect structures (160a, 160b, 161, 162, 163) in the dielectric material matrix (126, 111, 136, 103, 159).

[0152] In another embodiment, the first electrode 113 is electrically connected to the voltage supply terminal VDD, the second electrode 115 is electrically connected to the ground terminal GND, and the pair of gate electrodes 105a and 105b are electrically connected to the signal input terminal V in , and the third electrode 117 is electrically connected to the signal output terminal V out .

[0153] Another embodiment is related to a semiconductor device, which includes: a substrate 8 having a semiconductor material layer 9; a plurality of device structures 700 formed on or in the semiconductor material layer 9; at least one interconnect level dielectric layer (601, 610, 620, 630, 640, 102) located above the substrate 8 and the device structure 700 and including a conductive interconnect structure (612, 618, 622, 628, 632, 638, 642, 648, 120, 121); and a NOT gate logic circuit 100 located above the interconnect level dielectric layer (601, 610, 620, 630, 640, 102). The NOT gate logic circuit 100 may include: a first conductive type semiconductor layer 107; a second conductive type semiconductor layer 109; a first electrode 113 in contact with a first side surface 133 of the first conductive type semiconductor layer 107; a second electrode 115 in contact with a first side surface 143 of the second conductive type semiconductor layer 109; a dielectric isolation layer 111 extending between the first conductive type semiconductor layer 107 and the second conductive type semiconductor layer 109 and between the first electrode 113 and the second electrode 115; a third electrode 117 in contact with a second side surface 147 of the first conductive type semiconductor layer 107, a second side surface 146 of the second conductive type semiconductor layer 109 and a side surface of the dielectric isolation layer 111; a gate dielectric layer 103 in contact with the first conductive type semiconductor layer 107 and the second conductive type semiconductor layer 109; and a gate electrode (105a, 105b) in contact with the gate dielectric layer 103.

[0154] In an embodiment, an interface surface of the first conductivity type semiconductor layer 107 , an interface surface of the dielectric isolation layer 111 , and an interface surface of the second conductivity type semiconductor layer 109 are parallel to the main surface of the substrate 8 .

[0155] In another embodiment, the first conductive type semiconductor layer 107 includes a p-type semiconductor layer, the second conductive type semiconductor layer 109 includes an n-type semiconductor layer, the first electrode 113 is electrically connected to the voltage source terminal VDD, the second electrode 115 is electrically connected to the ground terminal GND, and the gate electrodes (105a, 105b) are electrically connected to the input signal terminal V in , and the third electrode 117 is electrically connected to the output signal terminal V out .

[0156] Another embodiment is related to a method for manufacturing a semiconductor device structure, the method comprising: forming a first conductive type semiconductor layer 107; forming a first electrode 113 in contact with a first side surface 133 of the first conductive type semiconductor layer 107; forming a dielectric isolation layer 111 on the first conductive type semiconductor layer 107 and the first electrode 113; forming a second conductive type semiconductor layer 109 on the dielectric isolation layer 111; forming a second electrode 115 in contact with a first side surface 143 of the second conductive type semiconductor layer 109; forming a third electrode 117 in contact with a second side surface 147 of the first conductive type semiconductor layer 107, a side surface of the dielectric isolation layer 111, and a second side surface 146 of the second conductive type semiconductor layer 109; A gate dielectric layer 103 is formed on the relative third side surfaces 153a and fourth side surfaces 153b of the first conductive type semiconductor layer 107, the relative side surfaces of the dielectric isolation layer 111, and the relative third side surfaces 152a and fourth side surfaces 152b of the second conductive type semiconductor layer 109; and a first gate electrode 105a in contact with the gate dielectric layer 103 is formed on the third side surface 153a of the first conductive type semiconductor layer 107 and the third side surface 152a of the second conductive type semiconductor layer 109, and a second gate electrode 105b in contact with the gate dielectric layer 103 is formed on the fourth side surface 153b of the first conductive type semiconductor layer 107 and the fourth side surface 152b of the second conductive type semiconductor layer 109.

[0157] In an embodiment, forming the gate dielectric layer 103 includes: forming a pair of trench openings 151, wherein the relative third side surfaces 152a and the fourth side surfaces 152b of the second conductive type semiconductor layer 109, the relative side surfaces of the dielectric isolation layer 111, and the relative third side surfaces 153a and the fourth side surfaces 153b of the first conductive type semiconductor layer 107 are exposed along the side walls of the corresponding trench openings; and depositing the gate dielectric layer 103 on the upper surface 134 of the second conductive type semiconductor layer 109 and along the side walls and bottom surfaces of each of the trench openings 151.

[0158] In another embodiment, forming the first gate electrode 105a and the second gate electrode 105b includes: filling the pair of trench openings 151 with a dielectric filling layer 154; forming a pair of second trench openings 157, wherein the gate dielectric layer 103 is exposed along the side walls of the corresponding second trench openings 157; and depositing a conductive material in contact with the gate dielectric layer 103 in each of the second trench openings 157 to provide the first gate electrode 105a and the second gate electrode 105b.

[0159] In another embodiment, the method further includes: forming a plurality of first conductive vias 121 in the first dielectric material layer 102, wherein the first electrode 113 and the third electrode 117 are formed on the first dielectric material layer 102, so that the first electrode 113 and the third electrode 117 respectively contact the first conductive vias 121; forming a fourth dielectric material layer 159 on the gate dielectric layer 103 and the first gate electrode 105a and the second gate electrode 105b; and forming a plurality of second conductive vias (160a, 160b, 162) in the fourth dielectric material layer 159 that contact the second electrode 115, the first gate electrode 105a and the second gate electrode 105b.

[0160] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. A semiconductor device structure, characterized in that: include: Layer stack, including: a first conductivity type semiconductor layer; a dielectric isolation layer, located on the first conductive type semiconductor layer; and A second conductive type semiconductor layer, located on the dielectric isolation layer; a first electrode adjacent to a first end of the layer stack and in contact with a first side surface of the first conductivity type semiconductor layer; a second electrode adjacent to the first end of the layer stack and in contact with a first side surface of the second conductivity type semiconductor layer; a third electrode adjacent to a second end of the layer stack opposite to the first end of the layer stack and in contact with a second side surface of the first conductive type semiconductor layer, a side surface of the dielectric isolation layer, and a second side surface of the second conductive type semiconductor layer; a gate dielectric layer in contact with opposing side surfaces of the layer stack over at least a portion of the length of the layer stack between the first end and the second end of the layer stack; and A pair of gate electrodes contact the gate dielectric layer over at least a portion of the length of the layer stack between the first end and the second end of the layer stack and extend over the opposing side surfaces of the layer stack.

2. The semiconductor device structure according to claim 1, wherein: A length of the layer stack along a first horizontal direction between the first end and the second end of the layer stack is at least 15 nanometers.

3. The semiconductor device structure according to claim 1, wherein: The gate dielectric layer includes a first portion extending over a first side surface of the layer stack, a second portion extending over a second side surface of the layer stack, and a third portion extending over an upper surface of the second conductive type semiconductor layer between the first and second portions of the gate dielectric layer.

4. The semiconductor device structure according to claim 1, wherein: The first conductive type semiconductor layer is formed on an interconnect level dielectric layer having a horizontal surface, and The interface surface of the first conductive type semiconductor layer, the interface surface of the dielectric isolation layer, and the interface surface of the second conductive type semiconductor layer are substantially parallel to the horizontal surface of the interconnect level dielectric layer.

5. The semiconductor device structure according to claim 4, characterized in that: The interconnect level dielectric layer further includes one or more electrical interconnect structures, and The first electrode and the third electrode are electrically connected to the one or more electrical interconnect structures.

6. The semiconductor device structure according to claim 5, characterized in that: A dielectric material matrix is ​​located above and laterally surrounds the semiconductor device structure, the dielectric material matrix includes one or more electrical interconnect structures, and the second electrode and the pair of gate electrodes are electrically connected to the one or more electrical interconnect structures in the dielectric material matrix.

7. The semiconductor device structure according to claim 1, wherein: The first electrode is electrically connected to a voltage supply terminal, the second electrode is electrically connected to a ground terminal, the pair of gate electrodes is electrically connected to a signal input terminal, and the third electrode is electrically connected to a signal output terminal.

8. A semiconductor device, characterized in that: include: a substrate including a semiconductor material layer; a plurality of device structures formed on or in the semiconductor material layer; at least one interconnect level dielectric layer disposed over the substrate and the plurality of device structures and comprising a conductive interconnect structure; as well as A NOT gate logic circuit is located on the at least one interconnect level dielectric layer, the NOT gate logic circuit comprising: a first conductivity type semiconductor layer; a second conductivity type semiconductor layer; a first electrode in contact with a first side surface of the first conductive type semiconductor layer; a second electrode in contact with the first side surface of the second conductive type semiconductor layer; a dielectric isolation layer extending between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer and between the first electrode and the second electrode; a third electrode in contact with a second side surface of the first conductive type semiconductor layer, a second side surface of the second conductive type semiconductor layer, and a side surface of the dielectric isolation layer; a gate dielectric layer, contacting the first conductive type semiconductor layer and the second conductive type semiconductor layer; and A gate electrode is in contact with the gate dielectric layer.

9. The semiconductor device according to claim 8, wherein: An interface surface of the first conductive type semiconductor layer, an interface surface of the dielectric isolation layer, and an interface surface of the second conductive type semiconductor layer are substantially parallel to a major surface of the substrate.

10. The semiconductor device according to claim 8, wherein: The first conductive type semiconductor layer includes a p-type semiconductor layer, the second conductive type semiconductor layer includes an n-type semiconductor layer, the first electrode is electrically connected to a voltage source terminal, the second electrode is electrically connected to a ground terminal, the gate electrode is electrically connected to an input signal terminal, and the third electrode is electrically connected to an output signal terminal.

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